From bafa9d95453387814ef25e6b6256ba8db2df612f Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Thu, 23 Jan 2020 16:10:22 -0800 Subject: Merge FPGA repository back into UHD repository MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams Co-authored-by: Andrej Rode Co-authored-by: Ashish Chaudhari Co-authored-by: Ben Hilburn Co-authored-by: Ciro Nishiguchi Co-authored-by: Daniel Jepson Co-authored-by: Derek Kozel Co-authored-by: EJ Kreinar Co-authored-by: Humberto Jimenez Co-authored-by: Ian Buckley Co-authored-by: Jörg Hofrichter Co-authored-by: Jon Kiser Co-authored-by: Josh Blum Co-authored-by: Jonathon Pendlum Co-authored-by: Martin Braun Co-authored-by: Matt Ettus Co-authored-by: Michael West Co-authored-by: Moritz Fischer Co-authored-by: Nick Foster Co-authored-by: Nicolas Cuervo Co-authored-by: Paul Butler Co-authored-by: Paul David Co-authored-by: Ryan Marlow Co-authored-by: Sugandha Gupta Co-authored-by: Sylvain Munaut Co-authored-by: Trung Tran Co-authored-by: Vidush Vishwanath Co-authored-by: Wade Fife --- fpga/usrp3/top/b200/.gitignore | 5 + fpga/usrp3/top/b200/Makefile | 97 + fpga/usrp3/top/b200/Makefile.b200.inc | 143 + fpga/usrp3/top/b200/S6CLK2PIN.v | 23 + fpga/usrp3/top/b200/b200.ucf | 245 + fpga/usrp3/top/b200/b200.v | 365 + fpga/usrp3/top/b200/b200_core.v | 423 + fpga/usrp3/top/b200/b200_io.v | 554 + fpga/usrp3/top/b200/check.sh | 1 + fpga/usrp3/top/b200/core_compile | 1 + fpga/usrp3/top/b200/coregen/.gitignore | 5 + .../usrp3/top/b200/coregen/b200_chipscope_icon.asy | 9 + .../b200_chipscope_icon.ucf | 9 + .../b200_chipscope_icon.xdc | 7 + .../usrp3/top/b200/coregen/b200_chipscope_icon.ncf | 0 .../usrp3/top/b200/coregen/b200_chipscope_icon.ngc | 3 + .../usrp3/top/b200/coregen/b200_chipscope_icon.ucf | 9 + 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fpga/usrp3/top/b200/sim/sim_b200_io/mimo/simulation_script.v create mode 100755 fpga/usrp3/top/b200/sim/sim_b200_io/run_isim create mode 100644 fpga/usrp3/top/b200/sim/sim_b200_io/siso/simulation_script.v create mode 100644 fpga/usrp3/top/b200/sim/sim_b200_io/siso/siso.wcfg create mode 100644 fpga/usrp3/top/b200/timing.ucf (limited to 'fpga/usrp3/top/b200') diff --git a/fpga/usrp3/top/b200/.gitignore b/fpga/usrp3/top/b200/.gitignore new file mode 100644 index 000000000..376246b05 --- /dev/null +++ b/fpga/usrp3/top/b200/.gitignore @@ -0,0 +1,5 @@ +build* +catcap_tb +catgen_tb +fuse* +isim* diff --git a/fpga/usrp3/top/b200/Makefile b/fpga/usrp3/top/b200/Makefile new file mode 100644 index 000000000..8a3569e00 --- /dev/null +++ b/fpga/usrp3/top/b200/Makefile @@ -0,0 +1,97 @@ +# +# Copyright 2012-2014 Ettus Research LLC +# + +# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target +##------------------- +##USRP B2X0 FPGA Help +##------------------- +##Usage: +## make +## +##Output: +## build/usrp__fpga.bit: Configuration bitstream with header +## build/usrp__fpga.bin: Configuration bitstream without header +## build/usrp__fpga.syr: Xilinx system report +## build/usrp__fpga.twr: Xilinx timing report + +# Build USRP B2x0 design with a debug UART on J400 +ifeq ($(DEBUG_UART),1) +OPTIONS += DEBUG_UART=1 +endif + +print_report = \ + echo "========================================================================"; \ + cat $(1)/b200.syr | grep "Device utilization summary:" -A 30; \ + echo "========================================================================"; \ + echo "Timing Summary:\n"; \ + cat $(1)/b200.twr | grep constraint | grep met | grep -v "*"; \ + echo "========================================================================"; + +# pre_build($1=Device) +ifeq ($(EXPORT_ONLY),1) + pre_build = @test -s build-$(1)/b200.bit || { echo "EXPORT_ONLY requires the project in build-$(1) to be fully built."; false; } +else + pre_build = @echo "ISE Version: $(shell xtclsh -h | head -n1)" +endif + +# ise_build($1=Device, $2=Definitions) +ifeq ($(PROJECT_ONLY),1) + ise_build = make -f Makefile.b200.inc proj NAME=$@ DEVICE=$1 EXTRA_DEFS="$2 $(OPTIONS)" +else ifeq ($(EXPORT_ONLY),1) + ise_build = @echo "Skipping ISE build and exporting pre-built files."; +else + ise_build = make -f Makefile.b200.inc bin NAME=$@ DEVICE=$1 EXTRA_DEFS="$2 $(OPTIONS)" +endif + +# post_build($1=Device) +ifeq ($(PROJECT_ONLY),1) + post_build = \ + @echo "Generated $(shell pwd)/build-$(1)/b200.xise"; \ + echo "\nProject Generation DONE ... $(1)\n"; +else + post_build = \ + @$(call print_report,build-$(1)) \ + mkdir -p build; \ + echo "Exporting bitstream files..."; \ + cp build-$(1)/b200.bin build/usrp_`echo $(1) | tr A-Z a-z`_fpga.bin; \ + cp build-$(1)/b200.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga.bit; \ + echo "Exporting logs..."; \ + cp build-$(1)/b200.syr build/usrp_`echo $(1) | tr A-Z a-z`_fpga.syr; \ + cp build-$(1)/b200.twr build/usrp_`echo $(1) | tr A-Z a-z`_fpga.twr; \ + echo "\nBuild DONE ... $(1)\n"; +endif + +## +##Supported Targets +##----------------- + +all: B200 B210 ##(Default target) + +B200: ##Build USRP B200 design. + $(call pre_build,B200) + $(call ise_build,XC6SLX75,) + $(call post_build,B200) + +B210: ##Build USRP B210 design. + $(call pre_build,B210) + $(call ise_build,XC6SLX150,TARGET_B210=1) + $(call post_build,B210) + +clean: ##Clean up all build output. + rm -rf build-* + rm -rf build + +help: ## Show this help message. + @grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//' + +## +##Supported Options +##----------------- +##PROJECT_ONLY=1 Only create a Xilinx project for the specified target(s). +## Useful for use with the ISE GUI. +##EXPORT_ONLY=1 Export build targets from a GUI build to the build directory. +## Requires the project in build-*_* to be built. +##DEBUG_UART=1 Build USRP B2x0 design with a debug UART on J400 + +.PHONY: all clean help diff --git a/fpga/usrp3/top/b200/Makefile.b200.inc b/fpga/usrp3/top/b200/Makefile.b200.inc new file mode 100644 index 000000000..788280c6a --- /dev/null +++ b/fpga/usrp3/top/b200/Makefile.b200.inc @@ -0,0 +1,143 @@ +# +# Copyright 2012-2013 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE := b200 +BUILD_DIR := build-$(NAME)/ +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +# set me in a custom makefile +CUSTOM_SRCS = +CUSTOM_DEFS = + +include ../Makefile.common +include ../../lib/gpif2/Makefile.srcs +include ../../lib/fifo/Makefile.srcs +include ../../lib/fifo_200/Makefile.srcs +include ../../lib/dsp/Makefile.srcs +include ../../lib/control/Makefile.srcs +include ../../lib/control_200/Makefile.srcs +include ../../lib/packet_proc/Makefile.srcs +include ../../lib/packet_proc_200/Makefile.srcs +include ../../lib/timing/Makefile.srcs +include ../../lib/vita_200/Makefile.srcs +include ../../lib/wishbone/Makefile.srcs +include ../../lib/axi/Makefile.srcs +include ../../lib/radio_200/Makefile.srcs +include ../../lib/io_cap_gen/Makefile.srcs +include coregen_dsp/Makefile.srcs + + +B200_COREGEN_SRCS = \ +coregen/b200_clk_gen.v \ +coregen/fifo_4k_2clk.xco \ +coregen/fifo_short_2clk.xco \ +coregen/chipscope_icon.v \ +coregen/chipscope_icon.xco \ +coregen/chipscope_ila_32.v \ +coregen/chipscope_ila_32.xco \ +coregen/chipscope_ila_128.v \ +coregen/chipscope_ila_128.xco \ +coregen/chipscope_ila_256.v \ +coregen/chipscope_ila_256.xco + + + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan6" \ +device $(DEVICE) \ +package fgg484 \ +speed -3 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +b200.v \ +b200_core.v \ +b200_io.v \ +b200.ucf \ +timing.ucf \ +S6CLK2PIN.v \ +$(B200_COREGEN_SRCS) + +# GPIO only available for B210 +# The LX75 on the B200 is missing the connection from the balls to the internal fabric +ifeq ($(NAME),B210) +TOP_SRCS+=gpio.ucf +endif + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) $(FIFO_200_SRCS) \ +$(CONTROL_LIB_SRCS) $(CONTROL_LIB_200_SRCS) $(SDR_LIB_SRCS) \ +$(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) \ +$(GPIF2_SRCS) $(PACKET_PROC_SRCS) $(PACKET_PROC_200_SRCS) \ +$(WISHBONE_SRCS) \ +$(TIMING_SRCS) \ +$(DSP_SRCS) \ +$(VITA_200_SRCS) \ +$(AXI_SRCS) \ +$(RADIO_200_SRCS) \ +$(CAT_CAP_GEN_SRCS) \ +$(COREGEN_DSP_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto \ +"Verilog Macros" "SPARTAN6=1 $(EXTRA_DEFS) $(CUSTOM_DEFS)" \ +"Other XST Command Line Options" "-loop_iteration_limit 16385" + +#"Number of Clock Buffers" 8 \ + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Generate Detailed MAP Report" TRUE \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Unused IOB Pins" "Pull Up" + +#"Configuration Rate" 6 \ +#"Enable Outputs (Output Events)" 6 \ + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp3/top/b200/S6CLK2PIN.v b/fpga/usrp3/top/b200/S6CLK2PIN.v new file mode 100644 index 000000000..a9d6332ef --- /dev/null +++ b/fpga/usrp3/top/b200/S6CLK2PIN.v @@ -0,0 +1,23 @@ +module S6CLK2PIN +( + input I, + output O +); + + ODDR2 #( + .DDR_ALIGNMENT("NONE"), // to "NONE", "C0" or "C1" + .INIT(1'b0), // output to 1'b0 or 1'b1 + .SRTYPE("ASYNC")) // set/reset "SYNC" or "ASYNC" + + ODDR2_S6CLK2PIN + ( + .Q(O), // 1-bit DDR output data + .C0(I), // 1-bit clock input + .C1(~I), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(1'b1), // 1-bit data input (associated with C0) + .D1(1'b0), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0) );// 1-bit set input + +endmodule //S6CLK2PIN diff --git a/fpga/usrp3/top/b200/b200.ucf b/fpga/usrp3/top/b200/b200.ucf new file mode 100644 index 000000000..501b06c33 --- /dev/null +++ b/fpga/usrp3/top/b200/b200.ucf @@ -0,0 +1,245 @@ +## SPI Nets + +NET "cat_ce" LOC = "Y1" | IOSTANDARD = LVCMOS18; +NET "cat_miso" LOC = "V1" | IOSTANDARD = LVCMOS18; +NET "cat_mosi" LOC = "T4" | IOSTANDARD = LVCMOS18; +NET "cat_sclk" LOC = "P7" | IOSTANDARD = LVCMOS18; + +NET "fx3_ce" LOC = "H20" | IOSTANDARD = LVCMOS18 ; +NET "fx3_miso" LOC = "G20" | IOSTANDARD = LVCMOS18 ; +NET "fx3_mosi" LOC = "AA20" | IOSTANDARD = LVCMOS18 ; +#NET "fx3_mosi" LOC = "A9" | IOSTANDARD = LVCMOS33 ; +NET "fx3_sclk" LOC = "Y21" | IOSTANDARD = LVCMOS18 ; + +NET "pll_ce" LOC = "W11" | IOSTANDARD = LVCMOS18 ; +NET "pll_mosi" LOC = "AB11" | IOSTANDARD = LVCMOS18 ; +NET "pll_sclk" LOC = "Y12" | IOSTANDARD = LVCMOS18 ; + +## UART header not always connected so has pullups. Can also be GPIO as build option. +NET "FPGA_RXD0" LOC = "AB8" | IOSTANDARD = LVCMOS18 | PULLUP ; +NET "FPGA_TXD0" LOC = "AB7" | IOSTANDARD = LVCMOS18 | PULLUP ; + +## Catalina Controls + +NET "codec_enable" LOC = "J6" | IOSTANDARD = LVCMOS18; +NET "codec_en_agc" LOC = "P6" | IOSTANDARD = LVCMOS18; +NET "codec_reset" LOC = "Y2" | IOSTANDARD = LVCMOS18; +NET "codec_sync" LOC = "M3" | IOSTANDARD = LVCMOS18; +NET "codec_txrx" LOC = "M7" | IOSTANDARD = LVCMOS18; + +NET "codec_ctrl_in<0>" LOC = "E3" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in<1>" LOC = "F2" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in<2>" LOC = "F1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in<3>" LOC = "E1" | IOSTANDARD = LVCMOS18; + +NET "codec_ctrl_out<0>" LOC = "D1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<1>" LOC = "C1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<2>" LOC = "H3" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<3>" LOC = "F3" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<4>" LOC = "P1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<5>" LOC = "J1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<6>" LOC = "B1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<7>" LOC = "H2" | IOSTANDARD = LVCMOS18; + +## Catalina Data TX + +NET "tx_codec_d<0>" LOC = "T2" | IOSTANDARD = LVCMOS18 ; +NET "tx_codec_d<1>" LOC = "R1" | IOSTANDARD = LVCMOS18 ; +NET "tx_codec_d<2>" LOC = "V2" | IOSTANDARD = LVCMOS18 ; +NET "tx_codec_d<3>" LOC = "N1" | IOSTANDARD = LVCMOS18 ; +NET "tx_codec_d<4>" LOC = "V3" | IOSTANDARD = LVCMOS18 ; +NET "tx_codec_d<5>" LOC = "T1" | IOSTANDARD = LVCMOS18 ; +NET "tx_codec_d<6>" LOC = "W1" | IOSTANDARD = LVCMOS18 ; +NET "tx_codec_d<7>" LOC = "U1" | IOSTANDARD = LVCMOS18 ; +NET "tx_codec_d<8>" LOC = "W3" | IOSTANDARD = LVCMOS18 ; +NET "tx_codec_d<9>" LOC = "U3" | IOSTANDARD = LVCMOS18 ; +NET "tx_codec_d<10>" LOC = "P2" | IOSTANDARD = LVCMOS18 ; +NET "tx_codec_d<11>" LOC = "R3" | IOSTANDARD = LVCMOS18 ; +NET "tx_codec_d*" DRIVE = 2; + +## Catalina Data RX + +NET "rx_codec_d<0>" LOC = "M1" | IOSTANDARD = LVCMOS18 ; +NET "rx_codec_d<1>" LOC = "K1" | IOSTANDARD = LVCMOS18 ; +NET "rx_codec_d<2>" LOC = "K2" | IOSTANDARD = LVCMOS18 ; +NET "rx_codec_d<3>" LOC = "G3" | IOSTANDARD = LVCMOS18 ; +NET "rx_codec_d<4>" LOC = "M2" | IOSTANDARD = LVCMOS18 ; +NET "rx_codec_d<5>" LOC = "J4" | IOSTANDARD = LVCMOS18 ; +NET "rx_codec_d<6>" LOC = "L3" | IOSTANDARD = LVCMOS18 ; +NET "rx_codec_d<7>" LOC = "H1" | IOSTANDARD = LVCMOS18 ; +NET "rx_codec_d<8>" LOC = "L4" | IOSTANDARD = LVCMOS18 ; +NET "rx_codec_d<9>" LOC = "G1" | IOSTANDARD = LVCMOS18 ; +NET "rx_codec_d<10>" LOC = "N3" | IOSTANDARD = LVCMOS18 ; +NET "rx_codec_d<11>" LOC = "M4" | IOSTANDARD = LVCMOS18 ; +NET "rx_codec_d*" DRIVE = 2; + +## Catalina Clocks + +NET "cat_clkout_fpga" LOC = "J3" | IOSTANDARD = LVCMOS18; +NET "codec_data_clk_p" LOC = "K3" | IOSTANDARD = LVCMOS18; +NET "codec_fb_clk_p" LOC = "P3" | IOSTANDARD = LVCMOS18 | DRIVE = 2 ; +NET "codec_main_clk_p" LOC = "K5" | IOSTANDARD = LVDS_25; +NET "codec_main_clk_n" LOC = "K4" | IOSTANDARD = LVDS_25; + +NET "rx_frame_p" LOC = "U4" | IOSTANDARD = LVCMOS18; +NET "tx_frame_p" LOC = "T3" | IOSTANDARD = LVCMOS18 | DRIVE = 2 ; + +## Debug Bus + +NET "debug<0>" LOC = "D10" | IOSTANDARD = LVCMOS33 ; +NET "debug<1>" LOC = "D9" | IOSTANDARD = LVCMOS33 ; +NET "debug<2>" LOC = "A8" | IOSTANDARD = LVCMOS33 ; +NET "debug<3>" LOC = "B8" | IOSTANDARD = LVCMOS33 ; +NET "debug<4>" LOC = "C8" | IOSTANDARD = LVCMOS33 ; +NET "debug<5>" LOC = "D8" | IOSTANDARD = LVCMOS33 ; +NET "debug<6>" LOC = "A7" | IOSTANDARD = LVCMOS33 ; +NET "debug<7>" LOC = "D7" | IOSTANDARD = LVCMOS33 ; +NET "debug<8>" LOC = "A6" | IOSTANDARD = LVCMOS33 ; +NET "debug<9>" LOC = "B6" | IOSTANDARD = LVCMOS33 ; +NET "debug<10>" LOC = "C6" | IOSTANDARD = LVCMOS33 ; +NET "debug<11>" LOC = "D6" | IOSTANDARD = LVCMOS33 ; +NET "debug<12>" LOC = "A5" | IOSTANDARD = LVCMOS33 ; +NET "debug<13>" LOC = "A4" | IOSTANDARD = LVCMOS33 ; +NET "debug<14>" LOC = "C5" | IOSTANDARD = LVCMOS33 ; +NET "debug<15>" LOC = "A3" | IOSTANDARD = LVCMOS33 ; +NET "debug<16>" LOC = "A18" | IOSTANDARD = LVCMOS33 ; +NET "debug<17>" LOC = "B18" | IOSTANDARD = LVCMOS33 ; +NET "debug<18>" LOC = "A17" | IOSTANDARD = LVCMOS33 ; +NET "debug<19>" LOC = "C17" | IOSTANDARD = LVCMOS33 ; +NET "debug<20>" LOC = "C14" | IOSTANDARD = LVCMOS33 ; +NET "debug<21>" LOC = "D12" | IOSTANDARD = LVCMOS33 ; +NET "debug<22>" LOC = "C10" | IOSTANDARD = LVCMOS33 ; +NET "debug<23>" LOC = "F15" | IOSTANDARD = LVCMOS33 ; +NET "debug<24>" LOC = "E14" | IOSTANDARD = LVCMOS33 ; +NET "debug<25>" LOC = "F14" | IOSTANDARD = LVCMOS33 ; +NET "debug<26>" LOC = "H14" | IOSTANDARD = LVCMOS33 ; +NET "debug<27>" LOC = "D13" | IOSTANDARD = LVCMOS33 ; +NET "debug<28>" LOC = "F13" | IOSTANDARD = LVCMOS33 ; +NET "debug<29>" LOC = "G13" | IOSTANDARD = LVCMOS33 ; +NET "debug<30>" LOC = "E12" | IOSTANDARD = LVCMOS33 ; +NET "debug<31>" LOC = "H13" | IOSTANDARD = LVCMOS33 ; + +NET "debug_clk<0>" LOC = "A12" | IOSTANDARD = LVCMOS33 ; +NET "debug_clk<1>" LOC = "C12" | IOSTANDARD = LVCMOS33 ; + +NET "debug*" DRIVE = 2; + +## GPIF + +NET "IFCLK" LOC = "H21" | IOSTANDARD = LVCMOS18 ; +NET "FX3_EXTINT" LOC = "U20" | IOSTANDARD = LVCMOS18 ; + +NET "IFCLK" DRIVE = 8; +NET "IFCLK" SLEW = SLOW; + +NET "GPIF_CTL0" LOC = "P22" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_CTL1" LOC = "N22" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_CTL2" LOC = "AA18" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_CTL3" LOC = "AB18" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_CTL4" LOC = "P19" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_CTL5" LOC = "AA2" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_CTL6" LOC = "M22" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_CTL7" LOC = "AB19" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_CTL8" LOC = "M19" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_CTL9" LOC = "R20" | IOSTANDARD = LVCMOS18 ; +##GPIF_CTL10 is "FPGA_CFG_DONE", defined later. +NET "GPIF_CTL11" LOC = "M21" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_CTL12" LOC = "M20" | IOSTANDARD = LVCMOS18 ; + +NET "GPIF_D<0>" LOC = "T17" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<1>" LOC = "U14" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<2>" LOC = "U13" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<3>" LOC = "AA6" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<4>" LOC = "AB6" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<5>" LOC = "Y3" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<6>" LOC = "AB3" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<7>" LOC = "AA4" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<8>" LOC = "V20" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<9>" LOC = "AB2" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<10>" LOC = "V21" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<11>" LOC = "T22" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<12>" LOC = "U22" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<13>" LOC = "R22" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<14>" LOC = "AA12" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<15>" LOC = "AB12" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<16>" LOC = "Y13" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<17>" LOC = "N20" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<18>" LOC = "T21" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<19>" LOC = "K18" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<20>" LOC = "H22" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<21>" LOC = "J20" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<22>" LOC = "K19" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<23>" LOC = "L19" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<24>" LOC = "N19" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<25>" LOC = "K22" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<26>" LOC = "L22" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<27>" LOC = "L20" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<28>" LOC = "J22" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<29>" LOC = "K20" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<30>" LOC = "G22" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<31>" LOC = "F22" | IOSTANDARD = LVCMOS18 ; + +NET "GPIF_*" DRIVE = 2; +NET "GPIF_*" SLEW = SLOW; + +## GPS + +NET "gps_lock" LOC = "B14" | IOSTANDARD = LVCMOS33 ; +NET "gps_rxd" LOC = "A15" | IOSTANDARD = LVCMOS33 ; +NET "gps_txd" LOC = "A14" | IOSTANDARD = LVCMOS33 | PULLUP; +NET "gps_txd_nmea" LOC = "C15" | IOSTANDARD = LVCMOS33 | PULLUP ; + +## LEDS + +NET "LED_RX1" LOC = "C22" | IOSTANDARD = LVCMOS18 ; +NET "LED_RX2" LOC = "L15" | IOSTANDARD = LVCMOS18 ; +NET "LED_TXRX1_TX" LOC = "C20" | IOSTANDARD = LVCMOS18 ; +NET "LED_TXRX2_RX" LOC = "D21" | IOSTANDARD = LVCMOS18 ; +NET "LED_TXRX1_RX" LOC = "K16" | IOSTANDARD = LVCMOS18 ; +NET "LED_TXRX2_TX" LOC = "D22" | IOSTANDARD = LVCMOS18 ; + +## Misc Hardware Control +NET "ref_sel" LOC = "AA14" | IOSTANDARD = LVCMOS18 ; +NET "pll_lock" LOC = "AB10" | IOSTANDARD = LVCMOS18 ; +NET "AUX_PWR_ON" LOC = "B16" | IOSTANDARD = LVCMOS33 ; +#NET "RFUSE" LOC = "P15" | IOSTANDARD = LVCMOS33 ; + +## PPS + +NET "PPS_IN_EXT" LOC = "B10" | IOSTANDARD = LVCMOS33 ; +NET "PPS_IN_INT" LOC = "A10" | IOSTANDARD = LVCMOS33 ; + +## RF Hardware Control + +NET "SFDX1_RX" LOC = "A16" | IOSTANDARD = LVCMOS33 ; +NET "SFDX1_TX" LOC = "D14" | IOSTANDARD = LVCMOS33 ; +NET "SFDX2_RX" LOC = "C11" | IOSTANDARD = LVCMOS33 ; +NET "SFDX2_TX" LOC = "A11" | IOSTANDARD = LVCMOS33 ; +NET "SRX1_RX" LOC = "D15" | IOSTANDARD = LVCMOS33 ; +NET "SRX1_TX" LOC = "C16" | IOSTANDARD = LVCMOS33 ; +NET "SRX2_RX" LOC = "B12" | IOSTANDARD = LVCMOS33 ; +NET "SRX2_TX" LOC = "D11" | IOSTANDARD = LVCMOS33 ; +NET "tx_bandsel_a" LOC = "C13" | IOSTANDARD = LVCMOS33 ; +NET "tx_bandsel_b" LOC = "D17" | IOSTANDARD = LVCMOS33 ; +NET "tx_enable1" LOC = "Y4" | IOSTANDARD = LVCMOS18 ; +NET "tx_enable2" LOC = "R19" | IOSTANDARD = LVCMOS18 ; +NET "rx_bandsel_a" LOC = "C9" | IOSTANDARD = LVCMOS33 ; +NET "rx_bandsel_b" LOC = "A13" | IOSTANDARD = LVCMOS33 ; +NET "rx_bandsel_c" LOC = "E16" | IOSTANDARD = LVCMOS33 ; + +## FPGA Config Pins + +#NET "FPGA_CFG_INIT_B" LOC = "T6" | IOSTANDARD = LVCMOS18 ; +#NET "FPGA_CFG_DONE" LOC = "Y22" | IOSTANDARD = LVCMOS18 ; +#NET "FPGA_CFG_M0" LOC = "AA22" | IOSTANDARD = LVCMOS18 ; +#NET "FPGA_CFG_M1" LOC = "U15" | IOSTANDARD = LVCMOS18 ; +#NET "FPGA_CFG_PROG_B" LOC = "AA1" | IOSTANDARD = LVCMOS18 ; + +## Special Pins + +#NET "VFS" LOC = "P16" | IOSTANDARD = LVCMOS33 ; +#NET "TMS" LOC = "C18" | IOSTANDARD = LVCMOS33 ; +#NET "TDO" LOC = "A19" | IOSTANDARD = LVCMOS33 ; +#NET "TDI" LOC = "E18" | IOSTANDARD = LVCMOS33 ; +#NET "TCK" LOC = "G15" | IOSTANDARD = LVCMOS33 ; +#NET "GND" LOC = "N15" | IOSTANDARD = LVCMOS33 ; diff --git a/fpga/usrp3/top/b200/b200.v b/fpga/usrp3/top/b200/b200.v new file mode 100644 index 000000000..811842f32 --- /dev/null +++ b/fpga/usrp3/top/b200/b200.v @@ -0,0 +1,365 @@ +// +// Copyright 2013 Ettus Research LLC +// Copyright 2017 Ettus Research, a National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + + +/*********************************************************** + * B200 Module Declaration + **********************************************************/ +module b200 ( + // SPI Interfaces + output cat_ce, + input cat_miso, + output cat_mosi, + output cat_sclk, + + input fx3_ce, + output fx3_miso, + input fx3_mosi, + input fx3_sclk, + + output pll_ce, + output pll_mosi, + output pll_sclk, + + // UART + // By default these provide an FX3 UART console output. Under compile time control they can alternatively + // provide 2 (1.8V) GPIO pins which are logically bits [9:8] of the fp_gpio bus. + // Used as a UART RXD is an input and TXD an output electrically. + // input FPGA_RXD0, // These pins goto 3 pin 0.1" header on B2x0 and + // output FPGA_TXD0, // carry FX3 UART. + inout FPGA_RXD0, // These pins goto 3 pin 0.1" header J400 on B2x0 and + inout FPGA_TXD0, // carry FX3 UART. + + // Catalina Controls + output codec_enable, + output codec_en_agc, + output codec_reset, + output codec_sync, + output codec_txrx, + output [3:0] codec_ctrl_in, // These should be outputs + input [7:0] codec_ctrl_out, // MUST BE INPUT + + // Catalina Data + input codec_data_clk_p, // Clock from CAT (RX) + output codec_fb_clk_p, // Clock to CAT (TX) + input [11:0] rx_codec_d, + output [11:0] tx_codec_d, + input rx_frame_p, + output tx_frame_p, + + input cat_clkout_fpga, + + //always on 40MHz clock + input codec_main_clk_p, + input codec_main_clk_n, + + // Debug Bus + output [31:0] debug, + output [1:0] debug_clk, + + // GPIF, FX3 Slave FIFO + output IFCLK, // pclk + input FX3_EXTINT, + output GPIF_CTL0, // n_slcs + output GPIF_CTL1, // n_slwr + output GPIF_CTL2, // n_sloe + output GPIF_CTL3, // n_slrd + output GPIF_CTL7, // n_pktend + input GPIF_CTL4, // slfifo_flags[0] + input GPIF_CTL5, // slfifo_flags[1] + input GPIF_CTL6, // Serial settings bus from FX3. SDA + input GPIF_CTL8, // Serial settings bus from FX3. SCL + output GPIF_CTL11, // slfifo_addr[1] + output GPIF_CTL12, // slfifo_addr[0] + inout [31:0] GPIF_D, + input GPIF_CTL9, // global_reset + + // GPS + input gps_lock, + output gps_rxd, + input gps_txd, // FPGA has pullup for unpopulated GPS + input gps_txd_nmea, // FPGA has pullup for unpopulated GPS + + // LEDS + output LED_RX1, + output LED_RX2, + output LED_TXRX1_RX, + output LED_TXRX1_TX, + output LED_TXRX2_RX, + output LED_TXRX2_TX, + + // GPIO Header J504 - 10 pin 0.1" 3.3V. + // Only present on Rev6 and later boards...these pins unused on Rev5 and earlier. + // NOTE: These pins are allocated from complimentry pairs and could potentially be used + // as differential style I/O. + `ifdef TARGET_B210 + inout [7:0] fp_gpio, + `endif + // Misc Hardware Control + output ref_sel, + input pll_lock, + input FPGA_CFG_CS, // Driven by FX3 gpio. + input AUX_PWR_ON, // Driven by FX3 gpio. + + // PPS + input PPS_IN_EXT, + input PPS_IN_INT, + + // RF Hardware Control + output SFDX1_RX, + output SFDX1_TX, + output SFDX2_RX, + output SFDX2_TX, + output SRX1_RX, + output SRX1_TX, + output SRX2_RX, + output SRX2_TX, + output tx_bandsel_a, + output tx_bandsel_b, + output tx_enable1, + output tx_enable2, + output rx_bandsel_a, + output rx_bandsel_b, + output rx_bandsel_c + ); + + wire reset_global = GPIF_CTL9; + + /////////////////////////////////////////////////////////////////////// + // generate clocks from always on codec main clk + /////////////////////////////////////////////////////////////////////// + wire bus_clk, gpif_clk, radio_clk; + wire locked; + b200_clk_gen gen_clks + ( + .CLK_IN1_40_P(codec_main_clk_p), .CLK_IN1_40_N(codec_main_clk_n), + .CLK_OUT1_40_int(), .CLK_OUT2_100_gpif(gpif_clk), .CLK_OUT3_100_bus(), + .RESET(reset_global), .LOCKED(locked) + ); + + // Bus Clock and GPIF Clock both same 100MHz clock. + assign bus_clk = gpif_clk; + + + //hold-off logic for clocks ready + reg [15:0] clocks_ready_count; + reg clocks_ready; + always @(posedge bus_clk or posedge reset_global or negedge locked) begin + if (reset_global | !locked) begin + clocks_ready_count <= 16'b0; + clocks_ready <= 1'b0; + end + else if (!clocks_ready) begin + clocks_ready_count <= clocks_ready_count + 1'b1; + clocks_ready <= (clocks_ready_count == 16'hffff); + end + end + + /////////////////////////////////////////////////////////////////////// + // drive output clocks + /////////////////////////////////////////////////////////////////////// + wire [1:0] debug_clk_int; + //S6CLK2PIN S6CLK2PIN_dbg0 (.I(debug_clk_int[0]), .O(debug_clk[0])); + //S6CLK2PIN S6CLK2PIN_dbg1 (.I(debug_clk_int[1]), .O(debug_clk[1])); + assign debug_clk[1:0] = 2'b0; + S6CLK2PIN S6CLK2PIN_gpif (.I(gpif_clk), .O(IFCLK)); + + /////////////////////////////////////////////////////////////////////// + // Create sync reset signals + /////////////////////////////////////////////////////////////////////// + wire gpif_rst, bus_rst, radio_rst; + reset_sync gpif_sync(.clk(gpif_clk), .reset_in(!clocks_ready), .reset_out(gpif_rst)); + reset_sync bus_sync(.clk(bus_clk), .reset_in(!clocks_ready), .reset_out(bus_rst)); + reset_sync radio_sync(.clk(radio_clk), .reset_in(!clocks_ready), .reset_out(radio_rst)); + + /////////////////////////////////////////////////////////////////////// + // I/O + /////////////////////////////////////////////////////////////////////// + wire [31:0] rx_data0, rx_data1; + wire [31:0] tx_data0, tx_data1; + wire mimo; + + b200_io b200_io_i0 + ( + .reset(reset), + .mimo(mimo), + + // Baseband sample interface + .radio_clk(radio_clk), + + .rx_i0(rx_data0[31:20]), + .rx_q0(rx_data0[15:4]), + .rx_i1(rx_data1[31:20]), + .rx_q1(rx_data1[15:4]), + + .tx_i0(tx_data0[31:20]), + .tx_q0(tx_data0[15:4]), + .tx_i1(tx_data1[31:20]), + .tx_q1(tx_data1[15:4]), + + // Catalina interface + .rx_clk(codec_data_clk_p), + .rx_frame(rx_frame_p), + .rx_data(rx_codec_d), + + .tx_clk(codec_fb_clk_p), + .tx_frame(tx_frame_p), + .tx_data(tx_codec_d) + ); + + assign {rx_data0[19:16],rx_data0[3:0],rx_data1[19:16],rx_data1[3:0]} = 16'h0; + + /////////////////////////////////////////////////////////////////////// + // SPI connections + /////////////////////////////////////////////////////////////////////// + wire mosi, miso, sclk; + wire [7:0] sen; + + //AD9361 Slave + assign cat_ce = sen[0]; + assign cat_mosi = ~sen[0] & mosi; + assign cat_sclk = ~sen[0] & sclk; + assign miso = cat_miso; //PLL does not have a miso + + //ADF4001 Slave + assign pll_ce = sen[1]; + assign pll_mosi = ~sen[1] & mosi; + assign pll_sclk = ~sen[1] & sclk; + + //FX3 Master + //The following signals are routed to the FX3 and were used by an obsolete + //bit-banging SPI engine. + // fx3_ce, fx3_sclk, fx3_mosi + assign fx3_miso = 1'bZ; //Safe state because we cannot guarantee the + //direction of this pin in the FX3 + + /////////////////////////////////////////////////////////////////////// + // bus signals + /////////////////////////////////////////////////////////////////////// + wire [63:0] ctrl_tdata, resp_tdata, rx_tdata, tx_tdata; + wire ctrl_tlast, resp_tlast, rx_tlast, tx_tlast; + wire ctrl_tvalid, resp_tvalid, rx_tvalid, tx_tvalid; + wire ctrl_tready, resp_tready, rx_tready, tx_tready; + + + /////////////////////////////////////////////////////////////////////// + // frontend assignments + // Most B2x0's have frontends swapped (radio0 to FE2), but some hardware revisions do not. + // The ATR pins are mapped from radio to frontend here based on the swap_atr_n bit. + /////////////////////////////////////////////////////////////////////// + wire swap_atr_n; + wire [7:0] radio0_gpio, radio1_gpio; + reg [7:0] fe0_gpio, fe1_gpio; + always @(posedge radio_clk) begin //Registers in the IOB + fe0_gpio <= swap_atr_n ? radio1_gpio : radio0_gpio; + fe1_gpio <= swap_atr_n ? radio0_gpio : radio1_gpio; + end + assign {tx_enable1, SFDX1_RX, SFDX1_TX, SRX1_RX, SRX1_TX, LED_RX1, LED_TXRX1_RX, LED_TXRX1_TX} = fe0_gpio; + assign {tx_enable2, SFDX2_RX, SFDX2_TX, SRX2_RX, SRX2_TX, LED_RX2, LED_TXRX2_RX, LED_TXRX2_TX} = fe1_gpio; + + wire [31:0] misc_outs; reg [31:0] misc_outs_r; + + always @(posedge bus_clk) misc_outs_r <= misc_outs; //register misc ios to ease routing to flop + + wire codec_arst; + + assign { swap_atr_n, tx_bandsel_a, tx_bandsel_b, rx_bandsel_a, rx_bandsel_b, rx_bandsel_c, codec_arst, mimo, ref_sel } = misc_outs_r[8:0]; + + assign codec_ctrl_in = 4'b1; + assign codec_en_agc = 1'b1; + assign codec_txrx = 1'b1; + assign codec_enable = 1'b1; + assign codec_reset = ~codec_arst; // Codec Reset // RESETB // Operates active-low + assign codec_sync = 1'b0; + + /////////////////////////////////////////////////////////////////////// + // b200 core + /////////////////////////////////////////////////////////////////////// + wire [9:0] fp_gpio_in, fp_gpio_out, fp_gpio_ddr; + + b200_core #(.EXTRA_BUFF_SIZE(12)) b200_core + ( + .bus_clk(bus_clk), .bus_rst(bus_rst), + .tx_tdata(tx_tdata), .tx_tlast(tx_tlast), .tx_tvalid(tx_tvalid), .tx_tready(tx_tready), + .rx_tdata(rx_tdata), .rx_tlast(rx_tlast), .rx_tvalid(rx_tvalid), .rx_tready(rx_tready), + .ctrl_tdata(ctrl_tdata), .ctrl_tlast(ctrl_tlast), .ctrl_tvalid(ctrl_tvalid), .ctrl_tready(ctrl_tready), + .resp_tdata(resp_tdata), .resp_tlast(resp_tlast), .resp_tvalid(resp_tvalid), .resp_tready(resp_tready), + + .radio_clk(radio_clk), .radio_rst(radio_rst), + .rx0(rx_data0), .rx1(rx_data1), + .tx0(tx_data0), .tx1(tx_data1), + .fe0_gpio_out(radio0_gpio), .fe1_gpio_out(radio1_gpio), + .fp_gpio_in(fp_gpio_in), .fp_gpio_out(fp_gpio_out), .fp_gpio_ddr(fp_gpio_ddr), + + .pps_int(PPS_IN_INT), .pps_ext(PPS_IN_EXT), + + .rxd(gps_txd), .txd(gps_rxd), + .sclk(sclk), .sen(sen), .mosi(mosi), .miso(miso), + .rb_misc({31'b0, pll_lock}), .misc_outs(misc_outs), + + .debug_scl(GPIF_CTL8), .debug_sda(GPIF_CTL6), +`ifdef DEBUG_UART + .debug_txd(FPGA_TXD0), .debug_rxd(FPGA_RXD0), +`else + .debug_txd(), .debug_rxd(1'b0), +`endif + + .lock_signals(codec_ctrl_out[7:6]), + .debug() + ); + +`ifdef TARGET_B210 + `ifdef DEBUG_UART + gpio_atr_io #(.WIDTH(8)) gpio_atr_io_inst ( // B210 with UART + .clk(radio_clk), .gpio_pins(fp_gpio), + .gpio_ddr(fp_gpio_ddr[7:0]), .gpio_out(fp_gpio_out[7:0]), .gpio_in(fp_gpio_in[7:0]) + ); + assign fp_gpio_in[9:8] = 2'b00; + `else + gpio_atr_io #(.WIDTH(10)) gpio_atr_io_inst ( // B210 no UART + .clk(radio_clk), .gpio_pins({FPGA_RXD0, FPGA_TXD0, fp_gpio}), + .gpio_ddr(fp_gpio_ddr), .gpio_out(fp_gpio_out), .gpio_in(fp_gpio_in) + ); + `endif +`else + `ifdef DEBUG_UART + assign fp_gpio_in = 10'h000; // B200 with UART + `else + gpio_atr_io #(.WIDTH(2)) gpio_atr_io_inst ( // B200 no UART + .clk(radio_clk), .gpio_pins({FPGA_RXD0, FPGA_TXD0}), + .gpio_ddr(fp_gpio_ddr[9:8]), .gpio_out(fp_gpio_out[9:8]), .gpio_in(fp_gpio_in[9:8]) + ); + assign fp_gpio_in[7:0] = 8'h00; + `endif +`endif + + /////////////////////////////////////////////////////////////////////// + // GPIF2 + /////////////////////////////////////////////////////////////////////// + + gpif2_slave_fifo32 #(.DATA_RX_FIFO_SIZE(13), .DATA_TX_FIFO_SIZE(13)) slave_fifo32 + ( + .gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_enb(1'b1), + .gpif_ctl({GPIF_CTL8, GPIF_CTL6, GPIF_CTL5, GPIF_CTL4}), .fifoadr({GPIF_CTL11,GPIF_CTL12}), + .slwr(GPIF_CTL1), .sloe(GPIF_CTL2), .slcs(GPIF_CTL0), .slrd(GPIF_CTL3), .pktend(GPIF_CTL7), + .gpif_d(GPIF_D), + + .fifo_clk(bus_clk), .fifo_rst(bus_rst), + .tx_tdata(tx_tdata), .tx_tlast(tx_tlast), .tx_tvalid(tx_tvalid), .tx_tready(tx_tready), + .rx_tdata(rx_tdata), .rx_tlast(rx_tlast), .rx_tvalid(rx_tvalid), .rx_tready(rx_tready), + .ctrl_tdata(ctrl_tdata), .ctrl_tlast(ctrl_tlast), .ctrl_tvalid(ctrl_tvalid), .ctrl_tready(ctrl_tready), + .resp_tdata(resp_tdata), .resp_tlast(resp_tlast), .resp_tvalid(resp_tvalid), .resp_tready(resp_tready), + + .debug() + ); + + /////////////////////////////////////////////////////////////////////// + // Debug port + /////////////////////////////////////////////////////////////////////// + assign debug = 0; + +endmodule // B200 diff --git a/fpga/usrp3/top/b200/b200_core.v b/fpga/usrp3/top/b200/b200_core.v new file mode 100644 index 000000000..f03c5ea1f --- /dev/null +++ b/fpga/usrp3/top/b200/b200_core.v @@ -0,0 +1,423 @@ +// +// Copyright 2013 Ettus Research LLC +// Copyright 2017 Ettus Research, a National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + + +/*********************************************************** + * B200 Core Guts + **********************************************************/ +module b200_core +#( + parameter R0_CTRL_SID = 8'h10, + parameter R1_CTRL_SID = 8'h20, + parameter U0_CTRL_SID = 8'h30, + parameter L0_CTRL_SID = 8'h40, + parameter R0_DATA_SID = 8'h50, + parameter R1_DATA_SID = 8'h60, + parameter DEMUX_SID_MASK = 8'hf0, + parameter EXTRA_BUFF_SIZE = 0, + parameter RADIO_FIFO_SIZE = 11, + parameter SAMPLE_FIFO_SIZE = 11 + +) +( + //////////////////////////////////////////////////////////////////// + // bus interfaces + //////////////////////////////////////////////////////////////////// + input bus_clk, + input bus_rst, + + input [63:0] tx_tdata, input tx_tlast, input tx_tvalid, output tx_tready, + output [63:0] rx_tdata, output rx_tlast, output rx_tvalid, input rx_tready, + input [63:0] ctrl_tdata, input ctrl_tlast, input ctrl_tvalid, output ctrl_tready, + output [63:0] resp_tdata, output resp_tlast, output resp_tvalid, input resp_tready, + + //////////////////////////////////////////////////////////////////// + // radio interfaces + //////////////////////////////////////////////////////////////////// + input radio_clk, + input radio_rst, + + input [31:0] rx0, input [31:0] rx1, + output [31:0] tx0, output [31:0] tx1, + output [7:0] fe0_gpio_out, output [7:0] fe1_gpio_out, + input [9:0] fp_gpio_in, output [9:0] fp_gpio_out, output [9:0] fp_gpio_ddr, + input pps_int, input pps_ext, + + //////////////////////////////////////////////////////////////////// + // gpsdo uart + //////////////////////////////////////////////////////////////////// + input rxd, + output txd, + + //////////////////////////////////////////////////////////////////// + // core interfaces + //////////////////////////////////////////////////////////////////// + output [7:0] sen, output sclk, output mosi, input miso, + input [31:0] rb_misc, + output [31:0] misc_outs, + //////////////////////////////////////////////////////////////////// + // debug UART + //////////////////////////////////////////////////////////////////// + output debug_txd, input debug_rxd, + input debug_scl, input debug_sda, + + //////////////////////////////////////////////////////////////////// + // fe lock signals + //////////////////////////////////////////////////////////////////// + input [1:0] lock_signals, + + //////////////////////////////////////////////////////////////////// + // debug signals + //////////////////////////////////////////////////////////////////// + output [63:0] debug +); + localparam SR_CORE_SPI = 8'd8; + localparam SR_CORE_MISC = 8'd16; + localparam SR_CORE_COMPAT = 8'd24; + localparam SR_CORE_READBACK = 8'd32; + localparam SR_CORE_GPSDO_ST = 8'd40; + localparam SR_CORE_SYNC = 8'd48; + localparam COMPAT_MAJOR = 16'h0010; + localparam COMPAT_MINOR = 16'h0000; + + reg [1:0] lock_state; + reg [1:0] lock_state_r; + + always @(posedge bus_clk) + if (bus_rst) + {lock_state_r, lock_state} <= 4'h0; + else + {lock_state_r, lock_state} <= {lock_state, lock_signals}; + + + /******************************************************************* + * PPS Timing stuff + ******************************************************************/ + + // Generate an internal PPS signal + wire int_pps; + pps_generator #(.CLK_FREQ(100000000)) pps_gen + (.clk(bus_clk), .reset(1'b0), .pps(int_pps)); + + // Flop PPS signals into radio clock domain + reg [1:0] gpsdo_pps_del, ext_pps_del, int_pps_del; + always @(posedge radio_clk) ext_pps_del[1:0] <= {ext_pps_del[0], pps_ext}; + always @(posedge radio_clk) gpsdo_pps_del[1:0] <= {gpsdo_pps_del[0], pps_int}; + always @(posedge radio_clk) int_pps_del[1:0] <= {int_pps_del[0], int_pps}; + + // PPS mux + wire [1:0] pps_select; + wire pps = (pps_select == 2'b00)? gpsdo_pps_del[1] : + (pps_select == 2'b01)? ext_pps_del[1] : + (pps_select == 2'b10)? int_pps_del[1] : + 1'b0; + + /******************************************************************* + * Response mux Routing logic + ******************************************************************/ + wire [63:0] r0_resp_tdata; wire r0_resp_tlast, r0_resp_tvalid, r0_resp_tready; + wire [63:0] r1_resp_tdata; wire r1_resp_tlast, r1_resp_tvalid, r1_resp_tready; + wire [63:0] u0_resp_tdata; wire u0_resp_tlast, u0_resp_tvalid, u0_resp_tready; + wire [63:0] l0_resp_tdata; wire l0_resp_tlast, l0_resp_tvalid, l0_resp_tready; + + axi_mux4 #(.WIDTH(64), .BUFFER(1)) mux_for_resp + (.clk(bus_clk), .reset(bus_rst), .clear(1'b0), + .i0_tdata(r0_resp_tdata), .i0_tlast(r0_resp_tlast), .i0_tvalid(r0_resp_tvalid), .i0_tready(r0_resp_tready), + .i1_tdata(r1_resp_tdata), .i1_tlast(r1_resp_tlast), .i1_tvalid(r1_resp_tvalid), .i1_tready(r1_resp_tready), + .i2_tdata(u0_resp_tdata), .i2_tlast(u0_resp_tlast), .i2_tvalid(u0_resp_tvalid), .i2_tready(u0_resp_tready), + .i3_tdata(l0_resp_tdata), .i3_tlast(l0_resp_tlast), .i3_tvalid(l0_resp_tvalid), .i3_tready(l0_resp_tready), + .o_tdata(resp_tdata), .o_tlast(resp_tlast), .o_tvalid(resp_tvalid), .o_tready(resp_tready)); + + /******************************************************************* + * Control demux Routing logic + ******************************************************************/ + wire [63:0] r0_ctrl_tdata; wire r0_ctrl_tlast, r0_ctrl_tvalid, r0_ctrl_tready; + wire [63:0] r1_ctrl_tdata; wire r1_ctrl_tlast, r1_ctrl_tvalid, r1_ctrl_tready; + wire [63:0] u0_ctrl_tdata; wire u0_ctrl_tlast, u0_ctrl_tvalid, u0_ctrl_tready; + wire [63:0] l0_ctrl_tdata; wire l0_ctrl_tlast, l0_ctrl_tvalid, l0_ctrl_tready; + + wire [63:0] ctrl_hdr; + wire [1:0] ctrl_dst = + ((ctrl_hdr[7:0] & DEMUX_SID_MASK) == R0_CTRL_SID)? 0 : ( + ((ctrl_hdr[7:0] & DEMUX_SID_MASK) == R1_CTRL_SID)? 1 : ( + ((ctrl_hdr[7:0] & DEMUX_SID_MASK) == U0_CTRL_SID)? 2 : ( + ((ctrl_hdr[7:0] & DEMUX_SID_MASK) == L0_CTRL_SID)? 3 : ( + 3)))); + axi_demux4 #(.ACTIVE_CHAN(4'b1111), .WIDTH(64), .BUFFER(1)) demux_for_ctrl + (.clk(bus_clk), .reset(bus_rst), .clear(1'b0), + .header(ctrl_hdr), .dest(ctrl_dst), + .i_tdata(ctrl_tdata), .i_tlast(ctrl_tlast), .i_tvalid(ctrl_tvalid), .i_tready(ctrl_tready), + .o0_tdata(r0_ctrl_tdata), .o0_tlast(r0_ctrl_tlast), .o0_tvalid(r0_ctrl_tvalid), .o0_tready(r0_ctrl_tready), + .o1_tdata(r1_ctrl_tdata), .o1_tlast(r1_ctrl_tlast), .o1_tvalid(r1_ctrl_tvalid), .o1_tready(r1_ctrl_tready), + .o2_tdata(u0_ctrl_tdata), .o2_tlast(u0_ctrl_tlast), .o2_tvalid(u0_ctrl_tvalid), .o2_tready(u0_ctrl_tready), + .o3_tdata(l0_ctrl_tdata), .o3_tlast(l0_ctrl_tlast), .o3_tvalid(l0_ctrl_tvalid), .o3_tready(l0_ctrl_tready)); + + /******************************************************************* + * UART + ******************************************************************/ + wire [63:0] u0i_ctrl_tdata; wire u0i_ctrl_tlast, u0i_ctrl_tvalid, u0i_ctrl_tready; + + axi_fifo #(.WIDTH(65), .SIZE(5)) uart_timing_fifo + ( + .clk(bus_clk), .reset(bus_rst), .clear(1'b0), + .i_tdata({u0_ctrl_tlast, u0_ctrl_tdata}), .i_tvalid(u0_ctrl_tvalid), .i_tready(u0_ctrl_tready), .space(), + .o_tdata({u0i_ctrl_tlast, u0i_ctrl_tdata}), .o_tvalid(u0i_ctrl_tvalid), .o_tready(u0i_ctrl_tready), .occupied() + ); + + cvita_uart #(.SIZE(7)) uart + ( + .clk(bus_clk), .rst(bus_rst), .rxd(rxd), .txd(txd), + .i_tdata(u0i_ctrl_tdata), .i_tlast(u0i_ctrl_tlast), .i_tvalid(u0i_ctrl_tvalid), .i_tready(u0i_ctrl_tready), + .o_tdata(u0_resp_tdata), .o_tlast(u0_resp_tlast), .o_tvalid(u0_resp_tvalid), .o_tready(u0_resp_tready) + ); + + /******************************************************************* + * Misc controls + ******************************************************************/ + wire set_stb; + wire [7:0] set_addr; + wire [31:0] set_data; + + wire spi_ready; + wire [31:0] spi_readback; + + wire [7:0] gpsdo_st; + wire [7:0] radio_st; + + wire [1:0] rb_addr; + reg [63:0] rb_data; + + wire [63:0] l0i_ctrl_tdata; wire l0i_ctrl_tlast, l0i_ctrl_tvalid, l0i_ctrl_tready; + + wire time_sync, time_sync_r; + + axi_fifo #(.WIDTH(65), .SIZE(5)) radio_ctrl_proc_timing_fifo + ( + .clk(bus_clk), .reset(bus_rst), .clear(1'b0), + .i_tdata({l0_ctrl_tlast, l0_ctrl_tdata}), .i_tvalid(l0_ctrl_tvalid), .i_tready(l0_ctrl_tready), .space(), + .o_tdata({l0i_ctrl_tlast, l0i_ctrl_tdata}), .o_tvalid(l0i_ctrl_tvalid), .o_tready(l0i_ctrl_tready), .occupied() + ); + + radio_ctrl_proc radio_ctrl_proc + (.clk(bus_clk), .reset(bus_rst), .clear(1'b0), + .ctrl_tdata(l0i_ctrl_tdata), .ctrl_tlast(l0i_ctrl_tlast), .ctrl_tvalid(l0i_ctrl_tvalid), .ctrl_tready(l0i_ctrl_tready), + .resp_tdata(l0_resp_tdata), .resp_tlast(l0_resp_tlast), .resp_tvalid(l0_resp_tvalid), .resp_tready(l0_resp_tready), + .vita_time(64'b0), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .ready(spi_ready), .readback(rb_data), + .debug()); + + setting_reg #(.my_addr(SR_CORE_MISC), .awidth(8), .width(32), .at_reset(8'h0)) sr_misc + (.clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data), + .out(misc_outs), .changed()); + + setting_reg #(.my_addr(SR_CORE_READBACK), .awidth(8), .width(2)) sr_rdback + (.clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data), + .out(rb_addr), .changed()); + + setting_reg #(.my_addr(SR_CORE_GPSDO_ST), .awidth(8), .width(8)) sr_gpsdo_st + (.clk(bus_clk), .rst(1'b0/*keep*/), .strobe(set_stb), .addr(set_addr), .in(set_data), + .out(gpsdo_st), .changed()); + + setting_reg #(.my_addr(SR_CORE_SYNC), .awidth(8), .width(3)) sr_sync + (.clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data), + .out({time_sync,pps_select}), .changed()); + + synchronizer time_sync_synchronizer + (.clk(radio_clk), .rst(radio_rst), .in(time_sync), .out(time_sync_r)); + + simple_spi_core #(.BASE(SR_CORE_SPI), .WIDTH(8), .CLK_IDLE(0), .SEN_IDLE(8'hFF)) misc_spi + (.clock(bus_clk), .reset(bus_rst), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .readback(spi_readback), .ready(spi_ready), + .sen(sen), .sclk(sclk), .mosi(mosi), .miso(miso), + .debug()); + + always @* + case(rb_addr) + 2'd0 : rb_data <= { 32'hACE0BA5E, COMPAT_MAJOR, COMPAT_MINOR }; + 2'd1 : rb_data <= { 32'b0, spi_readback }; + 2'd2 : rb_data <= { 16'b0, radio_st, gpsdo_st, rb_misc }; + 2'd3 : rb_data <= { 30'h0, lock_state_r }; + default : rb_data <= 64'd0; + endcase // case (rb_addr) + + /******************************************************************* + * RX Data mux Routing logic + ******************************************************************/ + wire [63:0] r0_rx_tdata; wire r0_rx_tlast, r0_rx_tvalid, r0_rx_tready; + wire [63:0] r1_rx_tdata; wire r1_rx_tlast, r1_rx_tvalid, r1_rx_tready; + wire [63:0] rx_tdata_int; wire rx_tlast_int, rx_tvalid_int, rx_tready_int; + + axi_mux4 #(.WIDTH(64), .BUFFER(1)) mux_for_rx + (.clk(bus_clk), .reset(bus_rst), .clear(1'b0), + .i0_tdata(r0_rx_tdata), .i0_tlast(r0_rx_tlast), .i0_tvalid(r0_rx_tvalid), .i0_tready(r0_rx_tready), + .i1_tdata(r1_rx_tdata), .i1_tlast(r1_rx_tlast), .i1_tvalid(r1_rx_tvalid), .i1_tready(r1_rx_tready), + .i2_tdata(64'b0), .i2_tlast(1'b0), .i2_tvalid(1'b0), .i2_tready(), + .i3_tdata(64'b0), .i3_tlast(1'b0), .i3_tvalid(1'b0), .i3_tready(), + .o_tdata(rx_tdata_int), .o_tlast(rx_tlast_int), .o_tvalid(rx_tvalid_int), .o_tready(rx_tready_int)); + + axi_fifo #(.WIDTH(65), .SIZE(EXTRA_BUFF_SIZE)) extra_rx_buff + (.clk(bus_clk), .reset(bus_rst),.clear(1'b0), + .i_tdata({rx_tlast_int, rx_tdata_int}), .i_tvalid(rx_tvalid_int), .i_tready(rx_tready_int), + .o_tdata({rx_tlast, rx_tdata}), .o_tvalid(rx_tvalid), .o_tready(rx_tready)); + + /******************************************************************* + * TX Data mux Routing logic + ******************************************************************/ + wire [63:0] r0_tx_tdata; wire r0_tx_tlast, r0_tx_tvalid, r0_tx_tready; + wire [63:0] r1_tx_tdata; wire r1_tx_tlast, r1_tx_tvalid, r1_tx_tready; + wire [63:0] tx_tdata_int; wire tx_tlast_int, tx_tvalid_int, tx_tready_int; + + axi_fifo #(.WIDTH(65), .SIZE(EXTRA_BUFF_SIZE)) extra_tx_buff + (.clk(bus_clk), .reset(bus_rst),.clear(1'b0), + .i_tdata({tx_tlast, tx_tdata}), .i_tvalid(tx_tvalid), .i_tready(tx_tready), + .o_tdata({tx_tlast_int, tx_tdata_int}), .o_tvalid(tx_tvalid_int), .o_tready(tx_tready_int)); + + wire [63:0] tx_hdr; + wire [1:0] tx_dst = + ((tx_hdr[7:0] & DEMUX_SID_MASK) == R0_DATA_SID)? 0 : ( + ((tx_hdr[7:0] & DEMUX_SID_MASK) == R1_DATA_SID)? 1 : ( + 3)); + axi_demux4 #(.ACTIVE_CHAN(4'b0011), .WIDTH(64), .BUFFER(1)) demux_for_tx + (.clk(bus_clk), .reset(bus_rst), .clear(1'b0), + .header(tx_hdr), .dest(tx_dst), + .i_tdata(tx_tdata_int), .i_tlast(tx_tlast_int), .i_tvalid(tx_tvalid_int), .i_tready(tx_tready_int), + .o0_tdata(r0_tx_tdata), .o0_tlast(r0_tx_tlast), .o0_tvalid(r0_tx_tvalid), .o0_tready(r0_tx_tready), + .o1_tdata(r1_tx_tdata), .o1_tlast(r1_tx_tlast), .o1_tvalid(r1_tx_tvalid), .o1_tready(r1_tx_tready), + .o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b1), + .o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b1)); + + /******************************************************************* + * Radio 0 + ******************************************************************/ + wire [63:0] radio0_debug; + wire [31:0] fe0_gpio_out32; + assign fe0_gpio_out = fe0_gpio_out32[7:0]; + + radio_legacy #( + .RADIO_FIFO_SIZE(RADIO_FIFO_SIZE), + .SAMPLE_FIFO_SIZE(SAMPLE_FIFO_SIZE), + .FP_GPIO(1), + .NEW_HB_INTERP(1), + .NEW_HB_DECIM(1), + .SOURCE_FLOW_CONTROL(0), + .USER_SETTINGS(0), + .DEVICE("SPARTAN6") + ) radio_0 ( + .radio_clk(radio_clk), .radio_rst(radio_rst), + .rx(rx0), .tx(tx0), .pps(pps), .time_sync(time_sync_r), + .fe_gpio_in(32'h00000000), .fe_gpio_out(fe0_gpio_out32), .fe_gpio_ddr(/* Always assumed to be outputs */), + .fp_gpio_in(fp_gpio_in), .fp_gpio_out(fp_gpio_out), .fp_gpio_ddr(fp_gpio_ddr), + .bus_clk(bus_clk), .bus_rst(bus_rst), + .tx_tdata(r0_tx_tdata), .tx_tlast(r0_tx_tlast), .tx_tvalid(r0_tx_tvalid), .tx_tready(r0_tx_tready), + .rx_tdata(r0_rx_tdata), .rx_tlast(r0_rx_tlast), .rx_tvalid(r0_rx_tvalid), .rx_tready(r0_rx_tready), + .ctrl_tdata(r0_ctrl_tdata), .ctrl_tlast(r0_ctrl_tlast), .ctrl_tvalid(r0_ctrl_tvalid), .ctrl_tready(r0_ctrl_tready), + .resp_tdata(r0_resp_tdata), .resp_tlast(r0_resp_tlast), .resp_tvalid(r0_resp_tvalid), .resp_tready(r0_resp_tready), + .debug(radio0_debug) + ); + + /******************************************************************* + * Radio 1 + ******************************************************************/ +`ifdef TARGET_B210 // B210 Has two radio instances. + assign radio_st = 8'h2; + + wire [63:0] radio1_debug; + wire [31:0] fe1_gpio_out32; + assign fe1_gpio_out = fe1_gpio_out32[7:0]; + + radio_legacy #( + .RADIO_FIFO_SIZE(RADIO_FIFO_SIZE), + .SAMPLE_FIFO_SIZE(SAMPLE_FIFO_SIZE), + .FP_GPIO(0), + .NEW_HB_INTERP(1), + .NEW_HB_DECIM(1), + .SOURCE_FLOW_CONTROL(0), + .USER_SETTINGS(0), + .DEVICE("SPARTAN6") + ) radio_1 ( + .radio_clk(radio_clk), .radio_rst(radio_rst), + .rx(rx1), .tx(tx1), .pps(pps), .time_sync(time_sync_r), + .fe_gpio_in(32'h00000000), .fe_gpio_out(fe1_gpio_out32), .fe_gpio_ddr(/* Always assumed to be outputs */), + .fp_gpio_in(32'h00000000), .fp_gpio_out(), .fp_gpio_ddr(), + .bus_clk(bus_clk), .bus_rst(bus_rst), + .tx_tdata(r1_tx_tdata), .tx_tlast(r1_tx_tlast), .tx_tvalid(r1_tx_tvalid), .tx_tready(r1_tx_tready), + .rx_tdata(r1_rx_tdata), .rx_tlast(r1_rx_tlast), .rx_tvalid(r1_rx_tvalid), .rx_tready(r1_rx_tready), + .ctrl_tdata(r1_ctrl_tdata), .ctrl_tlast(r1_ctrl_tlast), .ctrl_tvalid(r1_ctrl_tvalid), .ctrl_tready(r1_ctrl_tready), + .resp_tdata(r1_resp_tdata), .resp_tlast(r1_resp_tlast), .resp_tvalid(r1_resp_tvalid), .resp_tready(r1_resp_tready), + .debug(radio1_debug) + ); +`else + assign radio_st = 8'h1; + + //assign undriven outputs + assign fe1_gpio_out = 32'b0; //Always assumed to be outputs + assign tx1 = 32'b0; + + //unused control signals -- leave in loopback + assign r1_resp_tdata = r1_ctrl_tdata; + assign r1_resp_tlast = r1_ctrl_tlast; + assign r1_resp_tvalid = r1_ctrl_tvalid; + assign r1_ctrl_tready = r1_resp_tready; + + //unused data signals -- leave in loopback + assign r1_rx_tdata = r1_tx_tdata; + assign r1_rx_tlast = r1_tx_tlast; + assign r1_rx_tvalid = r1_tx_tvalid; + assign r1_tx_tready = r1_tx_tready; + +`endif // !`ifdef TARGET_B210 + + /******************************************************************* + * Debug UART for FX3 + ******************************************************************/ + + wire debug_stb; + wire [31:0] debug_data; + wire [7:0] debug_addr; + wire [31:0] debug_serial; + + + serial_to_settings serial_to_settings_i1 + ( + .clk(bus_clk), + .reset(bus_rst), + .scl(debug_scl), + .sda(debug_sda), + .set_stb(debug_stb), + .set_addr(debug_addr), + .set_data(debug_data), + .debug(debug_serial) + ); + + // Nasty Hack to convert settings to wishbone crudely. + reg wb_stb; + wire wb_ack_o; + + always @(posedge bus_clk) + wb_stb <= debug_stb ? 1 : ((wb_ack_o) ? 0 : wb_stb); + + simple_uart debug_uart + ( + .clk_i(bus_clk), + .rst_i(bus_rst), + .we_i(wb_stb), + .stb_i(wb_stb), + .cyc_i(wb_stb), + .ack_o(wb_ack_o), + .adr_i(debug_addr[2:0]), + .dat_i(debug_data[31:0]), + .dat_o(), + .rx_int_o(), + .tx_int_o(), + .tx_o(debug_txd), + .rx_i(debug_rxd), + .baud_o() + ); + +endmodule // b200_core diff --git a/fpga/usrp3/top/b200/b200_io.v b/fpga/usrp3/top/b200/b200_io.v new file mode 100644 index 000000000..1c6ea2dc9 --- /dev/null +++ b/fpga/usrp3/top/b200/b200_io.v @@ -0,0 +1,554 @@ +// +// Copyright 2013 Ettus Research LLC +// Copyright 2017 Ettus Research, a National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// +//------------------------------------------------------------------ +// +// In SISO mode, we output a clock thats 1x the frequency of the Catalina +// source-synchronous bus clock to be used as the radio_clk. +// In MIMO mode, we output a clock thats 1/2 the frequency of the Catalina +// source-synchronous bus clock to be used as the radio_clk. +// +//------------------------------------------------------------------ + +module b200_io + ( + input reset, + input mimo, + + // Baseband sample interface + output radio_clk, + output [11:0] rx_i0, + output [11:0] rx_q0, + output [11:0] rx_i1, + output [11:0] rx_q1, + input [11:0] tx_i0, + input [11:0] tx_q0, + input [11:0] tx_i1, + input [11:0] tx_q1, + + // Catalina interface + input rx_clk, + input rx_frame, + input [11:0] rx_data, + output tx_clk, + output tx_frame, + output [11:0] tx_data + ); + + + genvar z; + + //------------------------------------------------------------------ + // + // Synchronize MIMO signal from bus_clk to siso_clk. + // + //------------------------------------------------------------------ + reg mimo_sync, mimo_sync2; + + always @(posedge siso_clk) begin + mimo_sync <= mimo_sync2; + mimo_sync2 <= mimo; + end + + + //------------------------------------------------------------------ + // Clock Buffering. + // BUFIO2 drives all IDDR2 and ODDR2 cells directly in bank3. + // Need two pairs of BUFIO2 one pair each for Top Left and Bottom Left half banks. + //------------------------------------------------------------------ + wire rx_clk_buf; + wire mimo_clk_unbuf; + wire siso_clk_unbuf; + wire siso2_clk_unbuf; + + IBUFG clk_ibufg (.O(rx_clk_buf), .I(rx_clk)); + + //------------------------------------------------------------------ + // + // Buffers for LEFT TOP half bank pins + // BUFIO2_X0Y22 + // + //------------------------------------------------------------------ + BUFIO2 #( + .DIVIDE(4), + .DIVIDE_BYPASS("FALSE"), + .I_INVERT("FALSE"), + .USE_DOUBLER("TRUE")) + clk_bufio_lt + ( + .IOCLK(io_clk_lt), + .DIVCLK(mimo_clk_unbuf), // Non-inverted source of 1/2x interface clock for radio_clk + .SERDESSTROBE(), + .I(rx_clk_buf) + ); + + // BUFIO2_X0Y23 + BUFIO2 #( + .DIVIDE(1), + .DIVIDE_BYPASS("FALSE"), + .I_INVERT("TRUE"), + .USE_DOUBLER("FALSE")) + clk_bufio_lt_b + ( + .IOCLK(io_clk_lt_b), + .DIVCLK(siso_clk2_unbuf), // Inverted source of 1x interface clock for radio_clk + .SERDESSTROBE(), + .I(rx_clk_buf) + ); + + //------------------------------------------------------------------ + // + // Buffers for LEFT BOTTOM half bank pins + // BUFIO2_X1Y14 + // + //------------------------------------------------------------------ + BUFIO2 #( + .DIVIDE(1), + .DIVIDE_BYPASS("FALSE"), + .I_INVERT("FALSE"), + .USE_DOUBLER("FALSE")) + clk_bufio_lb + ( + .IOCLK(io_clk_lb), + .DIVCLK(siso_clk_unbuf), // Non-inverted source of 1x interface clock for local IO use + .SERDESSTROBE(), + .I(rx_clk_buf) + ); + + // BUFIO2_X1Y15 + BUFIO2 #( + .DIVIDE(1), + .DIVIDE_BYPASS("FALSE"), + .I_INVERT("TRUE"), + .USE_DOUBLER("FALSE")) + clk_bufio_lb_b + ( + .IOCLK(io_clk_lb_b), + .DIVCLK(), + .SERDESSTROBE(), + .I(rx_clk_buf) + ); + + //------------------------------------------------------------------ + // Always-on SISO clk needed to load/unload DDR2 I/O Regs + //------------------------------------------------------------------ + BUFG siso_clk_bufg ( + .I(siso_clk_unbuf), + .O(siso_clk) + ); + + //------------------------------------------------------------------ + // 2-1 mux combined with BUFG to drive global radio_clk. + // Note: Not addressed setup/hold constraints of S input ...unsure if anything "bad" can happen here. + //------------------------------------------------------------------ + BUFGMUX #( + .CLK_SEL_TYPE("SYNC")) + radio_clk_bufg ( + .I0(siso_clk2_unbuf), + .I1(mimo_clk_unbuf), + .S(mimo_sync), + .O(radio_clk) + ); + + //------------------------------------------------------------------ + // RX Frame Signal - In bank 3 LB + //------------------------------------------------------------------ + wire rx_frame_0, rx_frame_1; + + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_frame ( + .Q0(rx_frame_1), + .Q1(rx_frame_0), + .C0(io_clk_lb), + .C1(io_clk_lb_b), + .CE(1'b1), + .D(rx_frame), + .R(1'b0), + .S(1'b0)); + + reg rx_frame_d1, rx_frame_d2; + always @(posedge siso_clk) + if(~mimo_sync) + { rx_frame_d2, rx_frame_d1 } <= { rx_frame_1, 1'b0 }; + else + { rx_frame_d2, rx_frame_d1 } <= { rx_frame_d1, rx_frame_1 }; + + //------------------------------------------------------------------ + // RX Data Bus - In bank3 both LT and LB + //------------------------------------------------------------------ + wire [11:0] rx_i,rx_q; + + // Bit0 LB + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i0 ( + .Q0(rx_q[0]), + .Q1(rx_i[0]), + .C0(io_clk_lb), + .C1(io_clk_lb_b), + .CE(1'b1), + .D(rx_data[0]), + .R(1'b0), + .S(1'b0)); + + // Bit1 LB + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i1 ( + .Q0(rx_q[1]), + .Q1(rx_i[1]), + .C0(io_clk_lb), + .C1(io_clk_lb_b), + .CE(1'b1), + .D(rx_data[1]), + .R(1'b0), + .S(1'b0)); + + // Bit2 LB + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i2 ( + .Q0(rx_q[2]), + .Q1(rx_i[2]), + .C0(io_clk_lb), + .C1(io_clk_lb_b), + .CE(1'b1), + .D(rx_data[2]), + .R(1'b0), + .S(1'b0)); + + // Bit3 LT + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i3 ( + .Q0(rx_q[3]), + .Q1(rx_i[3]), + .C0(io_clk_lt), + .C1(io_clk_lt_b), + .CE(1'b1), + .D(rx_data[3]), + .R(1'b0), + .S(1'b0)); + + // Bit4 LB + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i4 ( + .Q0(rx_q[4]), + .Q1(rx_i[4]), + .C0(io_clk_lb), + .C1(io_clk_lb_b), + .CE(1'b1), + .D(rx_data[4]), + .R(1'b0), + .S(1'b0)); + + // Bit5 LT + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i5 ( + .Q0(rx_q[5]), + .Q1(rx_i[5]), + .C0(io_clk_lt), + .C1(io_clk_lt_b), + .CE(1'b1), + .D(rx_data[5]), + .R(1'b0), + .S(1'b0)); + + // Bit6 LB + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i6 ( + .Q0(rx_q[6]), + .Q1(rx_i[6]), + .C0(io_clk_lb), + .C1(io_clk_lb_b), + .CE(1'b1), + .D(rx_data[6]), + .R(1'b0), + .S(1'b0)); + + // Bit7 LT + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i7 ( + .Q0(rx_q[7]), + .Q1(rx_i[7]), + .C0(io_clk_lt), + .C1(io_clk_lt_b), + .CE(1'b1), + .D(rx_data[7]), + .R(1'b0), + .S(1'b0)); + + // Bit8 LB + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i8 ( + .Q0(rx_q[8]), + .Q1(rx_i[8]), + .C0(io_clk_lb), + .C1(io_clk_lb_b), + .CE(1'b1), + .D(rx_data[8]), + .R(1'b0), + .S(1'b0)); + + // Bit9 LT + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i9 ( + .Q0(rx_q[9]), + .Q1(rx_i[9]), + .C0(io_clk_lt), + .C1(io_clk_lt_b), + .CE(1'b1), + .D(rx_data[9]), + .R(1'b0), + .S(1'b0)); + + // Bit10 LB + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i10 ( + .Q0(rx_q[10]), + .Q1(rx_i[10]), + .C0(io_clk_lb), + .C1(io_clk_lb_b), + .CE(1'b1), + .D(rx_data[10]), + .R(1'b0), + .S(1'b0)); + + // Bit11 LB + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i11 ( + .Q0(rx_q[11]), + .Q1(rx_i[11]), + .C0(io_clk_lb), + .C1(io_clk_lb_b), + .CE(1'b1), + .D(rx_data[11]), + .R(1'b0), + .S(1'b0)); + + //------------------------------------------------------------------ + // + // De-mux I & Q, Ch A & B onto fullrate clock. + // + // In all modes we grab data from the IDDR2 using negedge of siso_clk. + // IDDR2 updates all Q pins on posedge of io_clk. siso_clk does not have aligned phase + // with siso_clk...siso_clk is always a little more delayed than io_clk. + // This small delay is always much smaller than half a clk cycle. Thus by sampling the Q outputs + // with negedge siso_clk we avoid any risk of a race condition (hold violation on receiveing register). + // + // In SISO mode data is replicated onto both CH0 and CH1 for max flexibility in using the DDC's. + // + //------------------------------------------------------------------ + reg [11:0] rx_i_del, rx_q_del; + reg [11:0] rx_i0_siso_pos; + reg [11:0] rx_q0_siso_pos; + reg [11:0] rx_i1_siso_pos; + reg [11:0] rx_q1_siso_pos; + reg [11:0] rx_i0_siso_neg; + reg [11:0] rx_q0_siso_neg; + reg [11:0] rx_i1_siso_neg; + reg [11:0] rx_q1_siso_neg; + reg [11:0] rx_i0_siso; + reg [11:0] rx_q0_siso; + reg [11:0] rx_i1_siso; + reg [11:0] rx_q1_siso; + + + always @(negedge siso_clk) + if(mimo_sync) + // rx_frame_0 was sampled by same falling io_clk edge as rx_i[x] + // rx_frame_0 == 0 causes I & Q to be allocated to CH0 + if(rx_frame_0) begin + rx_i_del[11:0] <= rx_i[11:0]; + rx_q_del[11:0] <= rx_q[11:0]; + end + else begin + // Deal with the fact that Ch A and Ch B are labelled in silkscreen opposite to their documentation in AD9361. + rx_i0_siso[11:0] <= rx_i[11:0]; + rx_q0_siso[11:0] <= rx_q[11:0]; + rx_i1_siso[11:0] <= rx_i_del[11:0]; + rx_q1_siso[11:0] <= rx_q_del[11:0]; + end + else begin + rx_i0_siso[11:0] <= rx_i[11:0]; + rx_q0_siso[11:0] <= rx_q[11:0]; + rx_i1_siso[11:0] <= rx_i[11:0]; + rx_q1_siso[11:0] <= rx_q[11:0]; + end // else: !if(rx_frame_0) + + //------------------------------------------------------------------ + // + // Now prepare data for crossing into radio_clk domain which can be for SISO mode (inverted) siso_clk or for MIMO mode siso_clk/2. + // In MIMO mode tx_strobe is used to maintain a known phase relationship betwwen siso_clk and radio_clk. + // (Note: Negedge or posedge is used conditionally so that we have massive margin against a fast-path race condition + // betwwen siso_clk and radio_clk). This kind of arrangement could still lead to confusion in timing analysis + // even if it works in the real world depending on how well the STA tool can do automatic case analysis. + // + //------------------------------------------------------------------ + // This code lock only relevent in MIMO mode. + always @(negedge siso_clk) + if (tx_strobe) + begin + rx_i0_siso_neg[11:0] <= rx_i0_siso[11:0]; + rx_q0_siso_neg[11:0] <= rx_q0_siso[11:0]; + rx_i1_siso_neg[11:0] <= rx_i1_siso[11:0]; + rx_q1_siso_neg[11:0] <= rx_q1_siso[11:0]; + end + // This code block only relevent in SISO mode. + always @(posedge siso_clk) + begin + rx_i0_siso_pos[11:0] <= rx_i0_siso[11:0]; + rx_q0_siso_pos[11:0] <= rx_q0_siso[11:0]; + rx_i1_siso_pos[11:0] <= rx_i1_siso[11:0]; + rx_q1_siso_pos[11:0] <= rx_q1_siso[11:0]; + end + + assign rx_i0 = (mimo_sync) ? rx_i0_siso_neg : rx_i0_siso_pos; + assign rx_q0 = (mimo_sync) ? rx_q0_siso_neg : rx_q0_siso_pos; + assign rx_i1 = (mimo_sync) ? rx_i1_siso_neg : rx_i1_siso_pos; + assign rx_q1 = (mimo_sync) ? rx_q1_siso_neg : rx_q1_siso_pos; + + + //------------------------------------------------------------------ + // TX Data Bus - In bank3 LB + //------------------------------------------------------------------ + reg [11:0] tx_i,tx_q; + reg tx_strobe_del; + + generate + for(z = 0; z < 12; z = z + 1) + begin : gen_pins + ODDR2 #( + .DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC")) + oddr2 ( + .Q(tx_data[z]), .C0(io_clk_lb), .C1(io_clk_lb_b), + .CE(1'b1), .D0(tx_i[z]), .D1(tx_q[z]), .R(1'b0), .S(1'b0)); + end + endgenerate + + //------------------------------------------------------------------ + // TX Frame Signal - In bank 3 LB + //------------------------------------------------------------------ + ODDR2 #( + .DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC")) + oddr2_frame ( + .Q(tx_frame), .C0(io_clk_lb), .C1(io_clk_lb_b), + .CE(1'b1), .D0(tx_strobe_del), .D1(mimo_sync & tx_strobe_del), .R(1'b0), .S(1'b0)); + + //------------------------------------------------------------------ + // TX Clock Signal - In bank 3 LB + //------------------------------------------------------------------ + ODDR2 #( + .DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC")) + oddr2_clk ( + .Q(tx_clk), .C0(io_clk_lb), .C1(io_clk_lb_b), + .CE(1'b1), .D0(1'b1), .D1(1'b0), .R(1'b0), .S(1'b0)); + + //------------------------------------------------------------------ + // + // Mux I & Q, Ch A & B onto fullrate clockTX bus to AD9361 + // + //------------------------------------------------------------------ + wire tx_strobe; + reg [11:0] tx_i_del, tx_q_del; + + reg find_radio_clk_phase = 1'b0; + reg find_radio_clk_phase_del; + + + always @(posedge radio_clk) + find_radio_clk_phase <= ~find_radio_clk_phase; + + always @(negedge radio_clk) + find_radio_clk_phase_del <= find_radio_clk_phase; + + assign tx_strobe = mimo_sync ? (find_radio_clk_phase_del ^ find_radio_clk_phase) : 1'b1; + + always @(posedge siso_clk) + tx_strobe_del <= tx_strobe; + + // This strange piece of logic allows either USRP DUC to drive the AD9361 in SISO mode. + // This is principly used in the CODEC loopback test. + wire [11:0] tx_im = (mimo_sync || tx_i0 != 12'h0) ? tx_i0 : tx_i1; + wire [11:0] tx_qm = (mimo_sync || tx_q0 != 12'h0) ? tx_q0 : tx_q1; + + + // Deal with the fact that Ch A and Ch B are labelled in silkscreen opposite to their documentation in AD9361. + // (Except on B200 based on AD9364 where only the true Ch A is stuffed) + always @(posedge siso_clk) + if(tx_strobe) + begin + {tx_i,tx_q} <= mimo_sync ? {tx_i1,tx_q1} : {tx_im,tx_qm}; + {tx_i_del,tx_q_del} <= {tx_i0,tx_q0}; + end + else + {tx_i,tx_q} <= {tx_i_del,tx_q_del}; + // + // Debug + // +/* -----\/----- EXCLUDED -----\/----- + wire [35:0] CONTROL0; + reg [11:0] tx_i_del_debug, tx_q_del_debug; + reg [11:0] tx_i_debug,tx_q_debug; + reg [11:0] tx_i0_debug,tx_q0_debug; + reg find_radio_clk_phase_debug; + reg find_radio_clk_phase_del_debug; + reg tx_strobe_debug; + reg tx_strobe_del_debug; + + + always @(posedge siso_clk) begin + tx_i_del_debug <= tx_i_del; + tx_q_del_debug <= tx_q_del; + tx_i_debug <= tx_i; + tx_q_debug <= tx_q; + tx_i0_debug <=tx_i0; + tx_q0_debug <= tx_q0; + find_radio_clk_phase_debug <= find_radio_clk_phase; + find_radio_clk_phase_del_debug <= find_radio_clk_phase_del; + tx_strobe_debug <= tx_strobe; + tx_strobe_del_debug <= tx_strobe_del; + end + + + + chipscope_icon chipscope_icon_i0 + ( + .CONTROL0(CONTROL0) // INOUT BUS [35:0] + ); + + chipscope_ila_128 chipscope_ila_i0 + ( + .CONTROL(CONTROL0), // INOUT BUS [35:0] + .CLK(siso_clk), // IN + .TRIG0( + { + tx_i_del_debug[11:0], + tx_q_del_debug[11:0], + tx_i_debug[11:0], + tx_q_debug[11:0], + tx_i0_debug[11:0], + tx_q0_debug[11:0], + find_radio_clk_phase_debug, + find_radio_clk_phase_del_debug, + tx_strobe_debug, + tx_strobe_del_debug + } + ) + + ); + -----/\----- EXCLUDED -----/\----- */ +endmodule diff --git a/fpga/usrp3/top/b200/check.sh b/fpga/usrp3/top/b200/check.sh new file mode 100644 index 000000000..5935de883 --- /dev/null +++ b/fpga/usrp3/top/b200/check.sh @@ -0,0 +1 @@ +iverilog ../top/b200/b200.v -y control/ -y timing/ -y fifo/ -y vita/ -y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ -y ../top/b200/ -y ../top/b200/coregen/ -y gpif2/ -y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/XilinxCoreLib/ -Wall | grep -v timescale diff --git a/fpga/usrp3/top/b200/core_compile b/fpga/usrp3/top/b200/core_compile new file mode 100755 index 000000000..553e9c8ad --- /dev/null +++ b/fpga/usrp3/top/b200/core_compile @@ -0,0 +1 @@ +iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpif2/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac B200.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models diff --git a/fpga/usrp3/top/b200/coregen/.gitignore b/fpga/usrp3/top/b200/coregen/.gitignore new file mode 100644 index 000000000..bdeac28ca --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/.gitignore @@ -0,0 +1,5 @@ +/tmp +/_xmsgs +/*.log +/*.gise +/*.xise diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.asy b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.asy new file mode 100644 index 000000000..eb4747f81 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.asy @@ -0,0 +1,9 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 b200_chipscope_icon +RECTANGLE Normal 32 32 544 864 +LINE Wide 576 112 544 112 +PIN 576 112 RIGHT 36 +PINATTR PinName control0[35:0] +PINATTR Polarity BOTH + diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.ucf b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.ucf new file mode 100644 index 000000000..b83296f8e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.ucf @@ -0,0 +1,9 @@ +NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ; +TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ; +#Update Constraints +NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ; +NET "U0/iSHIFT_OUT" TIG ; +TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ; +TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ; +TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ; +TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ; diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.xdc b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.xdc new file mode 100644 index 000000000..903799425 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.xdc @@ -0,0 +1,7 @@ +# icon XDC +create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] +create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}] +set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}] +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2 +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1 +set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK} diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ncf b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ngc b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ngc new file mode 100644 index 000000000..d43ee8b57 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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3`=02c=57>5;h4b>5<>i?:3:17pll3;291?6=8r.2m796;I3;6>N6?m1/4>4>b79'2c<03`<26=44i7c94?=n>k0;66g9c;29?j>52900qom=:186>5<7s-3j6:74H0:1?M70l2.3?7?m6:&5b?0>o1j3:17d8l:188k=4=831vnn?50;794?6|,0k1;45G1908L41c3-2860=n>00;66g9a;29?l0e2900e;m50;9l<7<722wio=4?:483>5}#1h0<56F>839K52b<,191=o84$7d90>o113:17d8n:188m3d=831b:n4?::m;6?6=3thij7>55;294~">i3=27E?72:J23a=#0:0:n;5+6g80?l0>2900e;o50;9j2g<722c=o7>5;n:1>5<30D<6=;I34`>"?;3;i:6*9f;08m3?=831b:l4?::k5f?6=3`428h=7)8i:0;8 =?=9h80e;750;9j2d<722c=n7>5;h4`>5<428h=7)8i:0;8 =?=90:0e;750;9j2d<722c=n7>5;h4`>5<428h=7)8i:0;8 =?=90;0e;750;9j2d<722c=n7>5;h4`>5<428h=7)8i:0;8 =?=9080e;750;9j2d<722c=n7>5;h4`>5<1<7;50;2x 428h=7)8i:0;8 =?=9090e;750;9j2d<722c=n7>5;h4`>5<428h=7)8i:0;8 =?=90>0e;750;9j2d<722c=n7>5;h4`>5<428h=7)8i:0;8 =?=90?0e;750;9j2d<722c=n7>5;h4`>5<428h=7)8i:0;8 =?=90=0e;750;9j2d<722c=n7>5;h4`>5<428h=7)8i:0;8 =?=9020e;750;9j2d<722c=n7>5;h4`>5<428h=7)8i:0;8 =?=9030e;750;9j2d<722c=n7>5;h4`>5<428h=7)8i:0;8 =?=9h90e;750;9j2d<722c=n7>5;h4`>5<1<7;50;2x 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ucf b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ucf new file mode 100644 index 000000000..b83296f8e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ucf @@ -0,0 +1,9 @@ +NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ; +TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ; +#Update Constraints +NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ; +NET "U0/iSHIFT_OUT" TIG ; +TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ; +TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ; +TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ; +TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ; diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.v b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.v new file mode 100644 index 000000000..30b31cca5 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.v @@ -0,0 +1,27 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : b200_chipscope_icon.v +// /___/ /\ Timestamp : Tue Feb 19 14:28:40 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: Verilog Synthesis Wrapper +/////////////////////////////////////////////////////////////////////////////// +// This wrapper is used to integrate with Project Navigator and PlanAhead + +`timescale 1ns/1ps + +module b200_chipscope_icon( + CONTROL0) /* synthesis syn_black_box syn_noprune=1 */; + + +inout [35 : 0] CONTROL0; + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.veo b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.veo new file mode 100644 index 000000000..6c82410b6 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.veo @@ -0,0 +1,28 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : b200_chipscope_icon.veo +// /___/ /\ Timestamp : Tue Feb 19 14:28:40 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: ISE Instantiation template +/////////////////////////////////////////////////////////////////////////////// + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +b200_chipscope_icon YourInstanceName ( + .CONTROL0(CONTROL0) // INOUT BUS [35:0] +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xco b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xco new file mode 100644 index 000000000..2b7395488 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xco @@ -0,0 +1,56 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Tue Feb 19 22:27:58 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a +# END Select +# BEGIN Parameters +CSET component_name=b200_chipscope_icon +CSET constraint_type=external +CSET enable_jtag_bufg=true +CSET example_design=false +CSET number_control_ports=1 +CSET use_ext_bscan=false +CSET use_softbscan=false +CSET use_unused_bscan=false +CSET user_scan_chain=USER1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-12-18T02:47:25Z +# END Extra information +GENERATE +# CRC: 729764e8 diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xdc b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xdc new file mode 100644 index 000000000..903799425 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xdc @@ -0,0 +1,7 @@ +# icon XDC +create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] +create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}] +set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}] +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2 +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1 +set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK} diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_flist.txt b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_flist.txt new file mode 100644 index 000000000..97a36c09d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_flist.txt @@ -0,0 +1,15 @@ +# Output products list for +b200_chipscope_icon.asy +b200_chipscope_icon.constraints/b200_chipscope_icon.ucf +b200_chipscope_icon.constraints/b200_chipscope_icon.xdc +b200_chipscope_icon.gise +b200_chipscope_icon.ngc +b200_chipscope_icon.ucf +b200_chipscope_icon.v +b200_chipscope_icon.veo +b200_chipscope_icon.xco +b200_chipscope_icon.xdc +b200_chipscope_icon.xise +b200_chipscope_icon_flist.txt +b200_chipscope_icon_readme.txt +b200_chipscope_icon_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_readme.txt b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_readme.txt new file mode 100644 index 000000000..c3b896f44 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_readme.txt @@ -0,0 +1,45 @@ +The following files were generated for 'b200_chipscope_icon' in directory +/home/bhilburn/xilinx/ + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * b200_chipscope_icon.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * b200_chipscope_icon.constraints/b200_chipscope_icon.ucf + * b200_chipscope_icon.constraints/b200_chipscope_icon.xdc + * b200_chipscope_icon.ngc + * b200_chipscope_icon.ucf + * b200_chipscope_icon.v + * b200_chipscope_icon.veo + * b200_chipscope_icon.xdc + * b200_chipscope_icon_xmdf.tcl + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * b200_chipscope_icon.asy + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * b200_chipscope_icon.gise + * b200_chipscope_icon.xise + +Deliver Readme: + Readme file for the IP. + + * b200_chipscope_icon_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * b200_chipscope_icon_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_xmdf.tcl b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_xmdf.tcl new file mode 100755 index 000000000..c9d1c0b14 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_xmdf.tcl @@ -0,0 +1,88 @@ +# The package naming convention is _xmdf +package provide b200_chipscope_icon_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::b200_chipscope_icon_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::b200_chipscope_icon_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name b200_chipscope_icon +} +# ::b200_chipscope_icon_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::b200_chipscope_icon_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.constraints/b200_chipscope_icon.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.ncf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.constraints/b200_chipscope_icon.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.xcf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module b200_chipscope_icon +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams + + diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.asy b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.asy new file mode 100644 index 000000000..fcca7f4e0 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.asy @@ -0,0 +1,21 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 b200_chipscope_ila +RECTANGLE Normal 32 32 288 704 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName control[35:0] +PINATTR Polarity IN +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Wide 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName data[63:0] +PINATTR Polarity IN +LINE Wide 0 176 32 176 +PIN 0 176 LEFT 36 +PINATTR PinName trig0[7:0] +PINATTR Polarity IN + diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.cdc b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.cdc new file mode 100644 index 000000000..985834f8d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.cdc @@ -0,0 +1,83 @@ +#ChipScope Core Generator Project File Version 3.0 +#Tue Feb 19 16:52:47 PST 2013 +SignalExport.clockChannel=CLK +SignalExport.dataChannel<0000>=DATA[0] +SignalExport.dataChannel<0001>=DATA[1] +SignalExport.dataChannel<0002>=DATA[2] +SignalExport.dataChannel<0003>=DATA[3] +SignalExport.dataChannel<0004>=DATA[4] +SignalExport.dataChannel<0005>=DATA[5] +SignalExport.dataChannel<0006>=DATA[6] +SignalExport.dataChannel<0007>=DATA[7] +SignalExport.dataChannel<0008>=DATA[8] +SignalExport.dataChannel<0009>=DATA[9] +SignalExport.dataChannel<0010>=DATA[10] +SignalExport.dataChannel<0011>=DATA[11] +SignalExport.dataChannel<0012>=DATA[12] +SignalExport.dataChannel<0013>=DATA[13] +SignalExport.dataChannel<0014>=DATA[14] +SignalExport.dataChannel<0015>=DATA[15] +SignalExport.dataChannel<0016>=DATA[16] +SignalExport.dataChannel<0017>=DATA[17] +SignalExport.dataChannel<0018>=DATA[18] +SignalExport.dataChannel<0019>=DATA[19] +SignalExport.dataChannel<0020>=DATA[20] +SignalExport.dataChannel<0021>=DATA[21] +SignalExport.dataChannel<0022>=DATA[22] +SignalExport.dataChannel<0023>=DATA[23] +SignalExport.dataChannel<0024>=DATA[24] +SignalExport.dataChannel<0025>=DATA[25] +SignalExport.dataChannel<0026>=DATA[26] +SignalExport.dataChannel<0027>=DATA[27] +SignalExport.dataChannel<0028>=DATA[28] +SignalExport.dataChannel<0029>=DATA[29] +SignalExport.dataChannel<0030>=DATA[30] +SignalExport.dataChannel<0031>=DATA[31] +SignalExport.dataChannel<0032>=DATA[32] +SignalExport.dataChannel<0033>=DATA[33] +SignalExport.dataChannel<0034>=DATA[34] +SignalExport.dataChannel<0035>=DATA[35] +SignalExport.dataChannel<0036>=DATA[36] +SignalExport.dataChannel<0037>=DATA[37] +SignalExport.dataChannel<0038>=DATA[38] +SignalExport.dataChannel<0039>=DATA[39] +SignalExport.dataChannel<0040>=DATA[40] +SignalExport.dataChannel<0041>=DATA[41] +SignalExport.dataChannel<0042>=DATA[42] +SignalExport.dataChannel<0043>=DATA[43] +SignalExport.dataChannel<0044>=DATA[44] +SignalExport.dataChannel<0045>=DATA[45] +SignalExport.dataChannel<0046>=DATA[46] +SignalExport.dataChannel<0047>=DATA[47] +SignalExport.dataChannel<0048>=DATA[48] +SignalExport.dataChannel<0049>=DATA[49] +SignalExport.dataChannel<0050>=DATA[50] +SignalExport.dataChannel<0051>=DATA[51] +SignalExport.dataChannel<0052>=DATA[52] +SignalExport.dataChannel<0053>=DATA[53] +SignalExport.dataChannel<0054>=DATA[54] +SignalExport.dataChannel<0055>=DATA[55] +SignalExport.dataChannel<0056>=DATA[56] +SignalExport.dataChannel<0057>=DATA[57] +SignalExport.dataChannel<0058>=DATA[58] +SignalExport.dataChannel<0059>=DATA[59] +SignalExport.dataChannel<0060>=DATA[60] +SignalExport.dataChannel<0061>=DATA[61] +SignalExport.dataChannel<0062>=DATA[62] +SignalExport.dataChannel<0063>=DATA[63] +SignalExport.dataEqualsTrigger=false +SignalExport.dataPortWidth=64 +SignalExport.triggerChannel<0000><0000>=TRIG0[0] +SignalExport.triggerChannel<0000><0001>=TRIG0[1] +SignalExport.triggerChannel<0000><0002>=TRIG0[2] +SignalExport.triggerChannel<0000><0003>=TRIG0[3] +SignalExport.triggerChannel<0000><0004>=TRIG0[4] +SignalExport.triggerChannel<0000><0005>=TRIG0[5] +SignalExport.triggerChannel<0000><0006>=TRIG0[6] +SignalExport.triggerChannel<0000><0007>=TRIG0[7] +SignalExport.triggerPort<0000>.name=TRIG0 +SignalExport.triggerPortCount=1 +SignalExport.triggerPortIsData<0000>=false +SignalExport.triggerPortWidth<0000>=8 +SignalExport.type=ila + diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.ucf b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.ucf new file mode 100644 index 000000000..e1ce12a9d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.ucf @@ -0,0 +1,17 @@ +# +# Clock constraints +# +NET "CLK" TNM_NET = D_CLK ; +INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; +TIMESPEC TS_D2_TO_T2_b200_chipscope_ila = FROM D2_CLK TO "FFS" TIG; +TIMESPEC TS_J2_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J3_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J4_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG; + +# +# Input keep/save net constraints +# +NET "TRIG0<*" S; +NET "TRIG0<*" KEEP; +NET "DATA<*" S; +NET "DATA<*" KEEP; diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.xdc b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.xdc new file mode 100644 index 000000000..49e2b9e7b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.xdc @@ -0,0 +1,6 @@ +# +# Clock constraints +# +set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] +set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] +set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ncf b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ngc b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ngc new file mode 100644 index 000000000..82baab030 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ucf b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ucf new file mode 100644 index 000000000..e1ce12a9d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ucf @@ -0,0 +1,17 @@ +# +# Clock constraints +# +NET "CLK" TNM_NET = D_CLK ; +INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; +TIMESPEC TS_D2_TO_T2_b200_chipscope_ila = FROM D2_CLK TO "FFS" TIG; +TIMESPEC TS_J2_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J3_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J4_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG; + +# +# Input keep/save net constraints +# +NET "TRIG0<*" S; +NET "TRIG0<*" KEEP; +NET "DATA<*" S; +NET "DATA<*" KEEP; diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.v b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.v new file mode 100644 index 000000000..a9abb90e8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.v @@ -0,0 +1,33 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : b200_chipscope_ila.v +// /___/ /\ Timestamp : Tue Feb 19 16:52:47 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: Verilog Synthesis Wrapper +/////////////////////////////////////////////////////////////////////////////// +// This wrapper is used to integrate with Project Navigator and PlanAhead + +`timescale 1ns/1ps + +module b200_chipscope_ila( + CONTROL, + CLK, + DATA, + TRIG0) /* synthesis syn_black_box syn_noprune=1 */; + + +inout [35 : 0] CONTROL; +input CLK; +input [63 : 0] DATA; +input [7 : 0] TRIG0; + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.veo b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.veo new file mode 100644 index 000000000..f72d6853c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.veo @@ -0,0 +1,31 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : b200_chipscope_ila.veo +// /___/ /\ Timestamp : Tue Feb 19 16:52:47 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: ISE Instantiation template +/////////////////////////////////////////////////////////////////////////////// + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +b200_chipscope_ila YourInstanceName ( + .CONTROL(CONTROL), // INOUT BUS [35:0] + .CLK(CLK), // IN + .DATA(DATA), // IN BUS [63:0] + .TRIG0(TRIG0) // IN BUS [7:0] +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xco b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xco new file mode 100644 index 000000000..ecae96127 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xco @@ -0,0 +1,141 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Wed Feb 20 00:50:54 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a +# END Select +# BEGIN Parameters +CSET check_bramcount=false +CSET component_name=b200_chipscope_ila +CSET constraint_type=external +CSET counter_width_1=Disabled +CSET counter_width_10=Disabled +CSET counter_width_11=Disabled +CSET counter_width_12=Disabled +CSET counter_width_13=Disabled +CSET counter_width_14=Disabled +CSET counter_width_15=Disabled +CSET counter_width_16=Disabled +CSET counter_width_2=Disabled +CSET counter_width_3=Disabled +CSET counter_width_4=Disabled +CSET counter_width_5=Disabled +CSET counter_width_6=Disabled +CSET counter_width_7=Disabled +CSET counter_width_8=Disabled +CSET counter_width_9=Disabled +CSET data_port_width=64 +CSET data_same_as_trigger=false +CSET disable_save_keep=false +CSET enable_storage_qualification=true +CSET enable_trigger_output_port=false +CSET example_design=false +CSET exclude_from_data_storage_1=true +CSET exclude_from_data_storage_10=true +CSET exclude_from_data_storage_11=true +CSET exclude_from_data_storage_12=true +CSET exclude_from_data_storage_13=true +CSET exclude_from_data_storage_14=true +CSET exclude_from_data_storage_15=true +CSET exclude_from_data_storage_16=true +CSET exclude_from_data_storage_2=true +CSET exclude_from_data_storage_3=true +CSET exclude_from_data_storage_4=true +CSET exclude_from_data_storage_5=true +CSET exclude_from_data_storage_6=true +CSET exclude_from_data_storage_7=true +CSET exclude_from_data_storage_8=true +CSET exclude_from_data_storage_9=true +CSET match_type_1=basic_with_edges +CSET match_type_10=basic_with_edges +CSET match_type_11=basic_with_edges +CSET match_type_12=basic_with_edges +CSET match_type_13=basic_with_edges +CSET match_type_14=basic_with_edges +CSET match_type_15=basic_with_edges +CSET match_type_16=basic_with_edges +CSET match_type_2=basic_with_edges +CSET match_type_3=basic_with_edges +CSET match_type_4=basic_with_edges +CSET match_type_5=basic_with_edges +CSET match_type_6=basic_with_edges +CSET match_type_7=basic_with_edges +CSET match_type_8=basic_with_edges +CSET match_type_9=basic_with_edges +CSET match_units_1=1 +CSET match_units_10=1 +CSET match_units_11=1 +CSET match_units_12=1 +CSET match_units_13=1 +CSET match_units_14=1 +CSET match_units_15=1 +CSET match_units_16=1 +CSET match_units_2=1 +CSET match_units_3=1 +CSET match_units_4=1 +CSET match_units_5=1 +CSET match_units_6=1 +CSET match_units_7=1 +CSET match_units_8=1 +CSET match_units_9=1 +CSET max_sequence_levels=1 +CSET number_of_trigger_ports=1 +CSET sample_data_depth=8192 +CSET sample_on=Rising +CSET trigger_port_width_1=8 +CSET trigger_port_width_10=8 +CSET trigger_port_width_11=8 +CSET trigger_port_width_12=8 +CSET trigger_port_width_13=8 +CSET trigger_port_width_14=8 +CSET trigger_port_width_15=8 +CSET trigger_port_width_16=8 +CSET trigger_port_width_2=8 +CSET trigger_port_width_3=8 +CSET trigger_port_width_4=8 +CSET trigger_port_width_5=8 +CSET trigger_port_width_6=8 +CSET trigger_port_width_7=8 +CSET trigger_port_width_8=8 +CSET trigger_port_width_9=8 +CSET use_rpms=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-12-18T02:47:40Z +# END Extra information +GENERATE +# CRC: 92d75d38 diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xdc b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xdc new file mode 100644 index 000000000..49e2b9e7b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xdc @@ -0,0 +1,6 @@ +# +# Clock constraints +# +set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] +set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] +set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_flist.txt b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_flist.txt new file mode 100644 index 000000000..4dfd1b082 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_flist.txt @@ -0,0 +1,18 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +b200_chipscope_ila.asy +b200_chipscope_ila.cdc +b200_chipscope_ila.constraints/b200_chipscope_ila.ucf +b200_chipscope_ila.constraints/b200_chipscope_ila.xdc +b200_chipscope_ila.gise +b200_chipscope_ila.ncf +b200_chipscope_ila.ngc +b200_chipscope_ila.ucf +b200_chipscope_ila.v +b200_chipscope_ila.veo +b200_chipscope_ila.xco +b200_chipscope_ila.xdc +b200_chipscope_ila.xise +b200_chipscope_ila_flist.txt +b200_chipscope_ila_readme.txt +b200_chipscope_ila_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_readme.txt b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_readme.txt new file mode 100644 index 000000000..28176abfb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_readme.txt @@ -0,0 +1,48 @@ +The following files were generated for 'b200_chipscope_ila' in directory +/home/bhilburn/code/ettus/b200_dev/fpgapriv.git/usrp3/top/b200/coregen/ + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * b200_chipscope_ila.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * b200_chipscope_ila.cdc + * b200_chipscope_ila.constraints/b200_chipscope_ila.ucf + * b200_chipscope_ila.constraints/b200_chipscope_ila.xdc + * b200_chipscope_ila.ncf + * b200_chipscope_ila.ngc + * b200_chipscope_ila.ucf + * b200_chipscope_ila.v + * b200_chipscope_ila.veo + * b200_chipscope_ila.xdc + * b200_chipscope_ila_xmdf.tcl + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * b200_chipscope_ila.asy + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * _xmsgs/pn_parser.xmsgs + * b200_chipscope_ila.gise + * b200_chipscope_ila.xise + +Deliver Readme: + Readme file for the IP. + + * b200_chipscope_ila_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * b200_chipscope_ila_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_xmdf.tcl b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_xmdf.tcl new file mode 100755 index 000000000..a0922f3ec --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_xmdf.tcl @@ -0,0 +1,87 @@ +# The package naming convention is _xmdf +package provide b200_chipscope_ila_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::b200_chipscope_ila_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::b200_chipscope_ila_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name b200_chipscope_ila +} +# ::b200_chipscope_ila_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::b200_chipscope_ila_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.cdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.constraints/b200_chipscope_ila.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.ncf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.constraints/b200_chipscope_ila.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module b200_chipscope_ila +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.asy b/fpga/usrp3/top/b200/coregen/b200_clk_gen.asy new file mode 100644 index 000000000..aad58f8d2 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.asy @@ -0,0 +1,33 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 b200_clk_gen +RECTANGLE Normal 32 32 576 1088 +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName clk_in1_p +PINATTR Polarity IN +LINE Normal 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName clk_in1_n +PINATTR Polarity IN +LINE Normal 0 432 32 432 +PIN 0 432 LEFT 36 +PINATTR PinName reset +PINATTR Polarity IN +LINE Normal 608 80 576 80 +PIN 608 80 RIGHT 36 +PINATTR PinName clk_out1 +PINATTR Polarity OUT +LINE Normal 608 176 576 176 +PIN 608 176 RIGHT 36 +PINATTR PinName clk_out2 +PINATTR Polarity OUT +LINE Normal 608 272 576 272 +PIN 608 272 RIGHT 36 +PINATTR PinName clk_out3 +PINATTR Polarity OUT +LINE Normal 608 976 576 976 +PIN 608 976 RIGHT 36 +PINATTR PinName locked +PINATTR Polarity OUT + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.ucf b/fpga/usrp3/top/b200/coregen/b200_clk_gen.ucf new file mode 100755 index 000000000..e3776c72b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.ucf @@ -0,0 +1,72 @@ +# file: b200_clk_gen.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +# Differential clock only needs one constraint +NET "CLK_IN1_P" TNM_NET = "CLK_IN1_P"; +TIMESPEC "TS_CLK_IN1_P" = PERIOD "CLK_IN1_P" 25.0 ns HIGH 50% INPUT_JITTER 250.0ps; + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- +# NET "clk_int[1]" TNM_NET = "CLK_OUT1"; +# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 40.000 MHz; + +# NET "clk_int[2]" TNM_NET = "CLK_OUT2"; +# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 100.000 MHz; +# NET "clk_int[3]" TNM_NET = "CLK_OUT3"; +# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 100.000 MHz; + +# FALSE PATH constraints +PIN "RESET" TIG; + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.v b/fpga/usrp3/top/b200/coregen/b200_clk_gen.v new file mode 100755 index 000000000..bb9a57dc2 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.v @@ -0,0 +1,163 @@ +// file: b200_clk_gen.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// "Output Output Phase Duty Pk-to-Pk Phase" +// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" +//---------------------------------------------------------------------------- +// CLK_OUT1____40.000______0.000______50.0______200.000____150.000 +// CLK_OUT2___100.000______0.000______50.0______400.000____150.000 +// CLK_OUT3___100.000______0.000______50.0______400.000____150.000 +// +//---------------------------------------------------------------------------- +// "Input Clock Freq (MHz) Input Jitter (UI)" +//---------------------------------------------------------------------------- +// __primary__________40.000____________0.010 + +`timescale 1ps/1ps + +(* CORE_GENERATION_INFO = "b200_clk_gen,clk_wiz_v3_6,{component_name=b200_clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=3,clkin1_period=25.0,clkin2_period=25.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *) +module b200_clk_gen + (// Clock in ports + input CLK_IN1_40_P, + input CLK_IN1_40_N, + // Clock out ports + output CLK_OUT1_40_int, + output CLK_OUT2_100_gpif, + output CLK_OUT3_100_bus, + // Status and control signals + input RESET, + output LOCKED + ); + + // Input buffering + //------------------------------------ + IBUFGDS clkin1_buf + (.O (clkin1), + .I (CLK_IN1_40_P), + .IB (CLK_IN1_40_N)); + + + // Clocking primitive + //------------------------------------ + + // Instantiation of the DCM primitive + // * Unused inputs are tied off + // * Unused outputs are labeled unused + wire psdone_unused; + wire locked_int; + wire [7:0] status_int; + wire clkfb; + wire clk0; + wire clkfx; + + DCM_SP + #(.CLKDV_DIVIDE (2.000), + .CLKFX_DIVIDE (2), + .CLKFX_MULTIPLY (5), + .CLKIN_DIVIDE_BY_2 ("FALSE"), + .CLKIN_PERIOD (25.0), + .CLKOUT_PHASE_SHIFT ("NONE"), + .CLK_FEEDBACK ("1X"), + .DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"), + .PHASE_SHIFT (0), + .STARTUP_WAIT ("FALSE")) + dcm_sp_inst + // Input clock + (.CLKIN (clkin1), + .CLKFB (clkfb), + // Output clocks + .CLK0 (clk0), + .CLK90 (), + .CLK180 (), + .CLK270 (), + .CLK2X (), + .CLK2X180 (), + .CLKFX (clkfx), + .CLKFX180 (), + .CLKDV (), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + // Other control and status signals + .LOCKED (locked_int), + .STATUS (status_int), + + .RST (RESET), + // Unused pin- tie low + .DSSEN (1'b0)); + + assign LOCKED = locked_int; + + // Output buffering + //----------------------------------- + assign clkfb = CLK_OUT1_40_int; + + BUFG clkout1_buf + (.O (CLK_OUT1_40_int), + .I (clk0)); + + + BUFG clkout2_buf + (.O (CLK_OUT2_100_gpif), + .I (clkfx)); + + BUFG clkout3_buf + (.O (CLK_OUT3_100_bus), + .I (clkfx)); + + + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.veo b/fpga/usrp3/top/b200/coregen/b200_clk_gen.veo new file mode 100755 index 000000000..111c02991 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.veo @@ -0,0 +1,83 @@ +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// "Output Output Phase Duty Pk-to-Pk Phase" +// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" +//---------------------------------------------------------------------------- +// CLK_OUT1____40.000______0.000______50.0______200.000____150.000 +// CLK_OUT2___100.000______0.000______50.0______400.000____150.000 +// CLK_OUT3___100.000______0.000______50.0______400.000____150.000 +// +//---------------------------------------------------------------------------- +// "Input Clock Freq (MHz) Input Jitter (UI)" +//---------------------------------------------------------------------------- +// __primary__________40.000____________0.010 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + + b200_clk_gen instance_name + (// Clock in ports + .CLK_IN1_40_P(CLK_IN1_40_P), // IN + .CLK_IN1_40_N(CLK_IN1_40_N), // IN + // Clock out ports + .CLK_OUT1_40_int(CLK_OUT1_40_int), // OUT + .CLK_OUT2_100_gpif(CLK_OUT2_100_gpif), // OUT + .CLK_OUT3_100_bus(CLK_OUT3_100_bus), // OUT + // Status and control signals + .RESET(RESET),// IN + .LOCKED(LOCKED)); // OUT +// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.xco b/fpga/usrp3/top/b200/coregen/b200_clk_gen.xco new file mode 100644 index 000000000..96c8193b3 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.xco @@ -0,0 +1,269 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Fri Jan 25 20:00:48 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:clk_wiz:3.6 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6 +# END Select +# BEGIN Parameters +CSET calc_done=DONE +CSET clk_in_sel_port=CLK_IN_SEL +CSET clk_out1_port=CLK_OUT1_40_int +CSET clk_out1_use_fine_ps_gui=false +CSET clk_out2_port=CLK_OUT2_100_gpif +CSET clk_out2_use_fine_ps_gui=false +CSET clk_out3_port=CLK_OUT3_100_bus +CSET clk_out3_use_fine_ps_gui=false +CSET clk_out4_port=CLK_OUT4 +CSET clk_out4_use_fine_ps_gui=false +CSET clk_out5_port=CLK_OUT5 +CSET clk_out5_use_fine_ps_gui=false +CSET clk_out6_port=CLK_OUT6 +CSET clk_out6_use_fine_ps_gui=false +CSET clk_out7_port=CLK_OUT7 +CSET clk_out7_use_fine_ps_gui=false +CSET clk_valid_port=CLK_VALID +CSET clkfb_in_n_port=CLKFB_IN_N +CSET clkfb_in_p_port=CLKFB_IN_P +CSET clkfb_in_port=CLKFB_IN +CSET clkfb_in_signaling=SINGLE +CSET clkfb_out_n_port=CLKFB_OUT_N +CSET clkfb_out_p_port=CLKFB_OUT_P +CSET clkfb_out_port=CLKFB_OUT +CSET clkfb_stopped_port=CLKFB_STOPPED +CSET clkin1_jitter_ps=250.0 +CSET clkin1_ui_jitter=0.010 +CSET clkin2_jitter_ps=100.0 +CSET clkin2_ui_jitter=0.010 +CSET clkout1_drives=BUFG +CSET clkout1_requested_duty_cycle=50.000 +CSET clkout1_requested_out_freq=40.000 +CSET clkout1_requested_phase=0.000 +CSET clkout2_drives=BUFG +CSET clkout2_requested_duty_cycle=50.000 +CSET clkout2_requested_out_freq=100.000 +CSET clkout2_requested_phase=0.000 +CSET clkout2_used=true +CSET clkout3_drives=BUFG +CSET clkout3_requested_duty_cycle=50.000 +CSET clkout3_requested_out_freq=100.000 +CSET clkout3_requested_phase=0.000 +CSET clkout3_used=true +CSET clkout4_drives=BUFG +CSET clkout4_requested_duty_cycle=50.000 +CSET clkout4_requested_out_freq=100.000 +CSET clkout4_requested_phase=0.000 +CSET clkout4_used=false +CSET clkout5_drives=BUFG +CSET clkout5_requested_duty_cycle=50.000 +CSET clkout5_requested_out_freq=100.000 +CSET clkout5_requested_phase=0.000 +CSET clkout5_used=false +CSET clkout6_drives=BUFG +CSET clkout6_requested_duty_cycle=50.000 +CSET clkout6_requested_out_freq=100.000 +CSET clkout6_requested_phase=0.000 +CSET clkout6_used=false +CSET clkout7_drives=BUFG +CSET clkout7_requested_duty_cycle=50.000 +CSET clkout7_requested_out_freq=100.000 +CSET clkout7_requested_phase=0.000 +CSET clkout7_used=false +CSET clock_mgr_type=AUTO +CSET component_name=b200_clk_gen +CSET daddr_port=DADDR +CSET dclk_port=DCLK +CSET dcm_clk_feedback=1X +CSET dcm_clk_out1_port=CLK0 +CSET dcm_clk_out2_port=CLKFX +CSET dcm_clk_out3_port=CLKFX +CSET dcm_clk_out4_port=CLK0 +CSET dcm_clk_out5_port=CLK0 +CSET dcm_clk_out6_port=CLK0 +CSET dcm_clkdv_divide=2.0 +CSET dcm_clkfx_divide=2 +CSET dcm_clkfx_multiply=5 +CSET dcm_clkgen_clk_out1_port=CLKFX +CSET dcm_clkgen_clk_out2_port=CLKFX +CSET dcm_clkgen_clk_out3_port=CLKFX +CSET dcm_clkgen_clkfx_divide=1 +CSET dcm_clkgen_clkfx_md_max=0.000 +CSET dcm_clkgen_clkfx_multiply=4 +CSET dcm_clkgen_clkfxdv_divide=2 +CSET dcm_clkgen_clkin_period=10.000 +CSET dcm_clkgen_notes=None +CSET dcm_clkgen_spread_spectrum=NONE +CSET dcm_clkgen_startup_wait=false +CSET dcm_clkin_divide_by_2=false +CSET dcm_clkin_period=25.000 +CSET dcm_clkout_phase_shift=NONE +CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS +CSET dcm_notes=None +CSET dcm_phase_shift=0 +CSET dcm_pll_cascade=NONE +CSET dcm_startup_wait=false +CSET den_port=DEN +CSET din_port=DIN +CSET dout_port=DOUT +CSET drdy_port=DRDY +CSET dwe_port=DWE +CSET feedback_source=FDBK_AUTO +CSET in_freq_units=Units_MHz +CSET in_jitter_units=Units_UI +CSET input_clk_stopped_port=INPUT_CLK_STOPPED +CSET jitter_options=UI +CSET jitter_sel=No_Jitter +CSET locked_port=LOCKED +CSET mmcm_bandwidth=OPTIMIZED +CSET mmcm_clkfbout_mult_f=4.000 +CSET mmcm_clkfbout_phase=0.000 +CSET mmcm_clkfbout_use_fine_ps=false +CSET mmcm_clkin1_period=10.000 +CSET mmcm_clkin2_period=10.000 +CSET mmcm_clkout0_divide_f=4.000 +CSET mmcm_clkout0_duty_cycle=0.500 +CSET mmcm_clkout0_phase=0.000 +CSET mmcm_clkout0_use_fine_ps=false +CSET mmcm_clkout1_divide=1 +CSET mmcm_clkout1_duty_cycle=0.500 +CSET mmcm_clkout1_phase=0.000 +CSET mmcm_clkout1_use_fine_ps=false +CSET mmcm_clkout2_divide=1 +CSET mmcm_clkout2_duty_cycle=0.500 +CSET mmcm_clkout2_phase=0.000 +CSET mmcm_clkout2_use_fine_ps=false +CSET mmcm_clkout3_divide=1 +CSET mmcm_clkout3_duty_cycle=0.500 +CSET mmcm_clkout3_phase=0.000 +CSET mmcm_clkout3_use_fine_ps=false +CSET mmcm_clkout4_cascade=false +CSET mmcm_clkout4_divide=1 +CSET mmcm_clkout4_duty_cycle=0.500 +CSET mmcm_clkout4_phase=0.000 +CSET mmcm_clkout4_use_fine_ps=false +CSET mmcm_clkout5_divide=1 +CSET mmcm_clkout5_duty_cycle=0.500 +CSET mmcm_clkout5_phase=0.000 +CSET mmcm_clkout5_use_fine_ps=false +CSET mmcm_clkout6_divide=1 +CSET mmcm_clkout6_duty_cycle=0.500 +CSET mmcm_clkout6_phase=0.000 +CSET mmcm_clkout6_use_fine_ps=false +CSET mmcm_clock_hold=false +CSET mmcm_compensation=ZHOLD +CSET mmcm_divclk_divide=1 +CSET mmcm_notes=None +CSET mmcm_ref_jitter1=0.010 +CSET mmcm_ref_jitter2=0.010 +CSET mmcm_startup_wait=false +CSET num_out_clks=3 +CSET override_dcm=false +CSET override_dcm_clkgen=false +CSET override_mmcm=false +CSET override_pll=false +CSET platform=lin64 +CSET pll_bandwidth=OPTIMIZED +CSET pll_clk_feedback=CLKFBOUT +CSET pll_clkfbout_mult=4 +CSET pll_clkfbout_phase=0.000 +CSET pll_clkin_period=10.000 +CSET pll_clkout0_divide=1 +CSET pll_clkout0_duty_cycle=0.500 +CSET pll_clkout0_phase=0.000 +CSET pll_clkout1_divide=1 +CSET pll_clkout1_duty_cycle=0.500 +CSET pll_clkout1_phase=0.000 +CSET pll_clkout2_divide=1 +CSET pll_clkout2_duty_cycle=0.500 +CSET pll_clkout2_phase=0.000 +CSET pll_clkout3_divide=1 +CSET pll_clkout3_duty_cycle=0.500 +CSET pll_clkout3_phase=0.000 +CSET pll_clkout4_divide=1 +CSET pll_clkout4_duty_cycle=0.500 +CSET pll_clkout4_phase=0.000 +CSET pll_clkout5_divide=1 +CSET pll_clkout5_duty_cycle=0.500 +CSET pll_clkout5_phase=0.000 +CSET pll_compensation=SYSTEM_SYNCHRONOUS +CSET pll_divclk_divide=1 +CSET pll_notes=None +CSET pll_ref_jitter=0.010 +CSET power_down_port=POWER_DOWN +CSET prim_in_freq=40.000 +CSET prim_in_jitter=0.010 +CSET prim_source=Differential_clock_capable_pin +CSET primary_port=CLK_IN1_40 +CSET primitive=MMCM +CSET primtype_sel=PLL_BASE +CSET psclk_port=PSCLK +CSET psdone_port=PSDONE +CSET psen_port=PSEN +CSET psincdec_port=PSINCDEC +CSET relative_inclk=REL_PRIMARY +CSET reset_port=RESET +CSET secondary_in_freq=100.000 +CSET secondary_in_jitter=0.010 +CSET secondary_port=CLK_IN2 +CSET secondary_source=Single_ended_clock_capable_pin +CSET ss_mod_freq=250 +CSET ss_mode=CENTER_HIGH +CSET status_port=STATUS +CSET summary_strings=empty +CSET use_clk_valid=false +CSET use_clkfb_stopped=false +CSET use_dyn_phase_shift=false +CSET use_dyn_reconfig=false +CSET use_freeze=false +CSET use_freq_synth=true +CSET use_inclk_stopped=false +CSET use_inclk_switchover=false +CSET use_locked=true +CSET use_max_i_jitter=false +CSET use_min_o_jitter=false +CSET use_min_power=false +CSET use_phase_alignment=true +CSET use_power_down=false +CSET use_reset=true +CSET use_spread_spectrum=false +CSET use_spread_spectrum_1=false +CSET use_status=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-05-10T12:44:55Z +# END Extra information +GENERATE +# CRC: af7323ea diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.xdc b/fpga/usrp3/top/b200/coregen/b200_clk_gen.xdc new file mode 100755 index 000000000..d57c7eec7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.xdc @@ -0,0 +1,68 @@ +# file: b200_clk_gen.xdc +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +# Differential clock only needs one constraint +create_clock -name CLK_IN1_P -period 25.0 [get_ports CLK_IN1_P] +set_propagated_clock CLK_IN1_P +set_input_jitter CLK_IN1_P 0.25 + +set_false_path -from [get_ports "RESET"] + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- + +#----------------------------------------------------------------- + +#----------------------------------------------------------------- diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/clk_wiz_v3_6_readme.txt b/fpga/usrp3/top/b200/coregen/b200_clk_gen/clk_wiz_v3_6_readme.txt new file mode 100644 index 000000000..19c5b73c6 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/clk_wiz_v3_6_readme.txt @@ -0,0 +1,181 @@ +CHANGE LOG for LogiCORE Clocking Wizard V3.6 + + Release Date: July 25, 2012 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/ + +................................................................................ + +2. DEVICE SUPPORT + + + 2.1 ISE + + + The following device families are supported by the core for this release. + + All 7 Series devices + + + Zynq-7000 devices + Zynq-7000 + Defense Grade Zynq-7000Q (XQ) + + + All Virtex-6 devices + + + All Spartan-6 devices + + +................................................................................ + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - Spread Spectrum support for 7 series MMCME2 + + - ISE 14.2 software support + +................................................................................ + +4. RESOLVED ISSUES + + + 4.1 ISE + + Resolved issue with Virtex6 MMCM instantiation for VHDL project + Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm + +................................................................................ + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + + The most recent information, including known issues, workarounds, and + resolutions for this version is provided in the IP Release Notes Guide + located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + +................................................................................ + +6. TECHNICAL SUPPORT & FEEDBACK + + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + +................................................................................ + +7. CORE RELEASE HISTORY + + +Date By Version Description +================================================================================ +10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support +07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support +04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support +01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support +06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support +03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support +12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support +09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support +07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support +04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support +12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support +09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support +06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support +04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support +================================================================================ + +................................................................................ + +8. LEGAL DISCLAIMER + +(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_readme.txt b/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_readme.txt new file mode 100644 index 000000000..19c5b73c6 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_readme.txt @@ -0,0 +1,181 @@ +CHANGE LOG for LogiCORE Clocking Wizard V3.6 + + Release Date: July 25, 2012 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/ + +................................................................................ + +2. DEVICE SUPPORT + + + 2.1 ISE + + + The following device families are supported by the core for this release. + + All 7 Series devices + + + Zynq-7000 devices + Zynq-7000 + Defense Grade Zynq-7000Q (XQ) + + + All Virtex-6 devices + + + All Spartan-6 devices + + +................................................................................ + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - Spread Spectrum support for 7 series MMCME2 + + - ISE 14.2 software support + +................................................................................ + +4. RESOLVED ISSUES + + + 4.1 ISE + + Resolved issue with Virtex6 MMCM instantiation for VHDL project + Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm + +................................................................................ + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + + The most recent information, including known issues, workarounds, and + resolutions for this version is provided in the IP Release Notes Guide + located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + +................................................................................ + +6. TECHNICAL SUPPORT & FEEDBACK + + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + +................................................................................ + +7. CORE RELEASE HISTORY + + +Date By Version Description +================================================================================ +10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support +07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support +04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support +01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support +06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support +03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support +12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support +09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support +07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support +04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support +12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support +09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support +06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support +04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support +================================================================================ + +................................................................................ + +8. LEGAL DISCLAIMER + +(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_vinfo.html b/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_vinfo.html new file mode 100644 index 000000000..7176ddb81 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_vinfo.html @@ -0,0 +1,192 @@ + + +clk_wiz_v3_6_vinfo + + + +

+CHANGE LOG for LogiCORE Clocking Wizard V3.6 
+
+                    Release Date: July 25, 2012
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
+solution. For the latest core updates, see the product page at:
+
+   www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
+
+................................................................................
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+
+
+  Zynq-7000 devices
+    Zynq-7000
+    Defense Grade Zynq-7000Q (XQ)
+
+
+  All Virtex-6 devices
+  
+  
+  All Spartan-6 devices
+  
+  
+................................................................................
+
+3. NEW FEATURE HISTORY 
+
+
+  3.1 ISE 
+  
+    - Spread Spectrum support for 7 series MMCME2
+
+    - ISE 14.2 software support
+
+................................................................................
+
+4. RESOLVED ISSUES
+
+
+  4.1 ISE 
+  
+      Resolved issue with Virtex6 MMCM instantiation for VHDL project
+      Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
+
+................................................................................
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+  5.1 ISE 
+  
+  
+  The most recent information, including known issues, workarounds, and
+  resolutions for this version is provided in the IP Release Notes Guide
+  located at
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+  
+  
+................................................................................
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+................................................................................
+
+7. CORE RELEASE HISTORY
+
+
+Date        By            Version      Description
+================================================================================
+10/16/2012  Xilinx, Inc.  3.6(Rev2)    ISE 14.3 support
+07/25/2012  Xilinx, Inc.  3.6          ISE 14.2 support
+04/24/2012  Xilinx, Inc.  3.5          ISE 14.1 support
+01/18/2012  Xilinx, Inc.  3.3          ISE 13.4 support
+06/22/2011  Xilinx, Inc.  3.2          ISE 13.2 support
+03/01/2011  Xilinx, Inc.  3.1          ISE 13.1 support
+12/14/2010  Xilinx, Inc.  1.8          ISE 12.4 support
+09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
+09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
+06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
+04/24/2009  Xilinx, Inc.  1.1          Initial release; 11.1 support
+================================================================================
+                          
+................................................................................
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
+
+
+ + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/pg065_clk_wiz.pdf b/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/pg065_clk_wiz.pdf new file mode 100644 index 000000000..a7daa6089 Binary files /dev/null and b/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/pg065_clk_wiz.pdf differ diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.ucf b/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.ucf new file mode 100755 index 000000000..62c243978 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.ucf @@ -0,0 +1,73 @@ +# file: b200_clk_gen_exdes.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +# Differential clock only needs one constraint +NET "CLK_IN1_P" TNM_NET = "CLK_IN1_P"; +TIMESPEC "TS_CLK_IN1_P" = PERIOD "CLK_IN1_P" 25.0 ns HIGH 50% INPUT_JITTER 250.0ps; + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- +# NET "clk_int[1]" TNM_NET = "CLK_OUT1"; +# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 40.000 MHz; + +# NET "clk_int[2]" TNM_NET = "CLK_OUT2"; +# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 100.000 MHz; +# NET "clk_int[3]" TNM_NET = "CLK_OUT3"; +# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 100.000 MHz; + +# FALSE PATH constraints +PIN "COUNTER_RESET" TIG; +PIN "RESET" TIG; + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.v b/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.v new file mode 100755 index 000000000..e22b83072 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.v @@ -0,0 +1,180 @@ +// file: b200_clk_gen_exdes.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard example design +//---------------------------------------------------------------------------- +// This example design instantiates the created clocking network, where each +// output clock drives a counter. The high bit of each counter is ported. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +module b200_clk_gen_exdes + #( + parameter TCQ = 100 + ) + (// Clock in ports + input CLK_IN1_P, + input CLK_IN1_N, + // Reset that only drives logic in example design + input COUNTER_RESET, + output [3:1] CLK_OUT, + // High bits of counters driven by clocks + output [3:1] COUNT, + // Status and control signals + input RESET, + output LOCKED + ); + + // Parameters for the counters + //------------------------------- + // Counter width + localparam C_W = 16; + // Number of counters + localparam NUM_C = 3; + genvar count_gen; + // When the clock goes out of lock, reset the counters + wire reset_int = !LOCKED || RESET || COUNTER_RESET; + + reg [NUM_C:1] rst_sync; + reg [NUM_C:1] rst_sync_int; + reg [NUM_C:1] rst_sync_int1; + reg [NUM_C:1] rst_sync_int2; + + + // Declare the clocks and counters + wire [NUM_C:1] clk_int; + wire [NUM_C:1] clk_n; + wire [NUM_C:1] clk; + reg [C_W-1:0] counter [NUM_C:1]; + + // Instantiation of the clocking network + //-------------------------------------- + b200_clk_gen clknetwork + (// Clock in ports + .CLK_IN1_40_P (CLK_IN1_P), + .CLK_IN1_40_N (CLK_IN1_N), + // Clock out ports + .CLK_OUT1_40_int (clk_int[1]), + .CLK_OUT2_100_gpif (clk_int[2]), + .CLK_OUT3_100_bus (clk_int[3]), + // Status and control signals + .RESET (RESET), + .LOCKED (LOCKED)); + +genvar clk_out_pins; + +generate + for (clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1) + begin: gen_outclk_oddr + assign clk_n[clk_out_pins] = ~clk[clk_out_pins]; + + ODDR2 clkout_oddr + (.Q (CLK_OUT[clk_out_pins1]), + .C0 (clk[clk_out_pins]), + .C1 (clk_n[clk_out_pins]), + .CE (1'b1), + .D0 (1'b1), + .D1 (1'b0), + .R (1'b0), + .S (1'b0)); + end +endgenerate + + // Connect the output clocks to the design + //----------------------------------------- + assign clk[1] = clk_int[1]; + assign clk[2] = clk_int[2]; + assign clk[3] = clk_int[3]; + + + // Reset synchronizer + //----------------------------------- + generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1 + always @(posedge reset_int or posedge clk[count_gen]) begin + if (reset_int) begin + rst_sync[count_gen] <= 1'b1; + rst_sync_int[count_gen]<= 1'b1; + rst_sync_int1[count_gen]<= 1'b1; + rst_sync_int2[count_gen]<= 1'b1; + end + else begin + rst_sync[count_gen] <= 1'b0; + rst_sync_int[count_gen] <= rst_sync[count_gen]; + rst_sync_int1[count_gen] <= rst_sync_int[count_gen]; + rst_sync_int2[count_gen] <= rst_sync_int1[count_gen]; + end + end + end + endgenerate + + + // Output clock sampling + //----------------------------------- + generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters + + always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin + if (rst_sync_int2[count_gen]) begin + counter[count_gen] <= #TCQ { C_W { 1'b 0 } }; + end else begin + counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1; + end + end + // alias the high bit of each counter to the corresponding + // bit in the output bus + assign COUNT[count_gen] = counter[count_gen][C_W-1]; + end + endgenerate + + + + + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.xdc b/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.xdc new file mode 100755 index 000000000..dc0aad84c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.xdc @@ -0,0 +1,70 @@ +# file: b200_clk_gen_exdes.xdc +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +# Differential clock only needs one constraint +create_clock -name CLK_IN1_P -period 25.0 [get_ports CLK_IN1_P] +set_propagated_clock CLK_IN1_P +set_input_jitter CLK_IN1_P 0.25 + +# FALSE PATH constraint added on COUNTER_RESET +set_false_path -from [get_ports "COUNTER_RESET"] +set_false_path -from [get_ports "RESET"] + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- + +#----------------------------------------------------------------- + +#----------------------------------------------------------------- diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.bat b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.bat new file mode 100755 index 000000000..32e315065 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.bat @@ -0,0 +1,90 @@ +REM file: implement.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM ----------------------------------------------------------------------------- +REM Script to synthesize and implement the RTL provided for the clocking wizard +REM ----------------------------------------------------------------------------- + +REM Clean up the results directory +rmdir /S /Q results +mkdir results + +REM Copy unisim_comp.v file to results directory +copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\ + +REM Synthesize the Verilog Wrapper Files +echo 'Synthesizing Clocking Wizard design with XST' +xst -ifn xst.scr +move b200_clk_gen_exdes.ngc results\ + +REM Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\b200_clk_gen_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' +ngdbuild -uc b200_clk_gen_exdes.ucf b200_clk_gen_exdes + +echo 'Running map' +map -timing -pr b b200_clk_gen_exdes -o mapped.ncd + +echo 'Running par' +par -w mapped.ncd routed mapped.pcf + +echo 'Running trce' +trce -e 10 routed -o routed mapped.pcf + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level model for the clocking wizard example design' +netgen -ofmt verilog -sim -sdf_anno false -tm b200_clk_gen_exdes -w routed.ncd routed.v +cd .. + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.sh new file mode 100755 index 000000000..d33e6c5f5 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.sh @@ -0,0 +1,91 @@ +#!/bin/sh +# file: implement.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the RTL provided for the clocking wizard +#----------------------------------------------------------------------------- + +# Clean up the results directory +rm -rf results +mkdir results + +# Copy unisim_comp.v file to results directory +cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/ + +# Synthesize the Verilog Wrapper Files +echo 'Synthesizing Clocking Wizard design with XST' +xst -ifn xst.scr +mv b200_clk_gen_exdes.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/b200_clk_gen_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' +ngdbuild -uc b200_clk_gen_exdes.ucf b200_clk_gen_exdes + +echo 'Running map' +map -timing b200_clk_gen_exdes -o mapped.ncd + +echo 'Running par' +par -w mapped.ncd routed mapped.pcf + +echo 'Running trce' +trce -e 10 routed -o routed mapped.pcf + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level model for the clocking wizard example design' +netgen -ofmt verilog -sim -sdf_anno false -tm b200_clk_gen_exdes -w routed.ncd routed.v + +cd .. diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.bat b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.bat new file mode 100755 index 000000000..8ac771810 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.bat @@ -0,0 +1,58 @@ +REM file: planAhead_ise.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM----------------------------------------------------------------------------- +REM Script to synthesize and implement the RTL provided for the clocking wizard +REM----------------------------------------------------------------------------- + +del \f results +mkdir results +cd results + +planAhead -mode batch -source ..\planAhead_ise.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.sh new file mode 100755 index 000000000..6c8c837d3 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.sh @@ -0,0 +1,59 @@ +#!/bin/sh +# file: planAhead_ise.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the RTL provided for the clocking wizard +#----------------------------------------------------------------------------- + +rm -rf results +mkdir results +cd results + +planAhead -mode batch -source ../planAhead_ise.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.tcl new file mode 100755 index 000000000..b87b6e4d5 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.tcl @@ -0,0 +1,78 @@ +# file: planAhead_ise.tcl +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +set projDir [file dirname [info script]] +set projName b200_clk_gen +set topName b200_clk_gen_exdes +set device xc6slx75csg484-2 + +create_project $projName $projDir/results/$projName -part $device + +set_property design_mode RTL [get_filesets sources_1] + +## Source files +#set verilogSources [glob $srcDir/*.v] +import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/b200_clk_gen_exdes.v +import_files -fileset [get_filesets sources_1] -force -norecurse ../../../b200_clk_gen.v + + +#UCF file +import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/b200_clk_gen_exdes.ucf + +set_property top $topName [get_property srcset [current_run]] + +launch_runs -runs synth_1 +wait_on_run synth_1 + +set_property add_step Bitgen [get_runs impl_1] +launch_runs -runs impl_1 +wait_on_run impl_1 + + + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.bat b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.bat new file mode 100755 index 000000000..42273f5d4 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.bat @@ -0,0 +1,58 @@ +REM file: planAhead_rdn.sh +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM----------------------------------------------------------------------------- +REM Script to synthesize and implement the RTL provided for the XADC wizard +REM----------------------------------------------------------------------------- + +del \f results +mkdir results +cd results + +planAhead -mode batch -source ..\planAhead_rdn.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.sh new file mode 100755 index 000000000..f4c14729e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.sh @@ -0,0 +1,57 @@ +#!/bin/sh +# file: planAhead_rdn.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the RTL provided for the XADC wizard +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +planAhead -mode batch -source ../planAhead_rdn.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.tcl new file mode 100755 index 000000000..5449fa5fb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.tcl @@ -0,0 +1,69 @@ +# file : planAhead_rdn.tcl +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +set device xc6slx75csg484-2 +set projName b200_clk_gen +set design b200_clk_gen +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module b200_clk_gen_exdes +set_property top b200_clk_gen_exdes [get_property srcset [current_run]] +add_files -norecurse {../../../b200_clk_gen.v} +add_files -norecurse {../../example_design/b200_clk_gen_exdes.v} +import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/b200_clk_gen_exdes.xdc} +synth_design +opt_design +place_design +route_design +write_sdf -rename_top_module b200_clk_gen_exdes -file routed.sdf +write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module b200_clk_gen_exdes -file routed.v +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file report.drc +write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.prj b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.prj new file mode 100755 index 000000000..51a950151 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.prj @@ -0,0 +1,2 @@ +verilog work ../../b200_clk_gen.v +verilog work ../example_design/b200_clk_gen_exdes.v diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.scr b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.scr new file mode 100755 index 000000000..ae0a09163 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.scr @@ -0,0 +1,9 @@ +run +-ifmt MIXED +-top b200_clk_gen_exdes +-p xc6slx75-csg484-2 +-ifn xst.prj +-ofn b200_clk_gen_exdes +-keep_hierarchy soft +-equivalent_register_removal no +-max_fanout 65535 diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/b200_clk_gen_tb.v b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/b200_clk_gen_tb.v new file mode 100755 index 000000000..f7dba4105 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/b200_clk_gen_tb.v @@ -0,0 +1,146 @@ +// file: b200_clk_gen_tb.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard demonstration testbench +//---------------------------------------------------------------------------- +// This demonstration testbench instantiates the example design for the +// clocking wizard. Input clocks are toggled, which cause the clocking +// network to lock and the counters to increment. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +`define wait_lock @(posedge LOCKED) + +module b200_clk_gen_tb (); + + // Clock to Q delay of 100ps + localparam TCQ = 100; + + + // timescale is 1ps/1ps + localparam ONE_NS = 1000; + localparam PHASE_ERR_MARGIN = 100; // 100ps + // how many cycles to run + localparam COUNT_PHASE = 1024; + // we'll be using the period in many locations + localparam time PER1 = 25.0*ONE_NS; + localparam time PER1_1 = PER1/2; + localparam time PER1_2 = PER1 - PER1/2; + + // Declare the input clock signals + reg CLK_IN1 = 1; + wire CLK_IN1_P = CLK_IN1; + wire CLK_IN1_N = ~CLK_IN1; + + // The high bits of the sampling counters + wire [3:1] COUNT; + // Status and control signals + reg RESET = 0; + wire LOCKED; + reg COUNTER_RESET = 0; +wire [3:1] CLK_OUT; +//Freq Check using the M & D values setting and actual Frequency generated + + + // Input clock generation + //------------------------------------ + always begin + CLK_IN1 = #PER1_1 ~CLK_IN1; + CLK_IN1 = #PER1_2 ~CLK_IN1; + end + + // Test sequence + reg [15*8-1:0] test_phase = ""; + initial begin + // Set up any display statements using time to be readable + $timeformat(-12, 2, "ps", 10); + COUNTER_RESET = 0; + test_phase = "reset"; + RESET = 1; + #(PER1*6); + RESET = 0; + test_phase = "wait lock"; + `wait_lock; + #(PER1*6); + COUNTER_RESET = 1; + #(PER1*20) + COUNTER_RESET = 0; + + test_phase = "counting"; + #(PER1*COUNT_PHASE); + + $display("SIMULATION PASSED"); + $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); + $finish; + end + + // Instantiation of the example design containing the clock + // network and sampling counters + //--------------------------------------------------------- + b200_clk_gen_exdes + #( + .TCQ (TCQ) + ) dut + (// Clock in ports + .CLK_IN1_P (CLK_IN1_P), + .CLK_IN1_N (CLK_IN1_N), + // Reset for logic in example design + .COUNTER_RESET (COUNTER_RESET), + .CLK_OUT (CLK_OUT), + // High bits of the counters + .COUNT (COUNT), + // Status and control signals + .RESET (RESET), + .LOCKED (LOCKED)); + +// Freq Check + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simcmds.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simcmds.tcl new file mode 100755 index 000000000..f22f9e447 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simcmds.tcl @@ -0,0 +1,8 @@ +# file: simcmds.tcl + +# create the simulation script +vcd dumpfile isim.vcd +vcd dumpvars -m /b200_clk_gen_tb -l 0 +wave add / +run 50000ns +quit diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.bat b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.bat new file mode 100755 index 000000000..227a07e0c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.bat @@ -0,0 +1,59 @@ +REM file: simulate_isim.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +vlogcomp -work work %XILINX%\verilog\src\glbl.v +vlogcomp -work work ..\..\..\b200_clk_gen.v +vlogcomp -work work ..\..\example_design\b200_clk_gen_exdes.v +vlogcomp -work work ..\b200_clk_gen_tb.v + +REM compile the project +fuse work.b200_clk_gen_tb work.glbl -L unisims_ver -o b200_clk_gen_isim.exe + +REM run the simulation script +.\b200_clk_gen_isim.exe -gui -tclbatch simcmds.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.sh new file mode 100755 index 000000000..db1b8cc4b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.sh @@ -0,0 +1,61 @@ +# file: simulate_isim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# lin64 +# create the project +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +vlogcomp -work work ../../../b200_clk_gen.v +vlogcomp -work work ../../example_design/b200_clk_gen_exdes.v +vlogcomp -work work ../b200_clk_gen_tb.v + +# compile the project +fuse work.b200_clk_gen_tb work.glbl -L unisims_ver -o b200_clk_gen_isim.exe + +# run the simulation script +./b200_clk_gen_isim.exe -gui -tclbatch simcmds.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.bat b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.bat new file mode 100755 index 000000000..86e433ecb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.bat @@ -0,0 +1,61 @@ +REM file: simulate_mti.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM set up the working directory +vlib work + +REM compile all of the files +vlog -work work %XILINX%\verilog\src\glbl.v +vlog -work work ..\..\..\b200_clk_gen.v +vlog -work work ..\..\example_design\b200_clk_gen_exdes.v +vlog -work work ..\b200_clk_gen_tb.v + +REM run the simulation +vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.b200_clk_gen_tb work.glbl + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.do b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.do new file mode 100755 index 000000000..fbb4124b9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.do @@ -0,0 +1,65 @@ +# file: simulate_mti.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $env(XILINX)/verilog/src/glbl.v +vlog -work work ../../../b200_clk_gen.v +vlog -work work ../../example_design/b200_clk_gen_exdes.v +vlog -work work ../b200_clk_gen_tb.v + +# run the simulation +vsim -t ps -voptargs="+acc" -L unisims_ver work.b200_clk_gen_tb work.glbl +do wave.do +log b200_clk_gen_tb/dut/counter +log -r /* +run 50000ns diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.sh new file mode 100755 index 000000000..1d9455134 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.sh @@ -0,0 +1,61 @@ +#/bin/sh +# file: simulate_mti.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $XILINX/verilog/src/glbl.v +vlog -work work ../../../b200_clk_gen.v +vlog -work work ../../example_design/b200_clk_gen_exdes.v +vlog -work work ../b200_clk_gen_tb.v + +# run the simulation +vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.b200_clk_gen_tb work.glbl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_ncsim.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_ncsim.sh new file mode 100755 index 000000000..eeb5b9712 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_ncsim.sh @@ -0,0 +1,62 @@ +#/bin/sh +# file: simulate_ncsim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +mkdir work + +# compile all of the files +ncvlog -work work ${XILINX}/verilog/src/glbl.v +ncvlog -work work ../../../b200_clk_gen.v +ncvlog -work work ../../example_design/b200_clk_gen_exdes.v +ncvlog -work work ../b200_clk_gen_tb.v + +# elaborate and run the simulation +ncelab -work work -access +wc work.b200_clk_gen_tb work.glbl +ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.b200_clk_gen_tb diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_vcs.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_vcs.sh new file mode 100755 index 000000000..66b2cfb09 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_vcs.sh @@ -0,0 +1,72 @@ +#!/bin/sh +# file: simulate_vcs.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# remove old files +rm -rf simv* csrc DVEfiles AN.DB + +# compile all of the files +# Note that -sverilog is not strictly required- You can +# remove the -sverilog if you change the type of the +# localparam for the periods in the testbench file to +# [63:0] from time +vlogan -sverilog \ + ${XILINX}/verilog/src/glbl.v \ + ../../../b200_clk_gen.v \ + ../../example_design/b200_clk_gen_exdes.v \ + ../b200_clk_gen_tb.v + +# prepare the simulation +vcs +vcs+lic+wait -debug b200_clk_gen_tb glbl + +# run the simulation +./simv -ucli -i ucli_commands.key + +# launch the viewer +dve -vpd vcdplus.vpd -session vcs_session.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/ucli_commands.key b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/ucli_commands.key new file mode 100755 index 000000000..d35a8a813 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/ucli_commands.key @@ -0,0 +1,5 @@ +call {$vcdpluson} +call {$vcdplusmemon(b200_clk_gen_tb.dut.counter)} +run +call {$vcdplusclose} +quit diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/vcs_session.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/vcs_session.tcl new file mode 100755 index 000000000..b751d0624 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/vcs_session.tcl @@ -0,0 +1,18 @@ +gui_open_window Wave +gui_sg_create b200_clk_gen_group +gui_list_add_group -id Wave.1 {b200_clk_gen_group} +gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.test_phase} +gui_set_radix -radix {ascii} -signals {b200_clk_gen_tb.test_phase} +gui_sg_addsignal -group b200_clk_gen_group {{Input_clocks}} -divider +gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.CLK_IN1} +gui_sg_addsignal -group b200_clk_gen_group {{Output_clocks}} -divider +gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.dut.clk} +gui_list_expand -id Wave.1 b200_clk_gen_tb.dut.clk +gui_sg_addsignal -group b200_clk_gen_group {{Status_control}} -divider +gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.RESET} +gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.LOCKED} +gui_sg_addsignal -group b200_clk_gen_group {{Counters}} -divider +gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.COUNT} +gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.dut.counter} +gui_list_expand -id Wave.1 b200_clk_gen_tb.dut.counter +gui_zoom -window Wave.1 -full diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.do b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.do new file mode 100755 index 000000000..f05bb5c2e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.do @@ -0,0 +1,60 @@ +# file: wave.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +add wave -noupdate -format Literal -radix ascii /b200_clk_gen_tb/test_phase +add wave -noupdate -divider {Input clocks} +add wave -noupdate -format Logic /b200_clk_gen_tb/CLK_IN1 +add wave -noupdate -divider {Output clocks} +add wave -noupdate -format Literal -expand /b200_clk_gen_tb/dut/clk +add wave -noupdate -divider Status/control +add wave -noupdate -format Logic /b200_clk_gen_tb/RESET +add wave -noupdate -format Logic /b200_clk_gen_tb/LOCKED +add wave -noupdate -divider Counters +add wave -noupdate -format Literal -radix hexadecimal /b200_clk_gen_tb/COUNT +add wave -noupdate -format Literal -radix hexadecimal -expand /b200_clk_gen_tb/dut/counter diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.sv b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.sv new file mode 100755 index 000000000..4bce3bcba --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.sv @@ -0,0 +1,119 @@ +# file: wave.sv +# +# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# Get the windows set up +# +if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} { + window geometry "Design Browser 1" 1054x819+536+322 +} +window target "Design Browser 1" on +browser using {Design Browser 1} +browser set \ + -scope nc::b200_clk_gen_tb +browser yview see nc::b200_clk_gen_tb +browser timecontrol set -lock 0 + +if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} { + window geometry "Waveform 1" 1010x600+0+541 +} +window target "Waveform 1" on +waveform using {Waveform 1} +waveform sidebar visibility partial +waveform set \ + -primarycursor TimeA \ + -signalnames name \ + -signalwidth 175 \ + -units ns \ + -valuewidth 75 +cursor set -using TimeA -time 0 +waveform baseline set -time 0 +waveform xview limits 0 20000n + +# +# Define signal groups +# +catch {group new -name {Output clocks} -overlay 0} +catch {group new -name {Status/control} -overlay 0} +catch {group new -name {Counters} -overlay 0} + +set id [waveform add -signals [list {nc::b200_clk_gen_tb.CLK_IN1}]] + +group using {Output clocks} +group set -overlay 0 +group set -comment {} +group clear 0 end + +group insert \ + {b200_clk_gen_tb.dut.clk[1]} \ + {b200_clk_gen_tb.dut.clk[2]} \ {b200_clk_gen_tb.dut.clk[3]} +group using {Counters} +group set -overlay 0 +group set -comment {} +group clear 0 end + +group insert \ + {b200_clk_gen_tb.dut.counter[1]} \ + {b200_clk_gen_tb.dut.counter[2]} \ {b200_clk_gen_tb.dut.counter[3]} +group using {Status/control} +group set -overlay 0 +group set -comment {} +group clear 0 end + +group insert \ + {nc::b200_clk_gen_tb.RESET} {nc::b200_clk_gen_tb.LOCKED} + + +set id [waveform add -signals [list {nc::b200_clk_gen_tb.COUNT} ]] + +set id [waveform add -signals [list {nc::b200_clk_gen_tb.test_phase} ]] +waveform format $id -radix %a + +set groupId [waveform add -groups {{Input clocks}}] +set groupId [waveform add -groups {{Output clocks}}] +set groupId [waveform add -groups {{Status/control}}] +set groupId [waveform add -groups {{Counters}}] diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/b200_clk_gen_tb.v b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/b200_clk_gen_tb.v new file mode 100755 index 000000000..4d0d01cb0 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/b200_clk_gen_tb.v @@ -0,0 +1,160 @@ +// file: b200_clk_gen_tb.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard demonstration testbench +//---------------------------------------------------------------------------- +// This demonstration testbench instantiates the example design for the +// clocking wizard. Input clocks are toggled, which cause the clocking +// network to lock and the counters to increment. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +`define wait_lock @(posedge LOCKED) + +module b200_clk_gen_tb (); + + // Clock to Q delay of 100ps + localparam TCQ = 100; + + + // timescale is 1ps/1ps + localparam ONE_NS = 1000; + localparam PHASE_ERR_MARGIN = 100; // 100ps + // how many cycles to run + localparam COUNT_PHASE = 1024; + // we'll be using the period in many locations + localparam time PER1 = 25.0*ONE_NS; + localparam time PER1_1 = PER1/2; + localparam time PER1_2 = PER1 - PER1/2; + + // Declare the input clock signals + reg CLK_IN1 = 1; + wire CLK_IN1_P = CLK_IN1; + wire CLK_IN1_N = ~CLK_IN1; + + // The high bits of the sampling counters + wire [3:1] COUNT; + // Status and control signals + reg RESET = 0; + wire LOCKED; + reg COUNTER_RESET = 0; +wire [3:1] CLK_OUT; +//Freq Check using the M & D values setting and actual Frequency generated + + reg [13:0] timeout_counter = 14'b00000000000000; + + // Input clock generation + //------------------------------------ + always begin + CLK_IN1 = #PER1_1 ~CLK_IN1; + CLK_IN1 = #PER1_2 ~CLK_IN1; + end + + // Test sequence + reg [15*8-1:0] test_phase = ""; + initial begin + // Set up any display statements using time to be readable + $timeformat(-12, 2, "ps", 10); + $display ("Timing checks are not valid"); + COUNTER_RESET = 0; + test_phase = "reset"; + RESET = 1; + #(PER1*6); + RESET = 0; + test_phase = "wait lock"; + `wait_lock; + #(PER1*6); + COUNTER_RESET = 1; + #(PER1*19.5) + COUNTER_RESET = 0; + #(PER1*1) + $display ("Timing checks are valid"); + test_phase = "counting"; + #(PER1*COUNT_PHASE); + + $display("SIMULATION PASSED"); + $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); + $finish; + end + + + always@(posedge CLK_IN1) begin + timeout_counter <= timeout_counter + 1'b1; + if (timeout_counter == 14'b10000000000000) begin + if (LOCKED != 1'b1) begin + $display("ERROR : NO LOCK signal"); + $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); + $finish; + end + end + end + + // Instantiation of the example design containing the clock + // network and sampling counters + //--------------------------------------------------------- + b200_clk_gen_exdes + dut + (// Clock in ports + .CLK_IN1_P (CLK_IN1_P), + .CLK_IN1_N (CLK_IN1_N), + // Reset for logic in example design + .COUNTER_RESET (COUNTER_RESET), + .CLK_OUT (CLK_OUT), + // High bits of the counters + .COUNT (COUNT), + // Status and control signals + .RESET (RESET), + .LOCKED (LOCKED)); + + +// Freq Check + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/sdf_cmd_file b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/sdf_cmd_file new file mode 100755 index 000000000..0e8696ce6 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/sdf_cmd_file @@ -0,0 +1,2 @@ +COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X", +SCOPE = b200_clk_gen_tb.dut; diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simcmds.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simcmds.tcl new file mode 100755 index 000000000..00e00dd03 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simcmds.tcl @@ -0,0 +1,9 @@ +# file: simcmds.tcl + +# create the simulation script +vcd dumpfile isim.vcd +vcd dumpvars -m /b200_clk_gen_tb -l 0 +wave add / +run 50000ns +quit + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_isim.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_isim.sh new file mode 100755 index 000000000..edf149164 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_isim.sh @@ -0,0 +1,62 @@ +# file: simulate_isim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# create the project +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +vlogcomp -work work ../../implement/results/routed.v +vlogcomp -work work b200_clk_gen_tb.v + +# compile the project +fuse work.b200_clk_gen_tb work.glbl -L secureip -L simprims_ver -o b200_clk_gen_isim.exe + +# run the simulation script +./b200_clk_gen_isim.exe -tclbatch simcmds.tcl -sdfmax /b200_clk_gen_tb/dut=../../implement/results/routed.sdf + +# run the simulation script +#./b200_clk_gen_isim.exe -gui -tclbatch simcmds.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.bat b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.bat new file mode 100755 index 000000000..b759f9529 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.bat @@ -0,0 +1,59 @@ +REM file: simulate_mti.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM +# set up the working directory +set work work +vlib work + +REM compile all of the files +vlog -work work %XILINX%\verilog\src\glbl.v +vlog -work work ..\..\implement\results\routed.v +vlog -work work b200_clk_gen_tb.v + +REM run the simulation +vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b200_clk_gen_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.b200_clk_gen_tb work.glbl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.do b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.do new file mode 100755 index 000000000..cfe22dc41 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.do @@ -0,0 +1,65 @@ +# file: simulate_mti.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $env(XILINX)/verilog/src/glbl.v +vlog -work work ../../implement/results/routed.v +vlog -work work b200_clk_gen_tb.v + +# run the simulation +vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b200_clk_gen_tb/dut=../../implement/results/routed.sdf +no_notifier work.b200_clk_gen_tb work.glbl +#do wave.do +#log -r /* +run 50000ns + + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.sh new file mode 100755 index 000000000..497db4bbd --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.sh @@ -0,0 +1,61 @@ +#/bin/sh +# file: simulate_mti.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $XILINX/verilog/src/glbl.v +vlog -work work ../../implement/results/routed.v +vlog -work work b200_clk_gen_tb.v + +# run the simulation +vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b200_clk_gen_tb/dut=../../implement/results/routed.sdf +no_notifier work.b200_clk_gen_tb work.glbl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_ncsim.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_ncsim.sh new file mode 100755 index 000000000..8dd610f57 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_ncsim.sh @@ -0,0 +1,64 @@ +#!/bin/sh +# file: simulate_ncsim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +mkdir work + +# compile all of the files +ncvlog -work work ${XILINX}/verilog/src/glbl.v +ncvlog -work work ../../implement/results/routed.v +ncvlog -work work b200_clk_gen_tb.v + +# elaborate and run the simulation +ncsdfc ../../implement/results/routed.sdf + +ncelab -work work -access +wc -pulse_r 10 -nonotifier work.b200_clk_gen_tb work.glbl -sdf_cmd_file sdf_cmd_file +ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.b200_clk_gen_tb + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_vcs.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_vcs.sh new file mode 100755 index 000000000..3566700b2 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_vcs.sh @@ -0,0 +1,72 @@ +#!/bin/sh +# file: simulate_vcs.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# remove old files +rm -rf simv* csrc DVEfiles AN.DB + +# compile all of the files +# Note that -sverilog is not strictly required- You can +# remove the -sverilog if you change the type of the +# localparam for the periods in the testbench file to +# [63:0] from time + vlogan -sverilog \ + b200_clk_gen_tb.v \ + ../../implement/results/routed.v + + +# prepare the simulation +vcs -sdf max:b200_clk_gen_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \ + +libext+.v -debug b200_clk_gen_tb.v ../../implement/results/routed.v + +# run the simulation +./simv -ucli -i ucli_commands.key + +# launch the viewer +#dve -vpd vcdplus.vpd -session vcs_session.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/ucli_commands.key b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/ucli_commands.key new file mode 100755 index 000000000..0548d1733 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/ucli_commands.key @@ -0,0 +1,5 @@ + +call {$vcdpluson} +run 50000ns +call {$vcdplusclose} +quit diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/vcs_session.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/vcs_session.tcl new file mode 100755 index 000000000..1438f6bed --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/vcs_session.tcl @@ -0,0 +1 @@ +gui_open_window Wave diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/wave.do b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/wave.do new file mode 100755 index 000000000..048ce6aa6 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/wave.do @@ -0,0 +1,72 @@ +# file: wave.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /b200_clk_gen_tb/CLK_IN1 +add wave -noupdate /b200_clk_gen_tb/COUNT +add wave -noupdate /b200_clk_gen_tb/LOCKED +add wave -noupdate /b200_clk_gen_tb/RESET +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {3223025 ps} 0} +configure wave -namecolwidth 238 +configure wave -valuecolwidth 107 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {74848022 ps} diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen_flist.txt b/fpga/usrp3/top/b200/coregen/b200_clk_gen_flist.txt new file mode 100644 index 000000000..044c06a12 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen_flist.txt @@ -0,0 +1,53 @@ +# Output products list for +b200_clk_gen/clk_wiz_v3_6_readme.txt +b200_clk_gen/doc/clk_wiz_v3_6_readme.txt +b200_clk_gen/doc/clk_wiz_v3_6_vinfo.html +b200_clk_gen/doc/pg065_clk_wiz.pdf +b200_clk_gen/example_design/b200_clk_gen_exdes.ucf +b200_clk_gen/example_design/b200_clk_gen_exdes.v +b200_clk_gen/example_design/b200_clk_gen_exdes.xdc +b200_clk_gen/implement/implement.bat +b200_clk_gen/implement/implement.sh +b200_clk_gen/implement/planAhead_ise.bat +b200_clk_gen/implement/planAhead_ise.sh +b200_clk_gen/implement/planAhead_ise.tcl +b200_clk_gen/implement/planAhead_rdn.bat +b200_clk_gen/implement/planAhead_rdn.sh +b200_clk_gen/implement/planAhead_rdn.tcl +b200_clk_gen/implement/xst.prj +b200_clk_gen/implement/xst.scr +b200_clk_gen/simulation/b200_clk_gen_tb.v +b200_clk_gen/simulation/functional/simcmds.tcl +b200_clk_gen/simulation/functional/simulate_isim.bat +b200_clk_gen/simulation/functional/simulate_isim.sh +b200_clk_gen/simulation/functional/simulate_mti.bat +b200_clk_gen/simulation/functional/simulate_mti.do +b200_clk_gen/simulation/functional/simulate_mti.sh +b200_clk_gen/simulation/functional/simulate_ncsim.sh +b200_clk_gen/simulation/functional/simulate_vcs.sh +b200_clk_gen/simulation/functional/ucli_commands.key +b200_clk_gen/simulation/functional/vcs_session.tcl +b200_clk_gen/simulation/functional/wave.do +b200_clk_gen/simulation/functional/wave.sv +b200_clk_gen/simulation/timing/b200_clk_gen_tb.v +b200_clk_gen/simulation/timing/sdf_cmd_file +b200_clk_gen/simulation/timing/simcmds.tcl +b200_clk_gen/simulation/timing/simulate_isim.sh +b200_clk_gen/simulation/timing/simulate_mti.bat +b200_clk_gen/simulation/timing/simulate_mti.do +b200_clk_gen/simulation/timing/simulate_mti.sh +b200_clk_gen/simulation/timing/simulate_ncsim.sh +b200_clk_gen/simulation/timing/simulate_vcs.sh +b200_clk_gen/simulation/timing/ucli_commands.key +b200_clk_gen/simulation/timing/vcs_session.tcl +b200_clk_gen/simulation/timing/wave.do +b200_clk_gen.asy +b200_clk_gen.gise +b200_clk_gen.ucf +b200_clk_gen.v +b200_clk_gen.veo +b200_clk_gen.xco +b200_clk_gen.xdc +b200_clk_gen.xise +b200_clk_gen_flist.txt +b200_clk_gen_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen_xmdf.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen_xmdf.tcl new file mode 100755 index 000000000..58f510c56 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen_xmdf.tcl @@ -0,0 +1,144 @@ +# The package naming convention is _xmdf +package provide b200_clk_gen_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::b200_clk_gen_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::b200_clk_gen_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name b200_clk_gen +} +# ::b200_clk_gen_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::b200_clk_gen_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/clk_wiz_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/example_design/b200_clk_gen_exdes.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/doc/clk_wiz_ds709.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/doc/clk_wiz_gsg521.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/example_design/b200_clk_gen_exdes.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/implement/implement.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/implement/implement.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/implement/xst.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/implement/xst.scr +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/b200_clk_gen_tb.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simcmds.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/wave.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/wave.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.ejp +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module b200_clk_gen +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.asy b/fpga/usrp3/top/b200/coregen/chipscope_icon.asy new file mode 100644 index 000000000..a0153d32c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.asy @@ -0,0 +1,9 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 chipscope_icon +RECTANGLE Normal 32 32 544 864 +LINE Wide 576 112 544 112 +PIN 576 112 RIGHT 36 +PINATTR PinName control0[35:0] +PINATTR Polarity BOTH + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.ucf b/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.ucf new file mode 100644 index 000000000..b83296f8e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.ucf @@ -0,0 +1,9 @@ +NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ; +TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ; +#Update Constraints +NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ; +NET "U0/iSHIFT_OUT" TIG ; +TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ; +TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ; +TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ; +TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ; diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.xdc b/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.xdc new file mode 100644 index 000000000..903799425 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.xdc @@ -0,0 +1,7 @@ +# icon XDC +create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] +create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}] +set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}] +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2 +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1 +set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK} diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.ncf b/fpga/usrp3/top/b200/coregen/chipscope_icon.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.ngc b/fpga/usrp3/top/b200/coregen/chipscope_icon.ngc new file mode 100644 index 000000000..db921aaf5 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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3`=l2.357?6d:k5=?6=3`j0;66a72;29?xde?3:197>50z&:e?1>3A;3>6F>7e9'<6<6j<1/:k4l;%::>4?b3`<26=44i7c94?=n>k0;66g9c;29?j>52900qol9:186>5<7s-3j6:74H0:1?M70l2.3?7?m5:&5b?g<,131=4k4i7;94?=n>h0;66g9b;29?l0d2900c5<50;9~fg3=83?1<7>t$8c93<=O9180D<9k;%:0>4d23-00;66g9a;29?l0e2900e;m50;9l<7<722win94?:483>5}#1h0<56F>839K52b<,191=o;4$7d9<>"?13;2j6g99;29?l0f2900e;l50;9j2f<722e3>7>5;|`a7?6==3:1o0<7)66:0c3?l0>2900e;o50;9j2g<722c=o7>5;n:1>5<30D<6=;I34`>"?;3;i96*9f;48 =?=9h:0e;750;9j2d<722c=n7>5;h4`>5<a09j2<<722c=m7>5;h4a>5<>{ej90;684?:1y'=d<012B:4?5G16f8 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.ucf b/fpga/usrp3/top/b200/coregen/chipscope_icon.ucf new file mode 100644 index 000000000..b83296f8e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.ucf @@ -0,0 +1,9 @@ +NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ; +TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ; +#Update Constraints +NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ; +NET "U0/iSHIFT_OUT" TIG ; +TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ; +TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ; +TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ; +TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ; diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.v b/fpga/usrp3/top/b200/coregen/chipscope_icon.v new file mode 100644 index 000000000..fe9223442 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.v @@ -0,0 +1,27 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : chipscope_icon.v +// /___/ /\ Timestamp : Tue Oct 22 17:04:59 PDT 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: Verilog Synthesis Wrapper +/////////////////////////////////////////////////////////////////////////////// +// This wrapper is used to integrate with Project Navigator and PlanAhead + +`timescale 1ns/1ps + +module chipscope_icon( + CONTROL0) /* synthesis syn_black_box syn_noprune=1 */; + + +inout [35 : 0] CONTROL0; + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.veo b/fpga/usrp3/top/b200/coregen/chipscope_icon.veo new file mode 100644 index 000000000..cf73c9226 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.veo @@ -0,0 +1,28 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : chipscope_icon.veo +// /___/ /\ Timestamp : Tue Oct 22 17:05:00 PDT 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: ISE Instantiation template +/////////////////////////////////////////////////////////////////////////////// + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +chipscope_icon YourInstanceName ( + .CONTROL0(CONTROL0) // INOUT BUS [35:0] +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.xco b/fpga/usrp3/top/b200/coregen/chipscope_icon.xco new file mode 100644 index 000000000..3d4beaaa0 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.xco @@ -0,0 +1,56 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Wed Oct 23 00:04:31 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Structural +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a +# END Select +# BEGIN Parameters +CSET component_name=chipscope_icon +CSET constraint_type=external +CSET enable_jtag_bufg=true +CSET example_design=false +CSET number_control_ports=1 +CSET use_ext_bscan=false +CSET use_softbscan=false +CSET use_unused_bscan=false +CSET user_scan_chain=USER1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-12-18T02:47:25Z +# END Extra information +GENERATE +# CRC: 5ccf4baf diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.xdc b/fpga/usrp3/top/b200/coregen/chipscope_icon.xdc new file mode 100644 index 000000000..903799425 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.xdc @@ -0,0 +1,7 @@ +# icon XDC +create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] +create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}] +set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}] +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2 +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1 +set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK} diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon_flist.txt b/fpga/usrp3/top/b200/coregen/chipscope_icon_flist.txt new file mode 100644 index 000000000..435dc80e2 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon_flist.txt @@ -0,0 +1,16 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +chipscope_icon.asy +chipscope_icon.constraints/chipscope_icon.ucf +chipscope_icon.constraints/chipscope_icon.xdc +chipscope_icon.gise +chipscope_icon.ngc +chipscope_icon.ucf +chipscope_icon.v +chipscope_icon.veo +chipscope_icon.xco +chipscope_icon.xdc +chipscope_icon.xise +chipscope_icon_flist.txt +chipscope_icon_readme.txt +chipscope_icon_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon_readme.txt b/fpga/usrp3/top/b200/coregen/chipscope_icon_readme.txt new file mode 100644 index 000000000..88118d782 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon_readme.txt @@ -0,0 +1,46 @@ +The following files were generated for 'chipscope_icon' in directory +/home/ianb/fpgadev/usrp3/top/b200/coregen/ + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * chipscope_icon.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * chipscope_icon.constraints/chipscope_icon.ucf + * chipscope_icon.constraints/chipscope_icon.xdc + * chipscope_icon.ngc + * chipscope_icon.ucf + * chipscope_icon.v + * chipscope_icon.veo + * chipscope_icon.xdc + * chipscope_icon_xmdf.tcl + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * chipscope_icon.asy + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * _xmsgs/pn_parser.xmsgs + * chipscope_icon.gise + * chipscope_icon.xise + +Deliver Readme: + Readme file for the IP. + + * chipscope_icon_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * chipscope_icon_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon_xmdf.tcl b/fpga/usrp3/top/b200/coregen/chipscope_icon_xmdf.tcl new file mode 100755 index 000000000..241f4d5ae --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon_xmdf.tcl @@ -0,0 +1,88 @@ +# The package naming convention is _xmdf +package provide chipscope_icon_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::chipscope_icon_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::chipscope_icon_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_icon +} +# ::chipscope_icon_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::chipscope_icon_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.constraints/chipscope_icon.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.ncf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.constraints/chipscope_icon.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.xcf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_icon +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams + + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.asy b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.asy new file mode 100644 index 000000000..5342fbe4f --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.asy @@ -0,0 +1,17 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 chipscope_ila_128 +RECTANGLE Normal 32 32 288 704 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName control[35:0] +PINATTR Polarity IN +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Wide 0 176 32 176 +PIN 0 176 LEFT 36 +PINATTR PinName trig0[127:0] +PINATTR Polarity IN + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.cdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.cdc new file mode 100644 index 000000000..9b29ca86f --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.cdc @@ -0,0 +1,144 @@ +#ChipScope Core Generator Project File Version 3.0 +#Tue Oct 22 15:45:46 PDT 2013 +SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 +SignalExport.bus<0000>.name=TRIG0 +SignalExport.bus<0000>.offset=0.0 +SignalExport.bus<0000>.precision=0 +SignalExport.bus<0000>.radix=Bin +SignalExport.bus<0000>.scaleFactor=1.0 +SignalExport.clockChannel=CLK +SignalExport.dataEqualsTrigger=true +SignalExport.triggerChannel<0000><0000>=TRIG0[0] +SignalExport.triggerChannel<0000><0001>=TRIG0[1] +SignalExport.triggerChannel<0000><0002>=TRIG0[2] +SignalExport.triggerChannel<0000><0003>=TRIG0[3] +SignalExport.triggerChannel<0000><0004>=TRIG0[4] +SignalExport.triggerChannel<0000><0005>=TRIG0[5] +SignalExport.triggerChannel<0000><0006>=TRIG0[6] +SignalExport.triggerChannel<0000><0007>=TRIG0[7] +SignalExport.triggerChannel<0000><0008>=TRIG0[8] +SignalExport.triggerChannel<0000><0009>=TRIG0[9] +SignalExport.triggerChannel<0000><0010>=TRIG0[10] +SignalExport.triggerChannel<0000><0011>=TRIG0[11] +SignalExport.triggerChannel<0000><0012>=TRIG0[12] +SignalExport.triggerChannel<0000><0013>=TRIG0[13] +SignalExport.triggerChannel<0000><0014>=TRIG0[14] +SignalExport.triggerChannel<0000><0015>=TRIG0[15] +SignalExport.triggerChannel<0000><0016>=TRIG0[16] +SignalExport.triggerChannel<0000><0017>=TRIG0[17] +SignalExport.triggerChannel<0000><0018>=TRIG0[18] +SignalExport.triggerChannel<0000><0019>=TRIG0[19] +SignalExport.triggerChannel<0000><0020>=TRIG0[20] +SignalExport.triggerChannel<0000><0021>=TRIG0[21] +SignalExport.triggerChannel<0000><0022>=TRIG0[22] +SignalExport.triggerChannel<0000><0023>=TRIG0[23] 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+SignalExport.triggerChannel<0000><0119>=TRIG0[119] +SignalExport.triggerChannel<0000><0120>=TRIG0[120] +SignalExport.triggerChannel<0000><0121>=TRIG0[121] +SignalExport.triggerChannel<0000><0122>=TRIG0[122] +SignalExport.triggerChannel<0000><0123>=TRIG0[123] +SignalExport.triggerChannel<0000><0124>=TRIG0[124] +SignalExport.triggerChannel<0000><0125>=TRIG0[125] +SignalExport.triggerChannel<0000><0126>=TRIG0[126] +SignalExport.triggerChannel<0000><0127>=TRIG0[127] +SignalExport.triggerPort<0000>.name=TRIG0 +SignalExport.triggerPortCount=1 +SignalExport.triggerPortIsData<0000>=true +SignalExport.triggerPortWidth<0000>=128 +SignalExport.type=ila + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.ucf b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.ucf new file mode 100644 index 000000000..736db76a7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.ucf @@ -0,0 +1,15 @@ +# +# Clock constraints +# +NET "CLK" TNM_NET = D_CLK ; +INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; +TIMESPEC TS_D2_TO_T2_chipscope_ila_128 = FROM D2_CLK TO "FFS" TIG; +TIMESPEC TS_J2_TO_D2_chipscope_ila_128 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J3_TO_D2_chipscope_ila_128 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J4_TO_D2_chipscope_ila_128 = FROM "FFS" TO D2_CLK TIG; + +# +# Input keep/save net constraints +# +NET "TRIG0<*" S; +NET "TRIG0<*" KEEP; diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.xdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.xdc new file mode 100644 index 000000000..49e2b9e7b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.xdc @@ -0,0 +1,6 @@ +# +# Clock constraints +# +set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] +set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] +set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ncf b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ngc b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ngc new file mode 100644 index 000000000..278d4f046 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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+_xmsgs/pn_parser.xmsgs +chipscope_ila_128.asy +chipscope_ila_128.cdc +chipscope_ila_128.constraints/chipscope_ila_128.ucf +chipscope_ila_128.constraints/chipscope_ila_128.xdc +chipscope_ila_128.gise +chipscope_ila_128.ncf +chipscope_ila_128.ngc +chipscope_ila_128.ucf +chipscope_ila_128.v +chipscope_ila_128.veo +chipscope_ila_128.xco +chipscope_ila_128.xdc +chipscope_ila_128.xise +chipscope_ila_128_flist.txt +chipscope_ila_128_readme.txt +chipscope_ila_128_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128_readme.txt b/fpga/usrp3/top/b200/coregen/chipscope_ila_128_readme.txt new file mode 100644 index 000000000..fbcd6cbfb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128_readme.txt @@ -0,0 +1,48 @@ +The following files were generated for 'chipscope_ila_128' in directory +/home/ianb/fpgadev/usrp3/top/b200/coregen/ + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * chipscope_ila_128.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * chipscope_ila_128.cdc + * chipscope_ila_128.constraints/chipscope_ila_128.ucf + * chipscope_ila_128.constraints/chipscope_ila_128.xdc + * chipscope_ila_128.ncf + * chipscope_ila_128.ngc + * chipscope_ila_128.ucf + * chipscope_ila_128.v + * chipscope_ila_128.veo + * chipscope_ila_128.xdc + * chipscope_ila_128_xmdf.tcl + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * chipscope_ila_128.asy + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * _xmsgs/pn_parser.xmsgs + * chipscope_ila_128.gise + * chipscope_ila_128.xise + +Deliver Readme: + Readme file for the IP. + + * chipscope_ila_128_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * chipscope_ila_128_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128_xmdf.tcl b/fpga/usrp3/top/b200/coregen/chipscope_ila_128_xmdf.tcl new file mode 100755 index 000000000..e4af2b327 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128_xmdf.tcl @@ -0,0 +1,87 @@ +# The package naming convention is _xmdf +package provide chipscope_ila_128_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::chipscope_ila_128_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::chipscope_ila_128_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_ila_128 +} +# ::chipscope_ila_128_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::chipscope_ila_128_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.cdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.constraints/chipscope_ila_128.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.ncf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.constraints/chipscope_ila_128.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_ila_128 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.asy b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.asy new file mode 100644 index 000000000..3eef48558 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.asy @@ -0,0 +1,17 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 chipscope_ila_256 +RECTANGLE Normal 32 32 288 704 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName control[35:0] +PINATTR Polarity IN +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Wide 0 176 32 176 +PIN 0 176 LEFT 36 +PINATTR PinName trig0[255:0] +PINATTR Polarity IN + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.cdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.cdc new file mode 100644 index 000000000..562f53ff9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.cdc @@ -0,0 +1,272 @@ +#ChipScope Core Generator Project File Version 3.0 +#Fri Mar 08 16:13:02 PST 2013 +SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 +SignalExport.bus<0000>.name=TRIG0 +SignalExport.bus<0000>.offset=0.0 +SignalExport.bus<0000>.precision=0 +SignalExport.bus<0000>.radix=Bin +SignalExport.bus<0000>.scaleFactor=1.0 +SignalExport.clockChannel=CLK +SignalExport.dataEqualsTrigger=true +SignalExport.triggerChannel<0000><0000>=TRIG0[0] +SignalExport.triggerChannel<0000><0001>=TRIG0[1] +SignalExport.triggerChannel<0000><0002>=TRIG0[2] +SignalExport.triggerChannel<0000><0003>=TRIG0[3] +SignalExport.triggerChannel<0000><0004>=TRIG0[4] +SignalExport.triggerChannel<0000><0005>=TRIG0[5] +SignalExport.triggerChannel<0000><0006>=TRIG0[6] +SignalExport.triggerChannel<0000><0007>=TRIG0[7] +SignalExport.triggerChannel<0000><0008>=TRIG0[8] +SignalExport.triggerChannel<0000><0009>=TRIG0[9] +SignalExport.triggerChannel<0000><0010>=TRIG0[10] +SignalExport.triggerChannel<0000><0011>=TRIG0[11] +SignalExport.triggerChannel<0000><0012>=TRIG0[12] +SignalExport.triggerChannel<0000><0013>=TRIG0[13] +SignalExport.triggerChannel<0000><0014>=TRIG0[14] +SignalExport.triggerChannel<0000><0015>=TRIG0[15] +SignalExport.triggerChannel<0000><0016>=TRIG0[16] +SignalExport.triggerChannel<0000><0017>=TRIG0[17] +SignalExport.triggerChannel<0000><0018>=TRIG0[18] +SignalExport.triggerChannel<0000><0019>=TRIG0[19] +SignalExport.triggerChannel<0000><0020>=TRIG0[20] +SignalExport.triggerChannel<0000><0021>=TRIG0[21] +SignalExport.triggerChannel<0000><0022>=TRIG0[22] +SignalExport.triggerChannel<0000><0023>=TRIG0[23] +SignalExport.triggerChannel<0000><0024>=TRIG0[24] +SignalExport.triggerChannel<0000><0025>=TRIG0[25] +SignalExport.triggerChannel<0000><0026>=TRIG0[26] +SignalExport.triggerChannel<0000><0027>=TRIG0[27] +SignalExport.triggerChannel<0000><0028>=TRIG0[28] +SignalExport.triggerChannel<0000><0029>=TRIG0[29] +SignalExport.triggerChannel<0000><0030>=TRIG0[30] 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+SignalExport.triggerChannel<0000><0050>=TRIG0[50] +SignalExport.triggerChannel<0000><0051>=TRIG0[51] +SignalExport.triggerChannel<0000><0052>=TRIG0[52] +SignalExport.triggerChannel<0000><0053>=TRIG0[53] +SignalExport.triggerChannel<0000><0054>=TRIG0[54] +SignalExport.triggerChannel<0000><0055>=TRIG0[55] +SignalExport.triggerChannel<0000><0056>=TRIG0[56] +SignalExport.triggerChannel<0000><0057>=TRIG0[57] +SignalExport.triggerChannel<0000><0058>=TRIG0[58] +SignalExport.triggerChannel<0000><0059>=TRIG0[59] +SignalExport.triggerChannel<0000><0060>=TRIG0[60] +SignalExport.triggerChannel<0000><0061>=TRIG0[61] +SignalExport.triggerChannel<0000><0062>=TRIG0[62] +SignalExport.triggerChannel<0000><0063>=TRIG0[63] +SignalExport.triggerChannel<0000><0064>=TRIG0[64] +SignalExport.triggerChannel<0000><0065>=TRIG0[65] +SignalExport.triggerChannel<0000><0066>=TRIG0[66] +SignalExport.triggerChannel<0000><0067>=TRIG0[67] +SignalExport.triggerChannel<0000><0068>=TRIG0[68] +SignalExport.triggerChannel<0000><0069>=TRIG0[69] +SignalExport.triggerChannel<0000><0070>=TRIG0[70] +SignalExport.triggerChannel<0000><0071>=TRIG0[71] +SignalExport.triggerChannel<0000><0072>=TRIG0[72] +SignalExport.triggerChannel<0000><0073>=TRIG0[73] +SignalExport.triggerChannel<0000><0074>=TRIG0[74] +SignalExport.triggerChannel<0000><0075>=TRIG0[75] +SignalExport.triggerChannel<0000><0076>=TRIG0[76] +SignalExport.triggerChannel<0000><0077>=TRIG0[77] +SignalExport.triggerChannel<0000><0078>=TRIG0[78] +SignalExport.triggerChannel<0000><0079>=TRIG0[79] +SignalExport.triggerChannel<0000><0080>=TRIG0[80] +SignalExport.triggerChannel<0000><0081>=TRIG0[81] +SignalExport.triggerChannel<0000><0082>=TRIG0[82] +SignalExport.triggerChannel<0000><0083>=TRIG0[83] +SignalExport.triggerChannel<0000><0084>=TRIG0[84] +SignalExport.triggerChannel<0000><0085>=TRIG0[85] +SignalExport.triggerChannel<0000><0086>=TRIG0[86] +SignalExport.triggerChannel<0000><0087>=TRIG0[87] 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+SignalExport.triggerChannel<0000><0107>=TRIG0[107] +SignalExport.triggerChannel<0000><0108>=TRIG0[108] +SignalExport.triggerChannel<0000><0109>=TRIG0[109] +SignalExport.triggerChannel<0000><0110>=TRIG0[110] +SignalExport.triggerChannel<0000><0111>=TRIG0[111] +SignalExport.triggerChannel<0000><0112>=TRIG0[112] +SignalExport.triggerChannel<0000><0113>=TRIG0[113] +SignalExport.triggerChannel<0000><0114>=TRIG0[114] +SignalExport.triggerChannel<0000><0115>=TRIG0[115] +SignalExport.triggerChannel<0000><0116>=TRIG0[116] +SignalExport.triggerChannel<0000><0117>=TRIG0[117] +SignalExport.triggerChannel<0000><0118>=TRIG0[118] +SignalExport.triggerChannel<0000><0119>=TRIG0[119] +SignalExport.triggerChannel<0000><0120>=TRIG0[120] +SignalExport.triggerChannel<0000><0121>=TRIG0[121] +SignalExport.triggerChannel<0000><0122>=TRIG0[122] +SignalExport.triggerChannel<0000><0123>=TRIG0[123] +SignalExport.triggerChannel<0000><0124>=TRIG0[124] +SignalExport.triggerChannel<0000><0125>=TRIG0[125] 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+SignalExport.triggerChannel<0000><0240>=TRIG0[240] +SignalExport.triggerChannel<0000><0241>=TRIG0[241] +SignalExport.triggerChannel<0000><0242>=TRIG0[242] +SignalExport.triggerChannel<0000><0243>=TRIG0[243] +SignalExport.triggerChannel<0000><0244>=TRIG0[244] +SignalExport.triggerChannel<0000><0245>=TRIG0[245] +SignalExport.triggerChannel<0000><0246>=TRIG0[246] +SignalExport.triggerChannel<0000><0247>=TRIG0[247] +SignalExport.triggerChannel<0000><0248>=TRIG0[248] +SignalExport.triggerChannel<0000><0249>=TRIG0[249] +SignalExport.triggerChannel<0000><0250>=TRIG0[250] +SignalExport.triggerChannel<0000><0251>=TRIG0[251] +SignalExport.triggerChannel<0000><0252>=TRIG0[252] +SignalExport.triggerChannel<0000><0253>=TRIG0[253] +SignalExport.triggerChannel<0000><0254>=TRIG0[254] +SignalExport.triggerChannel<0000><0255>=TRIG0[255] +SignalExport.triggerPort<0000>.name=TRIG0 +SignalExport.triggerPortCount=1 +SignalExport.triggerPortIsData<0000>=true +SignalExport.triggerPortWidth<0000>=256 +SignalExport.type=ila + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.ucf b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.ucf new file mode 100644 index 000000000..b458eed9c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.ucf @@ -0,0 +1,15 @@ +# +# Clock constraints +# +NET "CLK" TNM_NET = D_CLK ; +INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; +TIMESPEC TS_D2_TO_T2_chipscope_ila_256 = FROM D2_CLK TO "FFS" TIG; +TIMESPEC TS_J2_TO_D2_chipscope_ila_256 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J3_TO_D2_chipscope_ila_256 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J4_TO_D2_chipscope_ila_256 = FROM "FFS" TO D2_CLK TIG; + +# +# Input keep/save net constraints +# +NET "TRIG0<*" S; +NET "TRIG0<*" KEEP; diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.xdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.xdc new file mode 100644 index 000000000..49e2b9e7b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.xdc @@ -0,0 +1,6 @@ +# +# Clock constraints +# +set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] +set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] +set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ncf b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ngc b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ngc new file mode 100644 index 000000000..e6dfef4e8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ucf b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ucf new file mode 100644 index 000000000..b458eed9c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ucf @@ -0,0 +1,15 @@ +# +# Clock constraints +# +NET "CLK" TNM_NET = D_CLK ; +INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; +TIMESPEC TS_D2_TO_T2_chipscope_ila_256 = FROM D2_CLK TO "FFS" TIG; +TIMESPEC TS_J2_TO_D2_chipscope_ila_256 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J3_TO_D2_chipscope_ila_256 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J4_TO_D2_chipscope_ila_256 = FROM "FFS" TO D2_CLK TIG; + +# +# Input keep/save net constraints +# +NET "TRIG0<*" S; +NET "TRIG0<*" KEEP; diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.v b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.v new file mode 100644 index 000000000..2f0ec9349 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.v @@ -0,0 +1,31 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : chipscope_ila_256.v +// /___/ /\ Timestamp : Fri Mar 08 16:13:02 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: Verilog Synthesis Wrapper +/////////////////////////////////////////////////////////////////////////////// +// This wrapper is used to integrate with Project Navigator and PlanAhead + +`timescale 1ns/1ps + +module chipscope_ila_256( + CONTROL, + CLK, + TRIG0) /* synthesis syn_black_box syn_noprune=1 */; + + +inout [35 : 0] CONTROL; +input CLK; +input [255 : 0] TRIG0; + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.veo b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.veo new file mode 100644 index 000000000..201512ffb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.veo @@ -0,0 +1,30 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : chipscope_ila_256.veo +// /___/ /\ Timestamp : Fri Mar 08 16:13:02 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: ISE Instantiation template +/////////////////////////////////////////////////////////////////////////////// + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +chipscope_ila_256 YourInstanceName ( + .CONTROL(CONTROL), // INOUT BUS [35:0] + .CLK(CLK), // IN + .TRIG0(TRIG0) // IN BUS [255:0] +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xco b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xco new file mode 100644 index 000000000..4272296fc --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xco @@ -0,0 +1,141 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Sat Mar 9 00:11:24 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a +# END Select +# BEGIN Parameters +CSET check_bramcount=false +CSET component_name=chipscope_ila_256 +CSET constraint_type=external +CSET counter_width_1=Disabled +CSET counter_width_10=Disabled +CSET counter_width_11=Disabled +CSET counter_width_12=Disabled +CSET counter_width_13=Disabled +CSET counter_width_14=Disabled +CSET counter_width_15=Disabled +CSET counter_width_16=Disabled +CSET counter_width_2=Disabled +CSET counter_width_3=Disabled +CSET counter_width_4=Disabled +CSET counter_width_5=Disabled +CSET counter_width_6=Disabled +CSET counter_width_7=Disabled +CSET counter_width_8=Disabled +CSET counter_width_9=Disabled +CSET data_port_width=0 +CSET data_same_as_trigger=true +CSET disable_save_keep=false +CSET enable_storage_qualification=true +CSET enable_trigger_output_port=false +CSET example_design=false +CSET exclude_from_data_storage_1=false +CSET exclude_from_data_storage_10=false +CSET exclude_from_data_storage_11=false +CSET exclude_from_data_storage_12=false +CSET exclude_from_data_storage_13=false +CSET exclude_from_data_storage_14=false +CSET exclude_from_data_storage_15=false +CSET exclude_from_data_storage_16=false +CSET exclude_from_data_storage_2=false +CSET exclude_from_data_storage_3=false +CSET exclude_from_data_storage_4=false +CSET exclude_from_data_storage_5=false +CSET exclude_from_data_storage_6=false +CSET exclude_from_data_storage_7=false +CSET exclude_from_data_storage_8=false +CSET exclude_from_data_storage_9=false +CSET match_type_1=basic_with_edges +CSET match_type_10=basic_with_edges +CSET match_type_11=basic_with_edges +CSET match_type_12=basic_with_edges +CSET match_type_13=basic_with_edges +CSET match_type_14=basic_with_edges +CSET match_type_15=basic_with_edges +CSET match_type_16=basic_with_edges +CSET match_type_2=basic_with_edges +CSET match_type_3=basic_with_edges +CSET match_type_4=basic_with_edges +CSET match_type_5=basic_with_edges +CSET match_type_6=basic_with_edges +CSET match_type_7=basic_with_edges +CSET match_type_8=basic_with_edges +CSET match_type_9=basic_with_edges +CSET match_units_1=1 +CSET match_units_10=1 +CSET match_units_11=1 +CSET match_units_12=1 +CSET match_units_13=1 +CSET match_units_14=1 +CSET match_units_15=1 +CSET match_units_16=1 +CSET match_units_2=1 +CSET match_units_3=1 +CSET match_units_4=1 +CSET match_units_5=1 +CSET match_units_6=1 +CSET match_units_7=1 +CSET match_units_8=1 +CSET match_units_9=1 +CSET max_sequence_levels=1 +CSET number_of_trigger_ports=1 +CSET sample_data_depth=1024 +CSET sample_on=Rising +CSET trigger_port_width_1=256 +CSET trigger_port_width_10=8 +CSET trigger_port_width_11=8 +CSET trigger_port_width_12=8 +CSET trigger_port_width_13=8 +CSET trigger_port_width_14=8 +CSET trigger_port_width_15=8 +CSET trigger_port_width_16=8 +CSET trigger_port_width_2=8 +CSET trigger_port_width_3=8 +CSET trigger_port_width_4=8 +CSET trigger_port_width_5=8 +CSET trigger_port_width_6=8 +CSET trigger_port_width_7=8 +CSET trigger_port_width_8=8 +CSET trigger_port_width_9=8 +CSET use_rpms=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-12-18T02:47:40Z +# END Extra information +GENERATE +# CRC: b8a8f4bd diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xdc new file mode 100644 index 000000000..49e2b9e7b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xdc @@ -0,0 +1,6 @@ +# +# Clock constraints +# +set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] +set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] +set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256_flist.txt b/fpga/usrp3/top/b200/coregen/chipscope_ila_256_flist.txt new file mode 100644 index 000000000..da4f99bbe --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256_flist.txt @@ -0,0 +1,18 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +chipscope_ila_256.asy +chipscope_ila_256.cdc +chipscope_ila_256.constraints/chipscope_ila_256.ucf +chipscope_ila_256.constraints/chipscope_ila_256.xdc +chipscope_ila_256.gise +chipscope_ila_256.ncf +chipscope_ila_256.ngc +chipscope_ila_256.ucf +chipscope_ila_256.v +chipscope_ila_256.veo +chipscope_ila_256.xco +chipscope_ila_256.xdc +chipscope_ila_256.xise +chipscope_ila_256_flist.txt +chipscope_ila_256_readme.txt +chipscope_ila_256_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256_readme.txt b/fpga/usrp3/top/b200/coregen/chipscope_ila_256_readme.txt new file mode 100644 index 000000000..764247d3b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256_readme.txt @@ -0,0 +1,53 @@ +The following files were generated for 'chipscope_ila_256' in directory +/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b200/coregen/ + +ISE file generator: + Add description here... + + * chipscope_ila_32_flist.txt + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * chipscope_ila_256.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * chipscope_ila_256.cdc + * chipscope_ila_256.constraints/chipscope_ila_256.ucf + * chipscope_ila_256.constraints/chipscope_ila_256.xdc + * chipscope_ila_256.ncf + * chipscope_ila_256.ngc + * chipscope_ila_256.ucf + * chipscope_ila_256.v + * chipscope_ila_256.veo + * chipscope_ila_256.xdc + * chipscope_ila_256_xmdf.tcl + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * chipscope_ila_256.asy + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * _xmsgs/pn_parser.xmsgs + * chipscope_ila_256.gise + * chipscope_ila_256.xise + +Deliver Readme: + Readme file for the IP. + + * chipscope_ila_256_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * chipscope_ila_256_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256_xmdf.tcl b/fpga/usrp3/top/b200/coregen/chipscope_ila_256_xmdf.tcl new file mode 100755 index 000000000..1fb67dd98 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256_xmdf.tcl @@ -0,0 +1,87 @@ +# The package naming convention is _xmdf +package provide chipscope_ila_256_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::chipscope_ila_256_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::chipscope_ila_256_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_ila_256 +} +# ::chipscope_ila_256_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::chipscope_ila_256_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.cdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.constraints/chipscope_ila_256.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.ncf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.constraints/chipscope_ila_256.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_ila_256 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.asy b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.asy new file mode 100644 index 000000000..69e989c04 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.asy @@ -0,0 +1,17 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 chipscope_ila_32 +RECTANGLE Normal 32 32 288 704 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName control[35:0] +PINATTR Polarity IN +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Wide 0 176 32 176 +PIN 0 176 LEFT 36 +PINATTR PinName trig0[31:0] +PINATTR Polarity IN + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.cdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.cdc new file mode 100644 index 000000000..d0ba2170c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.cdc @@ -0,0 +1,48 @@ +#ChipScope Core Generator Project File Version 3.0 +#Fri Mar 08 11:59:29 PST 2013 +SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 +SignalExport.bus<0000>.name=TRIG0 +SignalExport.bus<0000>.offset=0.0 +SignalExport.bus<0000>.precision=0 +SignalExport.bus<0000>.radix=Bin +SignalExport.bus<0000>.scaleFactor=1.0 +SignalExport.clockChannel=CLK +SignalExport.dataEqualsTrigger=true +SignalExport.triggerChannel<0000><0000>=TRIG0[0] +SignalExport.triggerChannel<0000><0001>=TRIG0[1] +SignalExport.triggerChannel<0000><0002>=TRIG0[2] +SignalExport.triggerChannel<0000><0003>=TRIG0[3] +SignalExport.triggerChannel<0000><0004>=TRIG0[4] +SignalExport.triggerChannel<0000><0005>=TRIG0[5] +SignalExport.triggerChannel<0000><0006>=TRIG0[6] +SignalExport.triggerChannel<0000><0007>=TRIG0[7] +SignalExport.triggerChannel<0000><0008>=TRIG0[8] +SignalExport.triggerChannel<0000><0009>=TRIG0[9] +SignalExport.triggerChannel<0000><0010>=TRIG0[10] +SignalExport.triggerChannel<0000><0011>=TRIG0[11] +SignalExport.triggerChannel<0000><0012>=TRIG0[12] +SignalExport.triggerChannel<0000><0013>=TRIG0[13] +SignalExport.triggerChannel<0000><0014>=TRIG0[14] +SignalExport.triggerChannel<0000><0015>=TRIG0[15] +SignalExport.triggerChannel<0000><0016>=TRIG0[16] +SignalExport.triggerChannel<0000><0017>=TRIG0[17] +SignalExport.triggerChannel<0000><0018>=TRIG0[18] +SignalExport.triggerChannel<0000><0019>=TRIG0[19] +SignalExport.triggerChannel<0000><0020>=TRIG0[20] +SignalExport.triggerChannel<0000><0021>=TRIG0[21] +SignalExport.triggerChannel<0000><0022>=TRIG0[22] +SignalExport.triggerChannel<0000><0023>=TRIG0[23] +SignalExport.triggerChannel<0000><0024>=TRIG0[24] +SignalExport.triggerChannel<0000><0025>=TRIG0[25] +SignalExport.triggerChannel<0000><0026>=TRIG0[26] +SignalExport.triggerChannel<0000><0027>=TRIG0[27] +SignalExport.triggerChannel<0000><0028>=TRIG0[28] +SignalExport.triggerChannel<0000><0029>=TRIG0[29] +SignalExport.triggerChannel<0000><0030>=TRIG0[30] +SignalExport.triggerChannel<0000><0031>=TRIG0[31] +SignalExport.triggerPort<0000>.name=TRIG0 +SignalExport.triggerPortCount=1 +SignalExport.triggerPortIsData<0000>=true +SignalExport.triggerPortWidth<0000>=32 +SignalExport.type=ila + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.ucf b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.ucf new file mode 100644 index 000000000..228071c37 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.ucf @@ -0,0 +1,15 @@ +# +# Clock constraints +# +NET "CLK" TNM_NET = D_CLK ; +INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; +TIMESPEC TS_D2_TO_T2_chipscope_ila_32 = FROM D2_CLK TO "FFS" TIG; +TIMESPEC TS_J2_TO_D2_chipscope_ila_32 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J3_TO_D2_chipscope_ila_32 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J4_TO_D2_chipscope_ila_32 = FROM "FFS" TO D2_CLK TIG; + +# +# Input keep/save net constraints +# +NET "TRIG0<*" S; +NET "TRIG0<*" KEEP; diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.xdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.xdc new file mode 100644 index 000000000..49e2b9e7b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.xdc @@ -0,0 +1,6 @@ +# +# Clock constraints +# +set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] +set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] +set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ncf b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ngc b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ngc new file mode 100644 index 000000000..29677d942 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ucf b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ucf new file mode 100644 index 000000000..228071c37 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ucf @@ -0,0 +1,15 @@ +# +# Clock constraints +# +NET "CLK" TNM_NET = D_CLK ; +INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; +TIMESPEC TS_D2_TO_T2_chipscope_ila_32 = FROM D2_CLK TO "FFS" TIG; +TIMESPEC TS_J2_TO_D2_chipscope_ila_32 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J3_TO_D2_chipscope_ila_32 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J4_TO_D2_chipscope_ila_32 = FROM "FFS" TO D2_CLK TIG; + +# +# Input keep/save net constraints +# +NET "TRIG0<*" S; +NET "TRIG0<*" KEEP; diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.v b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.v new file mode 100644 index 000000000..5c409080b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.v @@ -0,0 +1,31 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : chipscope_ila_32.v +// /___/ /\ Timestamp : Fri Mar 08 11:59:29 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: Verilog Synthesis Wrapper +/////////////////////////////////////////////////////////////////////////////// +// This wrapper is used to integrate with Project Navigator and PlanAhead + +`timescale 1ns/1ps + +module chipscope_ila_32( + CONTROL, + CLK, + TRIG0) /* synthesis syn_black_box syn_noprune=1 */; + + +inout [35 : 0] CONTROL; +input CLK; +input [31 : 0] TRIG0; + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.veo b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.veo new file mode 100644 index 000000000..c949fbe7f --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.veo @@ -0,0 +1,30 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : chipscope_ila_32.veo +// /___/ /\ Timestamp : Fri Mar 08 11:59:29 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: ISE Instantiation template +/////////////////////////////////////////////////////////////////////////////// + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +chipscope_ila_32 YourInstanceName ( + .CONTROL(CONTROL), // INOUT BUS [35:0] + .CLK(CLK), // IN + .TRIG0(TRIG0) // IN BUS [31:0] +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xco b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xco new file mode 100644 index 000000000..15047431b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xco @@ -0,0 +1,141 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Fri Mar 8 19:57:57 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a +# END Select +# BEGIN Parameters +CSET check_bramcount=false +CSET component_name=chipscope_ila_32 +CSET constraint_type=external +CSET counter_width_1=Disabled +CSET counter_width_10=Disabled +CSET counter_width_11=Disabled +CSET counter_width_12=Disabled +CSET counter_width_13=Disabled +CSET counter_width_14=Disabled +CSET counter_width_15=Disabled +CSET counter_width_16=Disabled +CSET counter_width_2=Disabled +CSET counter_width_3=Disabled +CSET counter_width_4=Disabled +CSET counter_width_5=Disabled +CSET counter_width_6=Disabled +CSET counter_width_7=Disabled +CSET counter_width_8=Disabled +CSET counter_width_9=Disabled +CSET data_port_width=0 +CSET data_same_as_trigger=true +CSET disable_save_keep=false +CSET enable_storage_qualification=true +CSET enable_trigger_output_port=false +CSET example_design=false +CSET exclude_from_data_storage_1=false +CSET exclude_from_data_storage_10=false +CSET exclude_from_data_storage_11=false +CSET exclude_from_data_storage_12=false +CSET exclude_from_data_storage_13=false +CSET exclude_from_data_storage_14=false +CSET exclude_from_data_storage_15=false +CSET exclude_from_data_storage_16=false +CSET exclude_from_data_storage_2=false +CSET exclude_from_data_storage_3=false +CSET exclude_from_data_storage_4=false +CSET exclude_from_data_storage_5=false +CSET exclude_from_data_storage_6=false +CSET exclude_from_data_storage_7=false +CSET exclude_from_data_storage_8=false +CSET exclude_from_data_storage_9=false +CSET match_type_1=basic_with_edges +CSET match_type_10=basic_with_edges +CSET match_type_11=basic_with_edges +CSET match_type_12=basic_with_edges +CSET match_type_13=basic_with_edges +CSET match_type_14=basic_with_edges +CSET match_type_15=basic_with_edges +CSET match_type_16=basic_with_edges +CSET match_type_2=basic_with_edges +CSET match_type_3=basic_with_edges +CSET match_type_4=basic_with_edges +CSET match_type_5=basic_with_edges +CSET match_type_6=basic_with_edges +CSET match_type_7=basic_with_edges +CSET match_type_8=basic_with_edges +CSET match_type_9=basic_with_edges +CSET match_units_1=1 +CSET match_units_10=1 +CSET match_units_11=1 +CSET match_units_12=1 +CSET match_units_13=1 +CSET match_units_14=1 +CSET match_units_15=1 +CSET match_units_16=1 +CSET match_units_2=1 +CSET match_units_3=1 +CSET match_units_4=1 +CSET match_units_5=1 +CSET match_units_6=1 +CSET match_units_7=1 +CSET match_units_8=1 +CSET match_units_9=1 +CSET max_sequence_levels=1 +CSET number_of_trigger_ports=1 +CSET sample_data_depth=1024 +CSET sample_on=Rising +CSET trigger_port_width_1=32 +CSET trigger_port_width_10=8 +CSET trigger_port_width_11=8 +CSET trigger_port_width_12=8 +CSET trigger_port_width_13=8 +CSET trigger_port_width_14=8 +CSET trigger_port_width_15=8 +CSET trigger_port_width_16=8 +CSET trigger_port_width_2=8 +CSET trigger_port_width_3=8 +CSET trigger_port_width_4=8 +CSET trigger_port_width_5=8 +CSET trigger_port_width_6=8 +CSET trigger_port_width_7=8 +CSET trigger_port_width_8=8 +CSET trigger_port_width_9=8 +CSET use_rpms=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-12-18T02:47:40Z +# END Extra information +GENERATE +# CRC: aad58d16 diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xdc new file mode 100644 index 000000000..49e2b9e7b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xdc @@ -0,0 +1,6 @@ +# +# Clock constraints +# +set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] +set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] +set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32_flist.txt b/fpga/usrp3/top/b200/coregen/chipscope_ila_32_flist.txt new file mode 100644 index 000000000..0a88237f8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32_flist.txt @@ -0,0 +1,18 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +chipscope_ila_32.asy +chipscope_ila_32.cdc +chipscope_ila_32.constraints/chipscope_ila_32.ucf +chipscope_ila_32.constraints/chipscope_ila_32.xdc +chipscope_ila_32.gise +chipscope_ila_32.ncf +chipscope_ila_32.ngc +chipscope_ila_32.ucf +chipscope_ila_32.v +chipscope_ila_32.veo +chipscope_ila_32.xco +chipscope_ila_32.xdc +chipscope_ila_32.xise +chipscope_ila_32_flist.txt +chipscope_ila_32_readme.txt +chipscope_ila_32_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32_readme.txt b/fpga/usrp3/top/b200/coregen/chipscope_ila_32_readme.txt new file mode 100644 index 000000000..231b5d1ad --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32_readme.txt @@ -0,0 +1,48 @@ +The following files were generated for 'chipscope_ila_32' in directory +/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b200/coregen/ + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * chipscope_ila_32.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * chipscope_ila_32.cdc + * chipscope_ila_32.constraints/chipscope_ila_32.ucf + * chipscope_ila_32.constraints/chipscope_ila_32.xdc + * chipscope_ila_32.ncf + * chipscope_ila_32.ngc + * chipscope_ila_32.ucf + * chipscope_ila_32.v + * chipscope_ila_32.veo + * chipscope_ila_32.xdc + * chipscope_ila_32_xmdf.tcl + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * chipscope_ila_32.asy + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * _xmsgs/pn_parser.xmsgs + * chipscope_ila_32.gise + * chipscope_ila_32.xise + +Deliver Readme: + Readme file for the IP. + + * chipscope_ila_32_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * chipscope_ila_32_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32_xmdf.tcl b/fpga/usrp3/top/b200/coregen/chipscope_ila_32_xmdf.tcl new file mode 100755 index 000000000..f3617c66c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32_xmdf.tcl @@ -0,0 +1,87 @@ +# The package naming convention is _xmdf +package provide chipscope_ila_32_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::chipscope_ila_32_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::chipscope_ila_32_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_ila_32 +} +# ::chipscope_ila_32_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::chipscope_ila_32_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.cdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.constraints/chipscope_ila_32.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.ncf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.constraints/chipscope_ila_32.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_ila_32 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams + diff --git a/fpga/usrp3/top/b200/coregen/coregen.cgp b/fpga/usrp3/top/b200/coregen/coregen.cgp new file mode 100644 index 000000000..24f6041a1 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/coregen.cgp @@ -0,0 +1,9 @@ +SET busformat = BusFormatAngleBracketNotRipped +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET package = fgg484 +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.asy b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.asy new file mode 100644 index 000000000..fd6eef6f7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 fifo_4k_2clk +RECTANGLE Normal 32 32 800 4064 +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName rst +PINATTR Polarity IN +LINE Normal 0 208 32 208 +PIN 0 208 LEFT 36 +PINATTR PinName wr_clk +PINATTR Polarity IN +LINE Wide 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName din[71:0] +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName wr_en +PINATTR Polarity IN +LINE Normal 0 464 32 464 +PIN 0 464 LEFT 36 +PINATTR PinName full +PINATTR Polarity OUT +LINE Wide 0 624 32 624 +PIN 0 624 LEFT 36 +PINATTR PinName wr_data_count[9:0] +PINATTR Polarity OUT +LINE Normal 832 240 800 240 +PIN 832 240 RIGHT 36 +PINATTR PinName rd_clk +PINATTR Polarity IN +LINE Wide 832 272 800 272 +PIN 832 272 RIGHT 36 +PINATTR PinName dout[71:0] +PINATTR Polarity OUT +LINE Normal 832 304 800 304 +PIN 832 304 RIGHT 36 +PINATTR PinName rd_en +PINATTR Polarity IN +LINE Normal 832 496 800 496 +PIN 832 496 RIGHT 36 +PINATTR PinName empty +PINATTR Polarity OUT +LINE Wide 832 656 800 656 +PIN 832 656 RIGHT 36 +PINATTR PinName rd_data_count[9:0] +PINATTR Polarity OUT + diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.ncf b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.ngc b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.ngc new file mode 100644 index 000000000..b379066c6 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.v b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.v new file mode 100644 index 000000000..5724dd553 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.v @@ -0,0 +1,491 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2013 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// You must compile the wrapper file fifo_4k_2clk.v when simulating +// the core, fifo_4k_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +`timescale 1ns/1ps + +module fifo_4k_2clk( + rst, + wr_clk, + rd_clk, + din, + wr_en, + rd_en, + dout, + full, + empty, + rd_data_count, + wr_data_count +); + +input rst; +input wr_clk; +input rd_clk; +input [71 : 0] din; +input wr_en; +input rd_en; +output [71 : 0] dout; +output full; +output empty; +output [9 : 0] rd_data_count; +output [9 : 0] wr_data_count; + +// synthesis translate_off + + FIFO_GENERATOR_V9_3 #( + .C_ADD_NGC_CONSTRAINT(0), + .C_APPLICATION_TYPE_AXIS(0), + .C_APPLICATION_TYPE_RACH(0), + .C_APPLICATION_TYPE_RDCH(0), + .C_APPLICATION_TYPE_WACH(0), + .C_APPLICATION_TYPE_WDCH(0), + .C_APPLICATION_TYPE_WRCH(0), + .C_AXI_ADDR_WIDTH(32), + .C_AXI_ARUSER_WIDTH(1), + .C_AXI_AWUSER_WIDTH(1), + .C_AXI_BUSER_WIDTH(1), + .C_AXI_DATA_WIDTH(64), + .C_AXI_ID_WIDTH(4), + .C_AXI_RUSER_WIDTH(1), + .C_AXI_TYPE(0), + .C_AXI_WUSER_WIDTH(1), + .C_AXIS_TDATA_WIDTH(64), + .C_AXIS_TDEST_WIDTH(4), + .C_AXIS_TID_WIDTH(8), + .C_AXIS_TKEEP_WIDTH(4), + .C_AXIS_TSTRB_WIDTH(4), + .C_AXIS_TUSER_WIDTH(4), + .C_AXIS_TYPE(0), + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(9), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(72), + .C_DIN_WIDTH_AXIS(1), + .C_DIN_WIDTH_RACH(32), + .C_DIN_WIDTH_RDCH(64), + .C_DIN_WIDTH_WACH(32), + .C_DIN_WIDTH_WDCH(64), + .C_DIN_WIDTH_WRCH(2), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(72), + .C_ENABLE_RLOCS(0), + .C_ENABLE_RST_SYNC(1), + .C_ERROR_INJECTION_TYPE(0), + .C_ERROR_INJECTION_TYPE_AXIS(0), + .C_ERROR_INJECTION_TYPE_RACH(0), + .C_ERROR_INJECTION_TYPE_RDCH(0), + .C_ERROR_INJECTION_TYPE_WACH(0), + .C_ERROR_INJECTION_TYPE_WDCH(0), + .C_ERROR_INJECTION_TYPE_WRCH(0), + .C_FAMILY("spartan6"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_AXI_ARUSER(0), + .C_HAS_AXI_AWUSER(0), + .C_HAS_AXI_BUSER(0), + .C_HAS_AXI_RD_CHANNEL(0), + .C_HAS_AXI_RUSER(0), + .C_HAS_AXI_WR_CHANNEL(0), + .C_HAS_AXI_WUSER(0), + .C_HAS_AXIS_TDATA(0), + .C_HAS_AXIS_TDEST(0), + .C_HAS_AXIS_TID(0), + .C_HAS_AXIS_TKEEP(0), + .C_HAS_AXIS_TLAST(0), + .C_HAS_AXIS_TREADY(1), + .C_HAS_AXIS_TSTRB(0), + .C_HAS_AXIS_TUSER(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_DATA_COUNTS_AXIS(0), + .C_HAS_DATA_COUNTS_RACH(0), + .C_HAS_DATA_COUNTS_RDCH(0), + .C_HAS_DATA_COUNTS_WACH(0), + .C_HAS_DATA_COUNTS_WDCH(0), + .C_HAS_DATA_COUNTS_WRCH(0), + .C_HAS_INT_CLK(0), + .C_HAS_MASTER_CE(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_PROG_FLAGS_AXIS(0), + .C_HAS_PROG_FLAGS_RACH(0), + .C_HAS_PROG_FLAGS_RDCH(0), + .C_HAS_PROG_FLAGS_WACH(0), + .C_HAS_PROG_FLAGS_WDCH(0), + .C_HAS_PROG_FLAGS_WRCH(0), + .C_HAS_RD_DATA_COUNT(1), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SLAVE_CE(0), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(1), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_IMPLEMENTATION_TYPE_AXIS(1), + .C_IMPLEMENTATION_TYPE_RACH(1), + .C_IMPLEMENTATION_TYPE_RDCH(1), + .C_IMPLEMENTATION_TYPE_WACH(1), + .C_IMPLEMENTATION_TYPE_WDCH(1), + .C_IMPLEMENTATION_TYPE_WRCH(1), + .C_INIT_WR_PNTR_VAL(0), + .C_INTERFACE_TYPE(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("512x72"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_EMPTY_TYPE_AXIS(0), + .C_PROG_EMPTY_TYPE_RACH(0), + .C_PROG_EMPTY_TYPE_RDCH(0), + .C_PROG_EMPTY_TYPE_WACH(0), + .C_PROG_EMPTY_TYPE_WDCH(0), + .C_PROG_EMPTY_TYPE_WRCH(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(511), + .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023), + .C_PROG_FULL_THRESH_NEGATE_VAL(510), + .C_PROG_FULL_TYPE(0), + .C_PROG_FULL_TYPE_AXIS(0), + .C_PROG_FULL_TYPE_RACH(0), + .C_PROG_FULL_TYPE_RDCH(0), + .C_PROG_FULL_TYPE_WACH(0), + .C_PROG_FULL_TYPE_WDCH(0), + .C_PROG_FULL_TYPE_WRCH(0), + .C_RACH_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(10), + .C_RD_DEPTH(512), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(9), + .C_RDCH_TYPE(0), + .C_REG_SLICE_MODE_AXIS(0), + .C_REG_SLICE_MODE_RACH(0), + .C_REG_SLICE_MODE_RDCH(0), + .C_REG_SLICE_MODE_WACH(0), + .C_REG_SLICE_MODE_WDCH(0), + .C_REG_SLICE_MODE_WRCH(0), + .C_SYNCHRONIZER_STAGE(2), + .C_UNDERFLOW_LOW(0), + .C_USE_COMMON_OVERFLOW(0), + .C_USE_COMMON_UNDERFLOW(0), + .C_USE_DEFAULT_SETTINGS(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_ECC_AXIS(0), + .C_USE_ECC_RACH(0), + .C_USE_ECC_RDCH(0), + .C_USE_ECC_WACH(0), + .C_USE_ECC_WDCH(0), + .C_USE_ECC_WRCH(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(1), + .C_VALID_LOW(0), + .C_WACH_TYPE(0), + .C_WDCH_TYPE(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(10), + .C_WR_DEPTH(512), + .C_WR_DEPTH_AXIS(1024), + .C_WR_DEPTH_RACH(16), + .C_WR_DEPTH_RDCH(1024), + .C_WR_DEPTH_WACH(16), + .C_WR_DEPTH_WDCH(1024), + .C_WR_DEPTH_WRCH(16), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(9), + .C_WR_PNTR_WIDTH_AXIS(10), + .C_WR_PNTR_WIDTH_RACH(4), + .C_WR_PNTR_WIDTH_RDCH(10), + .C_WR_PNTR_WIDTH_WACH(4), + .C_WR_PNTR_WIDTH_WDCH(10), + .C_WR_PNTR_WIDTH_WRCH(4), + .C_WR_RESPONSE_LATENCY(1), + .C_WRCH_TYPE(0) + ) + inst ( + .RST(rst), + .WR_CLK(wr_clk), + .RD_CLK(rd_clk), + .DIN(din), + .WR_EN(wr_en), + .RD_EN(rd_en), + .DOUT(dout), + .FULL(full), + .EMPTY(empty), + .RD_DATA_COUNT(rd_data_count), + .WR_DATA_COUNT(wr_data_count), + .BACKUP(), + .BACKUP_MARKER(), + .CLK(), + .SRST(), + .WR_RST(), + .RD_RST(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .INT_CLK(), + .INJECTDBITERR(), + .INJECTSBITERR(), + .ALMOST_FULL(), + .WR_ACK(), + .OVERFLOW(), + .ALMOST_EMPTY(), + .VALID(), + .UNDERFLOW(), + .DATA_COUNT(), + .PROG_FULL(), + .PROG_EMPTY(), + .SBITERR(), + .DBITERR(), + .M_ACLK(), + .S_ACLK(), + .S_ARESETN(), + .M_ACLK_EN(), + .S_ACLK_EN(), + .S_AXI_AWID(), + .S_AXI_AWADDR(), + .S_AXI_AWLEN(), + .S_AXI_AWSIZE(), + .S_AXI_AWBURST(), + .S_AXI_AWLOCK(), + .S_AXI_AWCACHE(), + .S_AXI_AWPROT(), + .S_AXI_AWQOS(), + .S_AXI_AWREGION(), + .S_AXI_AWUSER(), + .S_AXI_AWVALID(), + .S_AXI_AWREADY(), + .S_AXI_WID(), + .S_AXI_WDATA(), + .S_AXI_WSTRB(), + .S_AXI_WLAST(), + .S_AXI_WUSER(), + .S_AXI_WVALID(), + .S_AXI_WREADY(), + .S_AXI_BID(), + .S_AXI_BRESP(), + .S_AXI_BUSER(), + .S_AXI_BVALID(), + .S_AXI_BREADY(), + .M_AXI_AWID(), + .M_AXI_AWADDR(), + .M_AXI_AWLEN(), + .M_AXI_AWSIZE(), + .M_AXI_AWBURST(), + .M_AXI_AWLOCK(), + .M_AXI_AWCACHE(), + .M_AXI_AWPROT(), + .M_AXI_AWQOS(), + .M_AXI_AWREGION(), + .M_AXI_AWUSER(), + .M_AXI_AWVALID(), + .M_AXI_AWREADY(), + .M_AXI_WID(), + .M_AXI_WDATA(), + .M_AXI_WSTRB(), + .M_AXI_WLAST(), + .M_AXI_WUSER(), + .M_AXI_WVALID(), + .M_AXI_WREADY(), + .M_AXI_BID(), + .M_AXI_BRESP(), + .M_AXI_BUSER(), + .M_AXI_BVALID(), + .M_AXI_BREADY(), + .S_AXI_ARID(), + .S_AXI_ARADDR(), + .S_AXI_ARLEN(), + .S_AXI_ARSIZE(), + .S_AXI_ARBURST(), + .S_AXI_ARLOCK(), + .S_AXI_ARCACHE(), + .S_AXI_ARPROT(), + .S_AXI_ARQOS(), + .S_AXI_ARREGION(), + .S_AXI_ARUSER(), + .S_AXI_ARVALID(), + .S_AXI_ARREADY(), + .S_AXI_RID(), + .S_AXI_RDATA(), + .S_AXI_RRESP(), + .S_AXI_RLAST(), + .S_AXI_RUSER(), + .S_AXI_RVALID(), + .S_AXI_RREADY(), + .M_AXI_ARID(), + .M_AXI_ARADDR(), + .M_AXI_ARLEN(), + .M_AXI_ARSIZE(), + .M_AXI_ARBURST(), + .M_AXI_ARLOCK(), + .M_AXI_ARCACHE(), + .M_AXI_ARPROT(), + .M_AXI_ARQOS(), + .M_AXI_ARREGION(), + .M_AXI_ARUSER(), + .M_AXI_ARVALID(), + .M_AXI_ARREADY(), + .M_AXI_RID(), + .M_AXI_RDATA(), + .M_AXI_RRESP(), + .M_AXI_RLAST(), + .M_AXI_RUSER(), + .M_AXI_RVALID(), + .M_AXI_RREADY(), + .S_AXIS_TVALID(), + .S_AXIS_TREADY(), + .S_AXIS_TDATA(), + .S_AXIS_TSTRB(), + .S_AXIS_TKEEP(), + .S_AXIS_TLAST(), + .S_AXIS_TID(), + .S_AXIS_TDEST(), + .S_AXIS_TUSER(), + .M_AXIS_TVALID(), + .M_AXIS_TREADY(), + .M_AXIS_TDATA(), + .M_AXIS_TSTRB(), + .M_AXIS_TKEEP(), + .M_AXIS_TLAST(), + .M_AXIS_TID(), + .M_AXIS_TDEST(), + .M_AXIS_TUSER(), + .AXI_AW_INJECTSBITERR(), + .AXI_AW_INJECTDBITERR(), + .AXI_AW_PROG_FULL_THRESH(), + .AXI_AW_PROG_EMPTY_THRESH(), + .AXI_AW_DATA_COUNT(), + .AXI_AW_WR_DATA_COUNT(), + .AXI_AW_RD_DATA_COUNT(), + .AXI_AW_SBITERR(), + .AXI_AW_DBITERR(), + .AXI_AW_OVERFLOW(), + .AXI_AW_UNDERFLOW(), + .AXI_AW_PROG_FULL(), + .AXI_AW_PROG_EMPTY(), + .AXI_W_INJECTSBITERR(), + .AXI_W_INJECTDBITERR(), + .AXI_W_PROG_FULL_THRESH(), + .AXI_W_PROG_EMPTY_THRESH(), + .AXI_W_DATA_COUNT(), + .AXI_W_WR_DATA_COUNT(), + .AXI_W_RD_DATA_COUNT(), + .AXI_W_SBITERR(), + .AXI_W_DBITERR(), + .AXI_W_OVERFLOW(), + .AXI_W_UNDERFLOW(), + .AXI_B_INJECTSBITERR(), + .AXI_W_PROG_FULL(), + .AXI_W_PROG_EMPTY(), + .AXI_B_INJECTDBITERR(), + .AXI_B_PROG_FULL_THRESH(), + .AXI_B_PROG_EMPTY_THRESH(), + .AXI_B_DATA_COUNT(), + .AXI_B_WR_DATA_COUNT(), + .AXI_B_RD_DATA_COUNT(), + .AXI_B_SBITERR(), + .AXI_B_DBITERR(), + .AXI_B_OVERFLOW(), + .AXI_B_UNDERFLOW(), + .AXI_AR_INJECTSBITERR(), + .AXI_B_PROG_FULL(), + .AXI_B_PROG_EMPTY(), + .AXI_AR_INJECTDBITERR(), + .AXI_AR_PROG_FULL_THRESH(), + .AXI_AR_PROG_EMPTY_THRESH(), + .AXI_AR_DATA_COUNT(), + .AXI_AR_WR_DATA_COUNT(), + .AXI_AR_RD_DATA_COUNT(), + .AXI_AR_SBITERR(), + .AXI_AR_DBITERR(), + .AXI_AR_OVERFLOW(), + .AXI_AR_UNDERFLOW(), + .AXI_AR_PROG_FULL(), + .AXI_AR_PROG_EMPTY(), + .AXI_R_INJECTSBITERR(), + .AXI_R_INJECTDBITERR(), + .AXI_R_PROG_FULL_THRESH(), + .AXI_R_PROG_EMPTY_THRESH(), + .AXI_R_DATA_COUNT(), + .AXI_R_WR_DATA_COUNT(), + .AXI_R_RD_DATA_COUNT(), + .AXI_R_SBITERR(), + .AXI_R_DBITERR(), + .AXI_R_OVERFLOW(), + .AXI_R_UNDERFLOW(), + .AXIS_INJECTSBITERR(), + .AXI_R_PROG_FULL(), + .AXI_R_PROG_EMPTY(), + .AXIS_INJECTDBITERR(), + .AXIS_PROG_FULL_THRESH(), + .AXIS_PROG_EMPTY_THRESH(), + .AXIS_DATA_COUNT(), + .AXIS_WR_DATA_COUNT(), + .AXIS_RD_DATA_COUNT(), + .AXIS_SBITERR(), + .AXIS_DBITERR(), + .AXIS_OVERFLOW(), + .AXIS_UNDERFLOW(), + .AXIS_PROG_FULL(), + .AXIS_PROG_EMPTY() + ); + +// synthesis translate_on + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.veo b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.veo new file mode 100644 index 000000000..12c025d5d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.veo @@ -0,0 +1,79 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2013 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ + +/******************************************************************************* +* Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 * +* * +* Rev 1. The FIFO Generator is a parameterizable first-in/first-out * +* memory queue generator. Use it to generate resource and performance * +* optimized FIFOs with common or independent read/write clock domains, * +* and optional fixed or programmable full and empty flags and * +* handshaking signals. Choose from a selection of memory resource * +* types for implementation. Optional Hamming code based error * +* detection and correction as well as error injection capability for * +* system test help to insure data integrity. FIFO width and depth are * +* parameterizable, and for native interface FIFOs, asymmetric read and * +* write port widths are also supported. * +*******************************************************************************/ + +// Interfaces: +// AXI4Stream_MASTER_M_AXIS +// AXI4Stream_SLAVE_S_AXIS +// AXI4_MASTER_M_AXI +// AXI4_SLAVE_S_AXI +// AXI4Lite_MASTER_M_AXI +// AXI4Lite_SLAVE_S_AXI +// master_aclk +// slave_aclk +// slave_aresetn + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_4k_2clk your_instance_name ( + .rst(rst), // input rst + .wr_clk(wr_clk), // input wr_clk + .rd_clk(rd_clk), // input rd_clk + .din(din), // input [71 : 0] din + .wr_en(wr_en), // input wr_en + .rd_en(rd_en), // input rd_en + .dout(dout), // output [71 : 0] dout + .full(full), // output full + .empty(empty), // output empty + .rd_data_count(rd_data_count), // output [9 : 0] rd_data_count + .wr_data_count(wr_data_count) // output [9 : 0] wr_data_count +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_4k_2clk.v when simulating +// the core, fifo_4k_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xco b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xco new file mode 100644 index 000000000..f617ee440 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xco @@ -0,0 +1,213 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Fri Jan 25 19:58:19 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fifo_generator:9.3 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 +# END Select +# BEGIN Parameters +CSET add_ngc_constraint_axi=false +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET aruser_width=1 +CSET awuser_width=1 +CSET axi_address_width=32 +CSET axi_data_width=64 +CSET axi_type=AXI4_Stream +CSET axis_type=FIFO +CSET buser_width=1 +CSET clock_enable_type=Slave_Interface_Clock_Enable +CSET clock_type_axi=Common_Clock +CSET component_name=fifo_4k_2clk +CSET data_count=false +CSET data_count_width=9 +CSET disable_timing_violations=false +CSET disable_timing_violations_axi=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_assert_value_axis=1022 +CSET empty_threshold_assert_value_rach=1022 +CSET empty_threshold_assert_value_rdch=1022 +CSET empty_threshold_assert_value_wach=1022 +CSET empty_threshold_assert_value_wdch=1022 +CSET empty_threshold_assert_value_wrch=1022 +CSET empty_threshold_negate_value=5 +CSET enable_aruser=false +CSET enable_awuser=false +CSET enable_buser=false +CSET enable_common_overflow=false +CSET enable_common_underflow=false +CSET enable_data_counts_axis=false +CSET enable_data_counts_rach=false +CSET enable_data_counts_rdch=false +CSET enable_data_counts_wach=false +CSET enable_data_counts_wdch=false +CSET enable_data_counts_wrch=false +CSET enable_ecc=false +CSET enable_ecc_axis=false +CSET enable_ecc_rach=false +CSET enable_ecc_rdch=false +CSET enable_ecc_wach=false +CSET enable_ecc_wdch=false +CSET enable_ecc_wrch=false +CSET enable_read_channel=false +CSET enable_read_pointer_increment_by2=false +CSET enable_reset_synchronization=true +CSET enable_ruser=false +CSET enable_tdata=false +CSET enable_tdest=false +CSET enable_tid=false +CSET enable_tkeep=false +CSET enable_tlast=false +CSET enable_tready=true +CSET enable_tstrobe=false +CSET enable_tuser=false +CSET enable_write_channel=false +CSET enable_wuser=false +CSET fifo_application_type_axis=Data_FIFO +CSET fifo_application_type_rach=Data_FIFO +CSET fifo_application_type_rdch=Data_FIFO +CSET fifo_application_type_wach=Data_FIFO +CSET fifo_application_type_wdch=Data_FIFO +CSET fifo_application_type_wrch=Data_FIFO +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET fifo_implementation_axis=Common_Clock_Block_RAM +CSET fifo_implementation_rach=Common_Clock_Block_RAM +CSET fifo_implementation_rdch=Common_Clock_Block_RAM +CSET fifo_implementation_wach=Common_Clock_Block_RAM +CSET fifo_implementation_wdch=Common_Clock_Block_RAM +CSET fifo_implementation_wrch=Common_Clock_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=511 +CSET full_threshold_assert_value_axis=1023 +CSET full_threshold_assert_value_rach=1023 +CSET full_threshold_assert_value_rdch=1023 +CSET full_threshold_assert_value_wach=1023 +CSET full_threshold_assert_value_wdch=1023 +CSET full_threshold_assert_value_wrch=1023 +CSET full_threshold_negate_value=510 +CSET id_width=4 +CSET inject_dbit_error=false +CSET inject_dbit_error_axis=false +CSET inject_dbit_error_rach=false +CSET inject_dbit_error_rdch=false +CSET inject_dbit_error_wach=false +CSET inject_dbit_error_wdch=false +CSET inject_dbit_error_wrch=false +CSET inject_sbit_error=false +CSET inject_sbit_error_axis=false +CSET inject_sbit_error_rach=false +CSET inject_sbit_error_rdch=false +CSET inject_sbit_error_wach=false +CSET inject_sbit_error_wdch=false +CSET inject_sbit_error_wrch=false +CSET input_data_width=72 +CSET input_depth=512 +CSET input_depth_axis=1024 +CSET input_depth_rach=16 +CSET input_depth_rdch=1024 +CSET input_depth_wach=16 +CSET input_depth_wdch=1024 +CSET input_depth_wrch=16 +CSET interface_type=Native +CSET output_data_width=72 +CSET output_depth=512 +CSET overflow_flag=false +CSET overflow_flag_axi=false +CSET overflow_sense=Active_High +CSET overflow_sense_axi=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET programmable_full_type_axis=No_Programmable_Full_Threshold +CSET programmable_full_type_rach=No_Programmable_Full_Threshold +CSET programmable_full_type_rdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wach=No_Programmable_Full_Threshold +CSET programmable_full_type_wdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wrch=No_Programmable_Full_Threshold +CSET rach_type=FIFO +CSET rdch_type=FIFO +CSET read_clock_frequency=1 +CSET read_data_count=true +CSET read_data_count_width=10 +CSET register_slice_mode_axis=Fully_Registered +CSET register_slice_mode_rach=Fully_Registered +CSET register_slice_mode_rdch=Fully_Registered +CSET register_slice_mode_wach=Fully_Registered +CSET register_slice_mode_wdch=Fully_Registered +CSET register_slice_mode_wrch=Fully_Registered +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET ruser_width=1 +CSET synchronization_stages=2 +CSET synchronization_stages_axi=2 +CSET tdata_width=64 +CSET tdest_width=4 +CSET tid_width=8 +CSET tkeep_width=4 +CSET tstrb_width=4 +CSET tuser_width=4 +CSET underflow_flag=false +CSET underflow_flag_axi=false +CSET underflow_sense=Active_High +CSET underflow_sense_axi=Active_High +CSET use_clock_enable=false +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=true +CSET valid_flag=false +CSET valid_sense=Active_High +CSET wach_type=FIFO +CSET wdch_type=FIFO +CSET wrch_type=FIFO +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=true +CSET write_data_count_width=10 +CSET wuser_width=1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-11-19T12:39:56Z +# END Extra information +GENERATE +# CRC: 372c204f diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/fifo_generator_v9_3_readme.txt b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/fifo_generator_v9_3_readme.txt new file mode 100644 index 000000000..7853ebde8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/fifo_generator_v9_3_readme.txt @@ -0,0 +1,236 @@ +CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1 + + Release Date: December 18, 2012 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm + +................................................................................ + + +2. DEVICE SUPPORT + + + 2.1 ISE + + The following device families are supported by the core for this release. + + + All 7 Series devices + Zynq-7000 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Spartan-3 devices + All Virtex-4 devices + + + 2.2 Vivado + + All 7 Series devices + Zynq-7000 devices + +................................................................................ + + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - ISE 14.4 software support + + + 3.2 Vivado + + - 2012.4 software support + - IP level constraint for Built-in FIFO reset synchronizer + +................................................................................ + + +4. RESOLVED ISSUES + + + 4.1 ISE + + - N/A + + + 4.2 Vivado + + - N/A + + +................................................................................ + + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Importing an XCO file alters the XCO configurations + + Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) + into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, + page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should. + + CR 467240 + AR 31379 + + 2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed + + Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA, + correct behavior of the FIFO status flags cannot be guaranteed after the first write. + + Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK. + For more information and additional workaround see Answer Record 41099. + + 5.2 Vivado + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen + ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work. + + CR 665836 + +The most recent information, including known issues, workarounds, and +resolutions for this version is provided in the IP Release Notes User Guide +located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + +................................................................................ + + +6. TECHNICAL SUPPORT & FEEDBACK + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + +................................................................................ + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer +10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO +07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO +04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support + AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO +01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support +10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support +06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support +03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support +10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support +09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support +07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support +06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support +04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support +12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support +09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support +06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support +04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support +09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes +03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes +10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs +08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO +04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support +09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support +07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support +01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3 +08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2 +04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1 +11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0 +05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support +04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release +================================================================================ + +................................................................................ + + +8. LEGAL DISCLAIMER + +(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/fifo_generator_v9_3_vinfo.html b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/fifo_generator_v9_3_vinfo.html new file mode 100644 index 000000000..fefce62a3 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/fifo_generator_v9_3_vinfo.html @@ -0,0 +1,247 @@ + + +fifo_generator_v9_3_vinfo + + + +


+CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1
+
+                    Release Date: December 18, 2012
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------  
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+   www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1
+solution. For the latest core updates, see the product page at:
+ 
+   www.xilinx.com/products/ipcenter/FIFO_Generator.htm
+
+................................................................................
+
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+    The following device families are supported by the core for this release.
+    
+    
+    All 7 Series devices
+    Zynq-7000 devices
+    All Virtex-6 devices
+    All Spartan-6 devices
+    All Virtex-5 devices
+    All Spartan-3 devices
+    All Virtex-4 devices
+  
+  
+  2.2 Vivado 
+  
+    All 7 Series devices
+    Zynq-7000 devices
+
+................................................................................
+
+
+3. NEW FEATURE HISTORY
+
+
+  3.1 ISE 
+  
+    - ISE 14.4 software support
+
+  
+  3.2 Vivado
+  
+    - 2012.4 software support
+    - IP level constraint for Built-in FIFO reset synchronizer
+
+................................................................................
+
+
+4. RESOLVED ISSUES 
+
+
+  4.1 ISE 
+
+    - N/A
+
+
+  4.2 Vivado 
+
+    - N/A
+
+
+................................................................................
+
+
+5. KNOWN ISSUES & LIMITATIONS 
+
+
+  5.1 ISE 
+  
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+  
+    1. Importing an XCO file alters the XCO configurations
+  
+       Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
+       into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, 
+       page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
+    
+       CR 467240
+       AR 31379
+  
+    2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
+  
+       Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
+       correct behavior of the FIFO status flags cannot be guaranteed after the first write.
+    
+       Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
+       For more information and additional workaround see Answer Record 41099.
+  
+  5.2 Vivado 
+
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+     
+    1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen 
+       ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
+      
+       CR 665836
+
+The most recent information, including known issues, workarounds, and
+resolutions for this version is provided in the IP Release Notes User Guide
+located at 
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf 
+
+................................................................................
+
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.  
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+................................................................................
+
+
+7. CORE RELEASE HISTORY 
+
+Date        By            Version      Description
+================================================================================
+12/18/2012  Xilinx, Inc.  9.3 Rev 1    ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer
+10/16/2012  Xilinx, Inc.  9.3          ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
+07/25/2012  Xilinx, Inc.  9.2          ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
+04/24/2012  Xilinx, Inc.  9.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
+                                       AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
+01/18/2012  Xilinx, Inc.  8.4          ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
+10/19/2011  Xilinx, Inc.  8.3          ISE 13.3 support and QVirtex-6L device support
+06/22/2011  Xilinx, Inc.  8.2          ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
+03/01/2011  Xilinx, Inc.  8.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
+10/29/2010  Xilinx, Inc.  7.3          ISE 13.0.2 support
+09/21/2010  Xilinx, Inc.  7.2          ISE 12.3 support; AXI4 Support
+07/30/2010  Xilinx, Inc.  7.1          ISE 13.0.1 support
+06/18/2010  Xilinx, Inc.  6.2          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  6.1          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  5.3 rev 1    ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
+09/16/2009  Xilinx, Inc.  5.3          Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
+06/24/2009  Xilinx, Inc.  5.2          Update to add 11.2 and Virtex-6 CXT device support
+04/24/2009  Xilinx, Inc.  5.1          Update to add 11.1 and Virtex-6 and Spartan-6 device support
+09/19/2008  Xilinx, Inc.  4.4          Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
+03/24/2008  Xilinx, Inc.  4.3          Update to add 10.1 support and miscellaneous bug fixes
+10/03/2007  Xilinx, Inc.  4.2          Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
+08/08/2007  Xilinx, Inc.  4.1          Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
+04/02/2007  Xilinx, Inc.  3.3          Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
+09/21/2006  Xilinx, Inc.  3.2          Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
+07/13/2006  Xilinx, Inc.  3.1          Update to add 8.2i support; Revised to v3.1; Virtex-5 support
+01/11/2006  Xilinx, Inc.  2.3          Update to add 8.1i support; Revised to v2.3
+08/31/2005  Xilinx, Inc.  2.2          Update to add 7.1i SP4 support; Revised to v2.2
+04/28/2005  Xilinx, Inc.  2.1          Update to add 7.1i SP1 support; Revised to v2.1
+11/04/2004  Xilinx, Inc.  2.0          Update to add 6.3i support; Revised to v2.0
+05/21/2004  Xilinx, Inc.  1.1          Revised to v1.1; Virtex-4 support
+04/23/2004  Xilinx, Inc.  1.0          Update to add 6.2i support; First release
+================================================================================
+
+................................................................................
+
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
+
+  This file contains confidential and proprietary information
+  of Xilinx, Inc. and is protected under U.S. and
+  international copyright and other intellectual property
+  laws.
+
+  DISCLAIMER
+  This disclaimer is not a license and does not grant any
+  rights to the materials distributed herewith. Except as
+  otherwise provided in a valid license issued to you by
+  Xilinx, and to the maximum extent permitted by applicable
+  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+  (2) Xilinx shall not be liable (whether in contract or tort,
+  including negligence, or under any other theory of
+  liability) for any loss or damage of any kind or nature
+  related to, arising under or in connection with these
+  materials, including for any direct, or any indirect,
+  special, incidental, or consequential loss or damage
+  (including loss of data, profits, goodwill, or any type of
+  loss or damage suffered as a result of any action brought
+  by a third party) even if such damage or loss was
+  reasonably foreseeable or Xilinx had been advised of the
+  possibility of the same. 
+
+  CRITICAL APPLICATIONS
+  Xilinx products are not designed or intended to be fail-
+  safe, or for use in any application requiring fail-safe
+  performance, such as life-support or safety devices or
+  systems, Class III medical devices, nuclear facilities,
+  applications related to the deployment of airbags, or any
+  other applications that could lead to death, personal
+  injury, or severe property or environmental damage
+  (individually and collectively, "Critical 
+  Applications"). Customer assumes the sole risk and 
+  liability of any use of Xilinx products in Critical 
+  Applications, subject only to applicable laws and 
+  regulations governing limitations on product liability. 
+ 
+  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+  PART OF THIS FILE AT ALL TIMES.
+
+
+ + diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/pg057-fifo-generator.pdf b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/pg057-fifo-generator.pdf new file mode 100644 index 000000000..5ec45fbcb Binary files /dev/null and b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/pg057-fifo-generator.pdf differ diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf new file mode 100755 index 000000000..62e5058ab --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf @@ -0,0 +1,56 @@ +################################################################################ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. + NET "RD_CLK" TNM_NET = "RD_CLK"; + NET "WR_CLK" TNM_NET = "WR_CLK"; + TIMESPEC "TS_RD_CLK" = PERIOD "RD_CLK" 50 MHZ; + TIMESPEC "TS_WR_CLK" = PERIOD "WR_CLK" 50 MHZ; +################################################################################ diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.vhd new file mode 100755 index 000000000..2674443c8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.vhd @@ -0,0 +1,145 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core - core top file for implementation +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_exdes.vhd +-- +-- Description: +-- This is the FIFO core wrapper with BUFG instances for clock connections. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library unisim; +use unisim.vcomponents.all; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +entity fifo_4k_2clk_exdes is + PORT ( + WR_CLK : IN std_logic; + RD_CLK : IN std_logic; + WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); + RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); + RST : IN std_logic; + WR_EN : IN std_logic; + RD_EN : IN std_logic; + DIN : IN std_logic_vector(72-1 DOWNTO 0); + DOUT : OUT std_logic_vector(72-1 DOWNTO 0); + FULL : OUT std_logic; + EMPTY : OUT std_logic); + +end fifo_4k_2clk_exdes; + + + +architecture xilinx of fifo_4k_2clk_exdes is + + signal wr_clk_i : std_logic; + signal rd_clk_i : std_logic; + + + + component fifo_4k_2clk is + PORT ( + WR_CLK : IN std_logic; + RD_CLK : IN std_logic; + WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); + RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); + RST : IN std_logic; + WR_EN : IN std_logic; + RD_EN : IN std_logic; + DIN : IN std_logic_vector(72-1 DOWNTO 0); + DOUT : OUT std_logic_vector(72-1 DOWNTO 0); + FULL : OUT std_logic; + EMPTY : OUT std_logic); + + end component; + + +begin + + wr_clk_buf: bufg + PORT map( + i => WR_CLK, + o => wr_clk_i + ); + + rd_clk_buf: bufg + PORT map( + i => RD_CLK, + o => rd_clk_i + ); + + + exdes_inst : fifo_4k_2clk + PORT MAP ( + WR_CLK => wr_clk_i, + RD_CLK => rd_clk_i, + WR_DATA_COUNT => wr_data_count, + RD_DATA_COUNT => rd_data_count, + RST => rst, + WR_EN => wr_en, + RD_EN => rd_en, + DIN => din, + DOUT => dout, + FULL => full, + EMPTY => empty); + +end xilinx; diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/fifo_generator_v9_3_readme.txt b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/fifo_generator_v9_3_readme.txt new file mode 100644 index 000000000..7853ebde8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/fifo_generator_v9_3_readme.txt @@ -0,0 +1,236 @@ +CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1 + + Release Date: December 18, 2012 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm + +................................................................................ + + +2. DEVICE SUPPORT + + + 2.1 ISE + + The following device families are supported by the core for this release. + + + All 7 Series devices + Zynq-7000 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Spartan-3 devices + All Virtex-4 devices + + + 2.2 Vivado + + All 7 Series devices + Zynq-7000 devices + +................................................................................ + + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - ISE 14.4 software support + + + 3.2 Vivado + + - 2012.4 software support + - IP level constraint for Built-in FIFO reset synchronizer + +................................................................................ + + +4. RESOLVED ISSUES + + + 4.1 ISE + + - N/A + + + 4.2 Vivado + + - N/A + + +................................................................................ + + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Importing an XCO file alters the XCO configurations + + Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) + into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, + page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should. + + CR 467240 + AR 31379 + + 2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed + + Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA, + correct behavior of the FIFO status flags cannot be guaranteed after the first write. + + Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK. + For more information and additional workaround see Answer Record 41099. + + 5.2 Vivado + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen + ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work. + + CR 665836 + +The most recent information, including known issues, workarounds, and +resolutions for this version is provided in the IP Release Notes User Guide +located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + +................................................................................ + + +6. TECHNICAL SUPPORT & FEEDBACK + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + +................................................................................ + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer +10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO +07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO +04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support + AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO +01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support +10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support +06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support +03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support +10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support +09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support +07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support +06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support +04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support +12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support +09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support +06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support +04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support +09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes +03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes +10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs +08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO +04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support +09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support +07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support +01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3 +08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2 +04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1 +11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0 +05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support +04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release +================================================================================ + +................................................................................ + + +8. LEGAL DISCLAIMER + +(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.bat new file mode 100755 index 000000000..f5fcf0a2b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.bat @@ -0,0 +1,88 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +copy fifo_4k_2clk_exdes.ngc .\results\ + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\fifo_4k_2clk.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\fifo_4k_2clk_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-csg484-2 -sd ../../../ fifo_4k_2clk_exdes + +echo 'Running map' +map fifo_4k_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_4k_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.sh new file mode 100755 index 000000000..9cb53f5c7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.sh @@ -0,0 +1,87 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +cp fifo_4k_2clk_exdes.ngc ./results/ + + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../fifo_4k_2clk.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/fifo_4k_2clk_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-csg484-2 -sd ../../../ fifo_4k_2clk_exdes + +echo 'Running map' +map fifo_4k_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_4k_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v + diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.bat new file mode 100755 index 000000000..9d99aaa5c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.bat @@ -0,0 +1,87 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with Synplify' +synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\fifo_4k_2clk.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\fifo_4k_2clk_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-csg484-2 -sd ../../../ fifo_4k_2clk_exdes + +echo 'Running map' +map fifo_4k_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_4k_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.sh new file mode 100755 index 000000000..db245edbb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.sh @@ -0,0 +1,86 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with Synplify' +synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx + + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../fifo_4k_2clk.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/fifo_4k_2clk_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-csg484-2 -sd ../../../ fifo_4k_2clk_exdes + +echo 'Running map' +map fifo_4k_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_4k_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v + diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.bat new file mode 100755 index 000000000..a48fea790 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.bat @@ -0,0 +1,54 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +rem ----------------------------------------------------------------------------- +rem Script to synthesize and implement the Coregen FIFO Generator +rem ----------------------------------------------------------------------------- +rmdir /S /Q results +mkdir results +cd results +copy ..\..\..\fifo_4k_2clk.ngc . +planAhead -mode batch -source ..\planAhead_ise.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.sh new file mode 100755 index 000000000..7171a0e5e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.sh @@ -0,0 +1,55 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the Coregen FIFO Generator +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +cp ../../../fifo_4k_2clk.ngc . +planAhead -mode batch -source ../planAhead_ise.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.tcl b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.tcl new file mode 100755 index 000000000..6af923b85 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.tcl @@ -0,0 +1,67 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + +set device xc6slx75csg484-2 +set projName fifo_4k_2clk +set design fifo_4k_2clk +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module fifo_4k_2clk_exdes +add_files -norecurse {../../example_design/fifo_4k_2clk_exdes.vhd} +add_files -norecurse {./fifo_4k_2clk.ngc} +import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/fifo_4k_2clk_exdes.xdc} +set_property top fifo_4k_2clk_exdes [get_property srcset [current_run]] +synth_design +opt_design +place_design +route_design +write_sdf -rename_top_module fifo_4k_2clk_exdes -file routed.sdf +write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module fifo_4k_2clk_exdes routed.v +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file report.drc +write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/xst.prj b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/xst.prj new file mode 100755 index 000000000..573a1716f --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/xst.prj @@ -0,0 +1 @@ +work ../example_design/fifo_4k_2clk_exdes.vhd diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/xst.scr b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/xst.scr new file mode 100755 index 000000000..bff287f78 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/xst.scr @@ -0,0 +1,13 @@ +run +-ifmt VHDL +-ent fifo_4k_2clk_exdes +-p xc6slx75-csg484-2 +-ifn xst.prj +-write_timing_constraints No +-iobuf YES +-max_fanout 100 +-ofn fifo_4k_2clk_exdes +-ofmt NGC +-bus_delimiter () +-hierarchy_separator / +-case Maintain diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dgen.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dgen.vhd new file mode 100755 index 000000000..d14bb7a51 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dgen.vhd @@ -0,0 +1,123 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_dgen.vhd +-- +-- Description: +-- Used for write interface stimulus generation +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +LIBRARY work; +USE work.fifo_4k_2clk_pkg.ALL; + +ENTITY fifo_4k_2clk_dgen IS + GENERIC ( + C_DIN_WIDTH : INTEGER := 32; + C_DOUT_WIDTH : INTEGER := 32; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT ( + RESET : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + PRC_WR_EN : IN STD_LOGIC; + FULL : IN STD_LOGIC; + WR_EN : OUT STD_LOGIC; + WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE fg_dg_arch OF fifo_4k_2clk_dgen IS + + CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); + CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8); + + SIGNAL pr_w_en : STD_LOGIC := '0'; + SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0); + SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); + BEGIN + + WR_EN <= PRC_WR_EN ; + WR_DATA <= wr_data_i AFTER 100 ns; + + ---------------------------------------------- + -- Generation of DATA + ---------------------------------------------- + gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE + rd_gen_inst1:fifo_4k_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED+N + ) + PORT MAP( + CLK => WR_CLK, + RESET => RESET, + RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N), + ENABLE => pr_w_en + ); + END GENERATE; + + pr_w_en <= PRC_WR_EN AND NOT FULL; + wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0); + + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dverif.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dverif.vhd new file mode 100755 index 000000000..0a7c2aa87 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dverif.vhd @@ -0,0 +1,150 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_dverif.vhd +-- +-- Description: +-- Used for FIFO read interface stimulus generation and data checking +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +LIBRARY work; +USE work.fifo_4k_2clk_pkg.ALL; + +ENTITY fifo_4k_2clk_dverif IS + GENERIC( + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_USE_EMBEDDED_REG : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + PRC_RD_EN : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + RD_EN : OUT STD_LOGIC; + DOUT_CHK : OUT STD_LOGIC + ); +END ENTITY; + + +ARCHITECTURE fg_dv_arch OF fifo_4k_2clk_dverif IS + + CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); + CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0); + CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8); + + SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_chk : STD_LOGIC := '1'; + SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0); + SIGNAL rd_en_i : STD_LOGIC := '0'; + SIGNAL pr_r_en : STD_LOGIC := '0'; + SIGNAL rd_en_d1 : STD_LOGIC := '1'; +BEGIN + + + DOUT_CHK <= data_chk; + RD_EN <= rd_en_i; + rd_en_i <= PRC_RD_EN; + rd_en_d1 <= '1'; + + + data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE + ------------------------------------------------------- + -- Expected data generation and checking for data_fifo + ------------------------------------------------------- + + pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1; + expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0); + + gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE + rd_gen_inst2:fifo_4k_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED+N + ) + PORT MAP( + CLK => RD_CLK, + RESET => RESET, + RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N), + ENABLE => pr_r_en + ); + END GENERATE; + + PROCESS (RD_CLK,RESET) + BEGIN + IF(RESET = '1') THEN + data_chk <= '0'; + ELSIF (RD_CLK'event AND RD_CLK='1') THEN + IF(EMPTY = '0') THEN + IF(DATA_OUT = expected_dout) THEN + data_chk <= '0'; + ELSE + data_chk <= '1'; + END IF; + END IF; + END IF; + END PROCESS; + END GENERATE data_fifo_chk; + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pctrl.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pctrl.vhd new file mode 100755 index 000000000..fa32e4781 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pctrl.vhd @@ -0,0 +1,541 @@ + +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_pctrl.vhd +-- +-- Description: +-- Used for protocol control on write and read interface stimulus and status generation +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +LIBRARY work; +USE work.fifo_4k_2clk_pkg.ALL; + +ENTITY fifo_4k_2clk_pctrl IS + GENERIC( + AXI_CHANNEL : STRING :="NONE"; + C_APPLICATION_TYPE : INTEGER := 0; + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_WR_PNTR_WIDTH : INTEGER := 0; + C_RD_PNTR_WIDTH : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 2; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET_WR : IN STD_LOGIC; + RESET_RD : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + FULL : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + ALMOST_FULL : IN STD_LOGIC; + ALMOST_EMPTY : IN STD_LOGIC; + DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + DOUT_CHK : IN STD_LOGIC; + PRC_WR_EN : OUT STD_LOGIC; + PRC_RD_EN : OUT STD_LOGIC; + RESET_EN : OUT STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE fg_pc_arch OF fifo_4k_2clk_pctrl IS + + CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); + CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8); + CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH); + + SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); + SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); + SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); + SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0'); + SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0'); + SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0'); + SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0'); + SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0'); + SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); + SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); + SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0'); + SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); + SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0'); + SIGNAL wr_en_i : STD_LOGIC := '0'; + SIGNAL rd_en_i : STD_LOGIC := '0'; + SIGNAL state : STD_LOGIC := '0'; + SIGNAL wr_control : STD_LOGIC := '0'; + SIGNAL rd_control : STD_LOGIC := '0'; + SIGNAL stop_on_err : STD_LOGIC := '0'; + SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8); + SIGNAL sim_done_i : STD_LOGIC := '0'; + SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1'); + SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1'); + SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0'); + SIGNAL prc_we_i : STD_LOGIC := '0'; + SIGNAL prc_re_i : STD_LOGIC := '0'; + SIGNAL reset_en_i : STD_LOGIC := '0'; + SIGNAL sim_done_d1 : STD_LOGIC := '0'; + SIGNAL sim_done_wr1 : STD_LOGIC := '0'; + SIGNAL sim_done_wr2 : STD_LOGIC := '0'; + SIGNAL empty_d1 : STD_LOGIC := '0'; + SIGNAL empty_wr_dom1 : STD_LOGIC := '0'; + SIGNAL state_d1 : STD_LOGIC := '0'; + SIGNAL state_rd_dom1 : STD_LOGIC := '0'; + SIGNAL rd_en_d1 : STD_LOGIC := '0'; + SIGNAL rd_en_wr1 : STD_LOGIC := '0'; + SIGNAL wr_en_d1 : STD_LOGIC := '0'; + SIGNAL wr_en_rd1 : STD_LOGIC := '0'; + SIGNAL full_chk_d1 : STD_LOGIC := '0'; + SIGNAL full_chk_rd1 : STD_LOGIC := '0'; + SIGNAL empty_wr_dom2 : STD_LOGIC := '0'; + + SIGNAL state_rd_dom2 : STD_LOGIC := '0'; + SIGNAL state_rd_dom3 : STD_LOGIC := '0'; + SIGNAL rd_en_wr2 : STD_LOGIC := '0'; + SIGNAL wr_en_rd2 : STD_LOGIC := '0'; + SIGNAL full_chk_rd2 : STD_LOGIC := '0'; + SIGNAL reset_en_d1 : STD_LOGIC := '0'; + SIGNAL reset_en_rd1 : STD_LOGIC := '0'; + SIGNAL reset_en_rd2 : STD_LOGIC := '0'; + + SIGNAL data_chk_wr_d1 : STD_LOGIC := '0'; + SIGNAL data_chk_rd1 : STD_LOGIC := '0'; + SIGNAL data_chk_rd2 : STD_LOGIC := '0'; + SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); + SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); +BEGIN + status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0'; + STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high); + + prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0'; + prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0'; + + SIM_DONE <= sim_done_i; + rdw_gt_wrw <= (OTHERS => '1'); + wrw_gt_rdw <= (OTHERS => '1'); + + PROCESS(RD_CLK) + BEGIN + IF (RD_CLK'event AND RD_CLK='1') THEN + IF(prc_re_i = '1') THEN + rd_activ_cont <= rd_activ_cont + "1"; + END IF; + END IF; + END PROCESS; + + + PROCESS(sim_done_i) + BEGIN + assert sim_done_i = '0' + report "Simulation Complete for:" & AXI_CHANNEL + severity note; + END PROCESS; + +----------------------------------------------------- +-- SIM_DONE SIGNAL GENERATION +----------------------------------------------------- +PROCESS (RD_CLK,RESET_RD) +BEGIN + IF(RESET_RD = '1') THEN + --sim_done_i <= '0'; + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN + sim_done_i <= '1'; + END IF; + END IF; +END PROCESS; + + -- TB Timeout/Stop + fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE + PROCESS (RD_CLK) + BEGIN + IF (RD_CLK'event AND RD_CLK='1') THEN + IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN + sim_stop_cntr <= sim_stop_cntr - "1"; + END IF; + END IF; + END PROCESS; + END GENERATE fifo_tb_stop_run; + + + -- Stop when error found + PROCESS (RD_CLK) + BEGIN + IF (RD_CLK'event AND RD_CLK='1') THEN + IF(sim_done_i = '0') THEN + status_d1_i <= status_i OR status_d1_i; + END IF; + IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN + stop_on_err <= '1'; + END IF; + END IF; + END PROCESS; + ----------------------------------------------------- + + ----------------------------------------------------- + -- CHECKS FOR FIFO + ----------------------------------------------------- + + + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + post_rst_dly_rd <= (OTHERS => '1'); + ELSIF (RD_CLK'event AND RD_CLK='1') THEN + post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4); + END IF; + END PROCESS; + + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + post_rst_dly_wr <= (OTHERS => '1'); + ELSIF (WR_CLK'event AND WR_CLK='1') THEN + post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4); + END IF; + END PROCESS; + + + -- FULL de-assert Counter + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + full_ds_timeout <= (OTHERS => '0'); + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(state = '1') THEN + IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN + full_ds_timeout <= full_ds_timeout + '1'; + END IF; + ELSE + full_ds_timeout <= (OTHERS => '0'); + END IF; + END IF; + END PROCESS; + + + -- EMPTY deassert counter + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + empty_ds_timeout <= (OTHERS => '0'); + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(state = '0') THEN + IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN + empty_ds_timeout <= empty_ds_timeout + '1'; + END IF; + ELSE + empty_ds_timeout <= (OTHERS => '0'); + END IF; + END IF; + END PROCESS; + + -- Full check signal generation + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + full_chk_i <= '0'; + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN + full_chk_i <= '0'; + ELSE + full_chk_i <= AND_REDUCE(full_as_timeout) OR + AND_REDUCE(full_ds_timeout); + END IF; + END IF; + END PROCESS; + + -- Empty checks + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + empty_chk_i <= '0'; + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN + empty_chk_i <= '0'; + ELSE + empty_chk_i <= AND_REDUCE(empty_as_timeout) OR + AND_REDUCE(empty_ds_timeout); + END IF; + END IF; + END PROCESS; + + fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE + PRC_WR_EN <= prc_we_i AFTER 100 ns; + PRC_RD_EN <= prc_re_i AFTER 50 ns; + data_chk_i <= dout_chk; + END GENERATE fifo_d_chk; + ----------------------------------------------------- + + + ----------------------------------------------------- + -- SYNCHRONIZERS B/W WRITE AND READ DOMAINS + ----------------------------------------------------- + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + empty_wr_dom1 <= '1'; + empty_wr_dom2 <= '1'; + state_d1 <= '0'; + wr_en_d1 <= '0'; + rd_en_wr1 <= '0'; + rd_en_wr2 <= '0'; + full_chk_d1 <= '0'; + reset_en_d1 <= '0'; + sim_done_wr1 <= '0'; + sim_done_wr2 <= '0'; + ELSIF (WR_CLK'event AND WR_CLK='1') THEN + sim_done_wr1 <= sim_done_d1; + sim_done_wr2 <= sim_done_wr1; + reset_en_d1 <= reset_en_i; + state_d1 <= state; + empty_wr_dom1 <= empty_d1; + empty_wr_dom2 <= empty_wr_dom1; + wr_en_d1 <= wr_en_i; + rd_en_wr1 <= rd_en_d1; + rd_en_wr2 <= rd_en_wr1; + full_chk_d1 <= full_chk_i; + END IF; + END PROCESS; + + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + empty_d1 <= '1'; + state_rd_dom1 <= '0'; + state_rd_dom2 <= '0'; + state_rd_dom3 <= '0'; + wr_en_rd1 <= '0'; + wr_en_rd2 <= '0'; + rd_en_d1 <= '0'; + full_chk_rd1 <= '0'; + full_chk_rd2 <= '0'; + reset_en_rd1 <= '0'; + reset_en_rd2 <= '0'; + sim_done_d1 <= '0'; + ELSIF (RD_CLK'event AND RD_CLK='1') THEN + sim_done_d1 <= sim_done_i; + reset_en_rd1 <= reset_en_d1; + reset_en_rd2 <= reset_en_rd1; + empty_d1 <= EMPTY; + rd_en_d1 <= rd_en_i; + state_rd_dom1 <= state_d1; + state_rd_dom2 <= state_rd_dom1; + state_rd_dom3 <= state_rd_dom2; + wr_en_rd1 <= wr_en_d1; + wr_en_rd2 <= wr_en_rd1; + full_chk_rd1 <= full_chk_d1; + full_chk_rd2 <= full_chk_rd1; + END IF; + END PROCESS; + + RESET_EN <= reset_en_rd2; + + + data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE + ----------------------------------------------------- + -- WR_EN GENERATION + ----------------------------------------------------- + gen_rand_wr_en:fifo_4k_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED+1 + ) + PORT MAP( + CLK => WR_CLK, + RESET => RESET_WR, + RANDOM_NUM => wr_en_gen, + ENABLE => '1' + ); + + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + wr_en_i <= '0'; + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(state = '1') THEN + wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control; + ELSE + wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4)); + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------- + -- WR_EN CONTROL + ----------------------------------------------------- + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + wr_cntr <= (OTHERS => '0'); + wr_control <= '1'; + full_as_timeout <= (OTHERS => '0'); + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(state = '1') THEN + IF(wr_en_i = '1') THEN + wr_cntr <= wr_cntr + "1"; + END IF; + full_as_timeout <= (OTHERS => '0'); + ELSE + wr_cntr <= (OTHERS => '0'); + IF(rd_en_wr2 = '0') THEN + IF(wr_en_i = '1') THEN + full_as_timeout <= full_as_timeout + "1"; + END IF; + ELSE + full_as_timeout <= (OTHERS => '0'); + END IF; + END IF; + + wr_control <= NOT wr_cntr(wr_cntr'high); + + END IF; + END PROCESS; + + ----------------------------------------------------- + -- RD_EN GENERATION + ----------------------------------------------------- + gen_rand_rd_en:fifo_4k_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED + ) + PORT MAP( + CLK => RD_CLK, + RESET => RESET_RD, + RANDOM_NUM => rd_en_gen, + ENABLE => '1' + ); + + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + rd_en_i <= '0'; + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(state_rd_dom2 = '0') THEN + rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4)); + ELSE + rd_en_i <= rd_en_gen(0) OR rd_en_gen(6); + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------- + -- RD_EN CONTROL + ----------------------------------------------------- + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + rd_cntr <= (OTHERS => '0'); + rd_control <= '1'; + empty_as_timeout <= (OTHERS => '0'); + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(state_rd_dom2 = '0') THEN + IF(rd_en_i = '1') THEN + rd_cntr <= rd_cntr + "1"; + END IF; + empty_as_timeout <= (OTHERS => '0'); + ELSE + rd_cntr <= (OTHERS => '0'); + IF(wr_en_rd2 = '0') THEN + IF(rd_en_i = '1') THEN + empty_as_timeout <= empty_as_timeout + "1"; + END IF; + ELSE + empty_as_timeout <= (OTHERS => '0'); + END IF; + END IF; + + rd_control <= NOT rd_cntr(rd_cntr'high); + + END IF; + END PROCESS; + + ----------------------------------------------------- + -- STIMULUS CONTROL + ----------------------------------------------------- + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + state <= '0'; + reset_en_i <= '0'; + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + CASE state IS + WHEN '0' => + IF(FULL = '1' AND empty_wr_dom2 = '0') THEN + state <= '1'; + reset_en_i <= '0'; + END IF; + WHEN '1' => + IF(empty_wr_dom2 = '1' AND FULL = '0') THEN + state <= '0'; + reset_en_i <= '1'; + END IF; + WHEN OTHERS => state <= state; + END CASE; + END IF; + END PROCESS; + END GENERATE data_fifo_en; + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pkg.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pkg.vhd new file mode 100755 index 000000000..46d4ac9cf --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pkg.vhd @@ -0,0 +1,350 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_pkg.vhd +-- +-- Description: +-- This is the demo testbench package file for FIFO Generator core. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE ieee.std_logic_arith.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +PACKAGE fifo_4k_2clk_pkg IS + + FUNCTION divroundup ( + data_value : INTEGER; + divisor : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : INTEGER; + false_case : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : STD_LOGIC; + false_case : STD_LOGIC) + RETURN STD_LOGIC; + ------------------------ + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : TIME; + false_case : TIME) + RETURN TIME; + ------------------------ + FUNCTION log2roundup ( + data_value : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION hexstr_to_std_logic_vec( + arg1 : string; + size : integer ) + RETURN std_logic_vector; + ------------------------ + COMPONENT fifo_4k_2clk_rng IS + GENERIC (WIDTH : integer := 8; + SEED : integer := 3); + PORT ( + CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + ENABLE : IN STD_LOGIC; + RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + + COMPONENT fifo_4k_2clk_dgen IS + GENERIC ( + C_DIN_WIDTH : INTEGER := 32; + C_DOUT_WIDTH : INTEGER := 32; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT ( + RESET : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + PRC_WR_EN : IN STD_LOGIC; + FULL : IN STD_LOGIC; + WR_EN : OUT STD_LOGIC; + WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + + COMPONENT fifo_4k_2clk_dverif IS + GENERIC( + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_USE_EMBEDDED_REG : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + PRC_RD_EN : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + RD_EN : OUT STD_LOGIC; + DOUT_CHK : OUT STD_LOGIC + ); + END COMPONENT; + ------------------------ + + COMPONENT fifo_4k_2clk_pctrl IS + GENERIC( + AXI_CHANNEL : STRING := "NONE"; + C_APPLICATION_TYPE : INTEGER := 0; + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_WR_PNTR_WIDTH : INTEGER := 0; + C_RD_PNTR_WIDTH : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 2; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET_WR : IN STD_LOGIC; + RESET_RD : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + FULL : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + ALMOST_FULL : IN STD_LOGIC; + ALMOST_EMPTY : IN STD_LOGIC; + DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + DOUT_CHK : IN STD_LOGIC; + PRC_WR_EN : OUT STD_LOGIC; + PRC_RD_EN : OUT STD_LOGIC; + RESET_EN : OUT STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + COMPONENT fifo_4k_2clk_synth IS + GENERIC( + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 0; + TB_SEED : INTEGER := 1 + ); + PORT( + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + COMPONENT fifo_4k_2clk_exdes IS + PORT ( + WR_CLK : IN std_logic; + RD_CLK : IN std_logic; + WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); + RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); + RST : IN std_logic; + WR_EN : IN std_logic; + RD_EN : IN std_logic; + DIN : IN std_logic_vector(72-1 DOWNTO 0); + DOUT : OUT std_logic_vector(72-1 DOWNTO 0); + FULL : OUT std_logic; + EMPTY : OUT std_logic); + + END COMPONENT; + ------------------------ + + +END fifo_4k_2clk_pkg; + + + +PACKAGE BODY fifo_4k_2clk_pkg IS + + FUNCTION divroundup ( + data_value : INTEGER; + divisor : INTEGER) + RETURN INTEGER IS + VARIABLE div : INTEGER; + BEGIN + div := data_value/divisor; + IF ( (data_value MOD divisor) /= 0) THEN + div := div+1; + END IF; + RETURN div; + END divroundup; + --------------------------------- + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : INTEGER; + false_case : INTEGER) + RETURN INTEGER IS + VARIABLE retval : INTEGER := 0; + BEGIN + IF condition=false THEN + retval:=false_case; + ELSE + retval:=true_case; + END IF; + RETURN retval; + END if_then_else; + --------------------------------- + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : STD_LOGIC; + false_case : STD_LOGIC) + RETURN STD_LOGIC IS + VARIABLE retval : STD_LOGIC := '0'; + BEGIN + IF condition=false THEN + retval:=false_case; + ELSE + retval:=true_case; + END IF; + RETURN retval; + END if_then_else; + --------------------------------- + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : TIME; + false_case : TIME) + RETURN TIME IS + VARIABLE retval : TIME := 0 ps; + BEGIN + IF condition=false THEN + retval:=false_case; + ELSE + retval:=true_case; + END IF; + RETURN retval; + END if_then_else; + ------------------------------- + FUNCTION log2roundup ( + data_value : INTEGER) + RETURN INTEGER IS + + VARIABLE width : INTEGER := 0; + VARIABLE cnt : INTEGER := 1; + BEGIN + IF (data_value <= 1) THEN + width := 1; + ELSE + WHILE (cnt < data_value) LOOP + width := width + 1; + cnt := cnt *2; + END LOOP; + END IF; + + RETURN width; + END log2roundup; + ------------------------------------------------------------------------------ + -- hexstr_to_std_logic_vec + -- This function converts a hex string to a std_logic_vector + ------------------------------------------------------------------------------ + FUNCTION hexstr_to_std_logic_vec( + arg1 : string; + size : integer ) + RETURN std_logic_vector IS + VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE bin : std_logic_vector(3 DOWNTO 0); + VARIABLE index : integer := 0; + BEGIN + FOR i IN arg1'reverse_range LOOP + CASE arg1(i) IS + WHEN '0' => bin := (OTHERS => '0'); + WHEN '1' => bin := (0 => '1', OTHERS => '0'); + WHEN '2' => bin := (1 => '1', OTHERS => '0'); + WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0'); + WHEN '4' => bin := (2 => '1', OTHERS => '0'); + WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0'); + WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0'); + WHEN '7' => bin := (3 => '0', OTHERS => '1'); + WHEN '8' => bin := (3 => '1', OTHERS => '0'); + WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0'); + WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1'); + WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1'); + WHEN 'B' => bin := (2 => '0', OTHERS => '1'); + WHEN 'b' => bin := (2 => '0', OTHERS => '1'); + WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1'); + WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1'); + WHEN 'D' => bin := (1 => '0', OTHERS => '1'); + WHEN 'd' => bin := (1 => '0', OTHERS => '1'); + WHEN 'E' => bin := (0 => '0', OTHERS => '1'); + WHEN 'e' => bin := (0 => '0', OTHERS => '1'); + WHEN 'F' => bin := (OTHERS => '1'); + WHEN 'f' => bin := (OTHERS => '1'); + WHEN OTHERS => + FOR j IN 0 TO 3 LOOP + bin(j) := 'X'; + END LOOP; + END CASE; + FOR j IN 0 TO 3 LOOP + IF (index*4)+j < size THEN + result((index*4)+j) := bin(j); + END IF; + END LOOP; + index := index + 1; + END LOOP; + RETURN result; + END hexstr_to_std_logic_vec; + +END fifo_4k_2clk_pkg; diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd new file mode 100755 index 000000000..bed58d88e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd @@ -0,0 +1,100 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_rng.vhd +-- +-- Description: +-- Used for generation of pseudo random numbers +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +ENTITY fifo_4k_2clk_rng IS + GENERIC ( + WIDTH : integer := 8; + SEED : integer := 3); + PORT ( + CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + ENABLE : IN STD_LOGIC; + RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)); +END ENTITY; + +ARCHITECTURE rg_arch OF fifo_4k_2clk_rng IS +BEGIN +PROCESS (CLK,RESET) + VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width); + VARIABLE temp : STD_LOGIC := '0'; +BEGIN + IF(RESET = '1') THEN + rand_temp := conv_std_logic_vector(SEED,width); + temp := '0'; + ELSIF (CLK'event AND CLK = '1') THEN + IF (ENABLE = '1') THEN + temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5); + rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0); + rand_temp(0) := temp; + END IF; + END IF; + + RANDOM_NUM <= rand_temp; + +END PROCESS; + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd new file mode 100755 index 000000000..4149735c5 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd @@ -0,0 +1,300 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_synth.vhd +-- +-- Description: +-- This is the demo testbench for fifo_generator core. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + + +LIBRARY ieee; +USE ieee.STD_LOGIC_1164.ALL; +USE ieee.STD_LOGIC_unsigned.ALL; +USE IEEE.STD_LOGIC_arith.ALL; +USE ieee.numeric_std.ALL; +USE ieee.STD_LOGIC_misc.ALL; + +LIBRARY std; +USE std.textio.ALL; + +LIBRARY work; +USE work.fifo_4k_2clk_pkg.ALL; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +ENTITY fifo_4k_2clk_synth IS + GENERIC( + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 0; + TB_SEED : INTEGER := 1 + ); + PORT( + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END ENTITY; + +ARCHITECTURE simulation_arch OF fifo_4k_2clk_synth IS + + -- FIFO interface signal declarations + SIGNAL wr_clk_i : STD_LOGIC; + SIGNAL rd_clk_i : STD_LOGIC; + SIGNAL wr_data_count : STD_LOGIC_VECTOR(10-1 DOWNTO 0); + SIGNAL rd_data_count : STD_LOGIC_VECTOR(10-1 DOWNTO 0); + SIGNAL rst : STD_LOGIC; + SIGNAL wr_en : STD_LOGIC; + SIGNAL rd_en : STD_LOGIC; + SIGNAL din : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL dout : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL full : STD_LOGIC; + SIGNAL empty : STD_LOGIC; + -- TB Signals + SIGNAL wr_data : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL dout_i : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL wr_en_i : STD_LOGIC := '0'; + SIGNAL rd_en_i : STD_LOGIC := '0'; + SIGNAL full_i : STD_LOGIC := '0'; + SIGNAL empty_i : STD_LOGIC := '0'; + SIGNAL almost_full_i : STD_LOGIC := '0'; + SIGNAL almost_empty_i : STD_LOGIC := '0'; + SIGNAL prc_we_i : STD_LOGIC := '0'; + SIGNAL prc_re_i : STD_LOGIC := '0'; + SIGNAL dout_chk_i : STD_LOGIC := '0'; + SIGNAL rst_int_rd : STD_LOGIC := '0'; + SIGNAL rst_int_wr : STD_LOGIC := '0'; + SIGNAL rst_s_wr1 : STD_LOGIC := '0'; + SIGNAL rst_s_wr2 : STD_LOGIC := '0'; + SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL rst_s_wr3 : STD_LOGIC := '0'; + SIGNAL rst_s_rd : STD_LOGIC := '0'; + SIGNAL reset_en : STD_LOGIC := '0'; + SIGNAL rst_async_wr1 : STD_LOGIC := '0'; + SIGNAL rst_async_wr2 : STD_LOGIC := '0'; + SIGNAL rst_async_wr3 : STD_LOGIC := '0'; + SIGNAL rst_async_rd1 : STD_LOGIC := '0'; + SIGNAL rst_async_rd2 : STD_LOGIC := '0'; + SIGNAL rst_async_rd3 : STD_LOGIC := '0'; + + + BEGIN + + ---- Reset generation logic ----- + rst_int_wr <= rst_async_wr3 OR rst_s_wr3; + rst_int_rd <= rst_async_rd3 OR rst_s_rd; + + --Testbench reset synchronization + PROCESS(rd_clk_i,RESET) + BEGIN + IF(RESET = '1') THEN + rst_async_rd1 <= '1'; + rst_async_rd2 <= '1'; + rst_async_rd3 <= '1'; + ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN + rst_async_rd1 <= RESET; + rst_async_rd2 <= rst_async_rd1; + rst_async_rd3 <= rst_async_rd2; + END IF; + END PROCESS; + + PROCESS(wr_clk_i,RESET) + BEGIN + IF(RESET = '1') THEN + rst_async_wr1 <= '1'; + rst_async_wr2 <= '1'; + rst_async_wr3 <= '1'; + ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN + rst_async_wr1 <= RESET; + rst_async_wr2 <= rst_async_wr1; + rst_async_wr3 <= rst_async_wr2; + END IF; + END PROCESS; + + --Soft reset for core and testbench + PROCESS(rd_clk_i) + BEGIN + IF(rd_clk_i'event AND rd_clk_i='1') THEN + rst_gen_rd <= rst_gen_rd + "1"; + IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN + rst_s_rd <= '1'; + assert false + report "Reset applied..Memory Collision checks are not valid" + severity note; + ELSE + IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN + rst_s_rd <= '0'; + END IF; + END IF; + END IF; + END PROCESS; + + PROCESS(wr_clk_i) + BEGIN + IF(wr_clk_i'event AND wr_clk_i='1') THEN + rst_s_wr1 <= rst_s_rd; + rst_s_wr2 <= rst_s_wr1; + rst_s_wr3 <= rst_s_wr2; + IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN + assert false + report "Reset removed..Memory Collision checks are valid" + severity note; + END IF; + END IF; + END PROCESS; + ------------------ + + ---- Clock buffers for testbench ---- + wr_clk_i <= WR_CLK; + rd_clk_i <= RD_CLK; + ------------------ + + rst <= RESET OR rst_s_rd AFTER 12 ns; + din <= wr_data; + dout_i <= dout; + wr_en <= wr_en_i; + rd_en <= rd_en_i; + full_i <= full; + empty_i <= empty; + + fg_dg_nv: fifo_4k_2clk_dgen + GENERIC MAP ( + C_DIN_WIDTH => 72, + C_DOUT_WIDTH => 72, + TB_SEED => TB_SEED, + C_CH_TYPE => 0 + ) + PORT MAP ( -- Write Port + RESET => rst_int_wr, + WR_CLK => wr_clk_i, + PRC_WR_EN => prc_we_i, + FULL => full_i, + WR_EN => wr_en_i, + WR_DATA => wr_data + ); + + fg_dv_nv: fifo_4k_2clk_dverif + GENERIC MAP ( + C_DOUT_WIDTH => 72, + C_DIN_WIDTH => 72, + C_USE_EMBEDDED_REG => 0, + TB_SEED => TB_SEED, + C_CH_TYPE => 0 + ) + PORT MAP( + RESET => rst_int_rd, + RD_CLK => rd_clk_i, + PRC_RD_EN => prc_re_i, + RD_EN => rd_en_i, + EMPTY => empty_i, + DATA_OUT => dout_i, + DOUT_CHK => dout_chk_i + ); + + fg_pc_nv: fifo_4k_2clk_pctrl + GENERIC MAP ( + AXI_CHANNEL => "Native", + C_APPLICATION_TYPE => 0, + C_DOUT_WIDTH => 72, + C_DIN_WIDTH => 72, + C_WR_PNTR_WIDTH => 9, + C_RD_PNTR_WIDTH => 9, + C_CH_TYPE => 0, + FREEZEON_ERROR => FREEZEON_ERROR, + TB_SEED => TB_SEED, + TB_STOP_CNT => TB_STOP_CNT + ) + PORT MAP( + RESET_WR => rst_int_wr, + RESET_RD => rst_int_rd, + RESET_EN => reset_en, + WR_CLK => wr_clk_i, + RD_CLK => rd_clk_i, + PRC_WR_EN => prc_we_i, + PRC_RD_EN => prc_re_i, + FULL => full_i, + ALMOST_FULL => almost_full_i, + ALMOST_EMPTY => almost_empty_i, + DOUT_CHK => dout_chk_i, + EMPTY => empty_i, + DATA_IN => wr_data, + DATA_OUT => dout, + SIM_DONE => SIM_DONE, + STATUS => STATUS + ); + + + + + + fifo_4k_2clk_inst : fifo_4k_2clk_exdes + PORT MAP ( + WR_CLK => wr_clk_i, + RD_CLK => rd_clk_i, + WR_DATA_COUNT => wr_data_count, + RD_DATA_COUNT => rd_data_count, + RST => rst, + WR_EN => wr_en, + RD_EN => rd_en, + DIN => din, + DOUT => dout, + FULL => full, + EMPTY => empty); + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd new file mode 100755 index 000000000..51d699e21 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd @@ -0,0 +1,208 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_tb.vhd +-- +-- Description: +-- This is the demo testbench top file for fifo_generator core. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +LIBRARY std; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; +USE IEEE.std_logic_arith.ALL; +USE IEEE.std_logic_misc.ALL; +USE ieee.numeric_std.ALL; +USE ieee.std_logic_textio.ALL; +USE std.textio.ALL; + +LIBRARY work; +USE work.fifo_4k_2clk_pkg.ALL; + +ENTITY fifo_4k_2clk_tb IS +END ENTITY; + + +ARCHITECTURE fifo_4k_2clk_arch OF fifo_4k_2clk_tb IS + SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; + SIGNAL wr_clk : STD_LOGIC; + SIGNAL rd_clk : STD_LOGIC; + SIGNAL reset : STD_LOGIC; + SIGNAL sim_done : STD_LOGIC := '0'; + SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0'); + -- Write and Read clock periods + CONSTANT wr_clk_period_by_2 : TIME := 200 ns; + CONSTANT rd_clk_period_by_2 : TIME := 100 ns; + -- Procedures to display strings + PROCEDURE disp_str(CONSTANT str:IN STRING) IS + variable dp_l : line := null; + BEGIN + write(dp_l,str); + writeline(output,dp_l); + END PROCEDURE; + + PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS + variable dp_lx : line := null; + BEGIN + hwrite(dp_lx,hex); + writeline(output,dp_lx); + END PROCEDURE; + +BEGIN + + -- Generation of clock + + PROCESS BEGIN + WAIT FOR 400 ns; -- Wait for global reset + WHILE 1 = 1 LOOP + wr_clk <= '0'; + WAIT FOR wr_clk_period_by_2; + wr_clk <= '1'; + WAIT FOR wr_clk_period_by_2; + END LOOP; + END PROCESS; + + PROCESS BEGIN + WAIT FOR 200 ns;-- Wait for global reset + WHILE 1 = 1 LOOP + rd_clk <= '0'; + WAIT FOR rd_clk_period_by_2; + rd_clk <= '1'; + WAIT FOR rd_clk_period_by_2; + END LOOP; + END PROCESS; + + -- Generation of Reset + + PROCESS BEGIN + reset <= '1'; + WAIT FOR 4200 ns; + reset <= '0'; + WAIT; + END PROCESS; + + + -- Error message printing based on STATUS signal from fifo_4k_2clk_synth + + PROCESS(status) + BEGIN + IF(status /= "0" AND status /= "1") THEN + disp_str("STATUS:"); + disp_hex(status); + END IF; + + IF(status(7) = '1') THEN + assert false + report "Data mismatch found" + severity error; + END IF; + + IF(status(1) = '1') THEN + END IF; + + IF(status(5) = '1') THEN + assert false + report "Empty flag Mismatch/timeout" + severity error; + END IF; + + IF(status(6) = '1') THEN + assert false + report "Full Flag Mismatch/timeout" + severity error; + END IF; + END PROCESS; + + + PROCESS + BEGIN + wait until sim_done = '1'; + IF(status /= "0" AND status /= "1") THEN + assert false + report "Simulation failed" + severity failure; + ELSE + assert false + report "Test Completed Successfully" + severity failure; + END IF; + END PROCESS; + + PROCESS + BEGIN + wait for 400 ms; + assert false + report "Test bench timed out" + severity failure; + END PROCESS; + + -- Instance of fifo_4k_2clk_synth + + fifo_4k_2clk_synth_inst:fifo_4k_2clk_synth + GENERIC MAP( + FREEZEON_ERROR => 0, + TB_STOP_CNT => 2, + TB_SEED => 76 + ) + PORT MAP( + WR_CLK => wr_clk, + RD_CLK => rd_clk, + RESET => reset, + SIM_DONE => sim_done, + STATUS => status + ); + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.bat new file mode 100755 index 000000000..3d0783055 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.bat @@ -0,0 +1,63 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ..\\..\\..\\fifo_4k_2clk.v +vhpcomp -work work ..\\..\\example_design\\fifo_4k_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vhpcomp -work work ..\\fifo_4k_2clk_pkg.vhd +vhpcomp -work work ..\\fifo_4k_2clk_rng.vhd +vhpcomp -work work ..\\fifo_4k_2clk_dgen.vhd +vhpcomp -work work ..\\fifo_4k_2clk_dverif.vhd +vhpcomp -work work ..\\fifo_4k_2clk_pctrl.vhd +vhpcomp -work work ..\\fifo_4k_2clk_synth.vhd +vhpcomp -work work ..\\fifo_4k_2clk_tb.vhd + +vlogcomp -work work $XILINX\\verilog\\src\\glbl.v +fuse work.fifo_4k_2clk_tb work.glbl -L xilinxcorelib_ver -L unisims_ver -o fifo_4k_2clk_tb.exe + +.\\fifo_4k_2clk_tb.exe -gui -tclbatch .\\wave_isim.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.sh new file mode 100755 index 000000000..c3abd5a51 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.sh @@ -0,0 +1,65 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ../../../fifo_4k_2clk.v +vhpcomp -work work ../../example_design/fifo_4k_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vhpcomp -work work ../fifo_4k_2clk_pkg.vhd +vhpcomp -work work ../fifo_4k_2clk_rng.vhd +vhpcomp -work work ../fifo_4k_2clk_dgen.vhd +vhpcomp -work work ../fifo_4k_2clk_dverif.vhd +vhpcomp -work work ../fifo_4k_2clk_pctrl.vhd +vhpcomp -work work ../fifo_4k_2clk_synth.vhd +vhpcomp -work work ../fifo_4k_2clk_tb.vhd + +vlogcomp -work work $XILINX/verilog/src/glbl.v +fuse work.fifo_4k_2clk_tb work.glbl -L xilinxcorelib_ver -L unisims_ver -o fifo_4k_2clk_tb.exe + +./fifo_4k_2clk_tb.exe -gui -tclbatch ./wave_isim.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.bat new file mode 100755 index 000000000..35375ce20 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.bat @@ -0,0 +1,47 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.do b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.do new file mode 100755 index 000000000..af53abefb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.do @@ -0,0 +1,74 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vlib work +vmap work work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlog -work work ../../../fifo_4k_2clk.v +vcom -work work ../../example_design/fifo_4k_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vcom -work work ../fifo_4k_2clk_pkg.vhd +vcom -work work ../fifo_4k_2clk_rng.vhd +vcom -work work ../fifo_4k_2clk_dgen.vhd +vcom -work work ../fifo_4k_2clk_dverif.vhd +vcom -work work ../fifo_4k_2clk_pctrl.vhd +vcom -work work ../fifo_4k_2clk_synth.vhd +vcom -work work ../fifo_4k_2clk_tb.vhd + +vlog -work work $env(XILINX)/verilog/src/glbl.v +vsim -t ps -voptargs="+acc" -L XilinxCoreLib_ver -L unisims_ver glbl work.fifo_4k_2clk_tb + +add log -r /* +do wave_mti.do +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.sh new file mode 100755 index 000000000..edb1b0dd9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.sh @@ -0,0 +1,49 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_ncsim.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_ncsim.sh new file mode 100755 index 000000000..0d3376452 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_ncsim.sh @@ -0,0 +1,69 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +mkdir work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +ncvlog -work work ../../../fifo_4k_2clk.v +ncvhdl -v93 -work work ../../example_design/fifo_4k_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +ncvhdl -v93 -work work ../fifo_4k_2clk_pkg.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_rng.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_dgen.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_dverif.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_pctrl.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_synth.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_tb.vhd + +echo "Elaborating Design" +ncvlog -work work $XILINX/verilog/src/glbl.v +ncelab -access +rwc glbl work.fifo_4k_2clk_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" work.fifo_4k_2clk_tb + diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_vcs.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_vcs.sh new file mode 100755 index 000000000..8c26af20c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_vcs.sh @@ -0,0 +1,69 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogan +v2k ../../../fifo_4k_2clk.v +vhdlan ../../example_design/fifo_4k_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vhdlan ../fifo_4k_2clk_pkg.vhd +vhdlan ../fifo_4k_2clk_rng.vhd +vhdlan ../fifo_4k_2clk_dgen.vhd +vhdlan ../fifo_4k_2clk_dverif.vhd +vhdlan ../fifo_4k_2clk_pctrl.vhd +vhdlan ../fifo_4k_2clk_synth.vhd +vhdlan ../fifo_4k_2clk_tb.vhd + +echo "Elaborating Design" +vlogan +v2k $XILINX/verilog/src/glbl.v +vcs -time_res 1ps +vcs+lic+wait -debug fifo_4k_2clk_tb glbl + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/ucli_commands.key b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/ucli_commands.key new file mode 100755 index 000000000..9c95a2ade --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/ucli_commands.key @@ -0,0 +1,4 @@ +dump -file fifo_4k_2clk.vpd -type VPD +dump -add fifo_4k_2clk_tb +run +quit diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/vcs_session.tcl b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/vcs_session.tcl new file mode 100755 index 000000000..b9ef9837a --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/vcs_session.tcl @@ -0,0 +1,77 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- +if { ![gui_is_db_opened -db {fifo_4k_2clk.vpd}] } { + gui_open_db -design V1 -file fifo_4k_2clk.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + + +gui_open_window Wave +gui_sg_create fifo_4k_2clk_Group +gui_list_add_group -id Wave.1 {fifo_4k_2clk_Group} + +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +gui_sg_addsignal -group fifo_4k_2clk_Group WRITE -divider +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +gui_sg_addsignal -group fifo_4k_2clk_Group READ -divider +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +gui_zoom -window Wave.1 -full diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_isim.tcl b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_isim.tcl new file mode 100755 index 000000000..10be1a965 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_isim.tcl @@ -0,0 +1,68 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_isim.tcl +# +# Description: +# This is the ISIM wave form file. +# +#-------------------------------------------------------------------------------- +wcfg new +isim set radix hex +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +run all +quit + diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_mti.do b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_mti.do new file mode 100755 index 000000000..adc4cb8d7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_mti.do @@ -0,0 +1,88 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +# Filename: wave_mti.do +# +# Description: +# This is the modelsim wave form file. +# +#-------------------------------------------------------------------------------- + +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +add wave -noupdate -divider WRITE +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +add wave -noupdate -radix hexadecimal /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/DIN +add wave -noupdate -divider READ +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +add wave -noupdate -radix hexadecimal /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/DOUT + +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {2164886 ps} 0} +configure wave -namecolwidth 197 +configure wave -valuecolwidth 106 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps} diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_ncsim.sv b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_ncsim.sv new file mode 100755 index 000000000..51819bad9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_ncsim.sv @@ -0,0 +1,70 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_ncsim.sv +# +# Description: +# This is the IUS wave form file. +# +#-------------------------------------------------------------------------------- + +window new WaveWindow -name "Waves for FIFO Generator Example Design" +waveform using "Waves for FIFO Generator Example Design" + +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +waveform add -label WRITE +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +waveform add -label READ +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +console submit -using simulator -wait no "run" diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.bat new file mode 100755 index 000000000..a6f8ce91f --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.bat @@ -0,0 +1,61 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ..\\..\\implement\\results\\routed.v + +echo "Compiling Test Bench Files" +vhpcomp -work work ..\\fifo_4k_2clk_pkg.vhd +vhpcomp -work work ..\\fifo_4k_2clk_rng.vhd +vhpcomp -work work ..\\fifo_4k_2clk_dgen.vhd +vhpcomp -work work ..\\fifo_4k_2clk_dverif.vhd +vhpcomp -work work ..\\fifo_4k_2clk_pctrl.vhd +vhpcomp -work work ..\\fifo_4k_2clk_synth.vhd +vhpcomp -work work ..\\fifo_4k_2clk_tb.vhd + +fuse work.fifo_4k_2clk_tb work.glbl -L simprims_ver -o fifo_4k_2clk_tb.exe + +.\\fifo_4k_2clk_tb.exe -sdfmax /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst=..\\..\\implement\\results\\routed.sdf -gui -tclbatch .\\wave_isim.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.sh new file mode 100755 index 000000000..f5ad36b7e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.sh @@ -0,0 +1,63 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +vhpcomp -work work ../fifo_4k_2clk_pkg.vhd +vhpcomp -work work ../fifo_4k_2clk_rng.vhd +vhpcomp -work work ../fifo_4k_2clk_dgen.vhd +vhpcomp -work work ../fifo_4k_2clk_dverif.vhd +vhpcomp -work work ../fifo_4k_2clk_pctrl.vhd +vhpcomp -work work ../fifo_4k_2clk_synth.vhd +vhpcomp -work work ../fifo_4k_2clk_tb.vhd + +fuse work.fifo_4k_2clk_tb work.glbl -L simprims_ver -o fifo_4k_2clk_tb.exe + +./fifo_4k_2clk_tb.exe -sdfmax /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst=../../implement/results/routed.sdf -gui -tclbatch ./wave_isim.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.bat new file mode 100755 index 000000000..35375ce20 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.bat @@ -0,0 +1,47 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.do b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.do new file mode 100755 index 000000000..74e930a13 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.do @@ -0,0 +1,72 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vlib work +vmap work work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlog -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +vcom -work work ../fifo_4k_2clk_pkg.vhd +vcom -work work ../fifo_4k_2clk_rng.vhd +vcom -work work ../fifo_4k_2clk_dgen.vhd +vcom -work work ../fifo_4k_2clk_dverif.vhd +vcom -work work ../fifo_4k_2clk_pctrl.vhd +vcom -work work ../fifo_4k_2clk_synth.vhd +vcom -work work ../fifo_4k_2clk_tb.vhd + +vsim -t ps -voptargs="+acc" +transport_int_delays -L simprims_ver glbl -sdfmax /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst=../../implement/results/routed.sdf work.fifo_4k_2clk_tb + +add log -r /* +do wave_mti.do +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.sh new file mode 100755 index 000000000..edb1b0dd9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.sh @@ -0,0 +1,49 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_ncsim.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_ncsim.sh new file mode 100755 index 000000000..a1967adcf --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_ncsim.sh @@ -0,0 +1,73 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +mkdir work +echo "Compiling Core Verilog UNISIM/Behavioral model" +ncvlog -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +ncvhdl -v93 -work work ../fifo_4k_2clk_pkg.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_rng.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_dgen.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_dverif.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_pctrl.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_synth.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_tb.vhd + +echo "Compiling SDF file" +ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X + +echo "Generating SDF command file" +echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd +echo 'SCOPE = :fifo_4k_2clk_synth_inst:fifo_4k_2clk_inst,' >> sdf.cmd +echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd + +echo "Elaborating Design" +ncelab -access +rwc glbl -sdf_cmd_file sdf.cmd work.fifo_4k_2clk_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" work.fifo_4k_2clk_tb diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_vcs.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_vcs.sh new file mode 100755 index 000000000..f62f540be --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_vcs.sh @@ -0,0 +1,67 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogan +v2k ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +vhdlan ../fifo_4k_2clk_pkg.vhd +vhdlan ../fifo_4k_2clk_rng.vhd +vhdlan ../fifo_4k_2clk_dgen.vhd +vhdlan ../fifo_4k_2clk_dverif.vhd +vhdlan ../fifo_4k_2clk_pctrl.vhd +vhdlan ../fifo_4k_2clk_synth.vhd +vhdlan ../fifo_4k_2clk_tb.vhd + +echo "Elaborating Design" +vcs -time_res 1ps +neg_tchk -sdf max:/fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst:../../implement/results/routed.sdf +vcs+lic+wait -debug fifo_4k_2clk_tb glbl + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/ucli_commands.key b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/ucli_commands.key new file mode 100755 index 000000000..9c95a2ade --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/ucli_commands.key @@ -0,0 +1,4 @@ +dump -file fifo_4k_2clk.vpd -type VPD +dump -add fifo_4k_2clk_tb +run +quit diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/vcs_session.tcl b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/vcs_session.tcl new file mode 100755 index 000000000..28ebc1163 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/vcs_session.tcl @@ -0,0 +1,76 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- +if { ![gui_is_db_opened -db {fifo_4k_2clk.vpd}] } { + gui_open_db -design V1 -file fifo_4k_2clk.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + +gui_open_window Wave +gui_sg_create fifo_4k_2clk_Group +gui_list_add_group -id Wave.1 {fifo_4k_2clk_Group} + +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +gui_sg_addsignal -group fifo_4k_2clk_Group WRITE -divider +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +gui_sg_addsignal -group fifo_4k_2clk_Group READ -divider +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +gui_zoom -window Wave.1 -full diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_isim.tcl b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_isim.tcl new file mode 100755 index 000000000..10be1a965 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_isim.tcl @@ -0,0 +1,68 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_isim.tcl +# +# Description: +# This is the ISIM wave form file. +# +#-------------------------------------------------------------------------------- +wcfg new +isim set radix hex +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +run all +quit + diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_mti.do b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_mti.do new file mode 100755 index 000000000..adc4cb8d7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_mti.do @@ -0,0 +1,88 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +# Filename: wave_mti.do +# +# Description: +# This is the modelsim wave form file. +# +#-------------------------------------------------------------------------------- + +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +add wave -noupdate -divider WRITE +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +add wave -noupdate -radix hexadecimal /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/DIN +add wave -noupdate -divider READ +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +add wave -noupdate -radix hexadecimal /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/DOUT + +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {2164886 ps} 0} +configure wave -namecolwidth 197 +configure wave -valuecolwidth 106 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps} diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_ncsim.sv b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_ncsim.sv new file mode 100755 index 000000000..51819bad9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_ncsim.sv @@ -0,0 +1,70 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_ncsim.sv +# +# Description: +# This is the IUS wave form file. +# +#-------------------------------------------------------------------------------- + +window new WaveWindow -name "Waves for FIFO Generator Example Design" +waveform using "Waves for FIFO Generator Example Design" + +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +waveform add -label WRITE +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +waveform add -label READ +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +console submit -using simulator -wait no "run" diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk_flist.txt b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk_flist.txt new file mode 100644 index 000000000..e33a4de1c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk_flist.txt @@ -0,0 +1,56 @@ +# Output products list for +fifo_4k_2clk/doc/fifo_generator_v9_3_readme.txt +fifo_4k_2clk/doc/fifo_generator_v9_3_vinfo.html +fifo_4k_2clk/doc/pg057-fifo-generator.pdf +fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf +fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.vhd +fifo_4k_2clk/fifo_generator_v9_3_readme.txt +fifo_4k_2clk/implement/implement.bat +fifo_4k_2clk/implement/implement.sh +fifo_4k_2clk/implement/implement_synplify.bat +fifo_4k_2clk/implement/implement_synplify.sh +fifo_4k_2clk/implement/planAhead_ise.bat +fifo_4k_2clk/implement/planAhead_ise.sh +fifo_4k_2clk/implement/planAhead_ise.tcl +fifo_4k_2clk/implement/xst.prj +fifo_4k_2clk/implement/xst.scr +fifo_4k_2clk/simulation/fifo_4k_2clk_dgen.vhd +fifo_4k_2clk/simulation/fifo_4k_2clk_dverif.vhd +fifo_4k_2clk/simulation/fifo_4k_2clk_pctrl.vhd +fifo_4k_2clk/simulation/fifo_4k_2clk_pkg.vhd +fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd +fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd +fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd +fifo_4k_2clk/simulation/functional/simulate_isim.bat +fifo_4k_2clk/simulation/functional/simulate_isim.sh +fifo_4k_2clk/simulation/functional/simulate_mti.bat +fifo_4k_2clk/simulation/functional/simulate_mti.do +fifo_4k_2clk/simulation/functional/simulate_mti.sh +fifo_4k_2clk/simulation/functional/simulate_ncsim.sh +fifo_4k_2clk/simulation/functional/simulate_vcs.sh +fifo_4k_2clk/simulation/functional/ucli_commands.key +fifo_4k_2clk/simulation/functional/vcs_session.tcl +fifo_4k_2clk/simulation/functional/wave_isim.tcl +fifo_4k_2clk/simulation/functional/wave_mti.do +fifo_4k_2clk/simulation/functional/wave_ncsim.sv +fifo_4k_2clk/simulation/timing/simulate_isim.bat +fifo_4k_2clk/simulation/timing/simulate_isim.sh +fifo_4k_2clk/simulation/timing/simulate_mti.bat +fifo_4k_2clk/simulation/timing/simulate_mti.do +fifo_4k_2clk/simulation/timing/simulate_mti.sh +fifo_4k_2clk/simulation/timing/simulate_ncsim.sh +fifo_4k_2clk/simulation/timing/simulate_vcs.sh +fifo_4k_2clk/simulation/timing/ucli_commands.key +fifo_4k_2clk/simulation/timing/vcs_session.tcl +fifo_4k_2clk/simulation/timing/wave_isim.tcl +fifo_4k_2clk/simulation/timing/wave_mti.do +fifo_4k_2clk/simulation/timing/wave_ncsim.sv +fifo_4k_2clk.asy +fifo_4k_2clk.gise +fifo_4k_2clk.ngc +fifo_4k_2clk.v +fifo_4k_2clk.veo +fifo_4k_2clk.xco +fifo_4k_2clk.xise +fifo_4k_2clk_flist.txt +fifo_4k_2clk_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk_xmdf.tcl b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk_xmdf.tcl new file mode 100644 index 000000000..bdc5c355d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk_xmdf.tcl @@ -0,0 +1,251 @@ +# The package naming convention is _xmdf +package provide fifo_4k_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_4k_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_4k_2clk_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_4k_2clk +} +# ::fifo_4k_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_4k_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/doc/fifo_generator_v9_3_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/doc/fifo_generator_v9_3_vinfo.html +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/doc/pg057-fifo-generator.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/fifo_generator_v9_3_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/implement.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/implement.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/implement_synplify.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/implement_synplify.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/planAhead_ise.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/planAhead_ise.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/planAhead_ise.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/xst.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/xst.scr +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_dgen.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_dverif.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_pctrl.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_pkg.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_isim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/wave_isim.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/wave_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/wave_ncsim.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_isim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/wave_isim.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/wave_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/wave_ncsim.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_4k_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.asy b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.asy new file mode 100644 index 000000000..1c03599f3 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 fifo_short_2clk +RECTANGLE Normal 32 32 800 4064 +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName rst +PINATTR Polarity IN +LINE Normal 0 208 32 208 +PIN 0 208 LEFT 36 +PINATTR PinName wr_clk +PINATTR Polarity IN +LINE Wide 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName din[71:0] +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName wr_en +PINATTR Polarity IN +LINE Normal 0 464 32 464 +PIN 0 464 LEFT 36 +PINATTR PinName full +PINATTR Polarity OUT +LINE Wide 0 624 32 624 +PIN 0 624 LEFT 36 +PINATTR PinName wr_data_count[5:0] +PINATTR Polarity OUT +LINE Normal 832 240 800 240 +PIN 832 240 RIGHT 36 +PINATTR PinName rd_clk +PINATTR Polarity IN +LINE Wide 832 272 800 272 +PIN 832 272 RIGHT 36 +PINATTR PinName dout[71:0] +PINATTR Polarity OUT +LINE Normal 832 304 800 304 +PIN 832 304 RIGHT 36 +PINATTR PinName rd_en +PINATTR Polarity IN +LINE Normal 832 496 800 496 +PIN 832 496 RIGHT 36 +PINATTR PinName empty +PINATTR Polarity OUT +LINE Wide 832 656 800 656 +PIN 832 656 RIGHT 36 +PINATTR PinName rd_data_count[5:0] +PINATTR Polarity OUT + diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.ncf b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.ngc b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.ngc new file mode 100644 index 000000000..ec6b0ff10 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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f1=<080bn853`98k136290/o:4;939mg3<4j21d88>50;&`3?2>:2dh:7=l;:m70c<72-i<697=;oa5>6b<3f>2:7>5$b590<45<#k>0?5?5ac780b>=h<0>1<7*l7;6:6>hd>3>;76a;9183>!e02=397cm9:538?j2?=3:1(n954808jf0=<;10c99n:18'g2<31;1eo;4;3:9l03`=83.h;7:62:l`2?2332e?:94?:%a4>1?53gi=69;4;n66=?6=,j=184<4nb4903=n6=4+c687=7=ik?0?;65`4`f94?"d?3>jo6`l6;28?j2fj3:1(n954`a8jf0=921d8lo50;&`3?2fk2dh:7<4;n6b=?6=,j=18lm4nb497>=hhd>3>07b:n7;29 f1=io7>5$b590gbih6`l6;08?j2ei3:1(n954cf8jf0=;21d8o750;&`3?2el2dh:7:4;n6a=hN4l01/m948;h7f>5<=1<75fc883>>idj3:17pl>b283>1<729q/h>468:J0``=O;m30(l:57:k6a?6=3`=<6=44ib;94?=hkk0;66sm1c094?2=83:p(i=5999K7ac<@:n27)o;:69j1`<722c<;7>5;ha:>5<5<3290;w)j<:848L6bb3A9o56*n4;08m0c=831b;>4?::k43?6=3fii6=44}c1``?6=<3:1i7>5;h54>5<>{e;m91<7:50;2x a5=111C?ik4H2f:?M3f3-h96i<4i4g94?=n?>0;66gl9;29?jee2900qo=l2;290?6=8r.o?777;I1ga>N4l01C9l5+b38g6>"f<3=0e8k50;9j32<722ch57>5;naa>5<53;294~"c;33>7E=ke:J0`<=O=h1/n?4k2:&b0?4>idj3:17pl6<729q/h>465:J0``=O;m30D8o4$c09`7=#i=097d;j:188m21=831doo4?::a7f7=83>1<7>t$e19===O;mo0D>j6;I7b?!d52m80(l:57:k6a?6=3`=<6=44ib;94?=hkk0;66sm3b:94?2=83:p(i=5999K7ac<@:n27)o;:69j1`<722c<;7>5;ha:>5<5<3290;w)j<:8:8L6bb3A9o56*n4;58m0c=831b;:4?::k`=?6=3fii6=44}c1`2?6=<3:15;|`0gc<72:0;6=u+d28:1>N4ll1C?i74H4c8 g4=l;1/m94=;h7f>5<=1<75`cc83>>{e;ji1<7:50;2x a5=111C?ik4H2f:?!g32>1b9h4?::k43?6=3`i26=44ob`94?=zj:ii6=4;:183!b42020D>jj;I1g=>"f<3=0e8k50;9j32<722ch57>5;naa>5<53;294~"c;33>7E=ke:J0`<=O=h1/n?4k2:&b0?4>idj3:17pl1<729q/h>468:J0``=O;m30D8o4$c09`7=#i=0<7d;j:188m21=831bo44?::m`f?6=3th94o4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`1N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9454?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`1<2<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th94;4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`1<0<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9494?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`1<6<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th94?4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`1<4<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th94=4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`13c<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;i4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`13f<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;o4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`13d<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;44?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`13=<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;:4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`133<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;84?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`131<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;?4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`134<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;=4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`12c<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9:h4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`12a<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9:n4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`12g<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9:l4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`12<<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9::4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`123<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9:84?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`121<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9:>4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`127<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9:<4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`125<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th99k4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`11`<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th99n4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`11g<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th99l4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`11<<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9954?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`112<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th99;4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`110<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9994?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`116<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th99<4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`115<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th98k4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`10`<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th98i4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`10f<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th98o4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`10d<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9844?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`10=<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th94i4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`1N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9444?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`13`<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;>4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`12=<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th99i4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`117<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th98:4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`103<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th95=4?:3494?6|,m91on5G3eg8L6b>3S?o6nu>8;3:>4g=9k0i6n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a5=kj1C?ik4H2f:?_3c2jq:47?6:0c95g6=#i>087)o7:29j7ad=831b?im50;9j3g<72-i<6:o4nb494>=n?00;6)m8:6c8jf0=921b;h4?:%a4>2b!e02>n0bn851:9j<4<72-i<65>4nb494>=n?o0;6)m8:928jf0=921b494?:%a4>=5!e02190bn851:9j00<72-i<69:4nb494>=n<:0;6)m8:568jf0=921b8?4?:%a4>1265f4083>!e02=>0bn853:9j05<72-i<69:4nb490>=n1g!e02=k0bn852:9j02<72-i<69o4nb497>=n06!e02<:0bn851:9j0`<72-i<68>4nb496>=n06!e02<<0bn850:9j10<72-i<6884nb495>=n==0;6)m8:448jf0=:21b9>4?:%a4>00!e02<<0bn854:9l<2<72-i<6584nb494>=h0<0;6)m8:948jf0=921d4l4?:%a4>=?!e02130bn851:9l=h0k0;6)m8:9a8jf0=921d5=4?:%a4>=`!e021l0bn851:9~f7?42909:7>50z&g7?ed3A9oi6Fa;3a>g0;32>44=u-k>6>5+a780?!g02:1/m54<;h1gf?6=3`9oo7>5;h5a>5<#k>0290/o:48a:l`2?7<3`=n6=4+c684`>hd>3:07d9l:18'g2<0l2dh:7?4;h:2>5<#k>03<6`l6;28?l1a290/o:470:l`2?7<3`2?6=4+c68;7>hd>3:07d6=:18'g25<#k>0?86`l6;28?l24290/o:4;4:l`2?7<3`>96=4+c6870>hd>3807d:>:18'g2<3<2dh:7=4;h63>5<#k>0?86`l6;68?l2e290/o:4;a:l`2?6<3`>26=4+c687e>hd>3;07d:7:18'g2<3i2dh:7<4;h64>5<#k>0?m6`l6;18?l21290/o:4;a:l`2?2<3`?:6=4+c6864>hd>3:07d:i:18'g2<282dh:7?4;h6f>5<#k>0><6`l6;08?l2c290/o:4:0:l`2?5<3`>h6=4+c6864>hd>3>07d;8:18'g2<2>2dh:7>4;h76>5<#k>0>:6`l6;38?l33290/o:4:6:l`2?4<3`?86=4+c6862>hd>3907d;=:18'g2<2>2dh:7:4;n:4>5<#k>03:6`l6;28?j>2290/o:476:l`2?7<3f2j6=4+c68;=>hd>3:07b67:18'g25<#k>03o6`l6;28?j>e290/o:47c:l`2?7<3f3;6=4+c68;b>hd>3:07b6j:18'g2N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8n<4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0ea<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8mo4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0e<<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8m:4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0e0<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8m>4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0e4<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th85k4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0=a<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th85o4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0=2<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8584?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0=6<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th85<4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th84i4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8444?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0<2<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8484?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0<4<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8;k4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`03a<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8;o4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`03<<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8;:4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`030<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8;>4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`034<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8:k4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`02g<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8:44?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`022<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8:84?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`026<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8:<4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`01c<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th89i4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`01g<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8944?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`010<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th89>4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`014<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th88k4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`00a<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th88o4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`00<<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th88:4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`000<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th88>4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`07c<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8?i4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`07g<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8?44?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`072<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8?84?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`076<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8?<4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`06c<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8>i4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0f=<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8n;4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0f5<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th85l4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0<1<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8:h4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`01=<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th88?4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`06f<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8>l4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`234<72=0;6=u+d28:2>N4ll1C?i74$`696>o2m3:17d9<:188m21=831doo4?::a526=83>1<7>t$e19=3=O;mo0D>j6;%c7>7=n=l0;66g83;29?l102900cnl50;9~f40a290?6=4?{%f0><0<@:nn7E=k9:&b0?4>o0?3:17bmm:188yg71m3:187>50z&g7??13A9oi6F0;66alb;29?xd6>m0;694?:1y'`6<>>2B8hh5G3e;8 d2=:2c>i7>5;h50>5<=1<75`cc83>>{e9?i1<7:50;2x a5=1?1C?ik4H2f:?!g32;1b9h4?::k47?6=3`=<6=44ob`94?=zj8k26=4::183!b420=0D>jj;I1g=>"f<380e8k50;9j25<722c5;h54>5<5<2290;w)j<:858L6bb3A9o56*n4;08m0c=831b:=4?::k47?6=3`=<6=44ob`94?=zj8k>6=4::183!b420=0D>jj;I1g=>"f<380e8k50;9j25<722c5;h54>5<5<2290;w)j<:858L6bb3A9o56*n4;08m0c=831b:=4?::k47?6=3`=<6=44ob`94?=zj83n6=4::183!b420=0D>jj;I1g=>"f<380e8k50;9j25<722c5;h54>5<5<2290;w)j<:858L6bb3A9o56*n4;08m0c=831b:=4?::k47?6=3`=<6=44ob`94?=zj83h6=4::183!b420=0D>jj;I1g=>"f<380e8k50;9j25<722c5;h54>5<5<2290;w)j<:858L6bb3A9o56*n4;08m0c=831b:=4?::k47?6=3`=<6=44ob`94?=zj8326=4::183!b42030D>jj;I1g=>"f<3=0e8k50;9j25<722c<;7>5;ha:>5<5<3290;w)j<:848L6bb3A9o56*n4;08m0c=831b;>4?::k43?6=3fii6=44}c343?6=<3:15;|`2<4<72=0;6=u+d28:2>N4ll1C?i74$`696>o2m3:17d9<:188m21=831doo4?::a52b=83>1<7>t$e19===O;mo0D>j6;%c7>2=n=l0;66g87;29?le>2900cnl50;9~f41d290?6=4?{%f0><><@:nn7E=k9:&b0?1>od13:17bmm:188yg7c03:187>50z&g7??13A9oi6F0;66alb;29?xd6l>0;694?:1y'`6<>>2B8hh5G3e;8 d2=:2c>i7>5;h50>5<=1<75`cc83>>{e9m<1<7:50;2x a5=1?1C?ik4H2f:?!g32;1b9h4?::k47?6=3`=<6=44ob`94?=zj8n>6=4;:183!b420<0D>jj;I1g=>"f<380e8k50;9j36<722c<;7>5;naa>5<54;294~"c;33=7E=ke:J0`<=#i=097d;j:188m25=831b;:4?::m`f?6=3th:h>4?:583>5}#l:02:6F1>6g:e;29?l142900e:950;9lgg<722wi=k750;794?6|,m915:5G3eg8L6b>3-k?6?5f5d83>>o183:17d9<:188m21=831doo4?::a5c>=83?1<7>t$e19=2=O;mo0D>j6;%c7>7=n=l0;66g90;29?l142900e:950;9lgg<722wi=k950;794?6|,m915:5G3eg8L6b>3-k?6?5f5d83>>o183:17d9<:188m21=831doo4?::a5c5=83?1<7>t$e19=2=O;mo0D>j6;%c7>7=n=l0;66g90;29?l142900e:950;9lgg<722wi=k<50;794?6|,m915:5G3eg8L6b>3-k?6?5f5d83>>o183:17d9<:188m21=831doo4?::a5c7=83?1<7>t$e19=2=O;mo0D>j6;%c7>7=n=l0;66g90;29?l142900e:950;9lgg<722wi=k>50;794?6|,m915:5G3eg8L6b>3-k?6?5f5d83>>o183:17d9<:188m21=831doo4?::a5``=83?1<7>t$e19=<=O;mo0D>j6;%c7>2=n=l0;66g90;29?l102900en750;9lgg<722wi=h750;794?6|,m915:5G3eg8L6b>3-k?6?5f5d83>>o183:17d9<:188m21=831doo4?::a5`>=83?1<7>t$e19=2=O;mo0D>j6;%c7>7=n=l0;66g90;29?l142900e:950;9lgg<722wi=h950;794?6|,m915:5G3eg8L6b>3-k?6?5f5d83>>o183:17d9<:188m21=831doo4?::a5`0=83?1<7>t$e19=<=O;mo0D>j6;%c7>2=n=l0;66g90;29?l102900en750;9lgg<722wij>4?:583>5}#l:02:6F0;66alb;29?xda<3:187>50z&g7??13A9oi6F6*n4;08m0c=831b;>4?::k43?6=3fii6=44}cd6>5<3290;w)j<:848L6bb3A9o56F:a:&a6?b53-k?6?5f5d83>>o0;3:17d98:188kfd=831vnk850;694?6|,m915;5G3eg8L6b>3A?j7)l=:e08 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.v b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.v new file mode 100644 index 000000000..82200a502 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.v @@ -0,0 +1,491 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2013 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// You must compile the wrapper file fifo_short_2clk.v when simulating +// the core, fifo_short_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +`timescale 1ns/1ps + +module fifo_short_2clk( + rst, + wr_clk, + rd_clk, + din, + wr_en, + rd_en, + dout, + full, + empty, + rd_data_count, + wr_data_count +); + +input rst; +input wr_clk; +input rd_clk; +input [71 : 0] din; +input wr_en; +input rd_en; +output [71 : 0] dout; +output full; +output empty; +output [5 : 0] rd_data_count; +output [5 : 0] wr_data_count; + +// synthesis translate_off + + FIFO_GENERATOR_V9_3 #( + .C_ADD_NGC_CONSTRAINT(0), + .C_APPLICATION_TYPE_AXIS(0), + .C_APPLICATION_TYPE_RACH(0), + .C_APPLICATION_TYPE_RDCH(0), + .C_APPLICATION_TYPE_WACH(0), + .C_APPLICATION_TYPE_WDCH(0), + .C_APPLICATION_TYPE_WRCH(0), + .C_AXI_ADDR_WIDTH(32), + .C_AXI_ARUSER_WIDTH(1), + .C_AXI_AWUSER_WIDTH(1), + .C_AXI_BUSER_WIDTH(1), + .C_AXI_DATA_WIDTH(64), + .C_AXI_ID_WIDTH(4), + .C_AXI_RUSER_WIDTH(1), + .C_AXI_TYPE(0), + .C_AXI_WUSER_WIDTH(1), + .C_AXIS_TDATA_WIDTH(64), + .C_AXIS_TDEST_WIDTH(4), + .C_AXIS_TID_WIDTH(8), + .C_AXIS_TKEEP_WIDTH(4), + .C_AXIS_TSTRB_WIDTH(4), + .C_AXIS_TUSER_WIDTH(4), + .C_AXIS_TYPE(0), + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(5), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(72), + .C_DIN_WIDTH_AXIS(1), + .C_DIN_WIDTH_RACH(32), + .C_DIN_WIDTH_RDCH(64), + .C_DIN_WIDTH_WACH(32), + .C_DIN_WIDTH_WDCH(64), + .C_DIN_WIDTH_WRCH(2), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(72), + .C_ENABLE_RLOCS(0), + .C_ENABLE_RST_SYNC(1), + .C_ERROR_INJECTION_TYPE(0), + .C_ERROR_INJECTION_TYPE_AXIS(0), + .C_ERROR_INJECTION_TYPE_RACH(0), + .C_ERROR_INJECTION_TYPE_RDCH(0), + .C_ERROR_INJECTION_TYPE_WACH(0), + .C_ERROR_INJECTION_TYPE_WDCH(0), + .C_ERROR_INJECTION_TYPE_WRCH(0), + .C_FAMILY("spartan6"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_AXI_ARUSER(0), + .C_HAS_AXI_AWUSER(0), + .C_HAS_AXI_BUSER(0), + .C_HAS_AXI_RD_CHANNEL(0), + .C_HAS_AXI_RUSER(0), + .C_HAS_AXI_WR_CHANNEL(0), + .C_HAS_AXI_WUSER(0), + .C_HAS_AXIS_TDATA(0), + .C_HAS_AXIS_TDEST(0), + .C_HAS_AXIS_TID(0), + .C_HAS_AXIS_TKEEP(0), + .C_HAS_AXIS_TLAST(0), + .C_HAS_AXIS_TREADY(1), + .C_HAS_AXIS_TSTRB(0), + .C_HAS_AXIS_TUSER(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_DATA_COUNTS_AXIS(0), + .C_HAS_DATA_COUNTS_RACH(0), + .C_HAS_DATA_COUNTS_RDCH(0), + .C_HAS_DATA_COUNTS_WACH(0), + .C_HAS_DATA_COUNTS_WDCH(0), + .C_HAS_DATA_COUNTS_WRCH(0), + .C_HAS_INT_CLK(0), + .C_HAS_MASTER_CE(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_PROG_FLAGS_AXIS(0), + .C_HAS_PROG_FLAGS_RACH(0), + .C_HAS_PROG_FLAGS_RDCH(0), + .C_HAS_PROG_FLAGS_WACH(0), + .C_HAS_PROG_FLAGS_WDCH(0), + .C_HAS_PROG_FLAGS_WRCH(0), + .C_HAS_RD_DATA_COUNT(1), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SLAVE_CE(0), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(1), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_IMPLEMENTATION_TYPE_AXIS(1), + .C_IMPLEMENTATION_TYPE_RACH(1), + .C_IMPLEMENTATION_TYPE_RDCH(1), + .C_IMPLEMENTATION_TYPE_WACH(1), + .C_IMPLEMENTATION_TYPE_WDCH(1), + .C_IMPLEMENTATION_TYPE_WRCH(1), + .C_INIT_WR_PNTR_VAL(0), + .C_INTERFACE_TYPE(0), + .C_MEMORY_TYPE(2), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("512x72"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_EMPTY_TYPE_AXIS(0), + .C_PROG_EMPTY_TYPE_RACH(0), + .C_PROG_EMPTY_TYPE_RDCH(0), + .C_PROG_EMPTY_TYPE_WACH(0), + .C_PROG_EMPTY_TYPE_WDCH(0), + .C_PROG_EMPTY_TYPE_WRCH(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(31), + .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023), + .C_PROG_FULL_THRESH_NEGATE_VAL(30), + .C_PROG_FULL_TYPE(0), + .C_PROG_FULL_TYPE_AXIS(0), + .C_PROG_FULL_TYPE_RACH(0), + .C_PROG_FULL_TYPE_RDCH(0), + .C_PROG_FULL_TYPE_WACH(0), + .C_PROG_FULL_TYPE_WDCH(0), + .C_PROG_FULL_TYPE_WRCH(0), + .C_RACH_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(6), + .C_RD_DEPTH(32), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(5), + .C_RDCH_TYPE(0), + .C_REG_SLICE_MODE_AXIS(0), + .C_REG_SLICE_MODE_RACH(0), + .C_REG_SLICE_MODE_RDCH(0), + .C_REG_SLICE_MODE_WACH(0), + .C_REG_SLICE_MODE_WDCH(0), + .C_REG_SLICE_MODE_WRCH(0), + .C_SYNCHRONIZER_STAGE(2), + .C_UNDERFLOW_LOW(0), + .C_USE_COMMON_OVERFLOW(0), + .C_USE_COMMON_UNDERFLOW(0), + .C_USE_DEFAULT_SETTINGS(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_ECC_AXIS(0), + .C_USE_ECC_RACH(0), + .C_USE_ECC_RDCH(0), + .C_USE_ECC_WACH(0), + .C_USE_ECC_WDCH(0), + .C_USE_ECC_WRCH(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(1), + .C_VALID_LOW(0), + .C_WACH_TYPE(0), + .C_WDCH_TYPE(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(6), + .C_WR_DEPTH(32), + .C_WR_DEPTH_AXIS(1024), + .C_WR_DEPTH_RACH(16), + .C_WR_DEPTH_RDCH(1024), + .C_WR_DEPTH_WACH(16), + .C_WR_DEPTH_WDCH(1024), + .C_WR_DEPTH_WRCH(16), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(5), + .C_WR_PNTR_WIDTH_AXIS(10), + .C_WR_PNTR_WIDTH_RACH(4), + .C_WR_PNTR_WIDTH_RDCH(10), + .C_WR_PNTR_WIDTH_WACH(4), + .C_WR_PNTR_WIDTH_WDCH(10), + .C_WR_PNTR_WIDTH_WRCH(4), + .C_WR_RESPONSE_LATENCY(1), + .C_WRCH_TYPE(0) + ) + inst ( + .RST(rst), + .WR_CLK(wr_clk), + .RD_CLK(rd_clk), + .DIN(din), + .WR_EN(wr_en), + .RD_EN(rd_en), + .DOUT(dout), + .FULL(full), + .EMPTY(empty), + .RD_DATA_COUNT(rd_data_count), + .WR_DATA_COUNT(wr_data_count), + .BACKUP(), + .BACKUP_MARKER(), + .CLK(), + .SRST(), + .WR_RST(), + .RD_RST(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .INT_CLK(), + .INJECTDBITERR(), + .INJECTSBITERR(), + .ALMOST_FULL(), + .WR_ACK(), + .OVERFLOW(), + .ALMOST_EMPTY(), + .VALID(), + .UNDERFLOW(), + .DATA_COUNT(), + .PROG_FULL(), + .PROG_EMPTY(), + .SBITERR(), + .DBITERR(), + .M_ACLK(), + .S_ACLK(), + .S_ARESETN(), + .M_ACLK_EN(), + .S_ACLK_EN(), + .S_AXI_AWID(), + .S_AXI_AWADDR(), + .S_AXI_AWLEN(), + .S_AXI_AWSIZE(), + .S_AXI_AWBURST(), + .S_AXI_AWLOCK(), + .S_AXI_AWCACHE(), + .S_AXI_AWPROT(), + .S_AXI_AWQOS(), + .S_AXI_AWREGION(), + .S_AXI_AWUSER(), + .S_AXI_AWVALID(), + .S_AXI_AWREADY(), + .S_AXI_WID(), + .S_AXI_WDATA(), + .S_AXI_WSTRB(), + .S_AXI_WLAST(), + .S_AXI_WUSER(), + .S_AXI_WVALID(), + .S_AXI_WREADY(), + .S_AXI_BID(), + .S_AXI_BRESP(), + .S_AXI_BUSER(), + .S_AXI_BVALID(), + .S_AXI_BREADY(), + .M_AXI_AWID(), + .M_AXI_AWADDR(), + .M_AXI_AWLEN(), + .M_AXI_AWSIZE(), + .M_AXI_AWBURST(), + .M_AXI_AWLOCK(), + .M_AXI_AWCACHE(), + .M_AXI_AWPROT(), + .M_AXI_AWQOS(), + .M_AXI_AWREGION(), + .M_AXI_AWUSER(), + .M_AXI_AWVALID(), + .M_AXI_AWREADY(), + .M_AXI_WID(), + .M_AXI_WDATA(), + .M_AXI_WSTRB(), + .M_AXI_WLAST(), + .M_AXI_WUSER(), + .M_AXI_WVALID(), + .M_AXI_WREADY(), + .M_AXI_BID(), + .M_AXI_BRESP(), + .M_AXI_BUSER(), + .M_AXI_BVALID(), + .M_AXI_BREADY(), + .S_AXI_ARID(), + .S_AXI_ARADDR(), + .S_AXI_ARLEN(), + .S_AXI_ARSIZE(), + .S_AXI_ARBURST(), + .S_AXI_ARLOCK(), + .S_AXI_ARCACHE(), + .S_AXI_ARPROT(), + .S_AXI_ARQOS(), + .S_AXI_ARREGION(), + .S_AXI_ARUSER(), + .S_AXI_ARVALID(), + .S_AXI_ARREADY(), + .S_AXI_RID(), + .S_AXI_RDATA(), + .S_AXI_RRESP(), + .S_AXI_RLAST(), + .S_AXI_RUSER(), + .S_AXI_RVALID(), + .S_AXI_RREADY(), + .M_AXI_ARID(), + .M_AXI_ARADDR(), + .M_AXI_ARLEN(), + .M_AXI_ARSIZE(), + .M_AXI_ARBURST(), + .M_AXI_ARLOCK(), + .M_AXI_ARCACHE(), + .M_AXI_ARPROT(), + .M_AXI_ARQOS(), + .M_AXI_ARREGION(), + .M_AXI_ARUSER(), + .M_AXI_ARVALID(), + .M_AXI_ARREADY(), + .M_AXI_RID(), + .M_AXI_RDATA(), + .M_AXI_RRESP(), + .M_AXI_RLAST(), + .M_AXI_RUSER(), + .M_AXI_RVALID(), + .M_AXI_RREADY(), + .S_AXIS_TVALID(), + .S_AXIS_TREADY(), + .S_AXIS_TDATA(), + .S_AXIS_TSTRB(), + .S_AXIS_TKEEP(), + .S_AXIS_TLAST(), + .S_AXIS_TID(), + .S_AXIS_TDEST(), + .S_AXIS_TUSER(), + .M_AXIS_TVALID(), + .M_AXIS_TREADY(), + .M_AXIS_TDATA(), + .M_AXIS_TSTRB(), + .M_AXIS_TKEEP(), + .M_AXIS_TLAST(), + .M_AXIS_TID(), + .M_AXIS_TDEST(), + .M_AXIS_TUSER(), + .AXI_AW_INJECTSBITERR(), + .AXI_AW_INJECTDBITERR(), + .AXI_AW_PROG_FULL_THRESH(), + .AXI_AW_PROG_EMPTY_THRESH(), + .AXI_AW_DATA_COUNT(), + .AXI_AW_WR_DATA_COUNT(), + .AXI_AW_RD_DATA_COUNT(), + .AXI_AW_SBITERR(), + .AXI_AW_DBITERR(), + .AXI_AW_OVERFLOW(), + .AXI_AW_UNDERFLOW(), + .AXI_AW_PROG_FULL(), + .AXI_AW_PROG_EMPTY(), + .AXI_W_INJECTSBITERR(), + .AXI_W_INJECTDBITERR(), + .AXI_W_PROG_FULL_THRESH(), + .AXI_W_PROG_EMPTY_THRESH(), + .AXI_W_DATA_COUNT(), + .AXI_W_WR_DATA_COUNT(), + .AXI_W_RD_DATA_COUNT(), + .AXI_W_SBITERR(), + .AXI_W_DBITERR(), + .AXI_W_OVERFLOW(), + .AXI_W_UNDERFLOW(), + .AXI_B_INJECTSBITERR(), + .AXI_W_PROG_FULL(), + .AXI_W_PROG_EMPTY(), + .AXI_B_INJECTDBITERR(), + .AXI_B_PROG_FULL_THRESH(), + .AXI_B_PROG_EMPTY_THRESH(), + .AXI_B_DATA_COUNT(), + .AXI_B_WR_DATA_COUNT(), + .AXI_B_RD_DATA_COUNT(), + .AXI_B_SBITERR(), + .AXI_B_DBITERR(), + .AXI_B_OVERFLOW(), + .AXI_B_UNDERFLOW(), + .AXI_AR_INJECTSBITERR(), + .AXI_B_PROG_FULL(), + .AXI_B_PROG_EMPTY(), + .AXI_AR_INJECTDBITERR(), + .AXI_AR_PROG_FULL_THRESH(), + .AXI_AR_PROG_EMPTY_THRESH(), + .AXI_AR_DATA_COUNT(), + .AXI_AR_WR_DATA_COUNT(), + .AXI_AR_RD_DATA_COUNT(), + .AXI_AR_SBITERR(), + .AXI_AR_DBITERR(), + .AXI_AR_OVERFLOW(), + .AXI_AR_UNDERFLOW(), + .AXI_AR_PROG_FULL(), + .AXI_AR_PROG_EMPTY(), + .AXI_R_INJECTSBITERR(), + .AXI_R_INJECTDBITERR(), + .AXI_R_PROG_FULL_THRESH(), + .AXI_R_PROG_EMPTY_THRESH(), + .AXI_R_DATA_COUNT(), + .AXI_R_WR_DATA_COUNT(), + .AXI_R_RD_DATA_COUNT(), + .AXI_R_SBITERR(), + .AXI_R_DBITERR(), + .AXI_R_OVERFLOW(), + .AXI_R_UNDERFLOW(), + .AXIS_INJECTSBITERR(), + .AXI_R_PROG_FULL(), + .AXI_R_PROG_EMPTY(), + .AXIS_INJECTDBITERR(), + .AXIS_PROG_FULL_THRESH(), + .AXIS_PROG_EMPTY_THRESH(), + .AXIS_DATA_COUNT(), + .AXIS_WR_DATA_COUNT(), + .AXIS_RD_DATA_COUNT(), + .AXIS_SBITERR(), + .AXIS_DBITERR(), + .AXIS_OVERFLOW(), + .AXIS_UNDERFLOW(), + .AXIS_PROG_FULL(), + .AXIS_PROG_EMPTY() + ); + +// synthesis translate_on + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.veo b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.veo new file mode 100644 index 000000000..06d74a77c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.veo @@ -0,0 +1,79 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2013 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ + +/******************************************************************************* +* Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 * +* * +* Rev 1. The FIFO Generator is a parameterizable first-in/first-out * +* memory queue generator. Use it to generate resource and performance * +* optimized FIFOs with common or independent read/write clock domains, * +* and optional fixed or programmable full and empty flags and * +* handshaking signals. Choose from a selection of memory resource * +* types for implementation. Optional Hamming code based error * +* detection and correction as well as error injection capability for * +* system test help to insure data integrity. FIFO width and depth are * +* parameterizable, and for native interface FIFOs, asymmetric read and * +* write port widths are also supported. * +*******************************************************************************/ + +// Interfaces: +// AXI4Stream_MASTER_M_AXIS +// AXI4Stream_SLAVE_S_AXIS +// AXI4_MASTER_M_AXI +// AXI4_SLAVE_S_AXI +// AXI4Lite_MASTER_M_AXI +// AXI4Lite_SLAVE_S_AXI +// master_aclk +// slave_aclk +// slave_aresetn + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_short_2clk your_instance_name ( + .rst(rst), // input rst + .wr_clk(wr_clk), // input wr_clk + .rd_clk(rd_clk), // input rd_clk + .din(din), // input [71 : 0] din + .wr_en(wr_en), // input wr_en + .rd_en(rd_en), // input rd_en + .dout(dout), // output [71 : 0] dout + .full(full), // output full + .empty(empty), // output empty + .rd_data_count(rd_data_count), // output [5 : 0] rd_data_count + .wr_data_count(wr_data_count) // output [5 : 0] wr_data_count +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_short_2clk.v when simulating +// the core, fifo_short_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xco b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xco new file mode 100644 index 000000000..0f256d496 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xco @@ -0,0 +1,213 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Fri Mar 8 18:15:07 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fifo_generator:9.3 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 +# END Select +# BEGIN Parameters +CSET add_ngc_constraint_axi=false +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET aruser_width=1 +CSET awuser_width=1 +CSET axi_address_width=32 +CSET axi_data_width=64 +CSET axi_type=AXI4_Stream +CSET axis_type=FIFO +CSET buser_width=1 +CSET clock_enable_type=Slave_Interface_Clock_Enable +CSET clock_type_axi=Common_Clock +CSET component_name=fifo_short_2clk +CSET data_count=false +CSET data_count_width=5 +CSET disable_timing_violations=false +CSET disable_timing_violations_axi=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_assert_value_axis=1022 +CSET empty_threshold_assert_value_rach=1022 +CSET empty_threshold_assert_value_rdch=1022 +CSET empty_threshold_assert_value_wach=1022 +CSET empty_threshold_assert_value_wdch=1022 +CSET empty_threshold_assert_value_wrch=1022 +CSET empty_threshold_negate_value=5 +CSET enable_aruser=false +CSET enable_awuser=false +CSET enable_buser=false +CSET enable_common_overflow=false +CSET enable_common_underflow=false +CSET enable_data_counts_axis=false +CSET enable_data_counts_rach=false +CSET enable_data_counts_rdch=false +CSET enable_data_counts_wach=false +CSET enable_data_counts_wdch=false +CSET enable_data_counts_wrch=false +CSET enable_ecc=false +CSET enable_ecc_axis=false +CSET enable_ecc_rach=false +CSET enable_ecc_rdch=false +CSET enable_ecc_wach=false +CSET enable_ecc_wdch=false +CSET enable_ecc_wrch=false +CSET enable_read_channel=false +CSET enable_read_pointer_increment_by2=false +CSET enable_reset_synchronization=true +CSET enable_ruser=false +CSET enable_tdata=false +CSET enable_tdest=false +CSET enable_tid=false +CSET enable_tkeep=false +CSET enable_tlast=false +CSET enable_tready=true +CSET enable_tstrobe=false +CSET enable_tuser=false +CSET enable_write_channel=false +CSET enable_wuser=false +CSET fifo_application_type_axis=Data_FIFO +CSET fifo_application_type_rach=Data_FIFO +CSET fifo_application_type_rdch=Data_FIFO +CSET fifo_application_type_wach=Data_FIFO +CSET fifo_application_type_wdch=Data_FIFO +CSET fifo_application_type_wrch=Data_FIFO +CSET fifo_implementation=Independent_Clocks_Distributed_RAM +CSET fifo_implementation_axis=Common_Clock_Block_RAM +CSET fifo_implementation_rach=Common_Clock_Block_RAM +CSET fifo_implementation_rdch=Common_Clock_Block_RAM +CSET fifo_implementation_wach=Common_Clock_Block_RAM +CSET fifo_implementation_wdch=Common_Clock_Block_RAM +CSET fifo_implementation_wrch=Common_Clock_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=31 +CSET full_threshold_assert_value_axis=1023 +CSET full_threshold_assert_value_rach=1023 +CSET full_threshold_assert_value_rdch=1023 +CSET full_threshold_assert_value_wach=1023 +CSET full_threshold_assert_value_wdch=1023 +CSET full_threshold_assert_value_wrch=1023 +CSET full_threshold_negate_value=30 +CSET id_width=4 +CSET inject_dbit_error=false +CSET inject_dbit_error_axis=false +CSET inject_dbit_error_rach=false +CSET inject_dbit_error_rdch=false +CSET inject_dbit_error_wach=false +CSET inject_dbit_error_wdch=false +CSET inject_dbit_error_wrch=false +CSET inject_sbit_error=false +CSET inject_sbit_error_axis=false +CSET inject_sbit_error_rach=false +CSET inject_sbit_error_rdch=false +CSET inject_sbit_error_wach=false +CSET inject_sbit_error_wdch=false +CSET inject_sbit_error_wrch=false +CSET input_data_width=72 +CSET input_depth=32 +CSET input_depth_axis=1024 +CSET input_depth_rach=16 +CSET input_depth_rdch=1024 +CSET input_depth_wach=16 +CSET input_depth_wdch=1024 +CSET input_depth_wrch=16 +CSET interface_type=Native +CSET output_data_width=72 +CSET output_depth=32 +CSET overflow_flag=false +CSET overflow_flag_axi=false +CSET overflow_sense=Active_High +CSET overflow_sense_axi=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET programmable_full_type_axis=No_Programmable_Full_Threshold +CSET programmable_full_type_rach=No_Programmable_Full_Threshold +CSET programmable_full_type_rdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wach=No_Programmable_Full_Threshold +CSET programmable_full_type_wdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wrch=No_Programmable_Full_Threshold +CSET rach_type=FIFO +CSET rdch_type=FIFO +CSET read_clock_frequency=1 +CSET read_data_count=true +CSET read_data_count_width=6 +CSET register_slice_mode_axis=Fully_Registered +CSET register_slice_mode_rach=Fully_Registered +CSET register_slice_mode_rdch=Fully_Registered +CSET register_slice_mode_wach=Fully_Registered +CSET register_slice_mode_wdch=Fully_Registered +CSET register_slice_mode_wrch=Fully_Registered +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET ruser_width=1 +CSET synchronization_stages=2 +CSET synchronization_stages_axi=2 +CSET tdata_width=64 +CSET tdest_width=4 +CSET tid_width=8 +CSET tkeep_width=4 +CSET tstrb_width=4 +CSET tuser_width=4 +CSET underflow_flag=false +CSET underflow_flag_axi=false +CSET underflow_sense=Active_High +CSET underflow_sense_axi=Active_High +CSET use_clock_enable=false +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=true +CSET valid_flag=false +CSET valid_sense=Active_High +CSET wach_type=FIFO +CSET wdch_type=FIFO +CSET wrch_type=FIFO +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=true +CSET write_data_count_width=6 +CSET wuser_width=1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-11-19T12:39:56Z +# END Extra information +GENERATE +# CRC: 8cc2c19d diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_readme.txt b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_readme.txt new file mode 100644 index 000000000..7853ebde8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_readme.txt @@ -0,0 +1,236 @@ +CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1 + + Release Date: December 18, 2012 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm + +................................................................................ + + +2. DEVICE SUPPORT + + + 2.1 ISE + + The following device families are supported by the core for this release. + + + All 7 Series devices + Zynq-7000 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Spartan-3 devices + All Virtex-4 devices + + + 2.2 Vivado + + All 7 Series devices + Zynq-7000 devices + +................................................................................ + + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - ISE 14.4 software support + + + 3.2 Vivado + + - 2012.4 software support + - IP level constraint for Built-in FIFO reset synchronizer + +................................................................................ + + +4. RESOLVED ISSUES + + + 4.1 ISE + + - N/A + + + 4.2 Vivado + + - N/A + + +................................................................................ + + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Importing an XCO file alters the XCO configurations + + Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) + into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, + page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should. + + CR 467240 + AR 31379 + + 2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed + + Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA, + correct behavior of the FIFO status flags cannot be guaranteed after the first write. + + Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK. + For more information and additional workaround see Answer Record 41099. + + 5.2 Vivado + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen + ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work. + + CR 665836 + +The most recent information, including known issues, workarounds, and +resolutions for this version is provided in the IP Release Notes User Guide +located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + +................................................................................ + + +6. TECHNICAL SUPPORT & FEEDBACK + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + +................................................................................ + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer +10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO +07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO +04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support + AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO +01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support +10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support +06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support +03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support +10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support +09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support +07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support +06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support +04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support +12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support +09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support +06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support +04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support +09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes +03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes +10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs +08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO +04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support +09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support +07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support +01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3 +08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2 +04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1 +11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0 +05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support +04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release +================================================================================ + +................................................................................ + + +8. LEGAL DISCLAIMER + +(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_vinfo.html b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_vinfo.html new file mode 100644 index 000000000..fefce62a3 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_vinfo.html @@ -0,0 +1,247 @@ + + +fifo_generator_v9_3_vinfo + + + +

+CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1
+
+                    Release Date: December 18, 2012
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------  
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+   www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1
+solution. For the latest core updates, see the product page at:
+ 
+   www.xilinx.com/products/ipcenter/FIFO_Generator.htm
+
+................................................................................
+
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+    The following device families are supported by the core for this release.
+    
+    
+    All 7 Series devices
+    Zynq-7000 devices
+    All Virtex-6 devices
+    All Spartan-6 devices
+    All Virtex-5 devices
+    All Spartan-3 devices
+    All Virtex-4 devices
+  
+  
+  2.2 Vivado 
+  
+    All 7 Series devices
+    Zynq-7000 devices
+
+................................................................................
+
+
+3. NEW FEATURE HISTORY
+
+
+  3.1 ISE 
+  
+    - ISE 14.4 software support
+
+  
+  3.2 Vivado
+  
+    - 2012.4 software support
+    - IP level constraint for Built-in FIFO reset synchronizer
+
+................................................................................
+
+
+4. RESOLVED ISSUES 
+
+
+  4.1 ISE 
+
+    - N/A
+
+
+  4.2 Vivado 
+
+    - N/A
+
+
+................................................................................
+
+
+5. KNOWN ISSUES & LIMITATIONS 
+
+
+  5.1 ISE 
+  
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+  
+    1. Importing an XCO file alters the XCO configurations
+  
+       Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
+       into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, 
+       page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
+    
+       CR 467240
+       AR 31379
+  
+    2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
+  
+       Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
+       correct behavior of the FIFO status flags cannot be guaranteed after the first write.
+    
+       Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
+       For more information and additional workaround see Answer Record 41099.
+  
+  5.2 Vivado 
+
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+     
+    1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen 
+       ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
+      
+       CR 665836
+
+The most recent information, including known issues, workarounds, and
+resolutions for this version is provided in the IP Release Notes User Guide
+located at 
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf 
+
+................................................................................
+
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.  
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+................................................................................
+
+
+7. CORE RELEASE HISTORY 
+
+Date        By            Version      Description
+================================================================================
+12/18/2012  Xilinx, Inc.  9.3 Rev 1    ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer
+10/16/2012  Xilinx, Inc.  9.3          ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
+07/25/2012  Xilinx, Inc.  9.2          ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
+04/24/2012  Xilinx, Inc.  9.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
+                                       AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
+01/18/2012  Xilinx, Inc.  8.4          ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
+10/19/2011  Xilinx, Inc.  8.3          ISE 13.3 support and QVirtex-6L device support
+06/22/2011  Xilinx, Inc.  8.2          ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
+03/01/2011  Xilinx, Inc.  8.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
+10/29/2010  Xilinx, Inc.  7.3          ISE 13.0.2 support
+09/21/2010  Xilinx, Inc.  7.2          ISE 12.3 support; AXI4 Support
+07/30/2010  Xilinx, Inc.  7.1          ISE 13.0.1 support
+06/18/2010  Xilinx, Inc.  6.2          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  6.1          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  5.3 rev 1    ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
+09/16/2009  Xilinx, Inc.  5.3          Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
+06/24/2009  Xilinx, Inc.  5.2          Update to add 11.2 and Virtex-6 CXT device support
+04/24/2009  Xilinx, Inc.  5.1          Update to add 11.1 and Virtex-6 and Spartan-6 device support
+09/19/2008  Xilinx, Inc.  4.4          Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
+03/24/2008  Xilinx, Inc.  4.3          Update to add 10.1 support and miscellaneous bug fixes
+10/03/2007  Xilinx, Inc.  4.2          Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
+08/08/2007  Xilinx, Inc.  4.1          Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
+04/02/2007  Xilinx, Inc.  3.3          Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
+09/21/2006  Xilinx, Inc.  3.2          Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
+07/13/2006  Xilinx, Inc.  3.1          Update to add 8.2i support; Revised to v3.1; Virtex-5 support
+01/11/2006  Xilinx, Inc.  2.3          Update to add 8.1i support; Revised to v2.3
+08/31/2005  Xilinx, Inc.  2.2          Update to add 7.1i SP4 support; Revised to v2.2
+04/28/2005  Xilinx, Inc.  2.1          Update to add 7.1i SP1 support; Revised to v2.1
+11/04/2004  Xilinx, Inc.  2.0          Update to add 6.3i support; Revised to v2.0
+05/21/2004  Xilinx, Inc.  1.1          Revised to v1.1; Virtex-4 support
+04/23/2004  Xilinx, Inc.  1.0          Update to add 6.2i support; First release
+================================================================================
+
+................................................................................
+
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
+
+  This file contains confidential and proprietary information
+  of Xilinx, Inc. and is protected under U.S. and
+  international copyright and other intellectual property
+  laws.
+
+  DISCLAIMER
+  This disclaimer is not a license and does not grant any
+  rights to the materials distributed herewith. Except as
+  otherwise provided in a valid license issued to you by
+  Xilinx, and to the maximum extent permitted by applicable
+  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+  (2) Xilinx shall not be liable (whether in contract or tort,
+  including negligence, or under any other theory of
+  liability) for any loss or damage of any kind or nature
+  related to, arising under or in connection with these
+  materials, including for any direct, or any indirect,
+  special, incidental, or consequential loss or damage
+  (including loss of data, profits, goodwill, or any type of
+  loss or damage suffered as a result of any action brought
+  by a third party) even if such damage or loss was
+  reasonably foreseeable or Xilinx had been advised of the
+  possibility of the same. 
+
+  CRITICAL APPLICATIONS
+  Xilinx products are not designed or intended to be fail-
+  safe, or for use in any application requiring fail-safe
+  performance, such as life-support or safety devices or
+  systems, Class III medical devices, nuclear facilities,
+  applications related to the deployment of airbags, or any
+  other applications that could lead to death, personal
+  injury, or severe property or environmental damage
+  (individually and collectively, "Critical 
+  Applications"). Customer assumes the sole risk and 
+  liability of any use of Xilinx products in Critical 
+  Applications, subject only to applicable laws and 
+  regulations governing limitations on product liability. 
+ 
+  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+  PART OF THIS FILE AT ALL TIMES.
+
+
+ + diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/pg057-fifo-generator.pdf b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/pg057-fifo-generator.pdf new file mode 100644 index 000000000..5ec45fbcb Binary files /dev/null and b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/pg057-fifo-generator.pdf differ diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf new file mode 100755 index 000000000..62e5058ab --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf @@ -0,0 +1,56 @@ +################################################################################ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. + NET "RD_CLK" TNM_NET = "RD_CLK"; + NET "WR_CLK" TNM_NET = "WR_CLK"; + TIMESPEC "TS_RD_CLK" = PERIOD "RD_CLK" 50 MHZ; + TIMESPEC "TS_WR_CLK" = PERIOD "WR_CLK" 50 MHZ; +################################################################################ diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd new file mode 100755 index 000000000..9e38bcb7c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd @@ -0,0 +1,145 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core - core top file for implementation +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_exdes.vhd +-- +-- Description: +-- This is the FIFO core wrapper with BUFG instances for clock connections. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library unisim; +use unisim.vcomponents.all; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +entity fifo_short_2clk_exdes is + PORT ( + WR_CLK : IN std_logic; + RD_CLK : IN std_logic; + WR_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); + RD_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); + RST : IN std_logic; + WR_EN : IN std_logic; + RD_EN : IN std_logic; + DIN : IN std_logic_vector(72-1 DOWNTO 0); + DOUT : OUT std_logic_vector(72-1 DOWNTO 0); + FULL : OUT std_logic; + EMPTY : OUT std_logic); + +end fifo_short_2clk_exdes; + + + +architecture xilinx of fifo_short_2clk_exdes is + + signal wr_clk_i : std_logic; + signal rd_clk_i : std_logic; + + + + component fifo_short_2clk is + PORT ( + WR_CLK : IN std_logic; + RD_CLK : IN std_logic; + WR_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); + RD_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); + RST : IN std_logic; + WR_EN : IN std_logic; + RD_EN : IN std_logic; + DIN : IN std_logic_vector(72-1 DOWNTO 0); + DOUT : OUT std_logic_vector(72-1 DOWNTO 0); + FULL : OUT std_logic; + EMPTY : OUT std_logic); + + end component; + + +begin + + wr_clk_buf: bufg + PORT map( + i => WR_CLK, + o => wr_clk_i + ); + + rd_clk_buf: bufg + PORT map( + i => RD_CLK, + o => rd_clk_i + ); + + + exdes_inst : fifo_short_2clk + PORT MAP ( + WR_CLK => wr_clk_i, + RD_CLK => rd_clk_i, + WR_DATA_COUNT => wr_data_count, + RD_DATA_COUNT => rd_data_count, + RST => rst, + WR_EN => wr_en, + RD_EN => rd_en, + DIN => din, + DOUT => dout, + FULL => full, + EMPTY => empty); + +end xilinx; diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/fifo_generator_v9_3_readme.txt b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/fifo_generator_v9_3_readme.txt new file mode 100644 index 000000000..7853ebde8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/fifo_generator_v9_3_readme.txt @@ -0,0 +1,236 @@ +CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1 + + Release Date: December 18, 2012 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm + +................................................................................ + + +2. DEVICE SUPPORT + + + 2.1 ISE + + The following device families are supported by the core for this release. + + + All 7 Series devices + Zynq-7000 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Spartan-3 devices + All Virtex-4 devices + + + 2.2 Vivado + + All 7 Series devices + Zynq-7000 devices + +................................................................................ + + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - ISE 14.4 software support + + + 3.2 Vivado + + - 2012.4 software support + - IP level constraint for Built-in FIFO reset synchronizer + +................................................................................ + + +4. RESOLVED ISSUES + + + 4.1 ISE + + - N/A + + + 4.2 Vivado + + - N/A + + +................................................................................ + + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Importing an XCO file alters the XCO configurations + + Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) + into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, + page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should. + + CR 467240 + AR 31379 + + 2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed + + Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA, + correct behavior of the FIFO status flags cannot be guaranteed after the first write. + + Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK. + For more information and additional workaround see Answer Record 41099. + + 5.2 Vivado + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen + ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work. + + CR 665836 + +The most recent information, including known issues, workarounds, and +resolutions for this version is provided in the IP Release Notes User Guide +located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + +................................................................................ + + +6. TECHNICAL SUPPORT & FEEDBACK + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + +................................................................................ + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer +10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO +07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO +04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support + AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO +01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support +10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support +06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support +03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support +10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support +09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support +07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support +06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support +04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support +12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support +09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support +06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support +04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support +09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes +03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes +10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs +08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO +04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support +09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support +07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support +01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3 +08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2 +04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1 +11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0 +05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support +04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release +================================================================================ + +................................................................................ + + +8. LEGAL DISCLAIMER + +(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement.bat new file mode 100755 index 000000000..f846d4485 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement.bat @@ -0,0 +1,88 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +copy fifo_short_2clk_exdes.ngc .\results\ + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\fifo_short_2clk.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\fifo_short_2clk_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-fgg484-3 -sd ../../../ fifo_short_2clk_exdes + +echo 'Running map' +map fifo_short_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_short_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement.sh new file mode 100755 index 000000000..e2453c4a1 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement.sh @@ -0,0 +1,87 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +cp fifo_short_2clk_exdes.ngc ./results/ + + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../fifo_short_2clk.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/fifo_short_2clk_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-fgg484-3 -sd ../../../ fifo_short_2clk_exdes + +echo 'Running map' +map fifo_short_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_short_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v + diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement_synplify.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement_synplify.bat new file mode 100755 index 000000000..4fe498bff --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement_synplify.bat @@ -0,0 +1,87 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with Synplify' +synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\fifo_short_2clk.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\fifo_short_2clk_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-fgg484-3 -sd ../../../ fifo_short_2clk_exdes + +echo 'Running map' +map fifo_short_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_short_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement_synplify.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement_synplify.sh new file mode 100755 index 000000000..882036474 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement_synplify.sh @@ -0,0 +1,86 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with Synplify' +synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx + + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../fifo_short_2clk.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/fifo_short_2clk_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-fgg484-3 -sd ../../../ fifo_short_2clk_exdes + +echo 'Running map' +map fifo_short_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_short_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v + diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.bat new file mode 100755 index 000000000..49053fd63 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.bat @@ -0,0 +1,54 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +rem ----------------------------------------------------------------------------- +rem Script to synthesize and implement the Coregen FIFO Generator +rem ----------------------------------------------------------------------------- +rmdir /S /Q results +mkdir results +cd results +copy ..\..\..\fifo_short_2clk.ngc . +planAhead -mode batch -source ..\planAhead_ise.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.sh new file mode 100755 index 000000000..42916c2bc --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.sh @@ -0,0 +1,55 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the Coregen FIFO Generator +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +cp ../../../fifo_short_2clk.ngc . +planAhead -mode batch -source ../planAhead_ise.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.tcl b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.tcl new file mode 100755 index 000000000..9f39b3e13 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.tcl @@ -0,0 +1,67 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + +set device xc6slx75fgg484-3 +set projName fifo_short_2clk +set design fifo_short_2clk +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module fifo_short_2clk_exdes +add_files -norecurse {../../example_design/fifo_short_2clk_exdes.vhd} +add_files -norecurse {./fifo_short_2clk.ngc} +import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/fifo_short_2clk_exdes.xdc} +set_property top fifo_short_2clk_exdes [get_property srcset [current_run]] +synth_design +opt_design +place_design +route_design +write_sdf -rename_top_module fifo_short_2clk_exdes -file routed.sdf +write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module fifo_short_2clk_exdes routed.v +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file report.drc +write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/xst.prj b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/xst.prj new file mode 100755 index 000000000..f16af4308 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/xst.prj @@ -0,0 +1 @@ +work ../example_design/fifo_short_2clk_exdes.vhd diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/xst.scr b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/xst.scr new file mode 100755 index 000000000..b5a9091c7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/xst.scr @@ -0,0 +1,13 @@ +run +-ifmt VHDL +-ent fifo_short_2clk_exdes +-p xc6slx75-fgg484-3 +-ifn xst.prj +-write_timing_constraints No +-iobuf YES +-max_fanout 100 +-ofn fifo_short_2clk_exdes +-ofmt NGC +-bus_delimiter () +-hierarchy_separator / +-case Maintain diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd new file mode 100755 index 000000000..bc7a1b525 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd @@ -0,0 +1,123 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_dgen.vhd +-- +-- Description: +-- Used for write interface stimulus generation +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +LIBRARY work; +USE work.fifo_short_2clk_pkg.ALL; + +ENTITY fifo_short_2clk_dgen IS + GENERIC ( + C_DIN_WIDTH : INTEGER := 32; + C_DOUT_WIDTH : INTEGER := 32; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT ( + RESET : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + PRC_WR_EN : IN STD_LOGIC; + FULL : IN STD_LOGIC; + WR_EN : OUT STD_LOGIC; + WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE fg_dg_arch OF fifo_short_2clk_dgen IS + + CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); + CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8); + + SIGNAL pr_w_en : STD_LOGIC := '0'; + SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0); + SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); + BEGIN + + WR_EN <= PRC_WR_EN ; + WR_DATA <= wr_data_i AFTER 100 ns; + + ---------------------------------------------- + -- Generation of DATA + ---------------------------------------------- + gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE + rd_gen_inst1:fifo_short_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED+N + ) + PORT MAP( + CLK => WR_CLK, + RESET => RESET, + RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N), + ENABLE => pr_w_en + ); + END GENERATE; + + pr_w_en <= PRC_WR_EN AND NOT FULL; + wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0); + + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dverif.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dverif.vhd new file mode 100755 index 000000000..b0465d84f --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dverif.vhd @@ -0,0 +1,150 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_dverif.vhd +-- +-- Description: +-- Used for FIFO read interface stimulus generation and data checking +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +LIBRARY work; +USE work.fifo_short_2clk_pkg.ALL; + +ENTITY fifo_short_2clk_dverif IS + GENERIC( + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_USE_EMBEDDED_REG : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + PRC_RD_EN : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + RD_EN : OUT STD_LOGIC; + DOUT_CHK : OUT STD_LOGIC + ); +END ENTITY; + + +ARCHITECTURE fg_dv_arch OF fifo_short_2clk_dverif IS + + CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); + CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0); + CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8); + + SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_chk : STD_LOGIC := '1'; + SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0); + SIGNAL rd_en_i : STD_LOGIC := '0'; + SIGNAL pr_r_en : STD_LOGIC := '0'; + SIGNAL rd_en_d1 : STD_LOGIC := '1'; +BEGIN + + + DOUT_CHK <= data_chk; + RD_EN <= rd_en_i; + rd_en_i <= PRC_RD_EN; + rd_en_d1 <= '1'; + + + data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE + ------------------------------------------------------- + -- Expected data generation and checking for data_fifo + ------------------------------------------------------- + + pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1; + expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0); + + gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE + rd_gen_inst2:fifo_short_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED+N + ) + PORT MAP( + CLK => RD_CLK, + RESET => RESET, + RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N), + ENABLE => pr_r_en + ); + END GENERATE; + + PROCESS (RD_CLK,RESET) + BEGIN + IF(RESET = '1') THEN + data_chk <= '0'; + ELSIF (RD_CLK'event AND RD_CLK='1') THEN + IF(EMPTY = '0') THEN + IF(DATA_OUT = expected_dout) THEN + data_chk <= '0'; + ELSE + data_chk <= '1'; + END IF; + END IF; + END IF; + END PROCESS; + END GENERATE data_fifo_chk; + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pctrl.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pctrl.vhd new file mode 100755 index 000000000..5d6506398 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pctrl.vhd @@ -0,0 +1,541 @@ + +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_pctrl.vhd +-- +-- Description: +-- Used for protocol control on write and read interface stimulus and status generation +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +LIBRARY work; +USE work.fifo_short_2clk_pkg.ALL; + +ENTITY fifo_short_2clk_pctrl IS + GENERIC( + AXI_CHANNEL : STRING :="NONE"; + C_APPLICATION_TYPE : INTEGER := 0; + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_WR_PNTR_WIDTH : INTEGER := 0; + C_RD_PNTR_WIDTH : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 2; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET_WR : IN STD_LOGIC; + RESET_RD : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + FULL : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + ALMOST_FULL : IN STD_LOGIC; + ALMOST_EMPTY : IN STD_LOGIC; + DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + DOUT_CHK : IN STD_LOGIC; + PRC_WR_EN : OUT STD_LOGIC; + PRC_RD_EN : OUT STD_LOGIC; + RESET_EN : OUT STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE fg_pc_arch OF fifo_short_2clk_pctrl IS + + CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); + CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8); + CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH); + + SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); + SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); + SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); + SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0'); + SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0'); + SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0'); + SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0'); + SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0'); + SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); + SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); + SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0'); + SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); + SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0'); + SIGNAL wr_en_i : STD_LOGIC := '0'; + SIGNAL rd_en_i : STD_LOGIC := '0'; + SIGNAL state : STD_LOGIC := '0'; + SIGNAL wr_control : STD_LOGIC := '0'; + SIGNAL rd_control : STD_LOGIC := '0'; + SIGNAL stop_on_err : STD_LOGIC := '0'; + SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8); + SIGNAL sim_done_i : STD_LOGIC := '0'; + SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1'); + SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1'); + SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0'); + SIGNAL prc_we_i : STD_LOGIC := '0'; + SIGNAL prc_re_i : STD_LOGIC := '0'; + SIGNAL reset_en_i : STD_LOGIC := '0'; + SIGNAL sim_done_d1 : STD_LOGIC := '0'; + SIGNAL sim_done_wr1 : STD_LOGIC := '0'; + SIGNAL sim_done_wr2 : STD_LOGIC := '0'; + SIGNAL empty_d1 : STD_LOGIC := '0'; + SIGNAL empty_wr_dom1 : STD_LOGIC := '0'; + SIGNAL state_d1 : STD_LOGIC := '0'; + SIGNAL state_rd_dom1 : STD_LOGIC := '0'; + SIGNAL rd_en_d1 : STD_LOGIC := '0'; + SIGNAL rd_en_wr1 : STD_LOGIC := '0'; + SIGNAL wr_en_d1 : STD_LOGIC := '0'; + SIGNAL wr_en_rd1 : STD_LOGIC := '0'; + SIGNAL full_chk_d1 : STD_LOGIC := '0'; + SIGNAL full_chk_rd1 : STD_LOGIC := '0'; + SIGNAL empty_wr_dom2 : STD_LOGIC := '0'; + + SIGNAL state_rd_dom2 : STD_LOGIC := '0'; + SIGNAL state_rd_dom3 : STD_LOGIC := '0'; + SIGNAL rd_en_wr2 : STD_LOGIC := '0'; + SIGNAL wr_en_rd2 : STD_LOGIC := '0'; + SIGNAL full_chk_rd2 : STD_LOGIC := '0'; + SIGNAL reset_en_d1 : STD_LOGIC := '0'; + SIGNAL reset_en_rd1 : STD_LOGIC := '0'; + SIGNAL reset_en_rd2 : STD_LOGIC := '0'; + + SIGNAL data_chk_wr_d1 : STD_LOGIC := '0'; + SIGNAL data_chk_rd1 : STD_LOGIC := '0'; + SIGNAL data_chk_rd2 : STD_LOGIC := '0'; + SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); + SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); +BEGIN + status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0'; + STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high); + + prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0'; + prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0'; + + SIM_DONE <= sim_done_i; + rdw_gt_wrw <= (OTHERS => '1'); + wrw_gt_rdw <= (OTHERS => '1'); + + PROCESS(RD_CLK) + BEGIN + IF (RD_CLK'event AND RD_CLK='1') THEN + IF(prc_re_i = '1') THEN + rd_activ_cont <= rd_activ_cont + "1"; + END IF; + END IF; + END PROCESS; + + + PROCESS(sim_done_i) + BEGIN + assert sim_done_i = '0' + report "Simulation Complete for:" & AXI_CHANNEL + severity note; + END PROCESS; + +----------------------------------------------------- +-- SIM_DONE SIGNAL GENERATION +----------------------------------------------------- +PROCESS (RD_CLK,RESET_RD) +BEGIN + IF(RESET_RD = '1') THEN + --sim_done_i <= '0'; + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN + sim_done_i <= '1'; + END IF; + END IF; +END PROCESS; + + -- TB Timeout/Stop + fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE + PROCESS (RD_CLK) + BEGIN + IF (RD_CLK'event AND RD_CLK='1') THEN + IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN + sim_stop_cntr <= sim_stop_cntr - "1"; + END IF; + END IF; + END PROCESS; + END GENERATE fifo_tb_stop_run; + + + -- Stop when error found + PROCESS (RD_CLK) + BEGIN + IF (RD_CLK'event AND RD_CLK='1') THEN + IF(sim_done_i = '0') THEN + status_d1_i <= status_i OR status_d1_i; + END IF; + IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN + stop_on_err <= '1'; + END IF; + END IF; + END PROCESS; + ----------------------------------------------------- + + ----------------------------------------------------- + -- CHECKS FOR FIFO + ----------------------------------------------------- + + + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + post_rst_dly_rd <= (OTHERS => '1'); + ELSIF (RD_CLK'event AND RD_CLK='1') THEN + post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4); + END IF; + END PROCESS; + + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + post_rst_dly_wr <= (OTHERS => '1'); + ELSIF (WR_CLK'event AND WR_CLK='1') THEN + post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4); + END IF; + END PROCESS; + + + -- FULL de-assert Counter + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + full_ds_timeout <= (OTHERS => '0'); + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(state = '1') THEN + IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN + full_ds_timeout <= full_ds_timeout + '1'; + END IF; + ELSE + full_ds_timeout <= (OTHERS => '0'); + END IF; + END IF; + END PROCESS; + + + -- EMPTY deassert counter + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + empty_ds_timeout <= (OTHERS => '0'); + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(state = '0') THEN + IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN + empty_ds_timeout <= empty_ds_timeout + '1'; + END IF; + ELSE + empty_ds_timeout <= (OTHERS => '0'); + END IF; + END IF; + END PROCESS; + + -- Full check signal generation + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + full_chk_i <= '0'; + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN + full_chk_i <= '0'; + ELSE + full_chk_i <= AND_REDUCE(full_as_timeout) OR + AND_REDUCE(full_ds_timeout); + END IF; + END IF; + END PROCESS; + + -- Empty checks + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + empty_chk_i <= '0'; + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN + empty_chk_i <= '0'; + ELSE + empty_chk_i <= AND_REDUCE(empty_as_timeout) OR + AND_REDUCE(empty_ds_timeout); + END IF; + END IF; + END PROCESS; + + fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE + PRC_WR_EN <= prc_we_i AFTER 100 ns; + PRC_RD_EN <= prc_re_i AFTER 50 ns; + data_chk_i <= dout_chk; + END GENERATE fifo_d_chk; + ----------------------------------------------------- + + + ----------------------------------------------------- + -- SYNCHRONIZERS B/W WRITE AND READ DOMAINS + ----------------------------------------------------- + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + empty_wr_dom1 <= '1'; + empty_wr_dom2 <= '1'; + state_d1 <= '0'; + wr_en_d1 <= '0'; + rd_en_wr1 <= '0'; + rd_en_wr2 <= '0'; + full_chk_d1 <= '0'; + reset_en_d1 <= '0'; + sim_done_wr1 <= '0'; + sim_done_wr2 <= '0'; + ELSIF (WR_CLK'event AND WR_CLK='1') THEN + sim_done_wr1 <= sim_done_d1; + sim_done_wr2 <= sim_done_wr1; + reset_en_d1 <= reset_en_i; + state_d1 <= state; + empty_wr_dom1 <= empty_d1; + empty_wr_dom2 <= empty_wr_dom1; + wr_en_d1 <= wr_en_i; + rd_en_wr1 <= rd_en_d1; + rd_en_wr2 <= rd_en_wr1; + full_chk_d1 <= full_chk_i; + END IF; + END PROCESS; + + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + empty_d1 <= '1'; + state_rd_dom1 <= '0'; + state_rd_dom2 <= '0'; + state_rd_dom3 <= '0'; + wr_en_rd1 <= '0'; + wr_en_rd2 <= '0'; + rd_en_d1 <= '0'; + full_chk_rd1 <= '0'; + full_chk_rd2 <= '0'; + reset_en_rd1 <= '0'; + reset_en_rd2 <= '0'; + sim_done_d1 <= '0'; + ELSIF (RD_CLK'event AND RD_CLK='1') THEN + sim_done_d1 <= sim_done_i; + reset_en_rd1 <= reset_en_d1; + reset_en_rd2 <= reset_en_rd1; + empty_d1 <= EMPTY; + rd_en_d1 <= rd_en_i; + state_rd_dom1 <= state_d1; + state_rd_dom2 <= state_rd_dom1; + state_rd_dom3 <= state_rd_dom2; + wr_en_rd1 <= wr_en_d1; + wr_en_rd2 <= wr_en_rd1; + full_chk_rd1 <= full_chk_d1; + full_chk_rd2 <= full_chk_rd1; + END IF; + END PROCESS; + + RESET_EN <= reset_en_rd2; + + + data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE + ----------------------------------------------------- + -- WR_EN GENERATION + ----------------------------------------------------- + gen_rand_wr_en:fifo_short_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED+1 + ) + PORT MAP( + CLK => WR_CLK, + RESET => RESET_WR, + RANDOM_NUM => wr_en_gen, + ENABLE => '1' + ); + + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + wr_en_i <= '0'; + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(state = '1') THEN + wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control; + ELSE + wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4)); + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------- + -- WR_EN CONTROL + ----------------------------------------------------- + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + wr_cntr <= (OTHERS => '0'); + wr_control <= '1'; + full_as_timeout <= (OTHERS => '0'); + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(state = '1') THEN + IF(wr_en_i = '1') THEN + wr_cntr <= wr_cntr + "1"; + END IF; + full_as_timeout <= (OTHERS => '0'); + ELSE + wr_cntr <= (OTHERS => '0'); + IF(rd_en_wr2 = '0') THEN + IF(wr_en_i = '1') THEN + full_as_timeout <= full_as_timeout + "1"; + END IF; + ELSE + full_as_timeout <= (OTHERS => '0'); + END IF; + END IF; + + wr_control <= NOT wr_cntr(wr_cntr'high); + + END IF; + END PROCESS; + + ----------------------------------------------------- + -- RD_EN GENERATION + ----------------------------------------------------- + gen_rand_rd_en:fifo_short_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED + ) + PORT MAP( + CLK => RD_CLK, + RESET => RESET_RD, + RANDOM_NUM => rd_en_gen, + ENABLE => '1' + ); + + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + rd_en_i <= '0'; + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(state_rd_dom2 = '0') THEN + rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4)); + ELSE + rd_en_i <= rd_en_gen(0) OR rd_en_gen(6); + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------- + -- RD_EN CONTROL + ----------------------------------------------------- + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + rd_cntr <= (OTHERS => '0'); + rd_control <= '1'; + empty_as_timeout <= (OTHERS => '0'); + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(state_rd_dom2 = '0') THEN + IF(rd_en_i = '1') THEN + rd_cntr <= rd_cntr + "1"; + END IF; + empty_as_timeout <= (OTHERS => '0'); + ELSE + rd_cntr <= (OTHERS => '0'); + IF(wr_en_rd2 = '0') THEN + IF(rd_en_i = '1') THEN + empty_as_timeout <= empty_as_timeout + "1"; + END IF; + ELSE + empty_as_timeout <= (OTHERS => '0'); + END IF; + END IF; + + rd_control <= NOT rd_cntr(rd_cntr'high); + + END IF; + END PROCESS; + + ----------------------------------------------------- + -- STIMULUS CONTROL + ----------------------------------------------------- + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + state <= '0'; + reset_en_i <= '0'; + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + CASE state IS + WHEN '0' => + IF(FULL = '1' AND empty_wr_dom2 = '0') THEN + state <= '1'; + reset_en_i <= '0'; + END IF; + WHEN '1' => + IF(empty_wr_dom2 = '1' AND FULL = '0') THEN + state <= '0'; + reset_en_i <= '1'; + END IF; + WHEN OTHERS => state <= state; + END CASE; + END IF; + END PROCESS; + END GENERATE data_fifo_en; + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pkg.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pkg.vhd new file mode 100755 index 000000000..4c0e4035b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pkg.vhd @@ -0,0 +1,350 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_pkg.vhd +-- +-- Description: +-- This is the demo testbench package file for FIFO Generator core. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE ieee.std_logic_arith.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +PACKAGE fifo_short_2clk_pkg IS + + FUNCTION divroundup ( + data_value : INTEGER; + divisor : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : INTEGER; + false_case : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : STD_LOGIC; + false_case : STD_LOGIC) + RETURN STD_LOGIC; + ------------------------ + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : TIME; + false_case : TIME) + RETURN TIME; + ------------------------ + FUNCTION log2roundup ( + data_value : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION hexstr_to_std_logic_vec( + arg1 : string; + size : integer ) + RETURN std_logic_vector; + ------------------------ + COMPONENT fifo_short_2clk_rng IS + GENERIC (WIDTH : integer := 8; + SEED : integer := 3); + PORT ( + CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + ENABLE : IN STD_LOGIC; + RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + + COMPONENT fifo_short_2clk_dgen IS + GENERIC ( + C_DIN_WIDTH : INTEGER := 32; + C_DOUT_WIDTH : INTEGER := 32; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT ( + RESET : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + PRC_WR_EN : IN STD_LOGIC; + FULL : IN STD_LOGIC; + WR_EN : OUT STD_LOGIC; + WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + + COMPONENT fifo_short_2clk_dverif IS + GENERIC( + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_USE_EMBEDDED_REG : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + PRC_RD_EN : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + RD_EN : OUT STD_LOGIC; + DOUT_CHK : OUT STD_LOGIC + ); + END COMPONENT; + ------------------------ + + COMPONENT fifo_short_2clk_pctrl IS + GENERIC( + AXI_CHANNEL : STRING := "NONE"; + C_APPLICATION_TYPE : INTEGER := 0; + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_WR_PNTR_WIDTH : INTEGER := 0; + C_RD_PNTR_WIDTH : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 2; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET_WR : IN STD_LOGIC; + RESET_RD : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + FULL : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + ALMOST_FULL : IN STD_LOGIC; + ALMOST_EMPTY : IN STD_LOGIC; + DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + DOUT_CHK : IN STD_LOGIC; + PRC_WR_EN : OUT STD_LOGIC; + PRC_RD_EN : OUT STD_LOGIC; + RESET_EN : OUT STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + COMPONENT fifo_short_2clk_synth IS + GENERIC( + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 0; + TB_SEED : INTEGER := 1 + ); + PORT( + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + COMPONENT fifo_short_2clk_exdes IS + PORT ( + WR_CLK : IN std_logic; + RD_CLK : IN std_logic; + WR_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); + RD_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); + RST : IN std_logic; + WR_EN : IN std_logic; + RD_EN : IN std_logic; + DIN : IN std_logic_vector(72-1 DOWNTO 0); + DOUT : OUT std_logic_vector(72-1 DOWNTO 0); + FULL : OUT std_logic; + EMPTY : OUT std_logic); + + END COMPONENT; + ------------------------ + + +END fifo_short_2clk_pkg; + + + +PACKAGE BODY fifo_short_2clk_pkg IS + + FUNCTION divroundup ( + data_value : INTEGER; + divisor : INTEGER) + RETURN INTEGER IS + VARIABLE div : INTEGER; + BEGIN + div := data_value/divisor; + IF ( (data_value MOD divisor) /= 0) THEN + div := div+1; + END IF; + RETURN div; + END divroundup; + --------------------------------- + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : INTEGER; + false_case : INTEGER) + RETURN INTEGER IS + VARIABLE retval : INTEGER := 0; + BEGIN + IF condition=false THEN + retval:=false_case; + ELSE + retval:=true_case; + END IF; + RETURN retval; + END if_then_else; + --------------------------------- + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : STD_LOGIC; + false_case : STD_LOGIC) + RETURN STD_LOGIC IS + VARIABLE retval : STD_LOGIC := '0'; + BEGIN + IF condition=false THEN + retval:=false_case; + ELSE + retval:=true_case; + END IF; + RETURN retval; + END if_then_else; + --------------------------------- + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : TIME; + false_case : TIME) + RETURN TIME IS + VARIABLE retval : TIME := 0 ps; + BEGIN + IF condition=false THEN + retval:=false_case; + ELSE + retval:=true_case; + END IF; + RETURN retval; + END if_then_else; + ------------------------------- + FUNCTION log2roundup ( + data_value : INTEGER) + RETURN INTEGER IS + + VARIABLE width : INTEGER := 0; + VARIABLE cnt : INTEGER := 1; + BEGIN + IF (data_value <= 1) THEN + width := 1; + ELSE + WHILE (cnt < data_value) LOOP + width := width + 1; + cnt := cnt *2; + END LOOP; + END IF; + + RETURN width; + END log2roundup; + ------------------------------------------------------------------------------ + -- hexstr_to_std_logic_vec + -- This function converts a hex string to a std_logic_vector + ------------------------------------------------------------------------------ + FUNCTION hexstr_to_std_logic_vec( + arg1 : string; + size : integer ) + RETURN std_logic_vector IS + VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE bin : std_logic_vector(3 DOWNTO 0); + VARIABLE index : integer := 0; + BEGIN + FOR i IN arg1'reverse_range LOOP + CASE arg1(i) IS + WHEN '0' => bin := (OTHERS => '0'); + WHEN '1' => bin := (0 => '1', OTHERS => '0'); + WHEN '2' => bin := (1 => '1', OTHERS => '0'); + WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0'); + WHEN '4' => bin := (2 => '1', OTHERS => '0'); + WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0'); + WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0'); + WHEN '7' => bin := (3 => '0', OTHERS => '1'); + WHEN '8' => bin := (3 => '1', OTHERS => '0'); + WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0'); + WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1'); + WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1'); + WHEN 'B' => bin := (2 => '0', OTHERS => '1'); + WHEN 'b' => bin := (2 => '0', OTHERS => '1'); + WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1'); + WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1'); + WHEN 'D' => bin := (1 => '0', OTHERS => '1'); + WHEN 'd' => bin := (1 => '0', OTHERS => '1'); + WHEN 'E' => bin := (0 => '0', OTHERS => '1'); + WHEN 'e' => bin := (0 => '0', OTHERS => '1'); + WHEN 'F' => bin := (OTHERS => '1'); + WHEN 'f' => bin := (OTHERS => '1'); + WHEN OTHERS => + FOR j IN 0 TO 3 LOOP + bin(j) := 'X'; + END LOOP; + END CASE; + FOR j IN 0 TO 3 LOOP + IF (index*4)+j < size THEN + result((index*4)+j) := bin(j); + END IF; + END LOOP; + index := index + 1; + END LOOP; + RETURN result; + END hexstr_to_std_logic_vec; + +END fifo_short_2clk_pkg; diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_rng.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_rng.vhd new file mode 100755 index 000000000..80c201c3b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_rng.vhd @@ -0,0 +1,100 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_rng.vhd +-- +-- Description: +-- Used for generation of pseudo random numbers +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +ENTITY fifo_short_2clk_rng IS + GENERIC ( + WIDTH : integer := 8; + SEED : integer := 3); + PORT ( + CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + ENABLE : IN STD_LOGIC; + RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)); +END ENTITY; + +ARCHITECTURE rg_arch OF fifo_short_2clk_rng IS +BEGIN +PROCESS (CLK,RESET) + VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width); + VARIABLE temp : STD_LOGIC := '0'; +BEGIN + IF(RESET = '1') THEN + rand_temp := conv_std_logic_vector(SEED,width); + temp := '0'; + ELSIF (CLK'event AND CLK = '1') THEN + IF (ENABLE = '1') THEN + temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5); + rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0); + rand_temp(0) := temp; + END IF; + END IF; + + RANDOM_NUM <= rand_temp; + +END PROCESS; + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_synth.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_synth.vhd new file mode 100755 index 000000000..e9139fc96 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_synth.vhd @@ -0,0 +1,300 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_synth.vhd +-- +-- Description: +-- This is the demo testbench for fifo_generator core. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + + +LIBRARY ieee; +USE ieee.STD_LOGIC_1164.ALL; +USE ieee.STD_LOGIC_unsigned.ALL; +USE IEEE.STD_LOGIC_arith.ALL; +USE ieee.numeric_std.ALL; +USE ieee.STD_LOGIC_misc.ALL; + +LIBRARY std; +USE std.textio.ALL; + +LIBRARY work; +USE work.fifo_short_2clk_pkg.ALL; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +ENTITY fifo_short_2clk_synth IS + GENERIC( + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 0; + TB_SEED : INTEGER := 1 + ); + PORT( + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END ENTITY; + +ARCHITECTURE simulation_arch OF fifo_short_2clk_synth IS + + -- FIFO interface signal declarations + SIGNAL wr_clk_i : STD_LOGIC; + SIGNAL rd_clk_i : STD_LOGIC; + SIGNAL wr_data_count : STD_LOGIC_VECTOR(6-1 DOWNTO 0); + SIGNAL rd_data_count : STD_LOGIC_VECTOR(6-1 DOWNTO 0); + SIGNAL rst : STD_LOGIC; + SIGNAL wr_en : STD_LOGIC; + SIGNAL rd_en : STD_LOGIC; + SIGNAL din : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL dout : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL full : STD_LOGIC; + SIGNAL empty : STD_LOGIC; + -- TB Signals + SIGNAL wr_data : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL dout_i : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL wr_en_i : STD_LOGIC := '0'; + SIGNAL rd_en_i : STD_LOGIC := '0'; + SIGNAL full_i : STD_LOGIC := '0'; + SIGNAL empty_i : STD_LOGIC := '0'; + SIGNAL almost_full_i : STD_LOGIC := '0'; + SIGNAL almost_empty_i : STD_LOGIC := '0'; + SIGNAL prc_we_i : STD_LOGIC := '0'; + SIGNAL prc_re_i : STD_LOGIC := '0'; + SIGNAL dout_chk_i : STD_LOGIC := '0'; + SIGNAL rst_int_rd : STD_LOGIC := '0'; + SIGNAL rst_int_wr : STD_LOGIC := '0'; + SIGNAL rst_s_wr1 : STD_LOGIC := '0'; + SIGNAL rst_s_wr2 : STD_LOGIC := '0'; + SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL rst_s_wr3 : STD_LOGIC := '0'; + SIGNAL rst_s_rd : STD_LOGIC := '0'; + SIGNAL reset_en : STD_LOGIC := '0'; + SIGNAL rst_async_wr1 : STD_LOGIC := '0'; + SIGNAL rst_async_wr2 : STD_LOGIC := '0'; + SIGNAL rst_async_wr3 : STD_LOGIC := '0'; + SIGNAL rst_async_rd1 : STD_LOGIC := '0'; + SIGNAL rst_async_rd2 : STD_LOGIC := '0'; + SIGNAL rst_async_rd3 : STD_LOGIC := '0'; + + + BEGIN + + ---- Reset generation logic ----- + rst_int_wr <= rst_async_wr3 OR rst_s_wr3; + rst_int_rd <= rst_async_rd3 OR rst_s_rd; + + --Testbench reset synchronization + PROCESS(rd_clk_i,RESET) + BEGIN + IF(RESET = '1') THEN + rst_async_rd1 <= '1'; + rst_async_rd2 <= '1'; + rst_async_rd3 <= '1'; + ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN + rst_async_rd1 <= RESET; + rst_async_rd2 <= rst_async_rd1; + rst_async_rd3 <= rst_async_rd2; + END IF; + END PROCESS; + + PROCESS(wr_clk_i,RESET) + BEGIN + IF(RESET = '1') THEN + rst_async_wr1 <= '1'; + rst_async_wr2 <= '1'; + rst_async_wr3 <= '1'; + ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN + rst_async_wr1 <= RESET; + rst_async_wr2 <= rst_async_wr1; + rst_async_wr3 <= rst_async_wr2; + END IF; + END PROCESS; + + --Soft reset for core and testbench + PROCESS(rd_clk_i) + BEGIN + IF(rd_clk_i'event AND rd_clk_i='1') THEN + rst_gen_rd <= rst_gen_rd + "1"; + IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN + rst_s_rd <= '1'; + assert false + report "Reset applied..Memory Collision checks are not valid" + severity note; + ELSE + IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN + rst_s_rd <= '0'; + END IF; + END IF; + END IF; + END PROCESS; + + PROCESS(wr_clk_i) + BEGIN + IF(wr_clk_i'event AND wr_clk_i='1') THEN + rst_s_wr1 <= rst_s_rd; + rst_s_wr2 <= rst_s_wr1; + rst_s_wr3 <= rst_s_wr2; + IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN + assert false + report "Reset removed..Memory Collision checks are valid" + severity note; + END IF; + END IF; + END PROCESS; + ------------------ + + ---- Clock buffers for testbench ---- + wr_clk_i <= WR_CLK; + rd_clk_i <= RD_CLK; + ------------------ + + rst <= RESET OR rst_s_rd AFTER 12 ns; + din <= wr_data; + dout_i <= dout; + wr_en <= wr_en_i; + rd_en <= rd_en_i; + full_i <= full; + empty_i <= empty; + + fg_dg_nv: fifo_short_2clk_dgen + GENERIC MAP ( + C_DIN_WIDTH => 72, + C_DOUT_WIDTH => 72, + TB_SEED => TB_SEED, + C_CH_TYPE => 0 + ) + PORT MAP ( -- Write Port + RESET => rst_int_wr, + WR_CLK => wr_clk_i, + PRC_WR_EN => prc_we_i, + FULL => full_i, + WR_EN => wr_en_i, + WR_DATA => wr_data + ); + + fg_dv_nv: fifo_short_2clk_dverif + GENERIC MAP ( + C_DOUT_WIDTH => 72, + C_DIN_WIDTH => 72, + C_USE_EMBEDDED_REG => 0, + TB_SEED => TB_SEED, + C_CH_TYPE => 0 + ) + PORT MAP( + RESET => rst_int_rd, + RD_CLK => rd_clk_i, + PRC_RD_EN => prc_re_i, + RD_EN => rd_en_i, + EMPTY => empty_i, + DATA_OUT => dout_i, + DOUT_CHK => dout_chk_i + ); + + fg_pc_nv: fifo_short_2clk_pctrl + GENERIC MAP ( + AXI_CHANNEL => "Native", + C_APPLICATION_TYPE => 0, + C_DOUT_WIDTH => 72, + C_DIN_WIDTH => 72, + C_WR_PNTR_WIDTH => 5, + C_RD_PNTR_WIDTH => 5, + C_CH_TYPE => 0, + FREEZEON_ERROR => FREEZEON_ERROR, + TB_SEED => TB_SEED, + TB_STOP_CNT => TB_STOP_CNT + ) + PORT MAP( + RESET_WR => rst_int_wr, + RESET_RD => rst_int_rd, + RESET_EN => reset_en, + WR_CLK => wr_clk_i, + RD_CLK => rd_clk_i, + PRC_WR_EN => prc_we_i, + PRC_RD_EN => prc_re_i, + FULL => full_i, + ALMOST_FULL => almost_full_i, + ALMOST_EMPTY => almost_empty_i, + DOUT_CHK => dout_chk_i, + EMPTY => empty_i, + DATA_IN => wr_data, + DATA_OUT => dout, + SIM_DONE => SIM_DONE, + STATUS => STATUS + ); + + + + + + fifo_short_2clk_inst : fifo_short_2clk_exdes + PORT MAP ( + WR_CLK => wr_clk_i, + RD_CLK => rd_clk_i, + WR_DATA_COUNT => wr_data_count, + RD_DATA_COUNT => rd_data_count, + RST => rst, + WR_EN => wr_en, + RD_EN => rd_en, + DIN => din, + DOUT => dout, + FULL => full, + EMPTY => empty); + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd new file mode 100755 index 000000000..6d86157db --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd @@ -0,0 +1,208 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_tb.vhd +-- +-- Description: +-- This is the demo testbench top file for fifo_generator core. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +LIBRARY std; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; +USE IEEE.std_logic_arith.ALL; +USE IEEE.std_logic_misc.ALL; +USE ieee.numeric_std.ALL; +USE ieee.std_logic_textio.ALL; +USE std.textio.ALL; + +LIBRARY work; +USE work.fifo_short_2clk_pkg.ALL; + +ENTITY fifo_short_2clk_tb IS +END ENTITY; + + +ARCHITECTURE fifo_short_2clk_arch OF fifo_short_2clk_tb IS + SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; + SIGNAL wr_clk : STD_LOGIC; + SIGNAL rd_clk : STD_LOGIC; + SIGNAL reset : STD_LOGIC; + SIGNAL sim_done : STD_LOGIC := '0'; + SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0'); + -- Write and Read clock periods + CONSTANT wr_clk_period_by_2 : TIME := 200 ns; + CONSTANT rd_clk_period_by_2 : TIME := 100 ns; + -- Procedures to display strings + PROCEDURE disp_str(CONSTANT str:IN STRING) IS + variable dp_l : line := null; + BEGIN + write(dp_l,str); + writeline(output,dp_l); + END PROCEDURE; + + PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS + variable dp_lx : line := null; + BEGIN + hwrite(dp_lx,hex); + writeline(output,dp_lx); + END PROCEDURE; + +BEGIN + + -- Generation of clock + + PROCESS BEGIN + WAIT FOR 400 ns; -- Wait for global reset + WHILE 1 = 1 LOOP + wr_clk <= '0'; + WAIT FOR wr_clk_period_by_2; + wr_clk <= '1'; + WAIT FOR wr_clk_period_by_2; + END LOOP; + END PROCESS; + + PROCESS BEGIN + WAIT FOR 200 ns;-- Wait for global reset + WHILE 1 = 1 LOOP + rd_clk <= '0'; + WAIT FOR rd_clk_period_by_2; + rd_clk <= '1'; + WAIT FOR rd_clk_period_by_2; + END LOOP; + END PROCESS; + + -- Generation of Reset + + PROCESS BEGIN + reset <= '1'; + WAIT FOR 4200 ns; + reset <= '0'; + WAIT; + END PROCESS; + + + -- Error message printing based on STATUS signal from fifo_short_2clk_synth + + PROCESS(status) + BEGIN + IF(status /= "0" AND status /= "1") THEN + disp_str("STATUS:"); + disp_hex(status); + END IF; + + IF(status(7) = '1') THEN + assert false + report "Data mismatch found" + severity error; + END IF; + + IF(status(1) = '1') THEN + END IF; + + IF(status(5) = '1') THEN + assert false + report "Empty flag Mismatch/timeout" + severity error; + END IF; + + IF(status(6) = '1') THEN + assert false + report "Full Flag Mismatch/timeout" + severity error; + END IF; + END PROCESS; + + + PROCESS + BEGIN + wait until sim_done = '1'; + IF(status /= "0" AND status /= "1") THEN + assert false + report "Simulation failed" + severity failure; + ELSE + assert false + report "Test Completed Successfully" + severity failure; + END IF; + END PROCESS; + + PROCESS + BEGIN + wait for 400 ms; + assert false + report "Test bench timed out" + severity failure; + END PROCESS; + + -- Instance of fifo_short_2clk_synth + + fifo_short_2clk_synth_inst:fifo_short_2clk_synth + GENERIC MAP( + FREEZEON_ERROR => 0, + TB_STOP_CNT => 2, + TB_SEED => 108 + ) + PORT MAP( + WR_CLK => wr_clk, + RD_CLK => rd_clk, + RESET => reset, + SIM_DONE => sim_done, + STATUS => status + ); + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_isim.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_isim.bat new file mode 100755 index 000000000..d40cb85cf --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_isim.bat @@ -0,0 +1,63 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ..\\..\\..\\fifo_short_2clk.v +vhpcomp -work work ..\\..\\example_design\\fifo_short_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vhpcomp -work work ..\\fifo_short_2clk_pkg.vhd +vhpcomp -work work ..\\fifo_short_2clk_rng.vhd +vhpcomp -work work ..\\fifo_short_2clk_dgen.vhd +vhpcomp -work work ..\\fifo_short_2clk_dverif.vhd +vhpcomp -work work ..\\fifo_short_2clk_pctrl.vhd +vhpcomp -work work ..\\fifo_short_2clk_synth.vhd +vhpcomp -work work ..\\fifo_short_2clk_tb.vhd + +vlogcomp -work work $XILINX\\verilog\\src\\glbl.v +fuse work.fifo_short_2clk_tb work.glbl -L xilinxcorelib_ver -L unisims_ver -o fifo_short_2clk_tb.exe + +.\\fifo_short_2clk_tb.exe -gui -tclbatch .\\wave_isim.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_isim.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_isim.sh new file mode 100755 index 000000000..78f9ce588 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_isim.sh @@ -0,0 +1,65 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ../../../fifo_short_2clk.v +vhpcomp -work work ../../example_design/fifo_short_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vhpcomp -work work ../fifo_short_2clk_pkg.vhd +vhpcomp -work work ../fifo_short_2clk_rng.vhd +vhpcomp -work work ../fifo_short_2clk_dgen.vhd +vhpcomp -work work ../fifo_short_2clk_dverif.vhd +vhpcomp -work work ../fifo_short_2clk_pctrl.vhd +vhpcomp -work work ../fifo_short_2clk_synth.vhd +vhpcomp -work work ../fifo_short_2clk_tb.vhd + +vlogcomp -work work $XILINX/verilog/src/glbl.v +fuse work.fifo_short_2clk_tb work.glbl -L xilinxcorelib_ver -L unisims_ver -o fifo_short_2clk_tb.exe + +./fifo_short_2clk_tb.exe -gui -tclbatch ./wave_isim.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.bat new file mode 100755 index 000000000..35375ce20 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.bat @@ -0,0 +1,47 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.do b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.do new file mode 100755 index 000000000..8deb52187 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.do @@ -0,0 +1,74 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vlib work +vmap work work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlog -work work ../../../fifo_short_2clk.v +vcom -work work ../../example_design/fifo_short_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vcom -work work ../fifo_short_2clk_pkg.vhd +vcom -work work ../fifo_short_2clk_rng.vhd +vcom -work work ../fifo_short_2clk_dgen.vhd +vcom -work work ../fifo_short_2clk_dverif.vhd +vcom -work work ../fifo_short_2clk_pctrl.vhd +vcom -work work ../fifo_short_2clk_synth.vhd +vcom -work work ../fifo_short_2clk_tb.vhd + +vlog -work work $env(XILINX)/verilog/src/glbl.v +vsim -t ps -voptargs="+acc" -L XilinxCoreLib_ver -L unisims_ver glbl work.fifo_short_2clk_tb + +add log -r /* +do wave_mti.do +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.sh new file mode 100755 index 000000000..edb1b0dd9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.sh @@ -0,0 +1,49 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_ncsim.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_ncsim.sh new file mode 100755 index 000000000..749f9db06 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_ncsim.sh @@ -0,0 +1,69 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +mkdir work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +ncvlog -work work ../../../fifo_short_2clk.v +ncvhdl -v93 -work work ../../example_design/fifo_short_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +ncvhdl -v93 -work work ../fifo_short_2clk_pkg.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_rng.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_dgen.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_dverif.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_pctrl.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_synth.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_tb.vhd + +echo "Elaborating Design" +ncvlog -work work $XILINX/verilog/src/glbl.v +ncelab -access +rwc glbl work.fifo_short_2clk_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" work.fifo_short_2clk_tb + diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_vcs.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_vcs.sh new file mode 100755 index 000000000..71a568e24 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_vcs.sh @@ -0,0 +1,69 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogan +v2k ../../../fifo_short_2clk.v +vhdlan ../../example_design/fifo_short_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vhdlan ../fifo_short_2clk_pkg.vhd +vhdlan ../fifo_short_2clk_rng.vhd +vhdlan ../fifo_short_2clk_dgen.vhd +vhdlan ../fifo_short_2clk_dverif.vhd +vhdlan ../fifo_short_2clk_pctrl.vhd +vhdlan ../fifo_short_2clk_synth.vhd +vhdlan ../fifo_short_2clk_tb.vhd + +echo "Elaborating Design" +vlogan +v2k $XILINX/verilog/src/glbl.v +vcs -time_res 1ps +vcs+lic+wait -debug fifo_short_2clk_tb glbl + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/ucli_commands.key b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/ucli_commands.key new file mode 100755 index 000000000..f90cccb67 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/ucli_commands.key @@ -0,0 +1,4 @@ +dump -file fifo_short_2clk.vpd -type VPD +dump -add fifo_short_2clk_tb +run +quit diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/vcs_session.tcl b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/vcs_session.tcl new file mode 100755 index 000000000..7f3170d74 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/vcs_session.tcl @@ -0,0 +1,77 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- +if { ![gui_is_db_opened -db {fifo_short_2clk.vpd}] } { + gui_open_db -design V1 -file fifo_short_2clk.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + + +gui_open_window Wave +gui_sg_create fifo_short_2clk_Group +gui_list_add_group -id Wave.1 {fifo_short_2clk_Group} + +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +gui_sg_addsignal -group fifo_short_2clk_Group WRITE -divider +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +gui_sg_addsignal -group fifo_short_2clk_Group READ -divider +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +gui_zoom -window Wave.1 -full diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_isim.tcl b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_isim.tcl new file mode 100755 index 000000000..156aad172 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_isim.tcl @@ -0,0 +1,68 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_isim.tcl +# +# Description: +# This is the ISIM wave form file. +# +#-------------------------------------------------------------------------------- +wcfg new +isim set radix hex +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +run all +quit + diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_mti.do b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_mti.do new file mode 100755 index 000000000..eafc64cf2 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_mti.do @@ -0,0 +1,88 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +# Filename: wave_mti.do +# +# Description: +# This is the modelsim wave form file. +# +#-------------------------------------------------------------------------------- + +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +add wave -noupdate -divider WRITE +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +add wave -noupdate -radix hexadecimal /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/DIN +add wave -noupdate -divider READ +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +add wave -noupdate -radix hexadecimal /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/DOUT + +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {2164886 ps} 0} +configure wave -namecolwidth 197 +configure wave -valuecolwidth 106 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps} diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_ncsim.sv b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_ncsim.sv new file mode 100755 index 000000000..655d5c65a --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_ncsim.sv @@ -0,0 +1,70 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_ncsim.sv +# +# Description: +# This is the IUS wave form file. +# +#-------------------------------------------------------------------------------- + +window new WaveWindow -name "Waves for FIFO Generator Example Design" +waveform using "Waves for FIFO Generator Example Design" + +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +waveform add -label WRITE +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +waveform add -label READ +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +console submit -using simulator -wait no "run" diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_isim.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_isim.bat new file mode 100755 index 000000000..536a7cfee --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_isim.bat @@ -0,0 +1,61 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ..\\..\\implement\\results\\routed.v + +echo "Compiling Test Bench Files" +vhpcomp -work work ..\\fifo_short_2clk_pkg.vhd +vhpcomp -work work ..\\fifo_short_2clk_rng.vhd +vhpcomp -work work ..\\fifo_short_2clk_dgen.vhd +vhpcomp -work work ..\\fifo_short_2clk_dverif.vhd +vhpcomp -work work ..\\fifo_short_2clk_pctrl.vhd +vhpcomp -work work ..\\fifo_short_2clk_synth.vhd +vhpcomp -work work ..\\fifo_short_2clk_tb.vhd + +fuse work.fifo_short_2clk_tb work.glbl -L simprims_ver -o fifo_short_2clk_tb.exe + +.\\fifo_short_2clk_tb.exe -sdfmax /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst=..\\..\\implement\\results\\routed.sdf -gui -tclbatch .\\wave_isim.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_isim.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_isim.sh new file mode 100755 index 000000000..2d9404294 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_isim.sh @@ -0,0 +1,63 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +vhpcomp -work work ../fifo_short_2clk_pkg.vhd +vhpcomp -work work ../fifo_short_2clk_rng.vhd +vhpcomp -work work ../fifo_short_2clk_dgen.vhd +vhpcomp -work work ../fifo_short_2clk_dverif.vhd +vhpcomp -work work ../fifo_short_2clk_pctrl.vhd +vhpcomp -work work ../fifo_short_2clk_synth.vhd +vhpcomp -work work ../fifo_short_2clk_tb.vhd + +fuse work.fifo_short_2clk_tb work.glbl -L simprims_ver -o fifo_short_2clk_tb.exe + +./fifo_short_2clk_tb.exe -sdfmax /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst=../../implement/results/routed.sdf -gui -tclbatch ./wave_isim.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.bat new file mode 100755 index 000000000..35375ce20 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.bat @@ -0,0 +1,47 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.do b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.do new file mode 100755 index 000000000..7ec785533 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.do @@ -0,0 +1,72 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vlib work +vmap work work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlog -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +vcom -work work ../fifo_short_2clk_pkg.vhd +vcom -work work ../fifo_short_2clk_rng.vhd +vcom -work work ../fifo_short_2clk_dgen.vhd +vcom -work work ../fifo_short_2clk_dverif.vhd +vcom -work work ../fifo_short_2clk_pctrl.vhd +vcom -work work ../fifo_short_2clk_synth.vhd +vcom -work work ../fifo_short_2clk_tb.vhd + +vsim -t ps -voptargs="+acc" +transport_int_delays -L simprims_ver glbl -sdfmax /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst=../../implement/results/routed.sdf work.fifo_short_2clk_tb + +add log -r /* +do wave_mti.do +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.sh new file mode 100755 index 000000000..edb1b0dd9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.sh @@ -0,0 +1,49 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_ncsim.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_ncsim.sh new file mode 100755 index 000000000..e9dc952cf --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_ncsim.sh @@ -0,0 +1,73 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +mkdir work +echo "Compiling Core Verilog UNISIM/Behavioral model" +ncvlog -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +ncvhdl -v93 -work work ../fifo_short_2clk_pkg.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_rng.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_dgen.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_dverif.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_pctrl.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_synth.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_tb.vhd + +echo "Compiling SDF file" +ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X + +echo "Generating SDF command file" +echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd +echo 'SCOPE = :fifo_short_2clk_synth_inst:fifo_short_2clk_inst,' >> sdf.cmd +echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd + +echo "Elaborating Design" +ncelab -access +rwc glbl -sdf_cmd_file sdf.cmd work.fifo_short_2clk_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" work.fifo_short_2clk_tb diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_vcs.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_vcs.sh new file mode 100755 index 000000000..bbd548a74 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_vcs.sh @@ -0,0 +1,67 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogan +v2k ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +vhdlan ../fifo_short_2clk_pkg.vhd +vhdlan ../fifo_short_2clk_rng.vhd +vhdlan ../fifo_short_2clk_dgen.vhd +vhdlan ../fifo_short_2clk_dverif.vhd +vhdlan ../fifo_short_2clk_pctrl.vhd +vhdlan ../fifo_short_2clk_synth.vhd +vhdlan ../fifo_short_2clk_tb.vhd + +echo "Elaborating Design" +vcs -time_res 1ps +neg_tchk -sdf max:/fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst:../../implement/results/routed.sdf +vcs+lic+wait -debug fifo_short_2clk_tb glbl + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/ucli_commands.key b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/ucli_commands.key new file mode 100755 index 000000000..f90cccb67 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/ucli_commands.key @@ -0,0 +1,4 @@ +dump -file fifo_short_2clk.vpd -type VPD +dump -add fifo_short_2clk_tb +run +quit diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/vcs_session.tcl b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/vcs_session.tcl new file mode 100755 index 000000000..e27baa9d8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/vcs_session.tcl @@ -0,0 +1,76 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- +if { ![gui_is_db_opened -db {fifo_short_2clk.vpd}] } { + gui_open_db -design V1 -file fifo_short_2clk.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + +gui_open_window Wave +gui_sg_create fifo_short_2clk_Group +gui_list_add_group -id Wave.1 {fifo_short_2clk_Group} + +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +gui_sg_addsignal -group fifo_short_2clk_Group WRITE -divider +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +gui_sg_addsignal -group fifo_short_2clk_Group READ -divider +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +gui_zoom -window Wave.1 -full diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_isim.tcl b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_isim.tcl new file mode 100755 index 000000000..156aad172 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_isim.tcl @@ -0,0 +1,68 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_isim.tcl +# +# Description: +# This is the ISIM wave form file. +# +#-------------------------------------------------------------------------------- +wcfg new +isim set radix hex +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +run all +quit + diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_mti.do b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_mti.do new file mode 100755 index 000000000..eafc64cf2 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_mti.do @@ -0,0 +1,88 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +# Filename: wave_mti.do +# +# Description: +# This is the modelsim wave form file. +# +#-------------------------------------------------------------------------------- + +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +add wave -noupdate -divider WRITE +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +add wave -noupdate -radix hexadecimal /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/DIN +add wave -noupdate -divider READ +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +add wave -noupdate -radix hexadecimal /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/DOUT + +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {2164886 ps} 0} +configure wave -namecolwidth 197 +configure wave -valuecolwidth 106 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps} diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_ncsim.sv b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_ncsim.sv new file mode 100755 index 000000000..655d5c65a --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_ncsim.sv @@ -0,0 +1,70 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_ncsim.sv +# +# Description: +# This is the IUS wave form file. +# +#-------------------------------------------------------------------------------- + +window new WaveWindow -name "Waves for FIFO Generator Example Design" +waveform using "Waves for FIFO Generator Example Design" + +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +waveform add -label WRITE +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +waveform add -label READ +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +console submit -using simulator -wait no "run" diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk_flist.txt b/fpga/usrp3/top/b200/coregen/fifo_short_2clk_flist.txt new file mode 100644 index 000000000..4ab119a52 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk_flist.txt @@ -0,0 +1,57 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +fifo_short_2clk/doc/fifo_generator_v9_3_readme.txt +fifo_short_2clk/doc/fifo_generator_v9_3_vinfo.html +fifo_short_2clk/doc/pg057-fifo-generator.pdf +fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf +fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd +fifo_short_2clk/fifo_generator_v9_3_readme.txt +fifo_short_2clk/implement/implement.bat +fifo_short_2clk/implement/implement.sh +fifo_short_2clk/implement/implement_synplify.bat +fifo_short_2clk/implement/implement_synplify.sh +fifo_short_2clk/implement/planAhead_ise.bat +fifo_short_2clk/implement/planAhead_ise.sh +fifo_short_2clk/implement/planAhead_ise.tcl +fifo_short_2clk/implement/xst.prj +fifo_short_2clk/implement/xst.scr +fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd +fifo_short_2clk/simulation/fifo_short_2clk_dverif.vhd +fifo_short_2clk/simulation/fifo_short_2clk_pctrl.vhd +fifo_short_2clk/simulation/fifo_short_2clk_pkg.vhd +fifo_short_2clk/simulation/fifo_short_2clk_rng.vhd +fifo_short_2clk/simulation/fifo_short_2clk_synth.vhd +fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd +fifo_short_2clk/simulation/functional/simulate_isim.bat +fifo_short_2clk/simulation/functional/simulate_isim.sh +fifo_short_2clk/simulation/functional/simulate_mti.bat +fifo_short_2clk/simulation/functional/simulate_mti.do +fifo_short_2clk/simulation/functional/simulate_mti.sh +fifo_short_2clk/simulation/functional/simulate_ncsim.sh +fifo_short_2clk/simulation/functional/simulate_vcs.sh +fifo_short_2clk/simulation/functional/ucli_commands.key +fifo_short_2clk/simulation/functional/vcs_session.tcl +fifo_short_2clk/simulation/functional/wave_isim.tcl +fifo_short_2clk/simulation/functional/wave_mti.do +fifo_short_2clk/simulation/functional/wave_ncsim.sv +fifo_short_2clk/simulation/timing/simulate_isim.bat +fifo_short_2clk/simulation/timing/simulate_isim.sh +fifo_short_2clk/simulation/timing/simulate_mti.bat +fifo_short_2clk/simulation/timing/simulate_mti.do +fifo_short_2clk/simulation/timing/simulate_mti.sh +fifo_short_2clk/simulation/timing/simulate_ncsim.sh +fifo_short_2clk/simulation/timing/simulate_vcs.sh +fifo_short_2clk/simulation/timing/ucli_commands.key +fifo_short_2clk/simulation/timing/vcs_session.tcl +fifo_short_2clk/simulation/timing/wave_isim.tcl +fifo_short_2clk/simulation/timing/wave_mti.do +fifo_short_2clk/simulation/timing/wave_ncsim.sv +fifo_short_2clk.asy +fifo_short_2clk.gise +fifo_short_2clk.ngc +fifo_short_2clk.v +fifo_short_2clk.veo +fifo_short_2clk.xco +fifo_short_2clk.xise +fifo_short_2clk_flist.txt +fifo_short_2clk_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk_xmdf.tcl b/fpga/usrp3/top/b200/coregen/fifo_short_2clk_xmdf.tcl new file mode 100644 index 000000000..0abe2bb7c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk_xmdf.tcl @@ -0,0 +1,251 @@ +# The package naming convention is _xmdf +package provide fifo_short_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_short_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_short_2clk_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_short_2clk +} +# ::fifo_short_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_short_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/doc/fifo_generator_v9_3_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/doc/fifo_generator_v9_3_vinfo.html +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/doc/pg057-fifo-generator.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/fifo_generator_v9_3_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/implement.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/implement.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/implement_synplify.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/implement_synplify.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/planAhead_ise.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/planAhead_ise.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/planAhead_ise.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/xst.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/xst.scr +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_dverif.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_pctrl.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_pkg.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_rng.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_synth.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_isim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/wave_isim.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/wave_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/wave_ncsim.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_isim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/wave_isim.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/wave_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/wave_ncsim.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_short_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp3/top/b200/coregen_dsp/.gitignore b/fpga/usrp3/top/b200/coregen_dsp/.gitignore new file mode 100644 index 000000000..f9823bca9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/.gitignore @@ -0,0 +1,6 @@ +_xmsgs +*.log +*.ncf +*.xise +*.gise + diff --git a/fpga/usrp3/top/b200/coregen_dsp/Makefile.srcs b/fpga/usrp3/top/b200/coregen_dsp/Makefile.srcs new file mode 100644 index 000000000..180686b89 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/Makefile.srcs @@ -0,0 +1,15 @@ +# +# Copyright 2012 Ettus Research LLC +# + +################################################## +# Coregen Sources +################################################## + +COREGEN_DSP_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/b200/coregen_dsp/, \ +hbdec1.v \ +hbdec1.xco \ +hbdec2.v \ +hbdec2.xco \ +)) + diff --git a/fpga/usrp3/top/b200/coregen_dsp/coregen.cgp b/fpga/usrp3/top/b200/coregen_dsp/coregen.cgp new file mode 100644 index 000000000..52a3a53e7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/coregen.cgp @@ -0,0 +1,9 @@ +SET busformat = BusFormatAngleBracketNotRipped +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Other +SET package = fgg484 +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false diff --git a/fpga/usrp3/top/b200/coregen_dsp/filt2.coe b/fpga/usrp3/top/b200/coregen_dsp/filt2.coe new file mode 100644 index 000000000..e18b5daa7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/filt2.coe @@ -0,0 +1,36 @@ + Radix=10; +CoefData = 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282; diff --git a/fpga/usrp3/top/b200/coregen_dsp/hb31.coe b/fpga/usrp3/top/b200/coregen_dsp/hb31.coe new file mode 100644 index 000000000..37f5a180e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hb31.coe @@ -0,0 +1,32 @@ +Radix=10; +CoefData = -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581; diff --git a/fpga/usrp3/top/b200/coregen_dsp/hb35.coe b/fpga/usrp3/top/b200/coregen_dsp/hb35.coe new file mode 100644 index 000000000..18078085d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hb35.coe @@ -0,0 +1,36 @@ +Radix=10; +CoefData = 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282; diff --git a/fpga/usrp3/top/b200/coregen_dsp/hb39.coe b/fpga/usrp3/top/b200/coregen_dsp/hb39.coe new file mode 100644 index 000000000..1d99fa946 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hb39.coe @@ -0,0 +1,40 @@ +Radix=10; +CoefData = -102, + 0, + 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282, + 0, + -102; diff --git a/fpga/usrp3/top/b200/coregen_dsp/hb43.coe b/fpga/usrp3/top/b200/coregen_dsp/hb43.coe new file mode 100644 index 000000000..c56c4c928 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hb43.coe @@ -0,0 +1,44 @@ +Radix=10; +CoefData = 100, +0, +-102, + 0, + 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282, + 0, + -102, +0, +100; diff --git a/fpga/usrp3/top/b200/coregen_dsp/hb47.coe b/fpga/usrp3/top/b200/coregen_dsp/hb47.coe new file mode 100644 index 000000000..85b9a0f3d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hb47.coe @@ -0,0 +1,51 @@ +; Generated with round((2^18-2)*halfgen_test(.21,12,1)) +; 83% effective BW, 64dB to 85dB rolloff +Radix=10; +CoefData = +-62, + 0, + 194, + 0, +-440, + 0, + 855, + 0, +-1505, + 0, + 2478, + 0, +-3900, + 0, + 5990, + 0, +-9187, + 0, + 14632, + 0, +-26536, + 0, + 83009, + 131071, + 83009, + 0, +-26536, + 0, + 14632, + 0, +-9187, + 0, + 5990, + 0, +-3900, + 0, + 2478, + 0, +-1505, + 0, + 855, + 0, +-440, + 0, + 194, + 0, +-62; diff --git a/fpga/usrp3/top/b200/coregen_dsp/hb51.coe b/fpga/usrp3/top/b200/coregen_dsp/hb51.coe new file mode 100644 index 000000000..ebfddb7fb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hb51.coe @@ -0,0 +1,52 @@ +Radix=10; +CoefData = 300, +0, +-200, +0, +100, +0, +-102, + 0, + 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282, + 0, + -102, +0, +100, +0, +-200, +0, +300; diff --git a/fpga/usrp3/top/b200/coregen_dsp/hb55.coe b/fpga/usrp3/top/b200/coregen_dsp/hb55.coe new file mode 100644 index 000000000..07f861818 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hb55.coe @@ -0,0 +1,56 @@ +Radix=10; +CoefData = -400, +0, +300, +0, +-200, +0, +100, +0, +-102, + 0, + 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282, + 0, + -102, +0, +100, +0, +-200, +0, +300, +0, +-400; diff --git a/fpga/usrp3/top/b200/coregen_dsp/hb59.coe b/fpga/usrp3/top/b200/coregen_dsp/hb59.coe new file mode 100644 index 000000000..79f1e362b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hb59.coe @@ -0,0 +1,60 @@ +Radix=10; +CoefData = 500, +0, +-400, +0, +300, +0, +-200, +0, +100, +0, +-102, + 0, + 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282, + 0, + -102, +0, +100, +0, +-200, +0, +300, +0, +-400, +0 +500; diff --git a/fpga/usrp3/top/b200/coregen_dsp/hb63.coe b/fpga/usrp3/top/b200/coregen_dsp/hb63.coe new file mode 100644 index 000000000..3b312036d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hb63.coe @@ -0,0 +1,67 @@ +; Generated with round((2^18-2)*halfgen_test(.22,16,1)) +; 88% effective BW, 64dB to 87dB rolloff +Radix=10; +CoefData = +-35, + 0, + 95, + 0, +-195, + 0, + 352, + 0, +-582, + 0, + 907, + 0, +-1354, + 0, + 1953, + 0, +-2751, + 0, + 3813, + 0, +-5249, + 0, + 7264, + 0, +-10296, + 0, + 15494, + 0, +-27083, + 0, + 83196, + 131071, + 83196, + 0, +-27083, + 0, + 15494, + 0, +-10296, + 0, + 7264, + 0, +-5249, + 0, + 3813, + 0, +-2751, + 0, + 1953, + 0, +-1354, + 0, + 907, + 0, +-582, + 0, + 352, + 0, + -195, + 0 + 95, + 0 +-35; diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1.asy b/fpga/usrp3/top/b200/coregen_dsp/hbdec1.asy new file mode 100644 index 000000000..7644e7bbe --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1.asy @@ -0,0 +1,61 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 hbdec1 +RECTANGLE Normal 32 32 544 2048 +LINE Normal 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName nd +PINATTR Polarity IN +LINE Wide 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName din_1[23:0] +PINATTR Polarity IN +LINE Wide 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName din_2[23:0] +PINATTR Polarity IN +LINE Normal 0 848 32 848 +PIN 0 848 LEFT 36 +PINATTR PinName coef_ld +PINATTR Polarity IN +LINE Normal 0 880 32 880 +PIN 0 880 LEFT 36 +PINATTR PinName coef_we +PINATTR Polarity IN +LINE Wide 0 912 32 912 +PIN 0 912 LEFT 36 +PINATTR PinName coef_din[17:0] +PINATTR Polarity IN +LINE Normal 0 1008 32 1008 +PIN 0 1008 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Normal 0 1040 32 1040 +PIN 0 1040 LEFT 36 +PINATTR PinName ce +PINATTR Polarity IN +LINE Normal 0 1072 32 1072 +PIN 0 1072 LEFT 36 +PINATTR PinName sclr +PINATTR Polarity IN +LINE Wide 576 240 544 240 +PIN 576 240 RIGHT 36 +PINATTR PinName dout_1[46:0] +PINATTR Polarity OUT +LINE Wide 576 272 544 272 +PIN 576 272 RIGHT 36 +PINATTR PinName dout_2[46:0] +PINATTR Polarity OUT +LINE Normal 576 1840 544 1840 +PIN 576 1840 RIGHT 36 +PINATTR PinName rfd +PINATTR Polarity OUT +LINE Normal 576 1872 544 1872 +PIN 576 1872 RIGHT 36 +PINATTR PinName rdy +PINATTR Polarity OUT +LINE Normal 576 1904 544 1904 +PIN 576 1904 RIGHT 36 +PINATTR PinName data_valid +PINATTR Polarity OUT + diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec1.mif new file mode 100644 index 000000000..78d2dd901 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1.mif @@ -0,0 +1,47 @@ +111111111111000010 +000000000000000000 +000000000011000010 +000000000000000000 +111111111001001000 +000000000000000000 +000000001101010111 +000000000000000000 +111111101000011111 +000000000000000000 +000000100110101110 +000000000000000000 +111111000011000100 +000000000000000000 +000001011101100110 +000000000000000000 +111101110000011101 +000000000000000000 +000011100100101000 +000000000000000000 +111001100001011000 +000000000000000000 +010100010001000001 +011111111111111111 +010100010001000001 +000000000000000000 +111001100001011000 +000000000000000000 +000011100100101000 +000000000000000000 +111101110000011101 +000000000000000000 +000001011101100110 +000000000000000000 +111111000011000100 +000000000000000000 +000000100110101110 +000000000000000000 +111111101000011111 +000000000000000000 +000000001101010111 +000000000000000000 +111111111001001000 +000000000000000000 +000000000011000010 +000000000000000000 +111111111111000010 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1.ngc b/fpga/usrp3/top/b200/coregen_dsp/hbdec1.ngc new file mode 100644 index 000000000..68581229e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$26b<~753-Xnzd}foo8#5+421).97 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1.v b/fpga/usrp3/top/b200/coregen_dsp/hbdec1.v new file mode 100644 index 000000000..24069fbac --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1.v @@ -0,0 +1,45924 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: P.49d +// \ \ Application: netgen +// / / Filename: hbdec1.v +// /___/ /\ Timestamp: Fri Jan 9 12:44:22 2015 +// \ \ / \ +// \___\/\___\ +// +// Command : -intstyle ise -w -sim -ofmt verilog ./tmp/_cg/hbdec1.ngc ./tmp/_cg/hbdec1.v +// Device : 6slx150tfgg484-3 +// Input file : ./tmp/_cg/hbdec1.ngc +// Output file : ./tmp/_cg/hbdec1.v +// # of Modules : 1 +// Design Name : hbdec1 +// Xilinx : /opt/Xilinx/14.4/ISE_DS/ISE/ +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module hbdec1 ( + sclr, ce, rfd, rdy, data_valid, coef_we, nd, clk, coef_ld, dout_1, dout_2, din_1, din_2, coef_din +)/* synthesis syn_black_box syn_noprune=1 */; + input sclr; + input ce; + output rfd; + output rdy; + output data_valid; + input coef_we; + input nd; + input clk; + input coef_ld; + output [46 : 0] dout_1; + output [46 : 0] dout_2; + input [23 : 0] din_1; + input [23 : 0] din_2; + input [17 : 0] coef_din; + + // synthesis translate_off + + wire NlwRenamedSig_OI_rfd; + wire \blk00000003/sig00000e8e ; + wire \blk00000003/sig00000e8d ; + wire \blk00000003/sig00000e8c ; + wire \blk00000003/sig00000e8b ; + wire \blk00000003/sig00000e8a ; + wire \blk00000003/sig00000e89 ; + wire \blk00000003/sig00000e88 ; + wire \blk00000003/sig00000e87 ; + wire \blk00000003/sig00000e86 ; + wire \blk00000003/sig00000e85 ; + wire \blk00000003/sig00000e84 ; + wire \blk00000003/sig00000e83 ; + wire \blk00000003/sig00000e82 ; + wire \blk00000003/sig00000e81 ; + wire \blk00000003/sig00000e80 ; + wire \blk00000003/sig00000e7f ; + wire \blk00000003/sig00000e7e ; + wire \blk00000003/sig00000e7d ; + wire \blk00000003/sig00000e7c ; + wire \blk00000003/sig00000e7b ; + wire \blk00000003/sig00000e7a ; + wire \blk00000003/sig00000e79 ; + wire \blk00000003/sig00000e78 ; + wire \blk00000003/sig00000e77 ; + wire \blk00000003/sig00000e76 ; + wire \blk00000003/sig00000e75 ; + wire \blk00000003/sig00000e74 ; + wire \blk00000003/sig00000e73 ; + wire \blk00000003/sig00000e72 ; + wire \blk00000003/sig00000e71 ; + wire \blk00000003/sig00000e70 ; + wire \blk00000003/sig00000e6f ; + wire \blk00000003/sig00000e6e ; + wire \blk00000003/sig00000e6d ; + wire \blk00000003/sig00000e6c ; + wire \blk00000003/sig00000e6b ; + wire \blk00000003/sig00000e6a ; + wire \blk00000003/sig00000e69 ; + wire \blk00000003/sig00000e68 ; + wire \blk00000003/sig00000e67 ; + wire \blk00000003/sig00000e66 ; + wire \blk00000003/sig00000e65 ; + wire \blk00000003/sig00000e64 ; + wire \blk00000003/sig00000e63 ; + wire \blk00000003/sig00000e62 ; + wire \blk00000003/sig00000e61 ; + wire \blk00000003/sig00000e60 ; + wire \blk00000003/sig00000e5f ; + wire \blk00000003/sig00000e5e ; + wire \blk00000003/sig00000e5d ; + wire \blk00000003/sig00000e5c ; + wire \blk00000003/sig00000e5b ; + wire \blk00000003/sig00000e5a ; + wire \blk00000003/sig00000e59 ; + wire \blk00000003/sig00000e58 ; + wire \blk00000003/sig00000e57 ; + wire \blk00000003/sig00000e56 ; + wire \blk00000003/sig00000e55 ; + wire \blk00000003/sig00000e54 ; + wire \blk00000003/sig00000e53 ; + wire \blk00000003/sig00000e52 ; + wire \blk00000003/sig00000e51 ; + wire \blk00000003/sig00000e50 ; + wire \blk00000003/sig00000e4f ; + wire \blk00000003/sig00000e4e ; + wire \blk00000003/sig00000e4d ; + wire \blk00000003/sig00000e4c ; + wire \blk00000003/sig00000e4b ; + wire \blk00000003/sig00000e4a ; + wire \blk00000003/sig00000e49 ; + wire \blk00000003/sig00000e48 ; + wire \blk00000003/sig00000e47 ; + wire \blk00000003/sig00000e46 ; + wire \blk00000003/sig00000e45 ; + wire \blk00000003/sig00000e44 ; + wire \blk00000003/sig00000e43 ; + wire \blk00000003/sig00000e42 ; + wire \blk00000003/sig00000e41 ; + wire \blk00000003/sig00000e40 ; + wire \blk00000003/sig00000e3f ; + wire \blk00000003/sig00000e3e ; + wire \blk00000003/sig00000e3d ; + wire \blk00000003/sig00000e3c ; + wire \blk00000003/sig00000e3b ; + wire \blk00000003/sig00000e3a ; + wire \blk00000003/sig00000e39 ; + wire \blk00000003/sig00000e38 ; + wire \blk00000003/sig00000e37 ; + wire \blk00000003/sig00000e36 ; + wire \blk00000003/sig00000e35 ; + wire \blk00000003/sig00000e34 ; + wire \blk00000003/sig00000e33 ; + wire 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\NLW_blk00000003/blk00000c77_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c75_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c73_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c71_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c6f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c6d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c6b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c69_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c67_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c65_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c63_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c61_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c5f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c5d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c5b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c59_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c57_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c55_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c53_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c51_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c4f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c4d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c4b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c49_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c47_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c45_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c43_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c41_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c3f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c3d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c3b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c39_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c37_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c35_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c33_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c31_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c2f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c2d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c2b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c29_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c27_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c25_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c23_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c21_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c1f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c1d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c1b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c19_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c17_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c15_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c13_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c11_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c0f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c0d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c0b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c09_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c07_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c05_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c03_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c01_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bfd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bfb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bf9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bf7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bf5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bf3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bf1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bef_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bed_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000beb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000be9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000be7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000be5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000be3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000be1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bdf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bdd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bdb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bd9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bd7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bd5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bd3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bd1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bcf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bcd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bcb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bc9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bc7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bc5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bc3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bc1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bbf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bbd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bbb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bb9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bb7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bb5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bb3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bb1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000baf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ba9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ba7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ba5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ba3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ba1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b9f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b9d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b9b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b99_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b97_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b95_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b93_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b91_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b8f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b8d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b8b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b89_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b87_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b85_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b83_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b81_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b7f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b7d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b7b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b79_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b77_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b75_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b73_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b71_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b6f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b6d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b6b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b69_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b67_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b65_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b63_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b61_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b5f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b5d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b5b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b59_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b57_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b55_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b53_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b51_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b4f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b4d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b4b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b49_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b47_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b45_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b43_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b41_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b3f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b3d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b3b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b39_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b37_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b35_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b33_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b31_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b2f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b2d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b2b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b29_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b27_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b25_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b23_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b21_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b1f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b1d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b1b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b19_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b17_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b15_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b13_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b11_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b0f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b0d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b0b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b09_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b07_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b05_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b03_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b01_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000afd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000afb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000af9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000af7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000af5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000af3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000af1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aef_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aed_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aeb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000adf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000add_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000adb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ad9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ad7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ad5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ad3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ad1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000acf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000acd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000acb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ac9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ac7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ac5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ac3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ac1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000abf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000abd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000abb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ab9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ab7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ab5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ab3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ab1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aaf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aa9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aa7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aa5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aa3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aa1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a9f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a9d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a9b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a99_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a97_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a95_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a93_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a91_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a8f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a8d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a8b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a89_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a87_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a85_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a83_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a81_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a7f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a7d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a7b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a79_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a77_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a75_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a73_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a71_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a6f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a6d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a6b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a69_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a67_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a65_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a63_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a61_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a5f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a5d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a5b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a59_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a57_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a55_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a53_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a51_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a4f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a4d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a4b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a49_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a47_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a45_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a43_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a41_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a3f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a3d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a3b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a39_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a37_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a35_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a33_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a31_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a2f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a2d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a2b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a29_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a27_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a25_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a23_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a21_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a1f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a1d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a1b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a19_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a17_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a15_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a13_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a11_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a0f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a0d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a0b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a09_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a07_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a05_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a03_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a01_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009ff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009fd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009fb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009f9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009f7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009f5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009f3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009f1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009ef_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009ed_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009eb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009e9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009e7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009e5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009cd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009cb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009c9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009c7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009c5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009c3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009c1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009bf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009bd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009bb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009b9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009b7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009b5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009b3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000099f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000099d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000099b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000999_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000997_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000995_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000993_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000991_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000098f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000098d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000098b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000989_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000987_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000985_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000983_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000981_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000097f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000097d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000097b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000979_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000977_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000975_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000973_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000971_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000096f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000096d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000096b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000969_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000967_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000965_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000963_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000961_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000095f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000095d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000095b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000959_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000957_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000955_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000953_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000951_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000094f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000094d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000858_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000858_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007ee_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000007ee_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f3_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f3_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e1_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e0_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000df_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000de_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000dd_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000dc_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d8_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d6_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d5_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d4_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d3_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cc_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cc_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c9_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c9_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b5_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b3_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk000000aa_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a8_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a6_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a4_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a3_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a0_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009f_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009d_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009d_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009b_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009a_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000027_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000023_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000021_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000020_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001a_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000c_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000009_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000096_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000095_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000094_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000093_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000092_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000091_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000090_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000008f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000008e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000008d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000008c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000008b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000008a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000089_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000088_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000087_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000086_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000085_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000084_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000083_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000082_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000081_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000080_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000007f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000007e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000007d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000007c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000007b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000007a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000079_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000078_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000077_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000076_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000075_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000074_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000073_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000072_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000071_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000070_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000006f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000006e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000006d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000006c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000006b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000006a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000069_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000068_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000067_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk0000015e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk0000015d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk0000015c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk0000015b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk0000015a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000159_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000158_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000157_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000156_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000155_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000154_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000153_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000152_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000151_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000150_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk0000014f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000181_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000180_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk0000017f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk0000017e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk0000017d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk0000017c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk0000017b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk0000017a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000179_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000178_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000177_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000176_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000175_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000174_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000173_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000172_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk000001a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk000001a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk000001a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk000001a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk000001a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk0000019f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk0000019e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk0000019d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk0000019c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk0000019b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk0000019a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk00000199_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk00000198_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk00000197_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk00000196_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk00000195_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001c7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001c6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001c5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001c4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001c3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001c2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001c1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001c0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001bf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001be_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001bd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001bc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001bb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001ba_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001b9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001b8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001ea_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000209_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000208_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000207_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000206_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000205_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000204_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000203_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000202_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000201_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000200_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk000001ff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk000001fe_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000230_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk0000022f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk0000022e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk0000022d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk0000022c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk0000022b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk0000022a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000229_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000228_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000227_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000226_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000225_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000224_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000223_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000222_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000221_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000253_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000252_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000251_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000250_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk0000024f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk0000024e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk0000024d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk0000024c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk0000024b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk0000024a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000249_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000248_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000247_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000246_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000245_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000244_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000276_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000275_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000274_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000273_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000272_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000271_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000270_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk0000026f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk0000026e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk0000026d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk0000026c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk0000026b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk0000026a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000269_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000268_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000267_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000299_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000298_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000297_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000296_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000295_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000294_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000293_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000292_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000291_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000290_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk0000028f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk0000028e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk0000028d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk0000028c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk0000028b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk0000028a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002bc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002bb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002ba_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk00000302_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk00000301_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk00000300_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002ff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002fe_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002fd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002fc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002fb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002fa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002f9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002f8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002f7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002f6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002f5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002f4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002f3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000325_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000324_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000323_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000322_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000321_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000320_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk0000031f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk0000031e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk0000031d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk0000031c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk0000031b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk0000031a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000319_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000318_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000317_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000316_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000348_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000347_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000346_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000345_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000344_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000343_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000342_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000341_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000340_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk0000033f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk0000033e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk0000033d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk0000033c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk0000033b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk0000033a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000339_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk0000036b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk0000036a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000369_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000368_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000367_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000366_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000365_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000364_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000363_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000362_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000361_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000360_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk0000035f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk0000035e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk0000035d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk0000035c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk0000038e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk0000038d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk0000038c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk0000038b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk0000038a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000389_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000388_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000387_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000386_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000385_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000384_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000383_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000382_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000381_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000380_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk0000037f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003cd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003cc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003cb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003ca_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003c9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003c8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003c7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003c6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003c5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003f7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003f6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003f5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003f4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003f3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003f2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003f1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003f0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003ef_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003ee_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003ed_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003ec_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003eb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003ea_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003e9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003e8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk0000041a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000419_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000418_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000417_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000416_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000415_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000414_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000413_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000412_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000411_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000410_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk0000040f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk0000040e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk0000040d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk0000040c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk0000040b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk0000043d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk0000043c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk0000043b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk0000043a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000439_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000438_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000437_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000436_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000435_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000434_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000433_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000432_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000431_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000430_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk0000042f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk0000042e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000460_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk0000045f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk0000045e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk0000045d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk0000045c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk0000045b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk0000045a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000459_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000458_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000457_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000456_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000455_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000454_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000453_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000452_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000451_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000483_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000482_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000481_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000480_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk0000047f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk0000047e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk0000047d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk0000047c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk0000047b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk0000047a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000479_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000478_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000477_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000476_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000475_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000474_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005c7_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005c6_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005c5_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005c4_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005c3_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005c2_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005c1_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005c0_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005bf_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005be_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005bd_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005bc_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005bb_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005ba_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005b9_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005b8_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005b7_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005b6_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c9/blk000005da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c9/blk000005d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c9/blk000005d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c9/blk000005d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c9/blk000005d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c9/blk000005d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c9/blk000005d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c9/blk000005d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc/blk000005ed_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc/blk000005ec_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc/blk000005eb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc/blk000005ea_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc/blk000005e9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc/blk000005e8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc/blk000005e7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc/blk000005e6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ef/blk00000600_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ef/blk000005ff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ef/blk000005fe_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ef/blk000005fd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ef/blk000005fc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ef/blk000005fb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ef/blk000005fa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ef/blk000005f9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602/blk00000613_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602/blk00000612_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602/blk00000611_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602/blk00000610_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602/blk0000060f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602/blk0000060e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602/blk0000060d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602/blk0000060c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000615/blk00000626_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000615/blk00000625_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000615/blk00000624_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000615/blk00000623_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000615/blk00000622_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000615/blk00000621_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000615/blk00000620_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000615/blk0000061f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628/blk00000639_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628/blk00000638_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628/blk00000637_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628/blk00000636_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628/blk00000635_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628/blk00000634_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628/blk00000633_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628/blk00000632_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063b/blk0000064c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063b/blk0000064b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063b/blk0000064a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063b/blk00000649_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063b/blk00000648_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063b/blk00000647_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063b/blk00000646_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063b/blk00000645_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e/blk0000065f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e/blk0000065e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e/blk0000065d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e/blk0000065c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e/blk0000065b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e/blk0000065a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e/blk00000659_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e/blk00000658_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000661/blk00000672_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000661/blk00000671_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000661/blk00000670_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000661/blk0000066f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000661/blk0000066e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000661/blk0000066d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000661/blk0000066c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000661/blk0000066b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674/blk00000685_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674/blk00000684_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674/blk00000683_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674/blk00000682_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674/blk00000681_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674/blk00000680_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674/blk0000067f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674/blk0000067e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000687/blk00000698_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000687/blk00000697_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000687/blk00000696_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000687/blk00000695_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000687/blk00000694_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000687/blk00000693_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000687/blk00000692_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000687/blk00000691_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a/blk000006ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a/blk000006aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a/blk000006a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a/blk000006a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a/blk000006a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a/blk000006a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a/blk000006a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a/blk000006a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ad/blk000006be_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ad/blk000006bd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ad/blk000006bc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ad/blk000006bb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ad/blk000006ba_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ad/blk000006b9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ad/blk000006b8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ad/blk000006b7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c0/blk000006d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c0/blk000006d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c0/blk000006cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c0/blk000006ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c0/blk000006cd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c0/blk000006cc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c0/blk000006cb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c0/blk000006ca_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d3/blk000006e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d3/blk000006e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d3/blk000006e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d3/blk000006e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d3/blk000006e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d3/blk000006df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d3/blk000006de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d3/blk000006dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e6/blk000006f7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e6/blk000006f6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e6/blk000006f5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e6/blk000006f4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e6/blk000006f3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e6/blk000006f2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e6/blk000006f1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e6/blk000006f0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f9/blk0000070a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f9/blk00000709_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f9/blk00000708_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f9/blk00000707_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f9/blk00000706_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f9/blk00000705_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f9/blk00000704_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f9/blk00000703_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070c/blk0000071d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070c/blk0000071c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070c/blk0000071b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070c/blk0000071a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070c/blk00000719_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070c/blk00000718_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070c/blk00000717_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070c/blk00000716_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071f/blk00000730_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071f/blk0000072f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071f/blk0000072e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071f/blk0000072d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071f/blk0000072c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071f/blk0000072b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071f/blk0000072a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071f/blk00000729_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000732/blk00000743_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000732/blk00000742_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000732/blk00000741_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000732/blk00000740_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000732/blk0000073f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000732/blk0000073e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000732/blk0000073d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000732/blk0000073c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000745/blk00000756_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000745/blk00000755_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000745/blk00000754_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000745/blk00000753_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000745/blk00000752_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000745/blk00000751_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000745/blk00000750_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000745/blk0000074f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000758/blk00000769_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000758/blk00000768_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000758/blk00000767_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000758/blk00000766_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000758/blk00000765_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000758/blk00000764_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000758/blk00000763_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000758/blk00000762_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076b/blk0000077c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076b/blk0000077b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076b/blk0000077a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076b/blk00000779_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076b/blk00000778_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076b/blk00000777_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076b/blk00000776_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076b/blk00000775_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077e/blk0000078f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077e/blk0000078e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077e/blk0000078d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077e/blk0000078c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077e/blk0000078b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077e/blk0000078a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077e/blk00000789_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077e/blk00000788_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007e6_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007e5_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007e4_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007e3_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007e2_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007e1_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007e0_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007df_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007de_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007dd_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007dc_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007db_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007da_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007d9_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007d8_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007d7_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007d6_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007d5_SPO_UNCONNECTED ; + wire [17 : 0] coef_din_0; + wire [23 : 0] din_1_1; + wire [23 : 0] din_2_2; + wire [46 : 0] NlwRenamedSig_OI_dout_1; + wire [46 : 0] NlwRenamedSig_OI_dout_2; + assign + rfd = NlwRenamedSig_OI_rfd, + dout_1[46] = NlwRenamedSig_OI_dout_1[46], + dout_1[45] = NlwRenamedSig_OI_dout_1[45], + dout_1[44] = NlwRenamedSig_OI_dout_1[44], + dout_1[43] = NlwRenamedSig_OI_dout_1[43], + dout_1[42] = NlwRenamedSig_OI_dout_1[42], + dout_1[41] = NlwRenamedSig_OI_dout_1[41], + dout_1[40] = NlwRenamedSig_OI_dout_1[40], + dout_1[39] = NlwRenamedSig_OI_dout_1[39], + dout_1[38] = NlwRenamedSig_OI_dout_1[38], + dout_1[37] = NlwRenamedSig_OI_dout_1[37], + dout_1[36] = NlwRenamedSig_OI_dout_1[36], + dout_1[35] = NlwRenamedSig_OI_dout_1[35], + dout_1[34] = NlwRenamedSig_OI_dout_1[34], + dout_1[33] = NlwRenamedSig_OI_dout_1[33], + dout_1[32] = NlwRenamedSig_OI_dout_1[32], + dout_1[31] = NlwRenamedSig_OI_dout_1[31], + dout_1[30] = NlwRenamedSig_OI_dout_1[30], + dout_1[29] = NlwRenamedSig_OI_dout_1[29], + dout_1[28] = NlwRenamedSig_OI_dout_1[28], + dout_1[27] = NlwRenamedSig_OI_dout_1[27], + dout_1[26] = NlwRenamedSig_OI_dout_1[26], + dout_1[25] = NlwRenamedSig_OI_dout_1[25], + dout_1[24] = NlwRenamedSig_OI_dout_1[24], + dout_1[23] = NlwRenamedSig_OI_dout_1[23], + dout_1[22] = NlwRenamedSig_OI_dout_1[22], + dout_1[21] = NlwRenamedSig_OI_dout_1[21], + dout_1[20] = NlwRenamedSig_OI_dout_1[20], + dout_1[19] = NlwRenamedSig_OI_dout_1[19], + dout_1[18] = NlwRenamedSig_OI_dout_1[18], + dout_1[17] = NlwRenamedSig_OI_dout_1[17], + dout_1[16] = NlwRenamedSig_OI_dout_1[16], + dout_1[15] = NlwRenamedSig_OI_dout_1[15], + dout_1[14] = NlwRenamedSig_OI_dout_1[14], + dout_1[13] = NlwRenamedSig_OI_dout_1[13], + dout_1[12] = NlwRenamedSig_OI_dout_1[12], + dout_1[11] = NlwRenamedSig_OI_dout_1[11], + dout_1[10] = NlwRenamedSig_OI_dout_1[10], + dout_1[9] = NlwRenamedSig_OI_dout_1[9], + dout_1[8] = NlwRenamedSig_OI_dout_1[8], + dout_1[7] = NlwRenamedSig_OI_dout_1[7], + dout_1[6] = NlwRenamedSig_OI_dout_1[6], + dout_1[5] = NlwRenamedSig_OI_dout_1[5], + dout_1[4] = NlwRenamedSig_OI_dout_1[4], + dout_1[3] = NlwRenamedSig_OI_dout_1[3], + dout_1[2] = NlwRenamedSig_OI_dout_1[2], + dout_1[1] = NlwRenamedSig_OI_dout_1[1], + dout_1[0] = NlwRenamedSig_OI_dout_1[0], + dout_2[46] = NlwRenamedSig_OI_dout_2[46], + dout_2[45] = NlwRenamedSig_OI_dout_2[45], + dout_2[44] = NlwRenamedSig_OI_dout_2[44], + dout_2[43] = NlwRenamedSig_OI_dout_2[43], + dout_2[42] = NlwRenamedSig_OI_dout_2[42], + dout_2[41] = NlwRenamedSig_OI_dout_2[41], + dout_2[40] = NlwRenamedSig_OI_dout_2[40], + dout_2[39] = NlwRenamedSig_OI_dout_2[39], + dout_2[38] = NlwRenamedSig_OI_dout_2[38], + dout_2[37] = NlwRenamedSig_OI_dout_2[37], + dout_2[36] = NlwRenamedSig_OI_dout_2[36], + dout_2[35] = NlwRenamedSig_OI_dout_2[35], + dout_2[34] = NlwRenamedSig_OI_dout_2[34], + dout_2[33] = NlwRenamedSig_OI_dout_2[33], + dout_2[32] = NlwRenamedSig_OI_dout_2[32], + dout_2[31] = NlwRenamedSig_OI_dout_2[31], + dout_2[30] = NlwRenamedSig_OI_dout_2[30], + dout_2[29] = NlwRenamedSig_OI_dout_2[29], + dout_2[28] = NlwRenamedSig_OI_dout_2[28], + dout_2[27] = NlwRenamedSig_OI_dout_2[27], + dout_2[26] = NlwRenamedSig_OI_dout_2[26], + dout_2[25] = NlwRenamedSig_OI_dout_2[25], + dout_2[24] = NlwRenamedSig_OI_dout_2[24], + dout_2[23] = NlwRenamedSig_OI_dout_2[23], + dout_2[22] = NlwRenamedSig_OI_dout_2[22], + dout_2[21] = NlwRenamedSig_OI_dout_2[21], + dout_2[20] = NlwRenamedSig_OI_dout_2[20], + dout_2[19] = NlwRenamedSig_OI_dout_2[19], + dout_2[18] = NlwRenamedSig_OI_dout_2[18], + dout_2[17] = NlwRenamedSig_OI_dout_2[17], + dout_2[16] = NlwRenamedSig_OI_dout_2[16], + dout_2[15] = NlwRenamedSig_OI_dout_2[15], + dout_2[14] = NlwRenamedSig_OI_dout_2[14], + dout_2[13] = NlwRenamedSig_OI_dout_2[13], + dout_2[12] = NlwRenamedSig_OI_dout_2[12], + dout_2[11] = NlwRenamedSig_OI_dout_2[11], + dout_2[10] = NlwRenamedSig_OI_dout_2[10], + dout_2[9] = NlwRenamedSig_OI_dout_2[9], + dout_2[8] = NlwRenamedSig_OI_dout_2[8], + dout_2[7] = NlwRenamedSig_OI_dout_2[7], + dout_2[6] = NlwRenamedSig_OI_dout_2[6], + dout_2[5] = NlwRenamedSig_OI_dout_2[5], + dout_2[4] = NlwRenamedSig_OI_dout_2[4], + dout_2[3] = NlwRenamedSig_OI_dout_2[3], + dout_2[2] = NlwRenamedSig_OI_dout_2[2], + dout_2[1] = NlwRenamedSig_OI_dout_2[1], + dout_2[0] = NlwRenamedSig_OI_dout_2[0], + din_1_1[23] = din_1[23], + din_1_1[22] = din_1[22], + din_1_1[21] = din_1[21], + din_1_1[20] = din_1[20], + din_1_1[19] = din_1[19], + din_1_1[18] = din_1[18], + din_1_1[17] = din_1[17], + din_1_1[16] = din_1[16], + din_1_1[15] = din_1[15], + din_1_1[14] = din_1[14], + din_1_1[13] = din_1[13], + din_1_1[12] = din_1[12], + din_1_1[11] = din_1[11], + din_1_1[10] = din_1[10], + din_1_1[9] = din_1[9], + din_1_1[8] = din_1[8], + din_1_1[7] = din_1[7], + din_1_1[6] = din_1[6], + din_1_1[5] = din_1[5], + din_1_1[4] = din_1[4], + din_1_1[3] = din_1[3], + din_1_1[2] = din_1[2], + din_1_1[1] = din_1[1], + din_1_1[0] = din_1[0], + din_2_2[23] = din_2[23], + din_2_2[22] = din_2[22], + din_2_2[21] = din_2[21], + din_2_2[20] = din_2[20], + din_2_2[19] = din_2[19], + din_2_2[18] = din_2[18], + din_2_2[17] = din_2[17], + din_2_2[16] = din_2[16], + din_2_2[15] = din_2[15], + din_2_2[14] = din_2[14], + din_2_2[13] = din_2[13], + din_2_2[12] = din_2[12], + din_2_2[11] = din_2[11], + din_2_2[10] = din_2[10], + din_2_2[9] = din_2[9], + din_2_2[8] = din_2[8], + din_2_2[7] = din_2[7], + din_2_2[6] = din_2[6], + din_2_2[5] = din_2[5], + din_2_2[4] = din_2[4], + din_2_2[3] = din_2[3], + din_2_2[2] = din_2[2], + din_2_2[1] = din_2[1], + din_2_2[0] = din_2[0], + coef_din_0[17] = coef_din[17], + coef_din_0[16] = coef_din[16], + coef_din_0[15] = coef_din[15], + coef_din_0[14] = coef_din[14], + coef_din_0[13] = coef_din[13], + coef_din_0[12] = coef_din[12], + coef_din_0[11] = coef_din[11], + coef_din_0[10] = coef_din[10], + coef_din_0[9] = coef_din[9], + coef_din_0[8] = coef_din[8], + coef_din_0[7] = coef_din[7], + coef_din_0[6] = coef_din[6], + coef_din_0[5] = coef_din[5], + coef_din_0[4] = coef_din[4], + coef_din_0[3] = coef_din[3], + coef_din_0[2] = coef_din[2], + coef_din_0[1] = coef_din[1], + coef_din_0[0] = coef_din[0]; + VCC blk00000001 ( + .P(NLW_blk00000001_P_UNCONNECTED) + ); + GND blk00000002 ( + .G(NLW_blk00000002_G_UNCONNECTED) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc4 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e8e ), + .Q(\blk00000003/sig00000bc2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000baa ), + .Q(\blk00000003/sig00000e8e ), + .Q15(\NLW_blk00000003/blk00000cc3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc2 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e8d ), + .Q(\blk00000003/sig00000bc1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000ba9 ), + .Q(\blk00000003/sig00000e8d ), + .Q15(\NLW_blk00000003/blk00000cc1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc0 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e8c ), + .Q(\blk00000003/sig00000bc0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cbf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000ba8 ), + .Q(\blk00000003/sig00000e8c ), + .Q15(\NLW_blk00000003/blk00000cbf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cbe ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e8b ), + .Q(\blk00000003/sig00000bbf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cbd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000ba7 ), + .Q(\blk00000003/sig00000e8b ), + .Q15(\NLW_blk00000003/blk00000cbd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cbc ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e8a ), + .Q(\blk00000003/sig00000bbe ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cbb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000ba6 ), + .Q(\blk00000003/sig00000e8a ), + .Q15(\NLW_blk00000003/blk00000cbb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cba ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e89 ), + .Q(\blk00000003/sig00000bbc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cb9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000ba4 ), + .Q(\blk00000003/sig00000e89 ), + .Q15(\NLW_blk00000003/blk00000cb9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cb8 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e88 ), + .Q(\blk00000003/sig00000bbb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cb7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000ba3 ), + .Q(\blk00000003/sig00000e88 ), + .Q15(\NLW_blk00000003/blk00000cb7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cb6 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e87 ), + .Q(\blk00000003/sig00000bbd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cb5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000ba5 ), + .Q(\blk00000003/sig00000e87 ), + .Q15(\NLW_blk00000003/blk00000cb5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cb4 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e86 ), + .Q(\blk00000003/sig00000bd2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cb3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000bb2 ), + .Q(\blk00000003/sig00000e86 ), + .Q15(\NLW_blk00000003/blk00000cb3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cb2 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e85 ), + .Q(\blk00000003/sig00000bd1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cb1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000bb1 ), + .Q(\blk00000003/sig00000e85 ), + .Q15(\NLW_blk00000003/blk00000cb1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cb0 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e84 ), + .Q(\blk00000003/sig00000bd0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000caf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000bb0 ), + .Q(\blk00000003/sig00000e84 ), + .Q15(\NLW_blk00000003/blk00000caf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cae ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e83 ), + .Q(\blk00000003/sig00000bcf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cad ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000baf ), + .Q(\blk00000003/sig00000e83 ), + .Q15(\NLW_blk00000003/blk00000cad_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cac ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e82 ), + .Q(\blk00000003/sig00000bce ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cab ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000bae ), + .Q(\blk00000003/sig00000e82 ), + .Q15(\NLW_blk00000003/blk00000cab_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000caa ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e81 ), + .Q(\blk00000003/sig00000bcd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ca9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000bad ), + .Q(\blk00000003/sig00000e81 ), + .Q15(\NLW_blk00000003/blk00000ca9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ca8 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e80 ), + .Q(\blk00000003/sig00000bcb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ca7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000bab ), + .Q(\blk00000003/sig00000e80 ), + .Q15(\NLW_blk00000003/blk00000ca7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ca6 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e7f ), + .Q(\blk00000003/sig00000bcc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ca5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000bac ), + .Q(\blk00000003/sig00000e7f ), + .Q15(\NLW_blk00000003/blk00000ca5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ca4 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e7e ), + .Q(\blk00000003/sig00000ad6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ca3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000aa6 ), + .Q(\blk00000003/sig00000e7e ), + .Q15(\NLW_blk00000003/blk00000ca3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ca2 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e7d ), + .Q(\blk00000003/sig00000ad5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ca1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000aa5 ), + .Q(\blk00000003/sig00000e7d ), + .Q15(\NLW_blk00000003/blk00000ca1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ca0 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e7c ), + .Q(\blk00000003/sig00000ad4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c9f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000aa4 ), + .Q(\blk00000003/sig00000e7c ), + .Q15(\NLW_blk00000003/blk00000c9f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c9e ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e7b ), + .Q(\blk00000003/sig00000ad3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c9d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000aa3 ), + .Q(\blk00000003/sig00000e7b ), + .Q15(\NLW_blk00000003/blk00000c9d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c9c ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e7a ), + .Q(\blk00000003/sig00000ad1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c9b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000aa1 ), + .Q(\blk00000003/sig00000e7a ), + .Q15(\NLW_blk00000003/blk00000c9b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c9a ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e79 ), + .Q(\blk00000003/sig00000ad0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c99 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000aa0 ), + .Q(\blk00000003/sig00000e79 ), + .Q15(\NLW_blk00000003/blk00000c99_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c98 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e78 ), + .Q(\blk00000003/sig00000ad2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c97 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000aa2 ), + .Q(\blk00000003/sig00000e78 ), + .Q15(\NLW_blk00000003/blk00000c97_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c96 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e77 ), + .Q(\blk00000003/sig00000acf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c95 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a9f ), + .Q(\blk00000003/sig00000e77 ), + .Q15(\NLW_blk00000003/blk00000c95_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c94 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e76 ), + .Q(\blk00000003/sig00000ace ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c93 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a9e ), + .Q(\blk00000003/sig00000e76 ), + .Q15(\NLW_blk00000003/blk00000c93_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c92 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e75 ), + .Q(\blk00000003/sig00000acd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c91 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a9d ), + .Q(\blk00000003/sig00000e75 ), + .Q15(\NLW_blk00000003/blk00000c91_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c90 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e74 ), + .Q(\blk00000003/sig00000acc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c8f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a9c ), + .Q(\blk00000003/sig00000e74 ), + .Q15(\NLW_blk00000003/blk00000c8f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c8e ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e73 ), + .Q(\blk00000003/sig00000aca ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c8d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a9a ), + .Q(\blk00000003/sig00000e73 ), + .Q15(\NLW_blk00000003/blk00000c8d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c8c ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e72 ), + .Q(\blk00000003/sig00000ac9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c8b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a99 ), + .Q(\blk00000003/sig00000e72 ), + .Q15(\NLW_blk00000003/blk00000c8b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c8a ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e71 ), + .Q(\blk00000003/sig00000acb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c89 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a9b ), + .Q(\blk00000003/sig00000e71 ), + .Q15(\NLW_blk00000003/blk00000c89_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c88 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e70 ), + .Q(\blk00000003/sig00000ac7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c87 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a97 ), + .Q(\blk00000003/sig00000e70 ), + .Q15(\NLW_blk00000003/blk00000c87_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c86 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e6f ), + .Q(\blk00000003/sig00000ac8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c85 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a98 ), + .Q(\blk00000003/sig00000e6f ), + .Q15(\NLW_blk00000003/blk00000c85_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c84 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e6e ), + .Q(\blk00000003/sig00000af5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c83 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000ab5 ), + .Q(\blk00000003/sig00000e6e ), + .Q15(\NLW_blk00000003/blk00000c83_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c82 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e6d ), + .Q(\blk00000003/sig00000af4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c81 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000ab4 ), + .Q(\blk00000003/sig00000e6d ), + .Q15(\NLW_blk00000003/blk00000c81_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c80 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e6c ), + .Q(\blk00000003/sig00000af6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c7f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000ab6 ), + .Q(\blk00000003/sig00000e6c ), + .Q15(\NLW_blk00000003/blk00000c7f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c7e ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e6b ), + .Q(\blk00000003/sig00000af3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c7d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000ab3 ), + .Q(\blk00000003/sig00000e6b ), + .Q15(\NLW_blk00000003/blk00000c7d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c7c ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e6a ), + .Q(\blk00000003/sig00000af2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c7b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000ab2 ), + .Q(\blk00000003/sig00000e6a ), + .Q15(\NLW_blk00000003/blk00000c7b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c7a ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e69 ), + .Q(\blk00000003/sig00000af1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c79 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000ab1 ), + .Q(\blk00000003/sig00000e69 ), + .Q15(\NLW_blk00000003/blk00000c79_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c78 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e68 ), + .Q(\blk00000003/sig00000af0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c77 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000ab0 ), + .Q(\blk00000003/sig00000e68 ), + .Q15(\NLW_blk00000003/blk00000c77_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c76 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e67 ), + .Q(\blk00000003/sig00000aee ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c75 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aae ), + .Q(\blk00000003/sig00000e67 ), + .Q15(\NLW_blk00000003/blk00000c75_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c74 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e66 ), + .Q(\blk00000003/sig00000aed ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c73 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aad ), + .Q(\blk00000003/sig00000e66 ), + .Q15(\NLW_blk00000003/blk00000c73_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c72 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e65 ), + .Q(\blk00000003/sig00000aef ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c71 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aaf ), + .Q(\blk00000003/sig00000e65 ), + .Q15(\NLW_blk00000003/blk00000c71_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c70 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e64 ), + .Q(\blk00000003/sig00000aec ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c6f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aac ), + .Q(\blk00000003/sig00000e64 ), + .Q15(\NLW_blk00000003/blk00000c6f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c6e ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e63 ), + .Q(\blk00000003/sig00000aeb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c6d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aab ), + .Q(\blk00000003/sig00000e63 ), + .Q15(\NLW_blk00000003/blk00000c6d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c6c ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e62 ), + .Q(\blk00000003/sig00000aea ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c6b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aaa ), + .Q(\blk00000003/sig00000e62 ), + .Q15(\NLW_blk00000003/blk00000c6b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c6a ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e61 ), + .Q(\blk00000003/sig00000ae9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c69 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aa9 ), + .Q(\blk00000003/sig00000e61 ), + .Q15(\NLW_blk00000003/blk00000c69_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c68 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e60 ), + .Q(\blk00000003/sig00000ae7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c67 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aa7 ), + .Q(\blk00000003/sig00000e60 ), + .Q15(\NLW_blk00000003/blk00000c67_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c66 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e5f ), + .Q(\blk00000003/sig00000ae8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c65 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aa8 ), + .Q(\blk00000003/sig00000e5f ), + .Q15(\NLW_blk00000003/blk00000c65_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c64 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e5e ), + .Q(\blk00000003/sig00000baa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c63 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b9a ), + .Q(\blk00000003/sig00000e5e ), + .Q15(\NLW_blk00000003/blk00000c63_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c62 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e5d ), + .Q(\blk00000003/sig00000ba9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c61 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b99 ), + .Q(\blk00000003/sig00000e5d ), + .Q15(\NLW_blk00000003/blk00000c61_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c60 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e5c ), + .Q(\blk00000003/sig00000ba8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c5f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b98 ), + .Q(\blk00000003/sig00000e5c ), + .Q15(\NLW_blk00000003/blk00000c5f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c5e ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e5b ), + .Q(\blk00000003/sig00000ba7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c5d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b97 ), + .Q(\blk00000003/sig00000e5b ), + .Q15(\NLW_blk00000003/blk00000c5d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c5c ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e5a ), + .Q(\blk00000003/sig00000ba5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c5b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b95 ), + .Q(\blk00000003/sig00000e5a ), + .Q15(\NLW_blk00000003/blk00000c5b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c5a ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e59 ), + .Q(\blk00000003/sig00000ba4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c59 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b94 ), + .Q(\blk00000003/sig00000e59 ), + .Q15(\NLW_blk00000003/blk00000c59_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c58 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e58 ), + .Q(\blk00000003/sig00000ba6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c57 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b96 ), + .Q(\blk00000003/sig00000e58 ), + .Q15(\NLW_blk00000003/blk00000c57_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c56 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e57 ), + .Q(\blk00000003/sig00000ba3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c55 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b93 ), + .Q(\blk00000003/sig00000e57 ), + .Q15(\NLW_blk00000003/blk00000c55_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c54 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e56 ), + .Q(\blk00000003/sig00000bb2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c53 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000ba2 ), + .Q(\blk00000003/sig00000e56 ), + .Q15(\NLW_blk00000003/blk00000c53_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c52 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e55 ), + .Q(\blk00000003/sig00000bb1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c51 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000ba1 ), + .Q(\blk00000003/sig00000e55 ), + .Q15(\NLW_blk00000003/blk00000c51_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c50 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e54 ), + .Q(\blk00000003/sig00000bb0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c4f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000ba0 ), + .Q(\blk00000003/sig00000e54 ), + .Q15(\NLW_blk00000003/blk00000c4f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c4e ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e53 ), + .Q(\blk00000003/sig00000baf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c4d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b9f ), + .Q(\blk00000003/sig00000e53 ), + .Q15(\NLW_blk00000003/blk00000c4d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c4c ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e52 ), + .Q(\blk00000003/sig00000bae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c4b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b9e ), + .Q(\blk00000003/sig00000e52 ), + .Q15(\NLW_blk00000003/blk00000c4b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c4a ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e51 ), + .Q(\blk00000003/sig00000bac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c49 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b9c ), + .Q(\blk00000003/sig00000e51 ), + .Q15(\NLW_blk00000003/blk00000c49_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c48 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e50 ), + .Q(\blk00000003/sig00000bab ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c47 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b9b ), + .Q(\blk00000003/sig00000e50 ), + .Q15(\NLW_blk00000003/blk00000c47_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c46 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e4f ), + .Q(\blk00000003/sig00000bad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c45 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b9d ), + .Q(\blk00000003/sig00000e4f ), + .Q15(\NLW_blk00000003/blk00000c45_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c44 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e4e ), + .Q(\blk00000003/sig00000aa6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c43 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a86 ), + .Q(\blk00000003/sig00000e4e ), + .Q15(\NLW_blk00000003/blk00000c43_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c42 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e4d ), + .Q(\blk00000003/sig00000aa4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c41 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a84 ), + .Q(\blk00000003/sig00000e4d ), + .Q15(\NLW_blk00000003/blk00000c41_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c40 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e4c ), + .Q(\blk00000003/sig00000aa3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c3f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a83 ), + .Q(\blk00000003/sig00000e4c ), + .Q15(\NLW_blk00000003/blk00000c3f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c3e ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e4b ), + .Q(\blk00000003/sig00000aa5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c3d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a85 ), + .Q(\blk00000003/sig00000e4b ), + .Q15(\NLW_blk00000003/blk00000c3d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c3c ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e4a ), + .Q(\blk00000003/sig00000aa2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c3b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a82 ), + .Q(\blk00000003/sig00000e4a ), + .Q15(\NLW_blk00000003/blk00000c3b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c3a ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e49 ), + .Q(\blk00000003/sig00000aa1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c39 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a81 ), + .Q(\blk00000003/sig00000e49 ), + .Q15(\NLW_blk00000003/blk00000c39_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c38 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e48 ), + .Q(\blk00000003/sig00000aa0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c37 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a80 ), + .Q(\blk00000003/sig00000e48 ), + .Q15(\NLW_blk00000003/blk00000c37_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c36 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e47 ), + .Q(\blk00000003/sig00000a9f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c35 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a7f ), + .Q(\blk00000003/sig00000e47 ), + .Q15(\NLW_blk00000003/blk00000c35_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c34 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e46 ), + .Q(\blk00000003/sig00000a9d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c33 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a7d ), + .Q(\blk00000003/sig00000e46 ), + .Q15(\NLW_blk00000003/blk00000c33_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c32 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e45 ), + .Q(\blk00000003/sig00000a9c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c31 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a7c ), + .Q(\blk00000003/sig00000e45 ), + .Q15(\NLW_blk00000003/blk00000c31_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c30 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e44 ), + .Q(\blk00000003/sig00000a9e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c2f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a7e ), + .Q(\blk00000003/sig00000e44 ), + .Q15(\NLW_blk00000003/blk00000c2f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c2e ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e43 ), + .Q(\blk00000003/sig00000a9b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c2d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a7b ), + .Q(\blk00000003/sig00000e43 ), + .Q15(\NLW_blk00000003/blk00000c2d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c2c ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e42 ), + .Q(\blk00000003/sig00000a9a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c2b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a7a ), + .Q(\blk00000003/sig00000e42 ), + .Q15(\NLW_blk00000003/blk00000c2b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c2a ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e41 ), + .Q(\blk00000003/sig00000a99 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c29 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a79 ), + .Q(\blk00000003/sig00000e41 ), + .Q15(\NLW_blk00000003/blk00000c29_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c28 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e40 ), + .Q(\blk00000003/sig00000a98 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c27 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a78 ), + .Q(\blk00000003/sig00000e40 ), + .Q15(\NLW_blk00000003/blk00000c27_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c26 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e3f ), + .Q(\blk00000003/sig00000a97 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c25 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a77 ), + .Q(\blk00000003/sig00000e3f ), + .Q15(\NLW_blk00000003/blk00000c25_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c24 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e3e ), + .Q(\blk00000003/sig00000ab6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c23 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a96 ), + .Q(\blk00000003/sig00000e3e ), + .Q15(\NLW_blk00000003/blk00000c23_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c22 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e3d ), + .Q(\blk00000003/sig00000ab5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c21 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a95 ), + .Q(\blk00000003/sig00000e3d ), + .Q15(\NLW_blk00000003/blk00000c21_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c20 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e3c ), + .Q(\blk00000003/sig00000ab4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c1f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a94 ), + .Q(\blk00000003/sig00000e3c ), + .Q15(\NLW_blk00000003/blk00000c1f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c1e ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e3b ), + .Q(\blk00000003/sig00000ab3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c1d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a93 ), + .Q(\blk00000003/sig00000e3b ), + .Q15(\NLW_blk00000003/blk00000c1d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c1c ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e3a ), + .Q(\blk00000003/sig00000ab2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c1b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a92 ), + .Q(\blk00000003/sig00000e3a ), + .Q15(\NLW_blk00000003/blk00000c1b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c1a ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e39 ), + .Q(\blk00000003/sig00000ab0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c19 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a90 ), + .Q(\blk00000003/sig00000e39 ), + .Q15(\NLW_blk00000003/blk00000c19_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c18 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e38 ), + .Q(\blk00000003/sig00000aaf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c17 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a8f ), + .Q(\blk00000003/sig00000e38 ), + .Q15(\NLW_blk00000003/blk00000c17_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c16 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e37 ), + .Q(\blk00000003/sig00000ab1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c15 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a91 ), + .Q(\blk00000003/sig00000e37 ), + .Q15(\NLW_blk00000003/blk00000c15_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c14 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e36 ), + .Q(\blk00000003/sig00000aae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c13 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a8e ), + .Q(\blk00000003/sig00000e36 ), + .Q15(\NLW_blk00000003/blk00000c13_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c12 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e35 ), + .Q(\blk00000003/sig00000aad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c11 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a8d ), + .Q(\blk00000003/sig00000e35 ), + .Q15(\NLW_blk00000003/blk00000c11_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c10 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e34 ), + .Q(\blk00000003/sig00000aac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c0f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a8c ), + .Q(\blk00000003/sig00000e34 ), + .Q15(\NLW_blk00000003/blk00000c0f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c0e ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e33 ), + .Q(\blk00000003/sig00000aab ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c0d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a8b ), + .Q(\blk00000003/sig00000e33 ), + .Q15(\NLW_blk00000003/blk00000c0d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c0c ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e32 ), + .Q(\blk00000003/sig00000aa9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c0b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a89 ), + .Q(\blk00000003/sig00000e32 ), + .Q15(\NLW_blk00000003/blk00000c0b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c0a ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e31 ), + .Q(\blk00000003/sig00000aa8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c09 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a88 ), + .Q(\blk00000003/sig00000e31 ), + .Q15(\NLW_blk00000003/blk00000c09_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c08 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e30 ), + .Q(\blk00000003/sig00000aaa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c07 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a8a ), + .Q(\blk00000003/sig00000e30 ), + .Q15(\NLW_blk00000003/blk00000c07_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c06 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e2f ), + .Q(\blk00000003/sig00000aa7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c05 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a87 ), + .Q(\blk00000003/sig00000e2f ), + .Q15(\NLW_blk00000003/blk00000c05_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c04 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000e2e ), + .Q(\blk00000003/sig00000c61 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c03 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a16 ), + .Q(\blk00000003/sig00000e2e ), + .Q15(\NLW_blk00000003/blk00000c03_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c02 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e2d ), + .Q(\blk00000003/sig00000b9a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c01 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b8a ), + .Q(\blk00000003/sig00000e2d ), + .Q15(\NLW_blk00000003/blk00000c01_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c00 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e2c ), + .Q(\blk00000003/sig00000b99 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bff ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b89 ), + .Q(\blk00000003/sig00000e2c ), + .Q15(\NLW_blk00000003/blk00000bff_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bfe ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e2b ), + .Q(\blk00000003/sig00000b97 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bfd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b87 ), + .Q(\blk00000003/sig00000e2b ), + .Q15(\NLW_blk00000003/blk00000bfd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bfc ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e2a ), + .Q(\blk00000003/sig00000b96 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bfb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b86 ), + .Q(\blk00000003/sig00000e2a ), + .Q15(\NLW_blk00000003/blk00000bfb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bfa ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e29 ), + .Q(\blk00000003/sig00000b98 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b88 ), + .Q(\blk00000003/sig00000e29 ), + .Q15(\NLW_blk00000003/blk00000bf9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf8 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e28 ), + .Q(\blk00000003/sig00000b95 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b85 ), + .Q(\blk00000003/sig00000e28 ), + .Q15(\NLW_blk00000003/blk00000bf7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf6 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e27 ), + .Q(\blk00000003/sig00000b94 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b84 ), + .Q(\blk00000003/sig00000e27 ), + .Q15(\NLW_blk00000003/blk00000bf5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf4 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e26 ), + .Q(\blk00000003/sig00000b93 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b83 ), + .Q(\blk00000003/sig00000e26 ), + .Q15(\NLW_blk00000003/blk00000bf3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf2 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e25 ), + .Q(\blk00000003/sig00000ba2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b92 ), + .Q(\blk00000003/sig00000e25 ), + .Q15(\NLW_blk00000003/blk00000bf1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf0 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e24 ), + .Q(\blk00000003/sig00000ba1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bef ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b91 ), + .Q(\blk00000003/sig00000e24 ), + .Q15(\NLW_blk00000003/blk00000bef_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bee ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e23 ), + .Q(\blk00000003/sig00000ba0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bed ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b90 ), + .Q(\blk00000003/sig00000e23 ), + .Q15(\NLW_blk00000003/blk00000bed_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bec ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e22 ), + .Q(\blk00000003/sig00000b9f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000beb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b8f ), + .Q(\blk00000003/sig00000e22 ), + .Q15(\NLW_blk00000003/blk00000beb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bea ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e21 ), + .Q(\blk00000003/sig00000b9d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b8d ), + .Q(\blk00000003/sig00000e21 ), + .Q15(\NLW_blk00000003/blk00000be9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be8 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e20 ), + .Q(\blk00000003/sig00000b9c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b8c ), + .Q(\blk00000003/sig00000e20 ), + .Q15(\NLW_blk00000003/blk00000be7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be6 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e1f ), + .Q(\blk00000003/sig00000b9e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b8e ), + .Q(\blk00000003/sig00000e1f ), + .Q15(\NLW_blk00000003/blk00000be5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be4 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e1e ), + .Q(\blk00000003/sig00000b9b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b8b ), + .Q(\blk00000003/sig00000e1e ), + .Q15(\NLW_blk00000003/blk00000be3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be2 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e1d ), + .Q(\blk00000003/sig00000a86 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a66 ), + .Q(\blk00000003/sig00000e1d ), + .Q15(\NLW_blk00000003/blk00000be1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be0 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e1c ), + .Q(\blk00000003/sig00000a85 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bdf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a65 ), + .Q(\blk00000003/sig00000e1c ), + .Q15(\NLW_blk00000003/blk00000bdf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bde ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e1b ), + .Q(\blk00000003/sig00000a84 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bdd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a64 ), + .Q(\blk00000003/sig00000e1b ), + .Q15(\NLW_blk00000003/blk00000bdd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bdc ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e1a ), + .Q(\blk00000003/sig00000a83 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bdb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a63 ), + .Q(\blk00000003/sig00000e1a ), + .Q15(\NLW_blk00000003/blk00000bdb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bda ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e19 ), + .Q(\blk00000003/sig00000a82 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a62 ), + .Q(\blk00000003/sig00000e19 ), + .Q15(\NLW_blk00000003/blk00000bd9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd8 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e18 ), + .Q(\blk00000003/sig00000a81 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a61 ), + .Q(\blk00000003/sig00000e18 ), + .Q15(\NLW_blk00000003/blk00000bd7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd6 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e17 ), + .Q(\blk00000003/sig00000a7f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a5f ), + .Q(\blk00000003/sig00000e17 ), + .Q15(\NLW_blk00000003/blk00000bd5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd4 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e16 ), + .Q(\blk00000003/sig00000a7e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a5e ), + .Q(\blk00000003/sig00000e16 ), + .Q15(\NLW_blk00000003/blk00000bd3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd2 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e15 ), + .Q(\blk00000003/sig00000a80 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a60 ), + .Q(\blk00000003/sig00000e15 ), + .Q15(\NLW_blk00000003/blk00000bd1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd0 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e14 ), + .Q(\blk00000003/sig00000a7d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bcf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a5d ), + .Q(\blk00000003/sig00000e14 ), + .Q15(\NLW_blk00000003/blk00000bcf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bce ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e13 ), + .Q(\blk00000003/sig00000a7c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bcd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a5c ), + .Q(\blk00000003/sig00000e13 ), + .Q15(\NLW_blk00000003/blk00000bcd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bcc ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e12 ), + .Q(\blk00000003/sig00000a7b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bcb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a5b ), + .Q(\blk00000003/sig00000e12 ), + .Q15(\NLW_blk00000003/blk00000bcb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bca ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e11 ), + .Q(\blk00000003/sig00000a7a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a5a ), + .Q(\blk00000003/sig00000e11 ), + .Q15(\NLW_blk00000003/blk00000bc9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc8 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e10 ), + .Q(\blk00000003/sig00000a78 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a58 ), + .Q(\blk00000003/sig00000e10 ), + .Q15(\NLW_blk00000003/blk00000bc7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc6 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e0f ), + .Q(\blk00000003/sig00000a77 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a57 ), + .Q(\blk00000003/sig00000e0f ), + .Q15(\NLW_blk00000003/blk00000bc5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc4 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e0e ), + .Q(\blk00000003/sig00000a79 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a59 ), + .Q(\blk00000003/sig00000e0e ), + .Q15(\NLW_blk00000003/blk00000bc3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc2 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e0d ), + .Q(\blk00000003/sig00000a96 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a76 ), + .Q(\blk00000003/sig00000e0d ), + .Q15(\NLW_blk00000003/blk00000bc1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc0 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e0c ), + .Q(\blk00000003/sig00000a95 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bbf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a75 ), + .Q(\blk00000003/sig00000e0c ), + .Q15(\NLW_blk00000003/blk00000bbf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bbe ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e0b ), + .Q(\blk00000003/sig00000a94 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bbd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a74 ), + .Q(\blk00000003/sig00000e0b ), + .Q15(\NLW_blk00000003/blk00000bbd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bbc ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e0a ), + .Q(\blk00000003/sig00000a92 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bbb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a72 ), + .Q(\blk00000003/sig00000e0a ), + .Q15(\NLW_blk00000003/blk00000bbb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bba ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e09 ), + .Q(\blk00000003/sig00000a91 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a71 ), + .Q(\blk00000003/sig00000e09 ), + .Q15(\NLW_blk00000003/blk00000bb9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb8 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e08 ), + .Q(\blk00000003/sig00000a93 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a73 ), + .Q(\blk00000003/sig00000e08 ), + .Q15(\NLW_blk00000003/blk00000bb7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb6 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e07 ), + .Q(\blk00000003/sig00000a90 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a70 ), + .Q(\blk00000003/sig00000e07 ), + .Q15(\NLW_blk00000003/blk00000bb5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb4 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e06 ), + .Q(\blk00000003/sig00000a8f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a6f ), + .Q(\blk00000003/sig00000e06 ), + .Q15(\NLW_blk00000003/blk00000bb3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb2 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e05 ), + .Q(\blk00000003/sig00000a8e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a6e ), + .Q(\blk00000003/sig00000e05 ), + .Q15(\NLW_blk00000003/blk00000bb1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb0 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e04 ), + .Q(\blk00000003/sig00000a8d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000baf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a6d ), + .Q(\blk00000003/sig00000e04 ), + .Q15(\NLW_blk00000003/blk00000baf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bae ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e03 ), + .Q(\blk00000003/sig00000a8b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bad ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a6b ), + .Q(\blk00000003/sig00000e03 ), + .Q15(\NLW_blk00000003/blk00000bad_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bac ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e02 ), + .Q(\blk00000003/sig00000a8a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bab ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a6a ), + .Q(\blk00000003/sig00000e02 ), + .Q15(\NLW_blk00000003/blk00000bab_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000baa ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e01 ), + .Q(\blk00000003/sig00000a8c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a6c ), + .Q(\blk00000003/sig00000e01 ), + .Q15(\NLW_blk00000003/blk00000ba9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba8 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e00 ), + .Q(\blk00000003/sig00000a88 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a68 ), + .Q(\blk00000003/sig00000e00 ), + .Q15(\NLW_blk00000003/blk00000ba7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba6 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000dff ), + .Q(\blk00000003/sig00000a87 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a67 ), + .Q(\blk00000003/sig00000dff ), + .Q15(\NLW_blk00000003/blk00000ba5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba4 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000dfe ), + .Q(\blk00000003/sig00000a89 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a69 ), + .Q(\blk00000003/sig00000dfe ), + .Q15(\NLW_blk00000003/blk00000ba3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dfd ), + .Q(\blk00000003/sig000002ad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba1 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a15 ), + .Q(\blk00000003/sig00000dfd ), + .Q15(\NLW_blk00000003/blk00000ba1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dfc ), + .Q(\blk00000003/sig00000258 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b9f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d98 ), + .Q(\blk00000003/sig00000dfc ), + .Q15(\NLW_blk00000003/blk00000b9f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b9e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dfb ), + .Q(\blk00000003/sig00000257 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b9d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d96 ), + .Q(\blk00000003/sig00000dfb ), + .Q15(\NLW_blk00000003/blk00000b9d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b9c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dfa ), + .Q(\blk00000003/sig00000259 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b9b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d9a ), + .Q(\blk00000003/sig00000dfa ), + .Q15(\NLW_blk00000003/blk00000b9b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b9a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df9 ), + .Q(\blk00000003/sig00000255 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b99 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d8e ), + .Q(\blk00000003/sig00000df9 ), + .Q15(\NLW_blk00000003/blk00000b99_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b98 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df8 ), + .Q(\blk00000003/sig00000254 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b97 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d92 ), + .Q(\blk00000003/sig00000df8 ), + .Q15(\NLW_blk00000003/blk00000b97_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b96 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df7 ), + .Q(\blk00000003/sig00000256 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b95 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d94 ), + .Q(\blk00000003/sig00000df7 ), + .Q15(\NLW_blk00000003/blk00000b95_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b94 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df6 ), + .Q(\blk00000003/sig00000253 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b93 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d90 ), + .Q(\blk00000003/sig00000df6 ), + .Q15(\NLW_blk00000003/blk00000b93_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b92 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df5 ), + .Q(\blk00000003/sig00000252 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b91 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d8c ), + .Q(\blk00000003/sig00000df5 ), + .Q15(\NLW_blk00000003/blk00000b91_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b90 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df4 ), + .Q(\blk00000003/sig00000251 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b8f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d8a ), + .Q(\blk00000003/sig00000df4 ), + .Q15(\NLW_blk00000003/blk00000b8f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b8e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df3 ), + .Q(\blk00000003/sig00000250 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b8d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d88 ), + .Q(\blk00000003/sig00000df3 ), + .Q15(\NLW_blk00000003/blk00000b8d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b8c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df2 ), + .Q(\blk00000003/sig0000024e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b8b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d80 ), + .Q(\blk00000003/sig00000df2 ), + .Q15(\NLW_blk00000003/blk00000b8b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b8a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df1 ), + .Q(\blk00000003/sig0000024d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b89 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d84 ), + .Q(\blk00000003/sig00000df1 ), + .Q15(\NLW_blk00000003/blk00000b89_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b88 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df0 ), + .Q(\blk00000003/sig0000024f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b87 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d86 ), + .Q(\blk00000003/sig00000df0 ), + .Q15(\NLW_blk00000003/blk00000b87_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b86 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000def ), + .Q(\blk00000003/sig0000024c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b85 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d82 ), + .Q(\blk00000003/sig00000def ), + .Q15(\NLW_blk00000003/blk00000b85_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b84 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dee ), + .Q(\blk00000003/sig0000024b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b83 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d7e ), + .Q(\blk00000003/sig00000dee ), + .Q15(\NLW_blk00000003/blk00000b83_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b82 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ded ), + .Q(\blk00000003/sig0000024a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b81 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d7c ), + .Q(\blk00000003/sig00000ded ), + .Q15(\NLW_blk00000003/blk00000b81_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b80 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dec ), + .Q(\blk00000003/sig00000219 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b7f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d7a ), + .Q(\blk00000003/sig00000dec ), + .Q15(\NLW_blk00000003/blk00000b7f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b7e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000deb ), + .Q(\blk00000003/sig00000217 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b7d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d72 ), + .Q(\blk00000003/sig00000deb ), + .Q15(\NLW_blk00000003/blk00000b7d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b7c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dea ), + .Q(\blk00000003/sig00000216 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b7b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d76 ), + .Q(\blk00000003/sig00000dea ), + .Q15(\NLW_blk00000003/blk00000b7b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b7a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de9 ), + .Q(\blk00000003/sig00000218 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b79 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d78 ), + .Q(\blk00000003/sig00000de9 ), + .Q15(\NLW_blk00000003/blk00000b79_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b78 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de8 ), + .Q(\blk00000003/sig00000215 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b77 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d74 ), + .Q(\blk00000003/sig00000de8 ), + .Q15(\NLW_blk00000003/blk00000b77_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b76 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de7 ), + .Q(\blk00000003/sig00000214 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b75 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d70 ), + .Q(\blk00000003/sig00000de7 ), + .Q15(\NLW_blk00000003/blk00000b75_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b74 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de6 ), + .Q(\blk00000003/sig00000213 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b73 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d6e ), + .Q(\blk00000003/sig00000de6 ), + .Q15(\NLW_blk00000003/blk00000b73_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b72 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de5 ), + .Q(\blk00000003/sig00000212 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b71 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d6c ), + .Q(\blk00000003/sig00000de5 ), + .Q15(\NLW_blk00000003/blk00000b71_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b70 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de4 ), + .Q(\blk00000003/sig000001d0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b6f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d64 ), + .Q(\blk00000003/sig00000de4 ), + .Q15(\NLW_blk00000003/blk00000b6f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b6e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de3 ), + .Q(\blk00000003/sig000001cf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b6d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d68 ), + .Q(\blk00000003/sig00000de3 ), + .Q15(\NLW_blk00000003/blk00000b6d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b6c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de2 ), + .Q(\blk00000003/sig000001d1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b6b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d6a ), + .Q(\blk00000003/sig00000de2 ), + .Q15(\NLW_blk00000003/blk00000b6b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b6a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de1 ), + .Q(\blk00000003/sig000001ce ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b69 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d66 ), + .Q(\blk00000003/sig00000de1 ), + .Q15(\NLW_blk00000003/blk00000b69_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b68 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de0 ), + .Q(\blk00000003/sig000001cd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b67 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d62 ), + .Q(\blk00000003/sig00000de0 ), + .Q15(\NLW_blk00000003/blk00000b67_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b66 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ddf ), + .Q(\blk00000003/sig000001cc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b65 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d60 ), + .Q(\blk00000003/sig00000ddf ), + .Q15(\NLW_blk00000003/blk00000b65_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b64 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dde ), + .Q(\blk00000003/sig000001cb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b63 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d5e ), + .Q(\blk00000003/sig00000dde ), + .Q15(\NLW_blk00000003/blk00000b63_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b62 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ddd ), + .Q(\blk00000003/sig000001c9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b61 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d56 ), + .Q(\blk00000003/sig00000ddd ), + .Q15(\NLW_blk00000003/blk00000b61_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b60 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ddc ), + .Q(\blk00000003/sig000001c8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b5f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d5a ), + .Q(\blk00000003/sig00000ddc ), + .Q15(\NLW_blk00000003/blk00000b5f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b5e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ddb ), + .Q(\blk00000003/sig000001ca ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b5d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d5c ), + .Q(\blk00000003/sig00000ddb ), + .Q15(\NLW_blk00000003/blk00000b5d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b5c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dda ), + .Q(\blk00000003/sig000001c7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b5b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d58 ), + .Q(\blk00000003/sig00000dda ), + .Q15(\NLW_blk00000003/blk00000b5b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b5a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd9 ), + .Q(\blk00000003/sig000001c6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b59 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d54 ), + .Q(\blk00000003/sig00000dd9 ), + .Q15(\NLW_blk00000003/blk00000b59_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b58 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd8 ), + .Q(\blk00000003/sig000001c5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b57 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d52 ), + .Q(\blk00000003/sig00000dd8 ), + .Q15(\NLW_blk00000003/blk00000b57_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b56 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd7 ), + .Q(\blk00000003/sig000001c4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b55 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d50 ), + .Q(\blk00000003/sig00000dd7 ), + .Q15(\NLW_blk00000003/blk00000b55_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b54 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd6 ), + .Q(\blk00000003/sig000001c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b53 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d48 ), + .Q(\blk00000003/sig00000dd6 ), + .Q15(\NLW_blk00000003/blk00000b53_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b52 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd5 ), + .Q(\blk00000003/sig0000017f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b51 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d4c ), + .Q(\blk00000003/sig00000dd5 ), + .Q15(\NLW_blk00000003/blk00000b51_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b50 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd4 ), + .Q(\blk00000003/sig000001c3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b4f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d4e ), + .Q(\blk00000003/sig00000dd4 ), + .Q15(\NLW_blk00000003/blk00000b4f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b4e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd3 ), + .Q(\blk00000003/sig0000017e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b4d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d4a ), + .Q(\blk00000003/sig00000dd3 ), + .Q15(\NLW_blk00000003/blk00000b4d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b4c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd2 ), + .Q(\blk00000003/sig0000017d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b4b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d46 ), + .Q(\blk00000003/sig00000dd2 ), + .Q15(\NLW_blk00000003/blk00000b4b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b4a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd1 ), + .Q(\blk00000003/sig0000017c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b49 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d44 ), + .Q(\blk00000003/sig00000dd1 ), + .Q15(\NLW_blk00000003/blk00000b49_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b48 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd0 ), + .Q(\blk00000003/sig0000017b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b47 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d42 ), + .Q(\blk00000003/sig00000dd0 ), + .Q15(\NLW_blk00000003/blk00000b47_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b46 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dcf ), + .Q(\blk00000003/sig00000179 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b45 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d3c ), + .Q(\blk00000003/sig00000dcf ), + .Q15(\NLW_blk00000003/blk00000b45_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b44 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dce ), + .Q(\blk00000003/sig00000178 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b43 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d3e ), + .Q(\blk00000003/sig00000dce ), + .Q15(\NLW_blk00000003/blk00000b43_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b42 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dcd ), + .Q(\blk00000003/sig0000017a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b41 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d40 ), + .Q(\blk00000003/sig00000dcd ), + .Q15(\NLW_blk00000003/blk00000b41_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b40 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dcc ), + .Q(\blk00000003/sig00000b8a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b3f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b7a ), + .Q(\blk00000003/sig00000dcc ), + .Q15(\NLW_blk00000003/blk00000b3f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b3e ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dcb ), + .Q(\blk00000003/sig00000b88 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b3d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b78 ), + .Q(\blk00000003/sig00000dcb ), + .Q15(\NLW_blk00000003/blk00000b3d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b3c ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dca ), + .Q(\blk00000003/sig00000b87 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b3b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b77 ), + .Q(\blk00000003/sig00000dca ), + .Q15(\NLW_blk00000003/blk00000b3b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b3a ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc9 ), + .Q(\blk00000003/sig00000b89 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b39 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b79 ), + .Q(\blk00000003/sig00000dc9 ), + .Q15(\NLW_blk00000003/blk00000b39_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b38 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc8 ), + .Q(\blk00000003/sig00000b86 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b37 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b76 ), + .Q(\blk00000003/sig00000dc8 ), + .Q15(\NLW_blk00000003/blk00000b37_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b36 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc7 ), + .Q(\blk00000003/sig00000b85 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b35 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b75 ), + .Q(\blk00000003/sig00000dc7 ), + .Q15(\NLW_blk00000003/blk00000b35_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b34 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc6 ), + .Q(\blk00000003/sig00000b84 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b33 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b74 ), + .Q(\blk00000003/sig00000dc6 ), + .Q15(\NLW_blk00000003/blk00000b33_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b32 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc5 ), + .Q(\blk00000003/sig00000b83 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b31 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b73 ), + .Q(\blk00000003/sig00000dc5 ), + .Q15(\NLW_blk00000003/blk00000b31_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b30 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc4 ), + .Q(\blk00000003/sig00000b92 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b2f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b82 ), + .Q(\blk00000003/sig00000dc4 ), + .Q15(\NLW_blk00000003/blk00000b2f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b2e ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc3 ), + .Q(\blk00000003/sig00000b91 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b2d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b81 ), + .Q(\blk00000003/sig00000dc3 ), + .Q15(\NLW_blk00000003/blk00000b2d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b2c ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc2 ), + .Q(\blk00000003/sig00000b90 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b2b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b80 ), + .Q(\blk00000003/sig00000dc2 ), + .Q15(\NLW_blk00000003/blk00000b2b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b2a ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc1 ), + .Q(\blk00000003/sig00000b8e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b29 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b7e ), + .Q(\blk00000003/sig00000dc1 ), + .Q15(\NLW_blk00000003/blk00000b29_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b28 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc0 ), + .Q(\blk00000003/sig00000b8d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b27 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b7d ), + .Q(\blk00000003/sig00000dc0 ), + .Q15(\NLW_blk00000003/blk00000b27_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b26 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dbf ), + .Q(\blk00000003/sig00000b8f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b25 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b7f ), + .Q(\blk00000003/sig00000dbf ), + .Q15(\NLW_blk00000003/blk00000b25_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b24 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dbe ), + .Q(\blk00000003/sig00000b8c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b23 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b7c ), + .Q(\blk00000003/sig00000dbe ), + .Q15(\NLW_blk00000003/blk00000b23_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b22 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dbd ), + .Q(\blk00000003/sig00000b8b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b21 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b7b ), + .Q(\blk00000003/sig00000dbd ), + .Q15(\NLW_blk00000003/blk00000b21_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b20 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000dbc ), + .Q(\blk00000003/sig00000a66 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b1f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a46 ), + .Q(\blk00000003/sig00000dbc ), + .Q15(\NLW_blk00000003/blk00000b1f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b1e ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000dbb ), + .Q(\blk00000003/sig00000a65 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b1d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a45 ), + .Q(\blk00000003/sig00000dbb ), + .Q15(\NLW_blk00000003/blk00000b1d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b1c ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000dba ), + .Q(\blk00000003/sig00000a64 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b1b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a44 ), + .Q(\blk00000003/sig00000dba ), + .Q15(\NLW_blk00000003/blk00000b1b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b1a ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db9 ), + .Q(\blk00000003/sig00000a63 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b19 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a43 ), + .Q(\blk00000003/sig00000db9 ), + .Q15(\NLW_blk00000003/blk00000b19_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b18 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db8 ), + .Q(\blk00000003/sig00000a61 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b17 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a41 ), + .Q(\blk00000003/sig00000db8 ), + .Q15(\NLW_blk00000003/blk00000b17_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b16 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db7 ), + .Q(\blk00000003/sig00000a60 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b15 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a40 ), + .Q(\blk00000003/sig00000db7 ), + .Q15(\NLW_blk00000003/blk00000b15_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b14 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db6 ), + .Q(\blk00000003/sig00000a62 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b13 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a42 ), + .Q(\blk00000003/sig00000db6 ), + .Q15(\NLW_blk00000003/blk00000b13_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b12 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db5 ), + .Q(\blk00000003/sig00000a5f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b11 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a3f ), + .Q(\blk00000003/sig00000db5 ), + .Q15(\NLW_blk00000003/blk00000b11_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b10 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db4 ), + .Q(\blk00000003/sig00000a5e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b0f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a3e ), + .Q(\blk00000003/sig00000db4 ), + .Q15(\NLW_blk00000003/blk00000b0f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b0e ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db3 ), + .Q(\blk00000003/sig00000a5d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b0d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a3d ), + .Q(\blk00000003/sig00000db3 ), + .Q15(\NLW_blk00000003/blk00000b0d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b0c ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db2 ), + .Q(\blk00000003/sig00000a5c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b0b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a3c ), + .Q(\blk00000003/sig00000db2 ), + .Q15(\NLW_blk00000003/blk00000b0b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b0a ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db1 ), + .Q(\blk00000003/sig00000a5a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b09 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a3a ), + .Q(\blk00000003/sig00000db1 ), + .Q15(\NLW_blk00000003/blk00000b09_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b08 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db0 ), + .Q(\blk00000003/sig00000a59 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b07 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a39 ), + .Q(\blk00000003/sig00000db0 ), + .Q15(\NLW_blk00000003/blk00000b07_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b06 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000daf ), + .Q(\blk00000003/sig00000a5b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b05 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a3b ), + .Q(\blk00000003/sig00000daf ), + .Q15(\NLW_blk00000003/blk00000b05_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b04 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000dae ), + .Q(\blk00000003/sig00000a58 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b03 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a38 ), + .Q(\blk00000003/sig00000dae ), + .Q15(\NLW_blk00000003/blk00000b03_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b02 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000dad ), + .Q(\blk00000003/sig00000a57 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b01 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a37 ), + .Q(\blk00000003/sig00000dad ), + .Q15(\NLW_blk00000003/blk00000b01_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b00 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000dac ), + .Q(\blk00000003/sig00000a75 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aff ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a55 ), + .Q(\blk00000003/sig00000dac ), + .Q15(\NLW_blk00000003/blk00000aff_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000afe ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000dab ), + .Q(\blk00000003/sig00000a74 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000afd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a54 ), + .Q(\blk00000003/sig00000dab ), + .Q15(\NLW_blk00000003/blk00000afd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000afc ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000daa ), + .Q(\blk00000003/sig00000a76 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000afb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a56 ), + .Q(\blk00000003/sig00000daa ), + .Q15(\NLW_blk00000003/blk00000afb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000afa ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da9 ), + .Q(\blk00000003/sig00000a73 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a53 ), + .Q(\blk00000003/sig00000da9 ), + .Q15(\NLW_blk00000003/blk00000af9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af8 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da8 ), + .Q(\blk00000003/sig00000a72 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a52 ), + .Q(\blk00000003/sig00000da8 ), + .Q15(\NLW_blk00000003/blk00000af7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af6 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da7 ), + .Q(\blk00000003/sig00000a71 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a51 ), + .Q(\blk00000003/sig00000da7 ), + .Q15(\NLW_blk00000003/blk00000af5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af4 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da6 ), + .Q(\blk00000003/sig00000a70 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a50 ), + .Q(\blk00000003/sig00000da6 ), + .Q15(\NLW_blk00000003/blk00000af3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af2 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da5 ), + .Q(\blk00000003/sig00000a6e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a4e ), + .Q(\blk00000003/sig00000da5 ), + .Q15(\NLW_blk00000003/blk00000af1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af0 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da4 ), + .Q(\blk00000003/sig00000a6d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aef ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a4d ), + .Q(\blk00000003/sig00000da4 ), + .Q15(\NLW_blk00000003/blk00000aef_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aee ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da3 ), + .Q(\blk00000003/sig00000a6f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aed ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a4f ), + .Q(\blk00000003/sig00000da3 ), + .Q15(\NLW_blk00000003/blk00000aed_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aec ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da2 ), + .Q(\blk00000003/sig00000a6c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aeb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a4c ), + .Q(\blk00000003/sig00000da2 ), + .Q15(\NLW_blk00000003/blk00000aeb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aea ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da1 ), + .Q(\blk00000003/sig00000a6b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a4b ), + .Q(\blk00000003/sig00000da1 ), + .Q15(\NLW_blk00000003/blk00000ae9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae8 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da0 ), + .Q(\blk00000003/sig00000a6a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a4a ), + .Q(\blk00000003/sig00000da0 ), + .Q15(\NLW_blk00000003/blk00000ae7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae6 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000d9f ), + .Q(\blk00000003/sig00000a69 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a49 ), + .Q(\blk00000003/sig00000d9f ), + .Q15(\NLW_blk00000003/blk00000ae5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae4 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000d9e ), + .Q(\blk00000003/sig00000a67 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a47 ), + .Q(\blk00000003/sig00000d9e ), + .Q15(\NLW_blk00000003/blk00000ae3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae2 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000d9d ), + .Q(\blk00000003/sig00000a68 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a48 ), + .Q(\blk00000003/sig00000d9d ), + .Q15(\NLW_blk00000003/blk00000ae1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d9c ), + .Q(\blk00000003/sig00000a16 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000adf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002af ), + .Q(\blk00000003/sig00000d9c ), + .Q15(\NLW_blk00000003/blk00000adf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ade ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d9b ), + .Q(\blk00000003/sig00000c62 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000add ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(NlwRenamedSig_OI_rfd), + .A3(NlwRenamedSig_OI_rfd), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000029c ), + .Q(\blk00000003/sig00000d9b ), + .Q15(\NLW_blk00000003/blk00000add_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000adc ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d99 ), + .Q(\blk00000003/sig00000d9a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000adb ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002ea ), + .Q(\blk00000003/sig00000d99 ), + .Q15(\NLW_blk00000003/blk00000adb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ada ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d97 ), + .Q(\blk00000003/sig00000d98 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad9 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e9 ), + .Q(\blk00000003/sig00000d97 ), + .Q15(\NLW_blk00000003/blk00000ad9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad8 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d95 ), + .Q(\blk00000003/sig00000d96 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad7 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e8 ), + .Q(\blk00000003/sig00000d95 ), + .Q15(\NLW_blk00000003/blk00000ad7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad6 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d93 ), + .Q(\blk00000003/sig00000d94 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad5 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e7 ), + .Q(\blk00000003/sig00000d93 ), + .Q15(\NLW_blk00000003/blk00000ad5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad4 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d91 ), + .Q(\blk00000003/sig00000d92 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad3 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e5 ), + .Q(\blk00000003/sig00000d91 ), + .Q15(\NLW_blk00000003/blk00000ad3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad2 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d8f ), + .Q(\blk00000003/sig00000d90 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad1 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e4 ), + .Q(\blk00000003/sig00000d8f ), + .Q15(\NLW_blk00000003/blk00000ad1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad0 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d8d ), + .Q(\blk00000003/sig00000d8e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000acf ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e6 ), + .Q(\blk00000003/sig00000d8d ), + .Q15(\NLW_blk00000003/blk00000acf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ace ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d8b ), + .Q(\blk00000003/sig00000d8c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000acd ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e3 ), + .Q(\blk00000003/sig00000d8b ), + .Q15(\NLW_blk00000003/blk00000acd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000acc ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d89 ), + .Q(\blk00000003/sig00000d8a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000acb ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e2 ), + .Q(\blk00000003/sig00000d89 ), + .Q15(\NLW_blk00000003/blk00000acb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aca ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d87 ), + .Q(\blk00000003/sig00000d88 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac9 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e1 ), + .Q(\blk00000003/sig00000d87 ), + .Q15(\NLW_blk00000003/blk00000ac9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac8 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d85 ), + .Q(\blk00000003/sig00000d86 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac7 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e0 ), + .Q(\blk00000003/sig00000d85 ), + .Q15(\NLW_blk00000003/blk00000ac7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac6 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d83 ), + .Q(\blk00000003/sig00000d84 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac5 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002de ), + .Q(\blk00000003/sig00000d83 ), + .Q15(\NLW_blk00000003/blk00000ac5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac4 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d81 ), + .Q(\blk00000003/sig00000d82 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac3 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002dd ), + .Q(\blk00000003/sig00000d81 ), + .Q15(\NLW_blk00000003/blk00000ac3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac2 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d7f ), + .Q(\blk00000003/sig00000d80 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac1 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002df ), + .Q(\blk00000003/sig00000d7f ), + .Q15(\NLW_blk00000003/blk00000ac1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac0 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d7d ), + .Q(\blk00000003/sig00000d7e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000abf ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002dc ), + .Q(\blk00000003/sig00000d7d ), + .Q15(\NLW_blk00000003/blk00000abf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abe ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d7b ), + .Q(\blk00000003/sig00000d7c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000abd ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002db ), + .Q(\blk00000003/sig00000d7b ), + .Q15(\NLW_blk00000003/blk00000abd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abc ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d79 ), + .Q(\blk00000003/sig00000d7a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000abb ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002da ), + .Q(\blk00000003/sig00000d79 ), + .Q15(\NLW_blk00000003/blk00000abb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aba ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d77 ), + .Q(\blk00000003/sig00000d78 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab9 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d9 ), + .Q(\blk00000003/sig00000d77 ), + .Q15(\NLW_blk00000003/blk00000ab9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab8 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d75 ), + .Q(\blk00000003/sig00000d76 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab7 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d7 ), + .Q(\blk00000003/sig00000d75 ), + .Q15(\NLW_blk00000003/blk00000ab7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab6 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d73 ), + .Q(\blk00000003/sig00000d74 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab5 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d6 ), + .Q(\blk00000003/sig00000d73 ), + .Q15(\NLW_blk00000003/blk00000ab5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab4 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d71 ), + .Q(\blk00000003/sig00000d72 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab3 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d8 ), + .Q(\blk00000003/sig00000d71 ), + .Q15(\NLW_blk00000003/blk00000ab3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab2 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d6f ), + .Q(\blk00000003/sig00000d70 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab1 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d5 ), + .Q(\blk00000003/sig00000d6f ), + .Q15(\NLW_blk00000003/blk00000ab1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab0 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d6d ), + .Q(\blk00000003/sig00000d6e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aaf ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d4 ), + .Q(\blk00000003/sig00000d6d ), + .Q15(\NLW_blk00000003/blk00000aaf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aae ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d6b ), + .Q(\blk00000003/sig00000d6c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aad ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d3 ), + .Q(\blk00000003/sig00000d6b ), + .Q15(\NLW_blk00000003/blk00000aad_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aac ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d69 ), + .Q(\blk00000003/sig00000d6a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aab ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d2 ), + .Q(\blk00000003/sig00000d69 ), + .Q15(\NLW_blk00000003/blk00000aab_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aaa ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d67 ), + .Q(\blk00000003/sig00000d68 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa9 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d0 ), + .Q(\blk00000003/sig00000d67 ), + .Q15(\NLW_blk00000003/blk00000aa9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa8 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d65 ), + .Q(\blk00000003/sig00000d66 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa7 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002cf ), + .Q(\blk00000003/sig00000d65 ), + .Q15(\NLW_blk00000003/blk00000aa7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa6 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d63 ), + .Q(\blk00000003/sig00000d64 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa5 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d1 ), + .Q(\blk00000003/sig00000d63 ), + .Q15(\NLW_blk00000003/blk00000aa5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa4 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d61 ), + .Q(\blk00000003/sig00000d62 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa3 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002ce ), + .Q(\blk00000003/sig00000d61 ), + .Q15(\NLW_blk00000003/blk00000aa3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa2 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d5f ), + .Q(\blk00000003/sig00000d60 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa1 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002cd ), + .Q(\blk00000003/sig00000d5f ), + .Q15(\NLW_blk00000003/blk00000aa1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa0 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d5d ), + .Q(\blk00000003/sig00000d5e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a9f ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002cc ), + .Q(\blk00000003/sig00000d5d ), + .Q15(\NLW_blk00000003/blk00000a9f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a9e ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d5b ), + .Q(\blk00000003/sig00000d5c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a9d ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002cb ), + .Q(\blk00000003/sig00000d5b ), + .Q15(\NLW_blk00000003/blk00000a9d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a9c ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d59 ), + .Q(\blk00000003/sig00000d5a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a9b ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c9 ), + .Q(\blk00000003/sig00000d59 ), + .Q15(\NLW_blk00000003/blk00000a9b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a9a ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d57 ), + .Q(\blk00000003/sig00000d58 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a99 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c8 ), + .Q(\blk00000003/sig00000d57 ), + .Q15(\NLW_blk00000003/blk00000a99_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a98 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d55 ), + .Q(\blk00000003/sig00000d56 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a97 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002ca ), + .Q(\blk00000003/sig00000d55 ), + .Q15(\NLW_blk00000003/blk00000a97_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a96 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d53 ), + .Q(\blk00000003/sig00000d54 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a95 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c7 ), + .Q(\blk00000003/sig00000d53 ), + .Q15(\NLW_blk00000003/blk00000a95_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a94 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d51 ), + .Q(\blk00000003/sig00000d52 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a93 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c6 ), + .Q(\blk00000003/sig00000d51 ), + .Q15(\NLW_blk00000003/blk00000a93_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a92 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d4f ), + .Q(\blk00000003/sig00000d50 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a91 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c5 ), + .Q(\blk00000003/sig00000d4f ), + .Q15(\NLW_blk00000003/blk00000a91_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a90 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d4d ), + .Q(\blk00000003/sig00000d4e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a8f ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c4 ), + .Q(\blk00000003/sig00000d4d ), + .Q15(\NLW_blk00000003/blk00000a8f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a8e ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d4b ), + .Q(\blk00000003/sig00000d4c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a8d ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig00000d4b ), + .Q15(\NLW_blk00000003/blk00000a8d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a8c ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d49 ), + .Q(\blk00000003/sig00000d4a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a8b ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c1 ), + .Q(\blk00000003/sig00000d49 ), + .Q15(\NLW_blk00000003/blk00000a8b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a8a ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d47 ), + .Q(\blk00000003/sig00000d48 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a89 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c3 ), + .Q(\blk00000003/sig00000d47 ), + .Q15(\NLW_blk00000003/blk00000a89_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a88 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d45 ), + .Q(\blk00000003/sig00000d46 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a87 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c0 ), + .Q(\blk00000003/sig00000d45 ), + .Q15(\NLW_blk00000003/blk00000a87_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a86 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d43 ), + .Q(\blk00000003/sig00000d44 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a85 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002bf ), + .Q(\blk00000003/sig00000d43 ), + .Q15(\NLW_blk00000003/blk00000a85_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a84 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d41 ), + .Q(\blk00000003/sig00000d42 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a83 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002be ), + .Q(\blk00000003/sig00000d41 ), + .Q15(\NLW_blk00000003/blk00000a83_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a82 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d3f ), + .Q(\blk00000003/sig00000d40 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a81 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002bd ), + .Q(\blk00000003/sig00000d3f ), + .Q15(\NLW_blk00000003/blk00000a81_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a80 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d3d ), + .Q(\blk00000003/sig00000d3e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a7f ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002bb ), + .Q(\blk00000003/sig00000d3d ), + .Q15(\NLW_blk00000003/blk00000a7f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a7e ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d3b ), + .Q(\blk00000003/sig00000d3c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a7d ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002bc ), + .Q(\blk00000003/sig00000d3b ), + .Q15(\NLW_blk00000003/blk00000a7d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a7c ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d3a ), + .Q(\blk00000003/sig00000b79 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a7b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b69 ), + .Q(\blk00000003/sig00000d3a ), + .Q15(\NLW_blk00000003/blk00000a7b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a7a ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d39 ), + .Q(\blk00000003/sig00000b78 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a79 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b68 ), + .Q(\blk00000003/sig00000d39 ), + .Q15(\NLW_blk00000003/blk00000a79_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a78 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d38 ), + .Q(\blk00000003/sig00000b7a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a77 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b6a ), + .Q(\blk00000003/sig00000d38 ), + .Q15(\NLW_blk00000003/blk00000a77_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a76 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d37 ), + .Q(\blk00000003/sig00000b77 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a75 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b67 ), + .Q(\blk00000003/sig00000d37 ), + .Q15(\NLW_blk00000003/blk00000a75_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a74 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d36 ), + .Q(\blk00000003/sig00000b76 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a73 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b66 ), + .Q(\blk00000003/sig00000d36 ), + .Q15(\NLW_blk00000003/blk00000a73_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a72 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d35 ), + .Q(\blk00000003/sig00000b75 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a71 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b65 ), + .Q(\blk00000003/sig00000d35 ), + .Q15(\NLW_blk00000003/blk00000a71_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a70 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d34 ), + .Q(\blk00000003/sig00000b74 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a6f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b64 ), + .Q(\blk00000003/sig00000d34 ), + .Q15(\NLW_blk00000003/blk00000a6f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a6e ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d33 ), + .Q(\blk00000003/sig00000b73 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a6d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b63 ), + .Q(\blk00000003/sig00000d33 ), + .Q15(\NLW_blk00000003/blk00000a6d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a6c ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d32 ), + .Q(\blk00000003/sig00000b82 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a6b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b72 ), + .Q(\blk00000003/sig00000d32 ), + .Q15(\NLW_blk00000003/blk00000a6b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a6a ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d31 ), + .Q(\blk00000003/sig00000b81 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a69 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b71 ), + .Q(\blk00000003/sig00000d31 ), + .Q15(\NLW_blk00000003/blk00000a69_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a68 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d30 ), + .Q(\blk00000003/sig00000b7f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a67 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b6f ), + .Q(\blk00000003/sig00000d30 ), + .Q15(\NLW_blk00000003/blk00000a67_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a66 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d2f ), + .Q(\blk00000003/sig00000b7e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a65 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b6e ), + .Q(\blk00000003/sig00000d2f ), + .Q15(\NLW_blk00000003/blk00000a65_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a64 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d2e ), + .Q(\blk00000003/sig00000b80 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a63 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b70 ), + .Q(\blk00000003/sig00000d2e ), + .Q15(\NLW_blk00000003/blk00000a63_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a62 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d2d ), + .Q(\blk00000003/sig00000b7d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a61 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b6d ), + .Q(\blk00000003/sig00000d2d ), + .Q15(\NLW_blk00000003/blk00000a61_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a60 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d2c ), + .Q(\blk00000003/sig00000b7c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a5f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b6c ), + .Q(\blk00000003/sig00000d2c ), + .Q15(\NLW_blk00000003/blk00000a5f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a5e ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d2b ), + .Q(\blk00000003/sig00000b7b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a5d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b6b ), + .Q(\blk00000003/sig00000d2b ), + .Q15(\NLW_blk00000003/blk00000a5d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a5c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d2a ), + .Q(\blk00000003/sig00000c6e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a5b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000299 ), + .Q(\blk00000003/sig00000d2a ), + .Q15(\NLW_blk00000003/blk00000a5b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a5a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d29 ), + .Q(\blk00000003/sig00000c6f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a59 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000297 ), + .Q(\blk00000003/sig00000d29 ), + .Q15(\NLW_blk00000003/blk00000a59_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a58 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d28 ), + .Q(\blk00000003/sig00000c71 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a57 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000296 ), + .Q(\blk00000003/sig00000d28 ), + .Q15(\NLW_blk00000003/blk00000a57_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a56 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d27 ), + .Q(\blk00000003/sig00000c70 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a55 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000298 ), + .Q(\blk00000003/sig00000d27 ), + .Q15(\NLW_blk00000003/blk00000a55_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a54 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d26 ), + .Q(\blk00000003/sig00000c73 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a53 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000295 ), + .Q(\blk00000003/sig00000d26 ), + .Q15(\NLW_blk00000003/blk00000a53_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a52 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d25 ), + .Q(\blk00000003/sig00000c72 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a51 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000294 ), + .Q(\blk00000003/sig00000d25 ), + .Q15(\NLW_blk00000003/blk00000a51_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a50 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d24 ), + .Q(\blk00000003/sig00000c74 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a4f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000293 ), + .Q(\blk00000003/sig00000d24 ), + .Q15(\NLW_blk00000003/blk00000a4f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a4e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d23 ), + .Q(\blk00000003/sig00000c76 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a4d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000292 ), + .Q(\blk00000003/sig00000d23 ), + .Q15(\NLW_blk00000003/blk00000a4d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a4c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d22 ), + .Q(\blk00000003/sig00000c77 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a4b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000290 ), + .Q(\blk00000003/sig00000d22 ), + .Q15(\NLW_blk00000003/blk00000a4b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a4a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d21 ), + .Q(\blk00000003/sig00000c79 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a49 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028f ), + .Q(\blk00000003/sig00000d21 ), + .Q15(\NLW_blk00000003/blk00000a49_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a48 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d20 ), + .Q(\blk00000003/sig00000c75 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a47 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000291 ), + .Q(\blk00000003/sig00000d20 ), + .Q15(\NLW_blk00000003/blk00000a47_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a46 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d1f ), + .Q(\blk00000003/sig00000c78 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a45 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028e ), + .Q(\blk00000003/sig00000d1f ), + .Q15(\NLW_blk00000003/blk00000a45_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a44 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d1e ), + .Q(\blk00000003/sig00000c7a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a43 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028d ), + .Q(\blk00000003/sig00000d1e ), + .Q15(\NLW_blk00000003/blk00000a43_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a42 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d1d ), + .Q(\blk00000003/sig00000c7c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a41 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028c ), + .Q(\blk00000003/sig00000d1d ), + .Q15(\NLW_blk00000003/blk00000a41_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a40 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d1c ), + .Q(\blk00000003/sig00000c7b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a3f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028b ), + .Q(\blk00000003/sig00000d1c ), + .Q15(\NLW_blk00000003/blk00000a3f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a3e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d1b ), + .Q(\blk00000003/sig00000c7e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a3d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000211 ), + .Q(\blk00000003/sig00000d1b ), + .Q15(\NLW_blk00000003/blk00000a3d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a3c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d1a ), + .Q(\blk00000003/sig00000c7f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a3b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000210 ), + .Q(\blk00000003/sig00000d1a ), + .Q15(\NLW_blk00000003/blk00000a3b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a3a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d19 ), + .Q(\blk00000003/sig00000c7d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a39 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028a ), + .Q(\blk00000003/sig00000d19 ), + .Q15(\NLW_blk00000003/blk00000a39_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a38 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d18 ), + .Q(\blk00000003/sig00000c80 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a37 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020f ), + .Q(\blk00000003/sig00000d18 ), + .Q15(\NLW_blk00000003/blk00000a37_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a36 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d17 ), + .Q(\blk00000003/sig00000c82 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a35 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020e ), + .Q(\blk00000003/sig00000d17 ), + .Q15(\NLW_blk00000003/blk00000a35_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a34 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d16 ), + .Q(\blk00000003/sig00000c81 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a33 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020d ), + .Q(\blk00000003/sig00000d16 ), + .Q15(\NLW_blk00000003/blk00000a33_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a32 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d15 ), + .Q(\blk00000003/sig00000c83 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a31 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020c ), + .Q(\blk00000003/sig00000d15 ), + .Q15(\NLW_blk00000003/blk00000a31_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a30 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d14 ), + .Q(\blk00000003/sig00000c84 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a2f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020a ), + .Q(\blk00000003/sig00000d14 ), + .Q15(\NLW_blk00000003/blk00000a2f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a2e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d13 ), + .Q(\blk00000003/sig00000c86 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a2d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000209 ), + .Q(\blk00000003/sig00000d13 ), + .Q15(\NLW_blk00000003/blk00000a2d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a2c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d12 ), + .Q(\blk00000003/sig00000c85 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a2b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020b ), + .Q(\blk00000003/sig00000d12 ), + .Q15(\NLW_blk00000003/blk00000a2b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a2a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d11 ), + .Q(\blk00000003/sig00000c88 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a29 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000208 ), + .Q(\blk00000003/sig00000d11 ), + .Q15(\NLW_blk00000003/blk00000a29_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a28 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d10 ), + .Q(\blk00000003/sig00000c87 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a27 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000207 ), + .Q(\blk00000003/sig00000d10 ), + .Q15(\NLW_blk00000003/blk00000a27_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a26 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d0f ), + .Q(\blk00000003/sig00000c89 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a25 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000206 ), + .Q(\blk00000003/sig00000d0f ), + .Q15(\NLW_blk00000003/blk00000a25_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a24 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d0e ), + .Q(\blk00000003/sig00000c8b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a23 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000205 ), + .Q(\blk00000003/sig00000d0e ), + .Q15(\NLW_blk00000003/blk00000a23_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a22 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d0d ), + .Q(\blk00000003/sig00000c8c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a21 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000203 ), + .Q(\blk00000003/sig00000d0d ), + .Q15(\NLW_blk00000003/blk00000a21_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a20 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d0c ), + .Q(\blk00000003/sig00000c8d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a1f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000202 ), + .Q(\blk00000003/sig00000d0c ), + .Q15(\NLW_blk00000003/blk00000a1f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a1e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d0b ), + .Q(\blk00000003/sig00000c8a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a1d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000204 ), + .Q(\blk00000003/sig00000d0b ), + .Q15(\NLW_blk00000003/blk00000a1d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a1c ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d0a ), + .Q(\blk00000003/sig00000a46 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a1b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a26 ), + .Q(\blk00000003/sig00000d0a ), + .Q15(\NLW_blk00000003/blk00000a1b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a1a ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d09 ), + .Q(\blk00000003/sig00000a45 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a19 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a25 ), + .Q(\blk00000003/sig00000d09 ), + .Q15(\NLW_blk00000003/blk00000a19_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a18 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d08 ), + .Q(\blk00000003/sig00000a43 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a17 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a23 ), + .Q(\blk00000003/sig00000d08 ), + .Q15(\NLW_blk00000003/blk00000a17_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a16 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d07 ), + .Q(\blk00000003/sig00000a42 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a15 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a22 ), + .Q(\blk00000003/sig00000d07 ), + .Q15(\NLW_blk00000003/blk00000a15_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a14 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d06 ), + .Q(\blk00000003/sig00000a44 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a13 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a24 ), + .Q(\blk00000003/sig00000d06 ), + .Q15(\NLW_blk00000003/blk00000a13_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a12 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d05 ), + .Q(\blk00000003/sig00000a41 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a11 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a21 ), + .Q(\blk00000003/sig00000d05 ), + .Q15(\NLW_blk00000003/blk00000a11_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a10 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d04 ), + .Q(\blk00000003/sig00000a40 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a0f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a20 ), + .Q(\blk00000003/sig00000d04 ), + .Q15(\NLW_blk00000003/blk00000a0f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a0e ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d03 ), + .Q(\blk00000003/sig00000a3f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a0d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a1f ), + .Q(\blk00000003/sig00000d03 ), + .Q15(\NLW_blk00000003/blk00000a0d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a0c ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d02 ), + .Q(\blk00000003/sig00000a3e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a0b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a1e ), + .Q(\blk00000003/sig00000d02 ), + .Q15(\NLW_blk00000003/blk00000a0b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a0a ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d01 ), + .Q(\blk00000003/sig00000a3c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a09 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a1c ), + .Q(\blk00000003/sig00000d01 ), + .Q15(\NLW_blk00000003/blk00000a09_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a08 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d00 ), + .Q(\blk00000003/sig00000a3b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a07 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a1b ), + .Q(\blk00000003/sig00000d00 ), + .Q15(\NLW_blk00000003/blk00000a07_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a06 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000cff ), + .Q(\blk00000003/sig00000a3d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a05 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a1d ), + .Q(\blk00000003/sig00000cff ), + .Q15(\NLW_blk00000003/blk00000a05_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a04 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000cfe ), + .Q(\blk00000003/sig00000a3a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a03 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a1a ), + .Q(\blk00000003/sig00000cfe ), + .Q15(\NLW_blk00000003/blk00000a03_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a02 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000cfd ), + .Q(\blk00000003/sig00000a39 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a01 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a19 ), + .Q(\blk00000003/sig00000cfd ), + .Q15(\NLW_blk00000003/blk00000a01_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a00 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000cfc ), + .Q(\blk00000003/sig00000a38 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ff ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a18 ), + .Q(\blk00000003/sig00000cfc ), + .Q15(\NLW_blk00000003/blk000009ff_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009fe ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000cfb ), + .Q(\blk00000003/sig00000a37 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009fd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a17 ), + .Q(\blk00000003/sig00000cfb ), + .Q15(\NLW_blk00000003/blk000009fd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009fc ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cfa ), + .Q(\blk00000003/sig00000a56 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009fb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a36 ), + .Q(\blk00000003/sig00000cfa ), + .Q15(\NLW_blk00000003/blk000009fb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009fa ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf9 ), + .Q(\blk00000003/sig00000a55 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a35 ), + .Q(\blk00000003/sig00000cf9 ), + .Q15(\NLW_blk00000003/blk000009f9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f8 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf8 ), + .Q(\blk00000003/sig00000a54 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a34 ), + .Q(\blk00000003/sig00000cf8 ), + .Q15(\NLW_blk00000003/blk000009f7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f6 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf7 ), + .Q(\blk00000003/sig00000a53 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a33 ), + .Q(\blk00000003/sig00000cf7 ), + .Q15(\NLW_blk00000003/blk000009f5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f4 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf6 ), + .Q(\blk00000003/sig00000a52 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a32 ), + .Q(\blk00000003/sig00000cf6 ), + .Q15(\NLW_blk00000003/blk000009f3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f2 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf5 ), + .Q(\blk00000003/sig00000a50 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a30 ), + .Q(\blk00000003/sig00000cf5 ), + .Q15(\NLW_blk00000003/blk000009f1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f0 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf4 ), + .Q(\blk00000003/sig00000a4f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ef ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a2f ), + .Q(\blk00000003/sig00000cf4 ), + .Q15(\NLW_blk00000003/blk000009ef_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ee ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf3 ), + .Q(\blk00000003/sig00000a51 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ed ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a31 ), + .Q(\blk00000003/sig00000cf3 ), + .Q15(\NLW_blk00000003/blk000009ed_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ec ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf2 ), + .Q(\blk00000003/sig00000a4e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009eb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a2e ), + .Q(\blk00000003/sig00000cf2 ), + .Q15(\NLW_blk00000003/blk000009eb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ea ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf1 ), + .Q(\blk00000003/sig00000a4d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a2d ), + .Q(\blk00000003/sig00000cf1 ), + .Q15(\NLW_blk00000003/blk000009e9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e8 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf0 ), + .Q(\blk00000003/sig00000a4c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a2c ), + .Q(\blk00000003/sig00000cf0 ), + .Q15(\NLW_blk00000003/blk000009e7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e6 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cef ), + .Q(\blk00000003/sig00000a4b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a2b ), + .Q(\blk00000003/sig00000cef ), + .Q15(\NLW_blk00000003/blk000009e5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e4 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cee ), + .Q(\blk00000003/sig00000a49 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a29 ), + .Q(\blk00000003/sig00000cee ), + .Q15(\NLW_blk00000003/blk000009e3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e2 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000ced ), + .Q(\blk00000003/sig00000a48 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a28 ), + .Q(\blk00000003/sig00000ced ), + .Q15(\NLW_blk00000003/blk000009e1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e0 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cec ), + .Q(\blk00000003/sig00000a4a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009df ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a2a ), + .Q(\blk00000003/sig00000cec ), + .Q15(\NLW_blk00000003/blk000009df_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009de ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000ceb ), + .Q(\blk00000003/sig00000a47 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009dd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a27 ), + .Q(\blk00000003/sig00000ceb ), + .Q15(\NLW_blk00000003/blk000009dd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cea ), + .Q(\blk00000003/sig00000ac6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009db ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002ea ), + .Q(\blk00000003/sig00000cea ), + .Q15(\NLW_blk00000003/blk000009db_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009da ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce9 ), + .Q(\blk00000003/sig00000ac5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d9 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e9 ), + .Q(\blk00000003/sig00000ce9 ), + .Q15(\NLW_blk00000003/blk000009d9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce8 ), + .Q(\blk00000003/sig00000ac4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d7 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e8 ), + .Q(\blk00000003/sig00000ce8 ), + .Q15(\NLW_blk00000003/blk000009d7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce7 ), + .Q(\blk00000003/sig00000ac2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d5 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e6 ), + .Q(\blk00000003/sig00000ce7 ), + .Q15(\NLW_blk00000003/blk000009d5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce6 ), + .Q(\blk00000003/sig00000ac1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d3 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e5 ), + .Q(\blk00000003/sig00000ce6 ), + .Q15(\NLW_blk00000003/blk000009d3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce5 ), + .Q(\blk00000003/sig00000ac3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d1 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e7 ), + .Q(\blk00000003/sig00000ce5 ), + .Q15(\NLW_blk00000003/blk000009d1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce4 ), + .Q(\blk00000003/sig00000ac0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009cf ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e4 ), + .Q(\blk00000003/sig00000ce4 ), + .Q15(\NLW_blk00000003/blk000009cf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce3 ), + .Q(\blk00000003/sig00000abf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009cd ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e3 ), + .Q(\blk00000003/sig00000ce3 ), + .Q15(\NLW_blk00000003/blk000009cd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce2 ), + .Q(\blk00000003/sig00000abe ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009cb ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e2 ), + .Q(\blk00000003/sig00000ce2 ), + .Q15(\NLW_blk00000003/blk000009cb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce1 ), + .Q(\blk00000003/sig00000abd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c9 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e1 ), + .Q(\blk00000003/sig00000ce1 ), + .Q15(\NLW_blk00000003/blk000009c9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce0 ), + .Q(\blk00000003/sig00000abb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c7 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002df ), + .Q(\blk00000003/sig00000ce0 ), + .Q15(\NLW_blk00000003/blk000009c7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cdf ), + .Q(\blk00000003/sig00000aba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c5 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002de ), + .Q(\blk00000003/sig00000cdf ), + .Q15(\NLW_blk00000003/blk000009c5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cde ), + .Q(\blk00000003/sig00000abc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c3 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e0 ), + .Q(\blk00000003/sig00000cde ), + .Q15(\NLW_blk00000003/blk000009c3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cdd ), + .Q(\blk00000003/sig00000ab9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c1 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002dd ), + .Q(\blk00000003/sig00000cdd ), + .Q15(\NLW_blk00000003/blk000009c1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cdc ), + .Q(\blk00000003/sig00000ab8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bf ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002dc ), + .Q(\blk00000003/sig00000cdc ), + .Q15(\NLW_blk00000003/blk000009bf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cdb ), + .Q(\blk00000003/sig00000ab7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bd ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002db ), + .Q(\blk00000003/sig00000cdb ), + .Q15(\NLW_blk00000003/blk000009bd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cda ), + .Q(\blk00000003/sig00000bba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bb ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002da ), + .Q(\blk00000003/sig00000cda ), + .Q15(\NLW_blk00000003/blk000009bb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd9 ), + .Q(\blk00000003/sig00000bb8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b9 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d8 ), + .Q(\blk00000003/sig00000cd9 ), + .Q15(\NLW_blk00000003/blk000009b9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd8 ), + .Q(\blk00000003/sig00000bb7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b7 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d7 ), + .Q(\blk00000003/sig00000cd8 ), + .Q15(\NLW_blk00000003/blk000009b7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd7 ), + .Q(\blk00000003/sig00000bb9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b5 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d9 ), + .Q(\blk00000003/sig00000cd7 ), + .Q15(\NLW_blk00000003/blk000009b5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd6 ), + .Q(\blk00000003/sig00000bb6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b3 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d6 ), + .Q(\blk00000003/sig00000cd6 ), + .Q15(\NLW_blk00000003/blk000009b3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd5 ), + .Q(\blk00000003/sig00000bb5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b1 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d5 ), + .Q(\blk00000003/sig00000cd5 ), + .Q15(\NLW_blk00000003/blk000009b1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd4 ), + .Q(\blk00000003/sig00000bb4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009af ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d4 ), + .Q(\blk00000003/sig00000cd4 ), + .Q15(\NLW_blk00000003/blk000009af_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd3 ), + .Q(\blk00000003/sig00000bb3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ad ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d3 ), + .Q(\blk00000003/sig00000cd3 ), + .Q15(\NLW_blk00000003/blk000009ad_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd2 ), + .Q(\blk00000003/sig00000ae5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ab ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d1 ), + .Q(\blk00000003/sig00000cd2 ), + .Q15(\NLW_blk00000003/blk000009ab_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd1 ), + .Q(\blk00000003/sig00000ae4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a9 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d0 ), + .Q(\blk00000003/sig00000cd1 ), + .Q15(\NLW_blk00000003/blk000009a9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd0 ), + .Q(\blk00000003/sig00000ae6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a7 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d2 ), + .Q(\blk00000003/sig00000cd0 ), + .Q15(\NLW_blk00000003/blk000009a7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ccf ), + .Q(\blk00000003/sig00000ae3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a5 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002cf ), + .Q(\blk00000003/sig00000ccf ), + .Q15(\NLW_blk00000003/blk000009a5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cce ), + .Q(\blk00000003/sig00000ae2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a3 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002ce ), + .Q(\blk00000003/sig00000cce ), + .Q15(\NLW_blk00000003/blk000009a3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ccd ), + .Q(\blk00000003/sig00000ae1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a1 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002cd ), + .Q(\blk00000003/sig00000ccd ), + .Q15(\NLW_blk00000003/blk000009a1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ccc ), + .Q(\blk00000003/sig00000ae0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000099f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002cc ), + .Q(\blk00000003/sig00000ccc ), + .Q15(\NLW_blk00000003/blk0000099f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000099e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ccb ), + .Q(\blk00000003/sig00000ade ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000099d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002ca ), + .Q(\blk00000003/sig00000ccb ), + .Q15(\NLW_blk00000003/blk0000099d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000099c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cca ), + .Q(\blk00000003/sig00000add ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000099b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c9 ), + .Q(\blk00000003/sig00000cca ), + .Q15(\NLW_blk00000003/blk0000099b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000099a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc9 ), + .Q(\blk00000003/sig00000adf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000999 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002cb ), + .Q(\blk00000003/sig00000cc9 ), + .Q15(\NLW_blk00000003/blk00000999_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000998 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc8 ), + .Q(\blk00000003/sig00000adc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000997 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c8 ), + .Q(\blk00000003/sig00000cc8 ), + .Q15(\NLW_blk00000003/blk00000997_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000996 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc7 ), + .Q(\blk00000003/sig00000adb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000995 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c7 ), + .Q(\blk00000003/sig00000cc7 ), + .Q15(\NLW_blk00000003/blk00000995_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000994 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc6 ), + .Q(\blk00000003/sig00000ada ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000993 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c6 ), + .Q(\blk00000003/sig00000cc6 ), + .Q15(\NLW_blk00000003/blk00000993_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000992 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc5 ), + .Q(\blk00000003/sig00000ad9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000991 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c5 ), + .Q(\blk00000003/sig00000cc5 ), + .Q15(\NLW_blk00000003/blk00000991_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000990 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc4 ), + .Q(\blk00000003/sig00000ad7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c3 ), + .Q(\blk00000003/sig00000cc4 ), + .Q15(\NLW_blk00000003/blk0000098f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc3 ), + .Q(\blk00000003/sig00000bca ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig00000cc3 ), + .Q15(\NLW_blk00000003/blk0000098d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc2 ), + .Q(\blk00000003/sig00000ad8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c4 ), + .Q(\blk00000003/sig00000cc2 ), + .Q15(\NLW_blk00000003/blk0000098b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc1 ), + .Q(\blk00000003/sig00000bc9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000989 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c1 ), + .Q(\blk00000003/sig00000cc1 ), + .Q15(\NLW_blk00000003/blk00000989_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000988 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc0 ), + .Q(\blk00000003/sig00000bc8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000987 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c0 ), + .Q(\blk00000003/sig00000cc0 ), + .Q15(\NLW_blk00000003/blk00000987_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000986 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cbf ), + .Q(\blk00000003/sig00000bc7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000985 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002bf ), + .Q(\blk00000003/sig00000cbf ), + .Q15(\NLW_blk00000003/blk00000985_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000984 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cbe ), + .Q(\blk00000003/sig00000bc6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000983 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002be ), + .Q(\blk00000003/sig00000cbe ), + .Q15(\NLW_blk00000003/blk00000983_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000982 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cbd ), + .Q(\blk00000003/sig00000bc4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000981 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002bc ), + .Q(\blk00000003/sig00000cbd ), + .Q15(\NLW_blk00000003/blk00000981_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000980 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cbc ), + .Q(\blk00000003/sig00000bc3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000097f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002bb ), + .Q(\blk00000003/sig00000cbc ), + .Q15(\NLW_blk00000003/blk0000097f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000097e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cbb ), + .Q(\blk00000003/sig00000bc5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000097d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002bd ), + .Q(\blk00000003/sig00000cbb ), + .Q15(\NLW_blk00000003/blk0000097d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000097c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cba ), + .Q(\blk00000003/sig00000378 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000097b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002a6 ), + .Q(\blk00000003/sig00000cba ), + .Q15(\NLW_blk00000003/blk0000097b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000097a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb9 ), + .Q(\blk00000003/sig00000379 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000979 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000373 ), + .Q(\blk00000003/sig00000cb9 ), + .Q15(\NLW_blk00000003/blk00000979_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000978 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb8 ), + .Q(\blk00000003/sig00000c66 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000977 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002a2 ), + .Q(\blk00000003/sig00000cb8 ), + .Q15(\NLW_blk00000003/blk00000977_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000976 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb7 ), + .Q(\blk00000003/sig00000b08 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000975 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[0]), + .Q(\blk00000003/sig00000cb7 ), + .Q15(\NLW_blk00000003/blk00000975_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000974 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb6 ), + .Q(\blk00000003/sig00000b06 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000973 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[2]), + .Q(\blk00000003/sig00000cb6 ), + .Q15(\NLW_blk00000003/blk00000973_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000972 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb5 ), + .Q(\blk00000003/sig00000b05 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000971 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[3]), + .Q(\blk00000003/sig00000cb5 ), + .Q15(\NLW_blk00000003/blk00000971_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000970 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb4 ), + .Q(\blk00000003/sig00000b07 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000096f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[1]), + .Q(\blk00000003/sig00000cb4 ), + .Q15(\NLW_blk00000003/blk0000096f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000096e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb3 ), + .Q(\blk00000003/sig00000b04 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000096d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[4]), + .Q(\blk00000003/sig00000cb3 ), + .Q15(\NLW_blk00000003/blk0000096d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000096c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb2 ), + .Q(\blk00000003/sig00000b03 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000096b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[5]), + .Q(\blk00000003/sig00000cb2 ), + .Q15(\NLW_blk00000003/blk0000096b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000096a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb1 ), + .Q(\blk00000003/sig00000b02 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000969 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[6]), + .Q(\blk00000003/sig00000cb1 ), + .Q15(\NLW_blk00000003/blk00000969_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000968 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb0 ), + .Q(\blk00000003/sig00000b01 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000967 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[7]), + .Q(\blk00000003/sig00000cb0 ), + .Q15(\NLW_blk00000003/blk00000967_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000966 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000caf ), + .Q(\blk00000003/sig00000aff ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000965 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[9]), + .Q(\blk00000003/sig00000caf ), + .Q15(\NLW_blk00000003/blk00000965_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000964 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cae ), + .Q(\blk00000003/sig00000afe ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000963 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[10]), + .Q(\blk00000003/sig00000cae ), + .Q15(\NLW_blk00000003/blk00000963_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000962 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cad ), + .Q(\blk00000003/sig00000b00 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000961 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[8]), + .Q(\blk00000003/sig00000cad ), + .Q15(\NLW_blk00000003/blk00000961_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000960 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cac ), + .Q(\blk00000003/sig00000afd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000095f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[11]), + .Q(\blk00000003/sig00000cac ), + .Q15(\NLW_blk00000003/blk0000095f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000095e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cab ), + .Q(\blk00000003/sig00000afc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000095d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[12]), + .Q(\blk00000003/sig00000cab ), + .Q15(\NLW_blk00000003/blk0000095d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000095c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000caa ), + .Q(\blk00000003/sig00000afb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000095b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[13]), + .Q(\blk00000003/sig00000caa ), + .Q15(\NLW_blk00000003/blk0000095b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000095a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ca9 ), + .Q(\blk00000003/sig00000afa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000959 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[14]), + .Q(\blk00000003/sig00000ca9 ), + .Q15(\NLW_blk00000003/blk00000959_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000958 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ca8 ), + .Q(\blk00000003/sig00000af8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000957 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[16]), + .Q(\blk00000003/sig00000ca8 ), + .Q15(\NLW_blk00000003/blk00000957_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000956 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ca7 ), + .Q(\blk00000003/sig00000af7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000955 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[17]), + .Q(\blk00000003/sig00000ca7 ), + .Q15(\NLW_blk00000003/blk00000955_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000954 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ca6 ), + .Q(\blk00000003/sig00000af9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000953 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[15]), + .Q(\blk00000003/sig00000ca6 ), + .Q15(\NLW_blk00000003/blk00000953_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000952 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ca5 ), + .Q(\blk00000003/sig000002af ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000951 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002b1 ), + .Q(\blk00000003/sig00000ca5 ), + .Q15(\NLW_blk00000003/blk00000951_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000950 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ca4 ), + .Q(\blk00000003/sig00000a15 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000094f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002a8 ), + .Q(\blk00000003/sig00000ca4 ), + .Q15(\NLW_blk00000003/blk0000094f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000094e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ca3 ), + .Q(\blk00000003/sig00000bd5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000094d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002a0 ), + .Q(\blk00000003/sig00000ca3 ), + .Q15(\NLW_blk00000003/blk0000094d_Q15_UNCONNECTED ) + ); + INV \blk00000003/blk0000094c ( + .I(\blk00000003/sig00000318 ), + .O(\blk00000003/sig0000034a ) + ); + INV \blk00000003/blk0000094b ( + .I(\blk00000003/sig000002f4 ), + .O(\blk00000003/sig00000306 ) + ); + INV \blk00000003/blk0000094a ( + .I(\blk00000003/sig00000353 ), + .O(\blk00000003/sig00000343 ) + ); + INV \blk00000003/blk00000949 ( + .I(\blk00000003/sig0000035a ), + .O(\blk00000003/sig00000349 ) + ); + INV \blk00000003/blk00000948 ( + .I(\blk00000003/sig000002a0 ), + .O(\blk00000003/sig00000358 ) + ); + INV \blk00000003/blk00000947 ( + .I(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig00000c60 ) + ); + INV \blk00000003/blk00000946 ( + .I(\blk00000003/sig0000031c ), + .O(\blk00000003/sig0000035b ) + ); + INV \blk00000003/blk00000945 ( + .I(\blk00000003/sig00000318 ), + .O(\blk00000003/sig00000344 ) + ); + INV \blk00000003/blk00000944 ( + .I(\blk00000003/sig000002ee ), + .O(\blk00000003/sig0000031d ) + ); + INV \blk00000003/blk00000943 ( + .I(\blk00000003/sig000002f4 ), + .O(\blk00000003/sig00000304 ) + ); + INV \blk00000003/blk00000942 ( + .I(\blk00000003/sig0000029e ), + .O(\blk00000003/sig0000016e ) + ); + INV \blk00000003/blk00000941 ( + .I(\blk00000003/sig00000161 ), + .O(\blk00000003/sig0000029d ) + ); + INV \blk00000003/blk00000940 ( + .I(\blk00000003/sig0000016b ), + .O(\blk00000003/sig0000016c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000093f ( + .I0(ce), + .I1(\blk00000003/sig000009f8 ), + .O(\blk00000003/sig00000bd3 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000093e ( + .I0(ce), + .I1(\blk00000003/sig000009f8 ), + .O(\blk00000003/sig00000bd4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000093d ( + .I0(ce), + .I1(\blk00000003/sig000009f8 ), + .O(\blk00000003/sig00000ca2 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000093c ( + .I0(ce), + .I1(\blk00000003/sig000009f8 ), + .O(\blk00000003/sig00000ca1 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000093b ( + .I0(ce), + .I1(\blk00000003/sig00000a0f ), + .O(\blk00000003/sig00000ca0 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000093a ( + .I0(ce), + .I1(\blk00000003/sig00000a0f ), + .O(\blk00000003/sig00000c9f ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000939 ( + .I0(ce), + .I1(\blk00000003/sig00000a0a ), + .O(\blk00000003/sig00000c9e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000938 ( + .I0(ce), + .I1(\blk00000003/sig00000a0a ), + .O(\blk00000003/sig00000c9d ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000937 ( + .I0(ce), + .I1(\blk00000003/sig00000a03 ), + .O(\blk00000003/sig00000c9c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000936 ( + .I0(ce), + .I1(\blk00000003/sig00000a03 ), + .O(\blk00000003/sig00000c9b ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000935 ( + .I0(ce), + .I1(\blk00000003/sig000009f7 ), + .O(\blk00000003/sig00000c9a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000934 ( + .I0(ce), + .I1(\blk00000003/sig000009f7 ), + .O(\blk00000003/sig00000c99 ) + ); + LUT3 #( + .INIT ( 8'h20 )) + \blk00000003/blk00000933 ( + .I0(\blk00000003/sig0000030e ), + .I1(\blk00000003/sig00000325 ), + .I2(coef_ld), + .O(\blk00000003/sig00000321 ) + ); + LUT5 #( + .INIT ( 32'h4F444444 )) + \blk00000003/blk00000932 ( + .I0(\blk00000003/sig00000322 ), + .I1(\blk00000003/sig00000316 ), + .I2(\blk00000003/sig00000325 ), + .I3(coef_ld), + .I4(\blk00000003/sig0000030e ), + .O(\blk00000003/sig00000319 ) + ); + LUT4 #( + .INIT ( 16'h1000 )) + \blk00000003/blk00000931 ( + .I0(coef_ld), + .I1(\blk00000003/sig00000310 ), + .I2(coef_we), + .I3(\blk00000003/sig0000030e ), + .O(\blk00000003/sig00000320 ) + ); + LUT5 #( + .INIT ( 32'h20AA2020 )) + \blk00000003/blk00000930 ( + .I0(\blk00000003/sig0000030e ), + .I1(\blk00000003/sig00000310 ), + .I2(coef_we), + .I3(\blk00000003/sig00000325 ), + .I4(coef_ld), + .O(\blk00000003/sig0000031f ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk0000092f ( + .I0(ce), + .I1(sclr), + .I2(\blk00000003/sig00000c67 ), + .O(\blk00000003/sig00000c90 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk0000092e ( + .I0(\blk00000003/sig00000353 ), + .I1(ce), + .I2(\blk00000003/sig00000316 ), + .I3(\blk00000003/sig000002ec ), + .O(\blk00000003/sig00000c98 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk0000092d ( + .I0(\blk00000003/sig0000035a ), + .I1(ce), + .I2(\blk00000003/sig00000314 ), + .I3(\blk00000003/sig0000034b ), + .O(\blk00000003/sig00000c97 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk0000092c ( + .I0(\blk00000003/sig00000c64 ), + .I1(ce), + .I2(\blk00000003/sig000002a6 ), + .I3(\blk00000003/sig000002a8 ), + .O(\blk00000003/sig00000c92 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk0000092b ( + .I0(ce), + .I1(\blk00000003/sig00000325 ), + .I2(\blk00000003/sig00000c65 ), + .O(\blk00000003/sig00000c8f ) + ); + LUT4 #( + .INIT ( 16'h6AAA )) + \blk00000003/blk0000092a ( + .I0(\blk00000003/sig000002b3 ), + .I1(\blk00000003/sig000002a8 ), + .I2(\blk00000003/sig00000c94 ), + .I3(ce), + .O(\blk00000003/sig00000c96 ) + ); + LUT5 #( + .INIT ( 32'h7FFF8000 )) + \blk00000003/blk00000929 ( + .I0(nd), + .I1(ce), + .I2(\blk00000003/sig00000159 ), + .I3(\blk00000003/sig00000c63 ), + .I4(\blk00000003/sig000002b8 ), + .O(\blk00000003/sig00000c95 ) + ); + LUT3 #( + .INIT ( 8'h6C )) + \blk00000003/blk00000928 ( + .I0(\blk00000003/sig000002a8 ), + .I1(\blk00000003/sig00000c94 ), + .I2(ce), + .O(\blk00000003/sig00000c93 ) + ); + LUT4 #( + .INIT ( 16'h6AAA )) + \blk00000003/blk00000927 ( + .I0(\blk00000003/sig00000c63 ), + .I1(\blk00000003/sig00000159 ), + .I2(ce), + .I3(nd), + .O(\blk00000003/sig00000c91 ) + ); + LUT4 #( + .INIT ( 16'hEAAA )) + \blk00000003/blk00000926 ( + .I0(\blk00000003/sig00000330 ), + .I1(\blk00000003/sig000002f8 ), + .I2(coef_we), + .I3(\blk00000003/sig00000302 ), + .O(\blk00000003/sig0000032a ) + ); + LUT4 #( + .INIT ( 16'hEAAA )) + \blk00000003/blk00000925 ( + .I0(\blk00000003/sig00000331 ), + .I1(\blk00000003/sig000002f8 ), + .I2(coef_we), + .I3(\blk00000003/sig00000302 ), + .O(\blk00000003/sig0000032d ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk00000924 ( + .C(clk), + .D(\blk00000003/sig00000c98 ), + .Q(\blk00000003/sig00000353 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk00000923 ( + .C(clk), + .D(\blk00000003/sig00000c97 ), + .Q(\blk00000003/sig0000035a ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000922 ( + .C(clk), + .D(\blk00000003/sig00000c96 ), + .R(sclr), + .Q(\blk00000003/sig000002b3 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000921 ( + .C(clk), + .D(\blk00000003/sig00000c95 ), + .R(sclr), + .Q(\blk00000003/sig000002b8 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000920 ( + .C(clk), + .D(\blk00000003/sig00000c93 ), + .R(sclr), + .Q(\blk00000003/sig00000c94 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000091f ( + .C(clk), + .D(\blk00000003/sig00000c92 ), + .R(sclr), + .Q(\blk00000003/sig00000c64 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000091e ( + .C(clk), + .D(\blk00000003/sig00000c91 ), + .R(sclr), + .Q(\blk00000003/sig00000c63 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000091d ( + .I0(\blk00000003/sig00000beb ), + .O(\blk00000003/sig00000be5 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000091c ( + .I0(\blk00000003/sig00000bea ), + .O(\blk00000003/sig00000be2 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000091b ( + .I0(\blk00000003/sig00000be9 ), + .O(\blk00000003/sig00000bdf ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000091a ( + .I0(\blk00000003/sig00000be8 ), + .O(\blk00000003/sig00000bdc ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000919 ( + .I0(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig00000bd9 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000918 ( + .I0(\blk00000003/sig00000375 ), + .O(\blk00000003/sig00000376 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000917 ( + .I0(\blk00000003/sig00000369 ), + .O(\blk00000003/sig00000363 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000916 ( + .I0(\blk00000003/sig00000334 ), + .O(\blk00000003/sig00000335 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000915 ( + .I0(\blk00000003/sig0000029e ), + .O(\blk00000003/sig0000016f ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000914 ( + .I0(\blk00000003/sig00000c63 ), + .O(\blk00000003/sig00000160 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000913 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c5a ), + .R(sclr), + .Q(\blk00000003/sig00000c5f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000912 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c57 ), + .R(sclr), + .Q(\blk00000003/sig00000c5e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000911 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c54 ), + .R(sclr), + .Q(\blk00000003/sig00000c5d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000910 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c51 ), + .R(sclr), + .Q(\blk00000003/sig00000c5c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000090f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c4e ), + .R(sclr), + .Q(\blk00000003/sig00000c5b ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000090e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bd7 ), + .S(sclr), + .Q(\blk00000003/sig00000bec ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000090d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000be6 ), + .R(sclr), + .Q(\blk00000003/sig00000beb ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000090c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000be3 ), + .S(sclr), + .Q(\blk00000003/sig00000bea ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000090b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000be0 ), + .S(sclr), + .Q(\blk00000003/sig00000be9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000090a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bdd ), + .R(sclr), + .Q(\blk00000003/sig00000be8 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000909 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bda ), + .S(sclr), + .Q(\blk00000003/sig00000be7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000908 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000377 ), + .R(\blk00000003/sig0000037a ), + .Q(\blk00000003/sig00000375 ) + ); + FDR \blk00000003/blk00000907 ( + .C(clk), + .D(\blk00000003/sig00000c90 ), + .R(ce), + .Q(\blk00000003/sig00000c67 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000906 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000371 ), + .R(\blk00000003/sig00000379 ), + .Q(\blk00000003/sig0000036f ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000905 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000036c ), + .S(\blk00000003/sig00000379 ), + .Q(\blk00000003/sig0000036a ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000904 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000364 ), + .S(sclr), + .Q(\blk00000003/sig00000369 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000903 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000367 ), + .R(sclr), + .Q(\blk00000003/sig00000368 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000902 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000035e ), + .R(sclr), + .Q(\blk00000003/sig000002ba ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000901 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000361 ), + .R(sclr), + .Q(\blk00000003/sig000002b9 ) + ); + FDR \blk00000003/blk00000900 ( + .C(clk), + .D(\blk00000003/sig00000c8f ), + .R(ce), + .Q(\blk00000003/sig00000c65 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000336 ), + .R(\blk00000003/sig00000339 ), + .Q(\blk00000003/sig00000334 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000328 ), + .R(coef_ld), + .Q(\blk00000003/sig00000332 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000032e ), + .R(coef_ld), + .Q(\blk00000003/sig00000331 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000032b ), + .R(coef_ld), + .Q(\blk00000003/sig00000330 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002f6 ), + .R(coef_ld), + .Q(\blk00000003/sig000002f4 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk000008fa ( + .I0(\blk00000003/sig0000016b ), + .I1(sclr), + .O(\blk00000003/sig00000c8e ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk000008f9 ( + .C(clk), + .D(\blk00000003/sig00000c8e ), + .Q(\blk00000003/sig0000016b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000163 ), + .R(sclr), + .Q(\blk00000003/sig00000161 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000008f7 ( + .I0(\blk00000003/sig00000c5b ), + .I1(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig00000c4d ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000008f6 ( + .I0(\blk00000003/sig00000c5c ), + .I1(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig00000c50 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000008f5 ( + .I0(\blk00000003/sig00000c5d ), + .I1(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig00000c53 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000008f4 ( + .I0(\blk00000003/sig00000c5e ), + .I1(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig00000c56 ) + ); + LUT3 #( + .INIT ( 8'hDE )) + \blk00000003/blk000008f3 ( + .I0(\blk00000003/sig00000c5f ), + .I1(\blk00000003/sig00000be7 ), + .I2(\blk00000003/sig000002ad ), + .O(\blk00000003/sig00000c59 ) + ); + LUT3 #( + .INIT ( 8'h04 )) + \blk00000003/blk000008f2 ( + .I0(\blk00000003/sig000002ad ), + .I1(\blk00000003/sig0000004a ), + .I2(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig00000c4b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008f1 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000de ), + .I3(NlwRenamedSig_OI_dout_2[45]), + .O(\blk00000003/sig00000c49 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008f0 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000dd ), + .I3(NlwRenamedSig_OI_dout_2[46]), + .O(\blk00000003/sig00000c4a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ef ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000df ), + .I3(NlwRenamedSig_OI_dout_2[44]), + .O(\blk00000003/sig00000c48 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ee ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e1 ), + .I3(NlwRenamedSig_OI_dout_2[42]), + .O(\blk00000003/sig00000c46 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ed ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e0 ), + .I3(NlwRenamedSig_OI_dout_2[43]), + .O(\blk00000003/sig00000c47 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ec ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e2 ), + .I3(NlwRenamedSig_OI_dout_2[41]), + .O(\blk00000003/sig00000c45 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008eb ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e4 ), + .I3(NlwRenamedSig_OI_dout_2[39]), + .O(\blk00000003/sig00000c43 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ea ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e3 ), + .I3(NlwRenamedSig_OI_dout_2[40]), + .O(\blk00000003/sig00000c44 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e9 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e5 ), + .I3(NlwRenamedSig_OI_dout_2[38]), + .O(\blk00000003/sig00000c42 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e8 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e7 ), + .I3(NlwRenamedSig_OI_dout_2[36]), + .O(\blk00000003/sig00000c40 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e7 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e6 ), + .I3(NlwRenamedSig_OI_dout_2[37]), + .O(\blk00000003/sig00000c41 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e6 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e8 ), + .I3(NlwRenamedSig_OI_dout_2[35]), + .O(\blk00000003/sig00000c3f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e5 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000ea ), + .I3(NlwRenamedSig_OI_dout_2[33]), + .O(\blk00000003/sig00000c3d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e4 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e9 ), + .I3(NlwRenamedSig_OI_dout_2[34]), + .O(\blk00000003/sig00000c3e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e3 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000eb ), + .I3(NlwRenamedSig_OI_dout_2[32]), + .O(\blk00000003/sig00000c3c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e2 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000ed ), + .I3(NlwRenamedSig_OI_dout_2[30]), + .O(\blk00000003/sig00000c3a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e1 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000ec ), + .I3(NlwRenamedSig_OI_dout_2[31]), + .O(\blk00000003/sig00000c3b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e0 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000ee ), + .I3(NlwRenamedSig_OI_dout_2[29]), + .O(\blk00000003/sig00000c39 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008df ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f0 ), + .I3(NlwRenamedSig_OI_dout_2[27]), + .O(\blk00000003/sig00000c37 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008de ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000ef ), + .I3(NlwRenamedSig_OI_dout_2[28]), + .O(\blk00000003/sig00000c38 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008dd ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f1 ), + .I3(NlwRenamedSig_OI_dout_2[26]), + .O(\blk00000003/sig00000c36 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008dc ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f3 ), + .I3(NlwRenamedSig_OI_dout_2[24]), + .O(\blk00000003/sig00000c34 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008db ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f2 ), + .I3(NlwRenamedSig_OI_dout_2[25]), + .O(\blk00000003/sig00000c35 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008da ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f4 ), + .I3(NlwRenamedSig_OI_dout_2[23]), + .O(\blk00000003/sig00000c33 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d9 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f6 ), + .I3(NlwRenamedSig_OI_dout_2[21]), + .O(\blk00000003/sig00000c31 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d8 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f5 ), + .I3(NlwRenamedSig_OI_dout_2[22]), + .O(\blk00000003/sig00000c32 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d7 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f7 ), + .I3(NlwRenamedSig_OI_dout_2[20]), + .O(\blk00000003/sig00000c30 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d6 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f9 ), + .I3(NlwRenamedSig_OI_dout_2[18]), + .O(\blk00000003/sig00000c2e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d5 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f8 ), + .I3(NlwRenamedSig_OI_dout_2[19]), + .O(\blk00000003/sig00000c2f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d4 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000fa ), + .I3(NlwRenamedSig_OI_dout_2[17]), + .O(\blk00000003/sig00000c2d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d3 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c8d ), + .I3(NlwRenamedSig_OI_dout_2[15]), + .O(\blk00000003/sig00000c2b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d2 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000fb ), + .I3(NlwRenamedSig_OI_dout_2[16]), + .O(\blk00000003/sig00000c2c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d1 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c8c ), + .I3(NlwRenamedSig_OI_dout_2[14]), + .O(\blk00000003/sig00000c2a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d0 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c8b ), + .I3(NlwRenamedSig_OI_dout_2[12]), + .O(\blk00000003/sig00000c28 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008cf ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c8a ), + .I3(NlwRenamedSig_OI_dout_2[13]), + .O(\blk00000003/sig00000c29 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ce ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c89 ), + .I3(NlwRenamedSig_OI_dout_2[11]), + .O(\blk00000003/sig00000c27 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008cd ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c88 ), + .I3(NlwRenamedSig_OI_dout_2[9]), + .O(\blk00000003/sig00000c25 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008cc ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c87 ), + .I3(NlwRenamedSig_OI_dout_2[10]), + .O(\blk00000003/sig00000c26 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008cb ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c86 ), + .I3(NlwRenamedSig_OI_dout_2[8]), + .O(\blk00000003/sig00000c24 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ca ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c85 ), + .I3(NlwRenamedSig_OI_dout_2[6]), + .O(\blk00000003/sig00000c22 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c9 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c84 ), + .I3(NlwRenamedSig_OI_dout_2[7]), + .O(\blk00000003/sig00000c23 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c8 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c83 ), + .I3(NlwRenamedSig_OI_dout_2[5]), + .O(\blk00000003/sig00000c21 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c7 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c82 ), + .I3(NlwRenamedSig_OI_dout_2[3]), + .O(\blk00000003/sig00000c1f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c6 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c81 ), + .I3(NlwRenamedSig_OI_dout_2[4]), + .O(\blk00000003/sig00000c20 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c5 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c80 ), + .I3(NlwRenamedSig_OI_dout_2[2]), + .O(\blk00000003/sig00000c1e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c4 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c7f ), + .I3(NlwRenamedSig_OI_dout_2[1]), + .O(\blk00000003/sig00000c1d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c3 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000133 ), + .I3(NlwRenamedSig_OI_dout_1[46]), + .O(\blk00000003/sig00000c1b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c2 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c7e ), + .I3(NlwRenamedSig_OI_dout_2[0]), + .O(\blk00000003/sig00000c1c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c1 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000134 ), + .I3(NlwRenamedSig_OI_dout_1[45]), + .O(\blk00000003/sig00000c1a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c0 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000136 ), + .I3(NlwRenamedSig_OI_dout_1[43]), + .O(\blk00000003/sig00000c18 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008bf ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000135 ), + .I3(NlwRenamedSig_OI_dout_1[44]), + .O(\blk00000003/sig00000c19 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008be ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000137 ), + .I3(NlwRenamedSig_OI_dout_1[42]), + .O(\blk00000003/sig00000c17 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008bd ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000139 ), + .I3(NlwRenamedSig_OI_dout_1[40]), + .O(\blk00000003/sig00000c15 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008bc ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000138 ), + .I3(NlwRenamedSig_OI_dout_1[41]), + .O(\blk00000003/sig00000c16 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008bb ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000013a ), + .I3(NlwRenamedSig_OI_dout_1[39]), + .O(\blk00000003/sig00000c14 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ba ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000013c ), + .I3(NlwRenamedSig_OI_dout_1[37]), + .O(\blk00000003/sig00000c12 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b9 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000013b ), + .I3(NlwRenamedSig_OI_dout_1[38]), + .O(\blk00000003/sig00000c13 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b8 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000013d ), + .I3(NlwRenamedSig_OI_dout_1[36]), + .O(\blk00000003/sig00000c11 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b7 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000013f ), + .I3(NlwRenamedSig_OI_dout_1[34]), + .O(\blk00000003/sig00000c0f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b6 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000013e ), + .I3(NlwRenamedSig_OI_dout_1[35]), + .O(\blk00000003/sig00000c10 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b5 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000140 ), + .I3(NlwRenamedSig_OI_dout_1[33]), + .O(\blk00000003/sig00000c0e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b4 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000142 ), + .I3(NlwRenamedSig_OI_dout_1[31]), + .O(\blk00000003/sig00000c0c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b3 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000141 ), + .I3(NlwRenamedSig_OI_dout_1[32]), + .O(\blk00000003/sig00000c0d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b2 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000143 ), + .I3(NlwRenamedSig_OI_dout_1[30]), + .O(\blk00000003/sig00000c0b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b1 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000145 ), + .I3(NlwRenamedSig_OI_dout_1[28]), + .O(\blk00000003/sig00000c09 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b0 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000144 ), + .I3(NlwRenamedSig_OI_dout_1[29]), + .O(\blk00000003/sig00000c0a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008af ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000146 ), + .I3(NlwRenamedSig_OI_dout_1[27]), + .O(\blk00000003/sig00000c08 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ae ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000148 ), + .I3(NlwRenamedSig_OI_dout_1[25]), + .O(\blk00000003/sig00000c06 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ad ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000147 ), + .I3(NlwRenamedSig_OI_dout_1[26]), + .O(\blk00000003/sig00000c07 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ac ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000149 ), + .I3(NlwRenamedSig_OI_dout_1[24]), + .O(\blk00000003/sig00000c05 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ab ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000014b ), + .I3(NlwRenamedSig_OI_dout_1[22]), + .O(\blk00000003/sig00000c03 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008aa ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000014a ), + .I3(NlwRenamedSig_OI_dout_1[23]), + .O(\blk00000003/sig00000c04 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a9 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000014c ), + .I3(NlwRenamedSig_OI_dout_1[21]), + .O(\blk00000003/sig00000c02 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a8 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000014e ), + .I3(NlwRenamedSig_OI_dout_1[19]), + .O(\blk00000003/sig00000c00 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a7 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000014d ), + .I3(NlwRenamedSig_OI_dout_1[20]), + .O(\blk00000003/sig00000c01 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a6 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000014f ), + .I3(NlwRenamedSig_OI_dout_1[18]), + .O(\blk00000003/sig00000bff ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a5 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000151 ), + .I3(NlwRenamedSig_OI_dout_1[16]), + .O(\blk00000003/sig00000bfd ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a4 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000150 ), + .I3(NlwRenamedSig_OI_dout_1[17]), + .O(\blk00000003/sig00000bfe ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a3 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c7d ), + .I3(NlwRenamedSig_OI_dout_1[15]), + .O(\blk00000003/sig00000bfc ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a2 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c7c ), + .I3(NlwRenamedSig_OI_dout_1[13]), + .O(\blk00000003/sig00000bfa ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a1 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c7b ), + .I3(NlwRenamedSig_OI_dout_1[14]), + .O(\blk00000003/sig00000bfb ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a0 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c7a ), + .I3(NlwRenamedSig_OI_dout_1[12]), + .O(\blk00000003/sig00000bf9 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000089f ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c79 ), + .I3(NlwRenamedSig_OI_dout_1[10]), + .O(\blk00000003/sig00000bf7 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000089e ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c78 ), + .I3(NlwRenamedSig_OI_dout_1[11]), + .O(\blk00000003/sig00000bf8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000089d ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c77 ), + .I3(NlwRenamedSig_OI_dout_1[9]), + .O(\blk00000003/sig00000bf6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000089c ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c76 ), + .I3(NlwRenamedSig_OI_dout_1[7]), + .O(\blk00000003/sig00000bf4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000089b ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c75 ), + .I3(NlwRenamedSig_OI_dout_1[8]), + .O(\blk00000003/sig00000bf5 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000089a ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c74 ), + .I3(NlwRenamedSig_OI_dout_1[6]), + .O(\blk00000003/sig00000bf3 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000899 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c73 ), + .I3(NlwRenamedSig_OI_dout_1[4]), + .O(\blk00000003/sig00000bf1 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000898 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c72 ), + .I3(NlwRenamedSig_OI_dout_1[5]), + .O(\blk00000003/sig00000bf2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000897 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c71 ), + .I3(NlwRenamedSig_OI_dout_1[3]), + .O(\blk00000003/sig00000bf0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000896 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c70 ), + .I3(NlwRenamedSig_OI_dout_1[1]), + .O(\blk00000003/sig00000bee ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000895 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c6f ), + .I3(NlwRenamedSig_OI_dout_1[2]), + .O(\blk00000003/sig00000bef ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000894 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c6e ), + .I3(NlwRenamedSig_OI_dout_1[0]), + .O(\blk00000003/sig00000bed ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000893 ( + .I0(\blk00000003/sig00000bec ), + .I1(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig00000bd6 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000892 ( + .I0(ce), + .I1(\blk00000003/sig000002af ), + .O(\blk00000003/sig00000c6d ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000891 ( + .I0(ce), + .I1(\blk00000003/sig00000a0f ), + .O(\blk00000003/sig00000c6c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000890 ( + .I0(ce), + .I1(\blk00000003/sig00000a0a ), + .O(\blk00000003/sig00000c6b ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000088f ( + .I0(ce), + .I1(\blk00000003/sig00000a03 ), + .O(\blk00000003/sig00000c6a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000088e ( + .I0(ce), + .I1(\blk00000003/sig000009f7 ), + .O(\blk00000003/sig00000c69 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000088d ( + .I0(ce), + .I1(\blk00000003/sig000009f8 ), + .O(\blk00000003/sig00000c68 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk0000088c ( + .I0(sclr), + .I1(\blk00000003/sig00000c67 ), + .O(\blk00000003/sig00000372 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000088b ( + .I0(\blk00000003/sig00000378 ), + .I1(\blk00000003/sig00000c66 ), + .O(\blk00000003/sig0000036d ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000088a ( + .I0(\blk00000003/sig0000036a ), + .I1(\blk00000003/sig00000378 ), + .O(\blk00000003/sig0000036b ) + ); + LUT3 #( + .INIT ( 8'hDA )) + \blk00000003/blk00000889 ( + .I0(\blk00000003/sig00000378 ), + .I1(\blk00000003/sig00000c66 ), + .I2(\blk00000003/sig0000036f ), + .O(\blk00000003/sig00000370 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000888 ( + .I0(\blk00000003/sig00000368 ), + .I1(\blk00000003/sig000002a8 ), + .O(\blk00000003/sig00000366 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000887 ( + .I0(nd), + .I1(\blk00000003/sig0000015f ), + .O(\blk00000003/sig00000362 ) + ); + LUT3 #( + .INIT ( 8'hF8 )) + \blk00000003/blk00000886 ( + .I0(nd), + .I1(\blk00000003/sig0000015f ), + .I2(\blk00000003/sig000002b9 ), + .O(\blk00000003/sig00000360 ) + ); + LUT3 #( + .INIT ( 8'hDA )) + \blk00000003/blk00000885 ( + .I0(nd), + .I1(\blk00000003/sig0000015f ), + .I2(\blk00000003/sig000002ba ), + .O(\blk00000003/sig0000035d ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000884 ( + .I0(\blk00000003/sig0000031c ), + .I1(\blk00000003/sig00000315 ), + .O(\blk00000003/sig00000359 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000883 ( + .I0(\blk00000003/sig0000031c ), + .I1(\blk00000003/sig00000314 ), + .O(\blk00000003/sig00000356 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000882 ( + .I0(\blk00000003/sig0000031c ), + .I1(\blk00000003/sig00000318 ), + .O(\blk00000003/sig00000354 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000881 ( + .I0(\blk00000003/sig0000031c ), + .I1(\blk00000003/sig0000031a ), + .I2(\blk00000003/sig00000322 ), + .O(\blk00000003/sig0000034f ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000880 ( + .I0(\blk00000003/sig0000031a ), + .I1(\blk00000003/sig00000318 ), + .I2(\blk00000003/sig0000031c ), + .O(\blk00000003/sig00000351 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000087f ( + .I0(\blk00000003/sig00000318 ), + .I1(\blk00000003/sig00000315 ), + .O(\blk00000003/sig00000348 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000087e ( + .I0(\blk00000003/sig00000318 ), + .I1(\blk00000003/sig00000314 ), + .O(\blk00000003/sig00000346 ) + ); + LUT3 #( + .INIT ( 8'hBF )) + \blk00000003/blk0000087d ( + .I0(\blk00000003/sig0000031c ), + .I1(\blk00000003/sig00000318 ), + .I2(\blk00000003/sig00000312 ), + .O(\blk00000003/sig00000341 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000087c ( + .I0(\blk00000003/sig00000317 ), + .I1(\blk00000003/sig00000318 ), + .O(\blk00000003/sig0000033d ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk0000087b ( + .I0(\blk00000003/sig00000316 ), + .I1(\blk00000003/sig00000318 ), + .I2(\blk00000003/sig00000322 ), + .O(\blk00000003/sig0000033f ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk0000087a ( + .I0(\blk00000003/sig00000325 ), + .I1(\blk00000003/sig00000c65 ), + .O(\blk00000003/sig00000338 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000879 ( + .I0(\blk00000003/sig000002f8 ), + .I1(coef_we), + .I2(\blk00000003/sig00000302 ), + .O(\blk00000003/sig0000032f ) + ); + LUT4 #( + .INIT ( 16'hDAAA )) + \blk00000003/blk00000878 ( + .I0(\blk00000003/sig00000332 ), + .I1(\blk00000003/sig000002f8 ), + .I2(\blk00000003/sig00000302 ), + .I3(coef_we), + .O(\blk00000003/sig00000327 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000877 ( + .I0(coef_ld), + .I1(\blk00000003/sig00000325 ), + .O(\blk00000003/sig0000031b ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000876 ( + .I0(coef_we), + .I1(\blk00000003/sig00000302 ), + .O(\blk00000003/sig000002f9 ) + ); + LUT3 #( + .INIT ( 8'h20 )) + \blk00000003/blk00000875 ( + .I0(coef_we), + .I1(coef_ld), + .I2(\blk00000003/sig00000310 ), + .O(\blk00000003/sig00000323 ) + ); + LUT3 #( + .INIT ( 8'h20 )) + \blk00000003/blk00000874 ( + .I0(\blk00000003/sig00000330 ), + .I1(\blk00000003/sig00000331 ), + .I2(\blk00000003/sig00000332 ), + .O(\blk00000003/sig000002fe ) + ); + LUT3 #( + .INIT ( 8'h04 )) + \blk00000003/blk00000873 ( + .I0(\blk00000003/sig00000331 ), + .I1(\blk00000003/sig00000330 ), + .I2(\blk00000003/sig00000332 ), + .O(\blk00000003/sig000002fc ) + ); + LUT3 #( + .INIT ( 8'hBF )) + \blk00000003/blk00000872 ( + .I0(\blk00000003/sig00000325 ), + .I1(\blk00000003/sig0000030e ), + .I2(coef_ld), + .O(\blk00000003/sig000002f3 ) + ); + LUT3 #( + .INIT ( 8'hBF )) + \blk00000003/blk00000871 ( + .I0(\blk00000003/sig00000310 ), + .I1(coef_we), + .I2(\blk00000003/sig0000030e ), + .O(\blk00000003/sig000002f0 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000870 ( + .I0(\blk00000003/sig000002f4 ), + .I1(coef_we), + .O(\blk00000003/sig000002f5 ) + ); + LUT5 #( + .INIT ( 32'hFFFF2AAA )) + \blk00000003/blk0000086f ( + .I0(\blk00000003/sig00000310 ), + .I1(coef_we), + .I2(\blk00000003/sig00000302 ), + .I3(\blk00000003/sig000002f8 ), + .I4(coef_ld), + .O(\blk00000003/sig0000030f ) + ); + LUT4 #( + .INIT ( 16'hFF8A )) + \blk00000003/blk0000086e ( + .I0(\blk00000003/sig0000030e ), + .I1(\blk00000003/sig00000310 ), + .I2(coef_we), + .I3(coef_ld), + .O(\blk00000003/sig0000030d ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000086d ( + .I0(\blk00000003/sig00000159 ), + .I1(nd), + .O(\blk00000003/sig000002b7 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000086c ( + .I0(\blk00000003/sig00000173 ), + .I1(\blk00000003/sig000002ad ), + .O(\blk00000003/sig000002b5 ) + ); + LUT3 #( + .INIT ( 8'h10 )) + \blk00000003/blk0000086b ( + .I0(\blk00000003/sig00000173 ), + .I1(\blk00000003/sig00000be7 ), + .I2(\blk00000003/sig000002ad ), + .O(\blk00000003/sig00000174 ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk0000086a ( + .I0(sclr), + .I1(ce), + .I2(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig000002ae ) + ); + LUT5 #( + .INIT ( 32'h00002000 )) + \blk00000003/blk00000869 ( + .I0(\blk00000003/sig00000c5b ), + .I1(\blk00000003/sig00000c5c ), + .I2(\blk00000003/sig00000c5d ), + .I3(\blk00000003/sig00000c5e ), + .I4(\blk00000003/sig00000c5f ), + .O(\blk00000003/sig00000177 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk00000868 ( + .I0(\blk00000003/sig000002a8 ), + .I1(\blk00000003/sig0000029c ), + .I2(\blk00000003/sig000002b6 ), + .O(\blk00000003/sig000002a7 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000867 ( + .I0(\blk00000003/sig00000369 ), + .I1(\blk00000003/sig000002b2 ), + .O(\blk00000003/sig000002a9 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00000866 ( + .I0(ce), + .I1(\blk00000003/sig00000c61 ), + .I2(\blk00000003/sig00000169 ), + .O(\blk00000003/sig00000168 ) + ); + LUT3 #( + .INIT ( 8'h72 )) + \blk00000003/blk00000865 ( + .I0(ce), + .I1(\blk00000003/sig00000c61 ), + .I2(\blk00000003/sig00000167 ), + .O(\blk00000003/sig00000166 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000864 ( + .I0(\blk00000003/sig00000161 ), + .I1(\blk00000003/sig0000029c ), + .O(\blk00000003/sig00000162 ) + ); + LUT5 #( + .INIT ( 32'hCEEE8AAA )) + \blk00000003/blk00000863 ( + .I0(\blk00000003/sig0000029c ), + .I1(\blk00000003/sig000002b6 ), + .I2(\blk00000003/sig000002a6 ), + .I3(\blk00000003/sig000002a8 ), + .I4(\blk00000003/sig000002a4 ), + .O(\blk00000003/sig000002a5 ) + ); + LUT4 #( + .INIT ( 16'h8808 )) + \blk00000003/blk00000862 ( + .I0(\blk00000003/sig000002a6 ), + .I1(\blk00000003/sig00000c64 ), + .I2(\blk00000003/sig000002a8 ), + .I3(\blk00000003/sig000002b6 ), + .O(\blk00000003/sig000002a1 ) + ); + LUT3 #( + .INIT ( 8'h09 )) + \blk00000003/blk00000861 ( + .I0(\blk00000003/sig00000c63 ), + .I1(\blk00000003/sig000002b9 ), + .I2(\blk00000003/sig000002ba ), + .O(\blk00000003/sig0000015d ) + ); + LUT4 #( + .INIT ( 16'h5540 )) + \blk00000003/blk00000860 ( + .I0(\blk00000003/sig000002b6 ), + .I1(\blk00000003/sig000002a6 ), + .I2(\blk00000003/sig000002a8 ), + .I3(\blk00000003/sig000002a4 ), + .O(\blk00000003/sig000002a3 ) + ); + LUT3 #( + .INIT ( 8'h9A )) + \blk00000003/blk0000085f ( + .I0(\blk00000003/sig00000368 ), + .I1(\blk00000003/sig00000369 ), + .I2(\blk00000003/sig000002b2 ), + .O(\blk00000003/sig000002ab ) + ); + LUT4 #( + .INIT ( 16'hFDA8 )) + \blk00000003/blk0000085e ( + .I0(ce), + .I1(\blk00000003/sig00000c61 ), + .I2(\blk00000003/sig00000c62 ), + .I3(\blk00000003/sig00000165 ), + .O(\blk00000003/sig00000164 ) + ); + MUXCY \blk00000003/blk0000085d ( + .CI(\blk00000003/sig00000049 ), + .DI(NlwRenamedSig_OI_rfd), + .S(\blk00000003/sig00000c60 ), + .O(\blk00000003/sig00000c58 ) + ); + MUXCY_L \blk00000003/blk0000085c ( + .CI(\blk00000003/sig00000c58 ), + .DI(\blk00000003/sig00000c5f ), + .S(\blk00000003/sig00000c59 ), + .LO(\blk00000003/sig00000c55 ) + ); + MUXCY_L \blk00000003/blk0000085b ( + .CI(\blk00000003/sig00000c55 ), + .DI(\blk00000003/sig00000c5e ), + .S(\blk00000003/sig00000c56 ), + .LO(\blk00000003/sig00000c52 ) + ); + MUXCY_L \blk00000003/blk0000085a ( + .CI(\blk00000003/sig00000c52 ), + .DI(\blk00000003/sig00000c5d ), + .S(\blk00000003/sig00000c53 ), + .LO(\blk00000003/sig00000c4f ) + ); + MUXCY_L \blk00000003/blk00000859 ( + .CI(\blk00000003/sig00000c4f ), + .DI(\blk00000003/sig00000c5c ), + .S(\blk00000003/sig00000c50 ), + .LO(\blk00000003/sig00000c4c ) + ); + MUXCY_D \blk00000003/blk00000858 ( + .CI(\blk00000003/sig00000c4c ), + .DI(\blk00000003/sig00000c5b ), + .S(\blk00000003/sig00000c4d ), + .O(\NLW_blk00000003/blk00000858_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk00000858_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000857 ( + .CI(\blk00000003/sig00000c58 ), + .LI(\blk00000003/sig00000c59 ), + .O(\blk00000003/sig00000c5a ) + ); + XORCY \blk00000003/blk00000856 ( + .CI(\blk00000003/sig00000c55 ), + .LI(\blk00000003/sig00000c56 ), + .O(\blk00000003/sig00000c57 ) + ); + XORCY \blk00000003/blk00000855 ( + .CI(\blk00000003/sig00000c52 ), + .LI(\blk00000003/sig00000c53 ), + .O(\blk00000003/sig00000c54 ) + ); + XORCY \blk00000003/blk00000854 ( + .CI(\blk00000003/sig00000c4f ), + .LI(\blk00000003/sig00000c50 ), + .O(\blk00000003/sig00000c51 ) + ); + XORCY \blk00000003/blk00000853 ( + .CI(\blk00000003/sig00000c4c ), + .LI(\blk00000003/sig00000c4d ), + .O(\blk00000003/sig00000c4e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000852 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c4b ), + .R(sclr), + .Q(\blk00000003/sig0000004a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000851 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c4a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000850 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c49 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000084f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c48 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000084e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c47 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000084d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c46 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000084c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c45 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000084b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c44 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000084a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c43 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000849 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c42 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000848 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c41 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000847 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c40 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000846 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c3f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000845 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c3e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000844 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c3d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000843 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c3c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000842 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c3b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000841 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c3a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000840 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c39 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000083f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c38 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000083e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c37 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000083d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c36 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000083c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c35 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000083b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c34 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000083a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c33 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000839 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c32 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000838 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c31 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000837 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c30 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000836 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c2f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000835 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c2e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000834 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c2d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000833 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c2c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000832 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c2b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000831 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c2a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000830 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c29 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000082f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c28 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000082e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c27 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000082d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c26 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000082c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c25 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000082b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c24 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000082a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c23 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000829 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c22 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000828 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c21 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000827 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c20 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000826 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c1f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000825 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c1e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000824 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c1d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000823 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c1c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[0]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000822 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c1b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000821 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c1a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000820 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c19 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000081f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c18 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000081e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c17 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000081d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c16 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000081c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c15 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000081b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c14 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000081a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c13 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000819 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c12 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000818 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c11 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000817 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c10 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000816 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c0f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000815 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c0e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000814 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c0d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000813 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c0c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000812 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c0b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000811 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c0a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000810 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c09 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000080f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c08 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000080e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c07 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000080d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c06 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000080c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c05 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000080b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c04 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000080a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c03 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000809 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c02 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000808 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c01 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000807 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c00 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000806 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bff ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000805 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bfe ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000804 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bfd ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000803 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bfc ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000802 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bfb ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000801 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bfa ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000800 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf9 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf8 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf7 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf6 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf5 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf4 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf3 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf2 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf1 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf0 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bef ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bee ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bed ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[0]) + ); + MUXCY_L \blk00000003/blk000007f3 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000bec ), + .S(\blk00000003/sig00000bd6 ), + .LO(\blk00000003/sig00000be4 ) + ); + MUXCY_L \blk00000003/blk000007f2 ( + .CI(\blk00000003/sig00000be4 ), + .DI(\blk00000003/sig00000beb ), + .S(\blk00000003/sig00000be5 ), + .LO(\blk00000003/sig00000be1 ) + ); + MUXCY_L \blk00000003/blk000007f1 ( + .CI(\blk00000003/sig00000be1 ), + .DI(\blk00000003/sig00000bea ), + .S(\blk00000003/sig00000be2 ), + .LO(\blk00000003/sig00000bde ) + ); + MUXCY_L \blk00000003/blk000007f0 ( + .CI(\blk00000003/sig00000bde ), + .DI(\blk00000003/sig00000be9 ), + .S(\blk00000003/sig00000bdf ), + .LO(\blk00000003/sig00000bdb ) + ); + MUXCY_L \blk00000003/blk000007ef ( + .CI(\blk00000003/sig00000bdb ), + .DI(\blk00000003/sig00000be8 ), + .S(\blk00000003/sig00000bdc ), + .LO(\blk00000003/sig00000bd8 ) + ); + MUXCY_D \blk00000003/blk000007ee ( + .CI(\blk00000003/sig00000bd8 ), + .DI(\blk00000003/sig00000be7 ), + .S(\blk00000003/sig00000bd9 ), + .O(\NLW_blk00000003/blk000007ee_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000007ee_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000007ed ( + .CI(\blk00000003/sig00000be4 ), + .LI(\blk00000003/sig00000be5 ), + .O(\blk00000003/sig00000be6 ) + ); + XORCY \blk00000003/blk000007ec ( + .CI(\blk00000003/sig00000be1 ), + .LI(\blk00000003/sig00000be2 ), + .O(\blk00000003/sig00000be3 ) + ); + XORCY \blk00000003/blk000007eb ( + .CI(\blk00000003/sig00000bde ), + .LI(\blk00000003/sig00000bdf ), + .O(\blk00000003/sig00000be0 ) + ); + XORCY \blk00000003/blk000007ea ( + .CI(\blk00000003/sig00000bdb ), + .LI(\blk00000003/sig00000bdc ), + .O(\blk00000003/sig00000bdd ) + ); + XORCY \blk00000003/blk000007e9 ( + .CI(\blk00000003/sig00000bd8 ), + .LI(\blk00000003/sig00000bd9 ), + .O(\blk00000003/sig00000bda ) + ); + XORCY \blk00000003/blk000007e8 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000bd6 ), + .O(\blk00000003/sig00000bd7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c0 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000777 ), + .R(sclr), + .Q(\blk00000003/sig00000a26 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bf ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000776 ), + .R(sclr), + .Q(\blk00000003/sig00000a25 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007be ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000775 ), + .R(sclr), + .Q(\blk00000003/sig00000a24 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bd ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000774 ), + .R(sclr), + .Q(\blk00000003/sig00000a23 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bc ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000773 ), + .R(sclr), + .Q(\blk00000003/sig00000a22 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bb ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000772 ), + .R(sclr), + .Q(\blk00000003/sig00000a21 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ba ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000771 ), + .R(sclr), + .Q(\blk00000003/sig00000a20 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b9 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000770 ), + .R(sclr), + .Q(\blk00000003/sig00000a1f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b8 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig0000076f ), + .R(sclr), + .Q(\blk00000003/sig00000a1e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b7 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig0000076e ), + .R(sclr), + .Q(\blk00000003/sig00000a1d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b6 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig0000076d ), + .R(sclr), + .Q(\blk00000003/sig00000a1c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b5 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig0000076c ), + .R(sclr), + .Q(\blk00000003/sig00000a1b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b4 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig0000076b ), + .R(sclr), + .Q(\blk00000003/sig00000a1a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b3 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig0000076a ), + .R(sclr), + .Q(\blk00000003/sig00000a19 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b2 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000769 ), + .R(sclr), + .Q(\blk00000003/sig00000a18 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b1 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000768 ), + .R(sclr), + .Q(\blk00000003/sig00000a17 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b0 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000004ed ), + .R(sclr), + .Q(\blk00000003/sig00000b6a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007af ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000004ec ), + .R(sclr), + .Q(\blk00000003/sig00000b69 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ae ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000004eb ), + .R(sclr), + .Q(\blk00000003/sig00000b68 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ad ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000004ea ), + .R(sclr), + .Q(\blk00000003/sig00000b67 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ac ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000004e9 ), + .R(sclr), + .Q(\blk00000003/sig00000b66 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ab ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000004e8 ), + .R(sclr), + .Q(\blk00000003/sig00000b65 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007aa ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000004e7 ), + .R(sclr), + .Q(\blk00000003/sig00000b64 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a9 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000004e6 ), + .R(sclr), + .Q(\blk00000003/sig00000b63 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a8 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000007c7 ), + .R(sclr), + .Q(\blk00000003/sig00000a36 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a7 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000007c6 ), + .R(sclr), + .Q(\blk00000003/sig00000a35 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a6 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000007c5 ), + .R(sclr), + .Q(\blk00000003/sig00000a34 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a5 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000007c4 ), + .R(sclr), + .Q(\blk00000003/sig00000a33 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a4 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000007c3 ), + .R(sclr), + .Q(\blk00000003/sig00000a32 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a3 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000007c2 ), + .R(sclr), + .Q(\blk00000003/sig00000a31 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a2 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000007c1 ), + .R(sclr), + .Q(\blk00000003/sig00000a30 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a1 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000007c0 ), + .R(sclr), + .Q(\blk00000003/sig00000a2f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a0 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig000007bf ), + .R(sclr), + .Q(\blk00000003/sig00000a2e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079f ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig000007be ), + .R(sclr), + .Q(\blk00000003/sig00000a2d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079e ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig000007bd ), + .R(sclr), + .Q(\blk00000003/sig00000a2c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079d ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig000007bc ), + .R(sclr), + .Q(\blk00000003/sig00000a2b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079c ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig000007bb ), + .R(sclr), + .Q(\blk00000003/sig00000a2a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079b ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig000007ba ), + .R(sclr), + .Q(\blk00000003/sig00000a29 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079a ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig000007b9 ), + .R(sclr), + .Q(\blk00000003/sig00000a28 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000799 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig000007b8 ), + .R(sclr), + .Q(\blk00000003/sig00000a27 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000798 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig0000053f ), + .R(sclr), + .Q(\blk00000003/sig00000b72 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000797 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig0000053e ), + .R(sclr), + .Q(\blk00000003/sig00000b71 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000796 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig0000053d ), + .R(sclr), + .Q(\blk00000003/sig00000b70 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000795 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig0000053c ), + .R(sclr), + .Q(\blk00000003/sig00000b6f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000794 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig0000053b ), + .R(sclr), + .Q(\blk00000003/sig00000b6e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000793 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig0000053a ), + .R(sclr), + .Q(\blk00000003/sig00000b6d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000792 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig00000539 ), + .R(sclr), + .Q(\blk00000003/sig00000b6c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000791 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig00000538 ), + .R(sclr), + .Q(\blk00000003/sig00000b6b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000375 ), + .R(sclr), + .Q(\blk00000003/sig00000a12 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000037b ), + .R(sclr), + .Q(\blk00000003/sig00000a11 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000036a ), + .R(sclr), + .Q(\blk00000003/sig00000a14 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000139 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a16 ), + .R(sclr), + .Q(\blk00000003/sig00000a10 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000138 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a15 ), + .R(sclr), + .Q(\blk00000003/sig00000a0f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000137 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000036f ), + .R(sclr), + .Q(\blk00000003/sig00000a13 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000136 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a14 ), + .R(sclr), + .Q(\blk00000003/sig00000a0d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000135 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a13 ), + .R(sclr), + .Q(\blk00000003/sig00000a0e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000134 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a12 ), + .R(sclr), + .Q(\blk00000003/sig00000a0c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000133 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a11 ), + .R(sclr), + .Q(\blk00000003/sig00000a0b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000132 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a10 ), + .R(sclr), + .Q(\blk00000003/sig00000a09 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000131 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a0f ), + .R(sclr), + .Q(\blk00000003/sig00000a0a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a0e ), + .R(sclr), + .Q(\blk00000003/sig00000a08 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a0d ), + .R(sclr), + .Q(\blk00000003/sig00000a07 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a0c ), + .R(sclr), + .Q(\blk00000003/sig00000a05 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a0b ), + .R(sclr), + .Q(\blk00000003/sig00000a04 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a0a ), + .R(sclr), + .Q(\blk00000003/sig00000a03 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a09 ), + .R(sclr), + .Q(\blk00000003/sig00000a06 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a08 ), + .R(sclr), + .Q(\blk00000003/sig00000a01 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000129 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a07 ), + .R(sclr), + .Q(\blk00000003/sig000009ff ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000128 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a06 ), + .R(sclr), + .Q(\blk00000003/sig000009f9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000127 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a05 ), + .R(sclr), + .Q(\blk00000003/sig000009fd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000126 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a04 ), + .R(sclr), + .Q(\blk00000003/sig000009fb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000125 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a03 ), + .R(sclr), + .Q(\blk00000003/sig000009f7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000124 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a01 ), + .R(sclr), + .Q(\blk00000003/sig00000a02 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000123 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ff ), + .R(sclr), + .Q(\blk00000003/sig00000a00 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000122 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009fd ), + .R(sclr), + .Q(\blk00000003/sig000009fe ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000121 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009fb ), + .R(sclr), + .Q(\blk00000003/sig000009fc ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f9 ), + .R(sclr), + .Q(\blk00000003/sig000009fa ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f7 ), + .R(sclr), + .Q(\blk00000003/sig000009f8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f5 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009f6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f4 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009f5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f3 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009f4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f2 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009f3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000030c ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009f2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ef ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009f1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000118 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ee ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009f0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ed ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009ef ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000116 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ec ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009ee ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000115 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009eb ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009ed ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000114 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ea ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009ec ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000113 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e9 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009eb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000112 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e8 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009ea ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000111 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000337 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009e9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000110 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000334 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009e8 ) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010f ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010f_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010f_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000009c8 , \blk00000003/sig000009c9 , \blk00000003/sig000009ca , +\blk00000003/sig000009cb , \blk00000003/sig000009cc , \blk00000003/sig000009cd , \blk00000003/sig000009ce , \blk00000003/sig000009cf , +\blk00000003/sig000009d0 , \blk00000003/sig000009d1 , \blk00000003/sig000009d2 , \blk00000003/sig000009d3 , \blk00000003/sig000009d4 , +\blk00000003/sig000009d5 , \blk00000003/sig000009d6 , \blk00000003/sig000009d7 }), + .BCOUT({\NLW_blk00000003/blk0000010f_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000998 , \blk00000003/sig00000999 , \blk00000003/sig0000099a , \blk00000003/sig0000099b , \blk00000003/sig0000099c , +\blk00000003/sig0000099d , \blk00000003/sig0000099e , \blk00000003/sig0000099f , \blk00000003/sig000009a0 , \blk00000003/sig000009a1 , +\blk00000003/sig000009a2 , \blk00000003/sig000009a3 , \blk00000003/sig000009a4 , \blk00000003/sig000009a5 , \blk00000003/sig000009a6 , +\blk00000003/sig000009a7 , \blk00000003/sig000009a8 , \blk00000003/sig000009a9 , \blk00000003/sig000009aa , \blk00000003/sig000009ab , +\blk00000003/sig000009ac , \blk00000003/sig000009ad , \blk00000003/sig000009ae , \blk00000003/sig000009af , \blk00000003/sig000009b0 , +\blk00000003/sig000009b1 , \blk00000003/sig000009b2 , \blk00000003/sig000009b3 , \blk00000003/sig000009b4 , \blk00000003/sig000009b5 , +\blk00000003/sig000009b6 , \blk00000003/sig000009b7 , \blk00000003/sig000009b8 , \blk00000003/sig000009b9 , \blk00000003/sig000009ba , +\blk00000003/sig000009bb , \blk00000003/sig000009bc , \blk00000003/sig000009bd , \blk00000003/sig000009be , \blk00000003/sig000009bf , +\blk00000003/sig000009c0 , \blk00000003/sig000009c1 , \blk00000003/sig000009c2 , \blk00000003/sig000009c3 , \blk00000003/sig000009c4 , +\blk00000003/sig000009c5 , \blk00000003/sig000009c6 , \blk00000003/sig000009c7 }), + .C({\NLW_blk00000003/blk0000010f_C<47>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<45>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<44>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<42>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<41>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<39>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<38>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<36>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010f_P<47>_UNCONNECTED , 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\NLW_blk00000003/blk0000010f_P<26>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<24>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<23>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<21>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<20>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<7>_UNCONNECTED , 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\blk00000003/sig000009e6 , \blk00000003/sig000009e7 }), + .PCOUT({\blk00000003/sig00000788 , \blk00000003/sig00000789 , \blk00000003/sig0000078a , \blk00000003/sig0000078b , \blk00000003/sig0000078c , +\blk00000003/sig0000078d , \blk00000003/sig0000078e , \blk00000003/sig0000078f , \blk00000003/sig00000790 , \blk00000003/sig00000791 , +\blk00000003/sig00000792 , \blk00000003/sig00000793 , \blk00000003/sig00000794 , \blk00000003/sig00000795 , \blk00000003/sig00000796 , +\blk00000003/sig00000797 , \blk00000003/sig00000798 , \blk00000003/sig00000799 , \blk00000003/sig0000079a , \blk00000003/sig0000079b , +\blk00000003/sig0000079c , \blk00000003/sig0000079d , \blk00000003/sig0000079e , \blk00000003/sig0000079f , \blk00000003/sig000007a0 , +\blk00000003/sig000007a1 , \blk00000003/sig000007a2 , \blk00000003/sig000007a3 , \blk00000003/sig000007a4 , \blk00000003/sig000007a5 , +\blk00000003/sig000007a6 , \blk00000003/sig000007a7 , \blk00000003/sig000007a8 , \blk00000003/sig000007a9 , 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.RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010e_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010e_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000978 , \blk00000003/sig00000979 , \blk00000003/sig0000097a , +\blk00000003/sig0000097b , \blk00000003/sig0000097c , \blk00000003/sig0000097d , \blk00000003/sig0000097e , \blk00000003/sig0000097f , +\blk00000003/sig00000980 , \blk00000003/sig00000981 , \blk00000003/sig00000982 , \blk00000003/sig00000983 , \blk00000003/sig00000984 , +\blk00000003/sig00000985 , \blk00000003/sig00000986 , \blk00000003/sig00000987 }), + .BCOUT({\NLW_blk00000003/blk0000010e_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000948 , \blk00000003/sig00000949 , \blk00000003/sig0000094a , \blk00000003/sig0000094b , \blk00000003/sig0000094c , +\blk00000003/sig0000094d , \blk00000003/sig0000094e , \blk00000003/sig0000094f , \blk00000003/sig00000950 , \blk00000003/sig00000951 , +\blk00000003/sig00000952 , \blk00000003/sig00000953 , \blk00000003/sig00000954 , \blk00000003/sig00000955 , \blk00000003/sig00000956 , +\blk00000003/sig00000957 , \blk00000003/sig00000958 , \blk00000003/sig00000959 , \blk00000003/sig0000095a , \blk00000003/sig0000095b , +\blk00000003/sig0000095c , \blk00000003/sig0000095d , \blk00000003/sig0000095e , \blk00000003/sig0000095f , \blk00000003/sig00000960 , +\blk00000003/sig00000961 , \blk00000003/sig00000962 , \blk00000003/sig00000963 , \blk00000003/sig00000964 , \blk00000003/sig00000965 , +\blk00000003/sig00000966 , \blk00000003/sig00000967 , \blk00000003/sig00000968 , \blk00000003/sig00000969 , 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\NLW_blk00000003/blk0000010e_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010e_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<30>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<29>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<27>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<26>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<24>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<23>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<21>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<20>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000988 , \blk00000003/sig00000989 , \blk00000003/sig0000098a , +\blk00000003/sig0000098b , \blk00000003/sig0000098c , \blk00000003/sig0000098d , \blk00000003/sig0000098e , \blk00000003/sig0000098f , +\blk00000003/sig00000990 , \blk00000003/sig00000991 , \blk00000003/sig00000992 , \blk00000003/sig00000993 , \blk00000003/sig00000994 , +\blk00000003/sig00000995 , \blk00000003/sig00000996 , \blk00000003/sig00000997 }), + .PCOUT({\blk00000003/sig00000998 , \blk00000003/sig00000999 , \blk00000003/sig0000099a , \blk00000003/sig0000099b , \blk00000003/sig0000099c , +\blk00000003/sig0000099d , \blk00000003/sig0000099e , \blk00000003/sig0000099f , \blk00000003/sig000009a0 , \blk00000003/sig000009a1 , +\blk00000003/sig000009a2 , \blk00000003/sig000009a3 , \blk00000003/sig000009a4 , \blk00000003/sig000009a5 , \blk00000003/sig000009a6 , +\blk00000003/sig000009a7 , \blk00000003/sig000009a8 , \blk00000003/sig000009a9 , \blk00000003/sig000009aa , \blk00000003/sig000009ab , +\blk00000003/sig000009ac , \blk00000003/sig000009ad , \blk00000003/sig000009ae , \blk00000003/sig000009af , \blk00000003/sig000009b0 , +\blk00000003/sig000009b1 , \blk00000003/sig000009b2 , \blk00000003/sig000009b3 , \blk00000003/sig000009b4 , \blk00000003/sig000009b5 , +\blk00000003/sig000009b6 , \blk00000003/sig000009b7 , \blk00000003/sig000009b8 , \blk00000003/sig000009b9 , \blk00000003/sig000009ba , +\blk00000003/sig000009bb , \blk00000003/sig000009bc , \blk00000003/sig000009bd , \blk00000003/sig000009be , \blk00000003/sig000009bf , +\blk00000003/sig000009c0 , \blk00000003/sig000009c1 , \blk00000003/sig000009c2 , \blk00000003/sig000009c3 , \blk00000003/sig000009c4 , +\blk00000003/sig000009c5 , \blk00000003/sig000009c6 , \blk00000003/sig000009c7 }), + .A({\blk00000003/sig00000624 , \blk00000003/sig00000625 , \blk00000003/sig00000626 , \blk00000003/sig00000627 , \blk00000003/sig00000628 , +\blk00000003/sig00000629 , \blk00000003/sig0000062a , \blk00000003/sig0000062b , \blk00000003/sig0000062c , \blk00000003/sig0000062d , +\blk00000003/sig0000062e , \blk00000003/sig0000062f , \blk00000003/sig00000630 , \blk00000003/sig00000631 , \blk00000003/sig00000632 , +\blk00000003/sig00000633 , \blk00000003/sig00000634 , \blk00000003/sig00000635 }), + .M({\NLW_blk00000003/blk0000010e_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010d ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010d_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010d_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000928 , \blk00000003/sig00000929 , \blk00000003/sig0000092a , +\blk00000003/sig0000092b , \blk00000003/sig0000092c , \blk00000003/sig0000092d , \blk00000003/sig0000092e , \blk00000003/sig0000092f , +\blk00000003/sig00000930 , \blk00000003/sig00000931 , \blk00000003/sig00000932 , \blk00000003/sig00000933 , \blk00000003/sig00000934 , +\blk00000003/sig00000935 , \blk00000003/sig00000936 , \blk00000003/sig00000937 }), + .BCOUT({\NLW_blk00000003/blk0000010d_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000008f8 , \blk00000003/sig000008f9 , \blk00000003/sig000008fa , \blk00000003/sig000008fb , \blk00000003/sig000008fc , +\blk00000003/sig000008fd , \blk00000003/sig000008fe , \blk00000003/sig000008ff , \blk00000003/sig00000900 , \blk00000003/sig00000901 , +\blk00000003/sig00000902 , \blk00000003/sig00000903 , \blk00000003/sig00000904 , \blk00000003/sig00000905 , \blk00000003/sig00000906 , +\blk00000003/sig00000907 , \blk00000003/sig00000908 , \blk00000003/sig00000909 , \blk00000003/sig0000090a , \blk00000003/sig0000090b , +\blk00000003/sig0000090c , \blk00000003/sig0000090d , \blk00000003/sig0000090e , \blk00000003/sig0000090f , \blk00000003/sig00000910 , +\blk00000003/sig00000911 , \blk00000003/sig00000912 , \blk00000003/sig00000913 , \blk00000003/sig00000914 , \blk00000003/sig00000915 , +\blk00000003/sig00000916 , \blk00000003/sig00000917 , \blk00000003/sig00000918 , \blk00000003/sig00000919 , \blk00000003/sig0000091a , +\blk00000003/sig0000091b , \blk00000003/sig0000091c , \blk00000003/sig0000091d , \blk00000003/sig0000091e , \blk00000003/sig0000091f , +\blk00000003/sig00000920 , \blk00000003/sig00000921 , \blk00000003/sig00000922 , \blk00000003/sig00000923 , \blk00000003/sig00000924 , +\blk00000003/sig00000925 , \blk00000003/sig00000926 , \blk00000003/sig00000927 }), + .C({\NLW_blk00000003/blk0000010d_C<47>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<45>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<44>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<42>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<41>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<39>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<38>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<36>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010d_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<30>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<29>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<27>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<26>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<24>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<23>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<21>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<20>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000938 , \blk00000003/sig00000939 , \blk00000003/sig0000093a , +\blk00000003/sig0000093b , \blk00000003/sig0000093c , \blk00000003/sig0000093d , \blk00000003/sig0000093e , \blk00000003/sig0000093f , +\blk00000003/sig00000940 , \blk00000003/sig00000941 , \blk00000003/sig00000942 , \blk00000003/sig00000943 , \blk00000003/sig00000944 , +\blk00000003/sig00000945 , \blk00000003/sig00000946 , \blk00000003/sig00000947 }), + .PCOUT({\blk00000003/sig00000948 , \blk00000003/sig00000949 , \blk00000003/sig0000094a , \blk00000003/sig0000094b , \blk00000003/sig0000094c , +\blk00000003/sig0000094d , \blk00000003/sig0000094e , \blk00000003/sig0000094f , \blk00000003/sig00000950 , \blk00000003/sig00000951 , +\blk00000003/sig00000952 , \blk00000003/sig00000953 , \blk00000003/sig00000954 , \blk00000003/sig00000955 , \blk00000003/sig00000956 , +\blk00000003/sig00000957 , \blk00000003/sig00000958 , \blk00000003/sig00000959 , \blk00000003/sig0000095a , \blk00000003/sig0000095b , +\blk00000003/sig0000095c , \blk00000003/sig0000095d , \blk00000003/sig0000095e , \blk00000003/sig0000095f , \blk00000003/sig00000960 , +\blk00000003/sig00000961 , \blk00000003/sig00000962 , \blk00000003/sig00000963 , \blk00000003/sig00000964 , \blk00000003/sig00000965 , +\blk00000003/sig00000966 , \blk00000003/sig00000967 , \blk00000003/sig00000968 , \blk00000003/sig00000969 , \blk00000003/sig0000096a , +\blk00000003/sig0000096b , \blk00000003/sig0000096c , \blk00000003/sig0000096d , \blk00000003/sig0000096e , \blk00000003/sig0000096f , +\blk00000003/sig00000970 , \blk00000003/sig00000971 , \blk00000003/sig00000972 , \blk00000003/sig00000973 , \blk00000003/sig00000974 , +\blk00000003/sig00000975 , \blk00000003/sig00000976 , \blk00000003/sig00000977 }), + .A({\blk00000003/sig000005d2 , \blk00000003/sig000005d3 , \blk00000003/sig000005d4 , \blk00000003/sig000005d5 , \blk00000003/sig000005d6 , +\blk00000003/sig000005d7 , \blk00000003/sig000005d8 , \blk00000003/sig000005d9 , \blk00000003/sig000005da , \blk00000003/sig000005db , +\blk00000003/sig000005dc , \blk00000003/sig000005dd , \blk00000003/sig000005de , \blk00000003/sig000005df , \blk00000003/sig000005e0 , +\blk00000003/sig000005e1 , \blk00000003/sig000005e2 , \blk00000003/sig000005e3 }), + .M({\NLW_blk00000003/blk0000010d_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<29>_UNCONNECTED , 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\NLW_blk00000003/blk0000010d_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010c ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010c_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010c_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000008d8 , \blk00000003/sig000008d9 , \blk00000003/sig000008da , +\blk00000003/sig000008db , \blk00000003/sig000008dc , \blk00000003/sig000008dd , \blk00000003/sig000008de , \blk00000003/sig000008df , +\blk00000003/sig000008e0 , \blk00000003/sig000008e1 , \blk00000003/sig000008e2 , \blk00000003/sig000008e3 , \blk00000003/sig000008e4 , +\blk00000003/sig000008e5 , \blk00000003/sig000008e6 , \blk00000003/sig000008e7 }), + .BCOUT({\NLW_blk00000003/blk0000010c_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010c_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_BCOUT<15>_UNCONNECTED , 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\blk00000003/sig000004a9 , \blk00000003/sig000004aa , +\blk00000003/sig000004ab , \blk00000003/sig000004ac , \blk00000003/sig000004ad }), + .C({\NLW_blk00000003/blk0000010c_C<47>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<45>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<44>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<42>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<41>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<39>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<38>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<36>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010c_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<39>_UNCONNECTED , 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+\NLW_blk00000003/blk0000010c_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , 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.A({\blk00000003/sig00000580 , \blk00000003/sig00000581 , \blk00000003/sig00000582 , \blk00000003/sig00000583 , \blk00000003/sig00000584 , +\blk00000003/sig00000585 , \blk00000003/sig00000586 , \blk00000003/sig00000587 , \blk00000003/sig00000588 , \blk00000003/sig00000589 , +\blk00000003/sig0000058a , \blk00000003/sig0000058b , \blk00000003/sig0000058c , \blk00000003/sig0000058d , \blk00000003/sig0000058e , +\blk00000003/sig0000058f , \blk00000003/sig00000590 , \blk00000003/sig00000591 }), + .M({\NLW_blk00000003/blk0000010c_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010b ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010b_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010b_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000008b8 , \blk00000003/sig000008b9 , \blk00000003/sig000008ba , +\blk00000003/sig000008bb , \blk00000003/sig000008bc , \blk00000003/sig000008bd , \blk00000003/sig000008be , \blk00000003/sig000008bf , +\blk00000003/sig000008c0 , \blk00000003/sig000008c1 , \blk00000003/sig000008c2 , \blk00000003/sig000008c3 , \blk00000003/sig000008c4 , +\blk00000003/sig000008c5 , \blk00000003/sig000008c6 , \blk00000003/sig000008c7 }), + .BCOUT({\NLW_blk00000003/blk0000010b_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000888 , \blk00000003/sig00000889 , \blk00000003/sig0000088a , \blk00000003/sig0000088b , \blk00000003/sig0000088c , +\blk00000003/sig0000088d , \blk00000003/sig0000088e , \blk00000003/sig0000088f , \blk00000003/sig00000890 , \blk00000003/sig00000891 , +\blk00000003/sig00000892 , \blk00000003/sig00000893 , \blk00000003/sig00000894 , \blk00000003/sig00000895 , \blk00000003/sig00000896 , +\blk00000003/sig00000897 , \blk00000003/sig00000898 , \blk00000003/sig00000899 , \blk00000003/sig0000089a , \blk00000003/sig0000089b , +\blk00000003/sig0000089c , \blk00000003/sig0000089d , \blk00000003/sig0000089e , \blk00000003/sig0000089f , \blk00000003/sig000008a0 , +\blk00000003/sig000008a1 , \blk00000003/sig000008a2 , \blk00000003/sig000008a3 , \blk00000003/sig000008a4 , \blk00000003/sig000008a5 , +\blk00000003/sig000008a6 , \blk00000003/sig000008a7 , \blk00000003/sig000008a8 , \blk00000003/sig000008a9 , \blk00000003/sig000008aa , +\blk00000003/sig000008ab , \blk00000003/sig000008ac , \blk00000003/sig000008ad , \blk00000003/sig000008ae , \blk00000003/sig000008af , +\blk00000003/sig000008b0 , \blk00000003/sig000008b1 , \blk00000003/sig000008b2 , \blk00000003/sig000008b3 , \blk00000003/sig000008b4 , +\blk00000003/sig000008b5 , \blk00000003/sig000008b6 , \blk00000003/sig000008b7 }), + .C({\NLW_blk00000003/blk0000010b_C<47>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<45>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<44>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<42>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<41>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<39>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<38>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<36>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010b_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<37>_UNCONNECTED , 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\NLW_blk00000003/blk0000010b_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000008c8 , \blk00000003/sig000008c9 , \blk00000003/sig000008ca , +\blk00000003/sig000008cb , \blk00000003/sig000008cc , \blk00000003/sig000008cd , \blk00000003/sig000008ce , \blk00000003/sig000008cf , +\blk00000003/sig000008d0 , \blk00000003/sig000008d1 , \blk00000003/sig000008d2 , \blk00000003/sig000008d3 , \blk00000003/sig000008d4 , +\blk00000003/sig000008d5 , \blk00000003/sig000008d6 , \blk00000003/sig000008d7 }), + .PCOUT({\blk00000003/sig00000738 , \blk00000003/sig00000739 , \blk00000003/sig0000073a , \blk00000003/sig0000073b , \blk00000003/sig0000073c , +\blk00000003/sig0000073d , \blk00000003/sig0000073e , \blk00000003/sig0000073f , \blk00000003/sig00000740 , \blk00000003/sig00000741 , +\blk00000003/sig00000742 , \blk00000003/sig00000743 , \blk00000003/sig00000744 , \blk00000003/sig00000745 , \blk00000003/sig00000746 , +\blk00000003/sig00000747 , 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\NLW_blk00000003/blk0000010b_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010a ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010a_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010a_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000868 , \blk00000003/sig00000869 , \blk00000003/sig0000086a , +\blk00000003/sig0000086b , \blk00000003/sig0000086c , \blk00000003/sig0000086d , \blk00000003/sig0000086e , \blk00000003/sig0000086f , +\blk00000003/sig00000870 , \blk00000003/sig00000871 , \blk00000003/sig00000872 , \blk00000003/sig00000873 , \blk00000003/sig00000874 , +\blk00000003/sig00000875 , \blk00000003/sig00000876 , \blk00000003/sig00000877 }), + .BCOUT({\NLW_blk00000003/blk0000010a_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_BCOUT<11>_UNCONNECTED , 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\NLW_blk00000003/blk0000010a_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010a_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<30>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<29>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<27>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<26>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<24>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<23>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<21>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<20>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000878 , \blk00000003/sig00000879 , \blk00000003/sig0000087a , +\blk00000003/sig0000087b , \blk00000003/sig0000087c , \blk00000003/sig0000087d , \blk00000003/sig0000087e , \blk00000003/sig0000087f , +\blk00000003/sig00000880 , \blk00000003/sig00000881 , \blk00000003/sig00000882 , \blk00000003/sig00000883 , \blk00000003/sig00000884 , +\blk00000003/sig00000885 , \blk00000003/sig00000886 , \blk00000003/sig00000887 }), + .PCOUT({\blk00000003/sig00000888 , \blk00000003/sig00000889 , \blk00000003/sig0000088a , \blk00000003/sig0000088b , \blk00000003/sig0000088c , +\blk00000003/sig0000088d , \blk00000003/sig0000088e , \blk00000003/sig0000088f , \blk00000003/sig00000890 , \blk00000003/sig00000891 , +\blk00000003/sig00000892 , \blk00000003/sig00000893 , \blk00000003/sig00000894 , \blk00000003/sig00000895 , \blk00000003/sig00000896 , +\blk00000003/sig00000897 , \blk00000003/sig00000898 , \blk00000003/sig00000899 , \blk00000003/sig0000089a , \blk00000003/sig0000089b , +\blk00000003/sig0000089c , \blk00000003/sig0000089d , \blk00000003/sig0000089e , \blk00000003/sig0000089f , \blk00000003/sig000008a0 , +\blk00000003/sig000008a1 , \blk00000003/sig000008a2 , \blk00000003/sig000008a3 , \blk00000003/sig000008a4 , \blk00000003/sig000008a5 , +\blk00000003/sig000008a6 , \blk00000003/sig000008a7 , \blk00000003/sig000008a8 , \blk00000003/sig000008a9 , \blk00000003/sig000008aa , +\blk00000003/sig000008ab , \blk00000003/sig000008ac , \blk00000003/sig000008ad , \blk00000003/sig000008ae , \blk00000003/sig000008af , +\blk00000003/sig000008b0 , \blk00000003/sig000008b1 , \blk00000003/sig000008b2 , \blk00000003/sig000008b3 , \blk00000003/sig000008b4 , +\blk00000003/sig000008b5 , \blk00000003/sig000008b6 , \blk00000003/sig000008b7 }), + .A({\blk00000003/sig00000624 , \blk00000003/sig00000625 , \blk00000003/sig00000626 , \blk00000003/sig00000627 , \blk00000003/sig00000628 , +\blk00000003/sig00000629 , \blk00000003/sig0000062a , \blk00000003/sig0000062b , \blk00000003/sig0000062c , \blk00000003/sig0000062d , +\blk00000003/sig0000062e , \blk00000003/sig0000062f , \blk00000003/sig00000630 , \blk00000003/sig00000631 , \blk00000003/sig00000632 , +\blk00000003/sig00000633 , \blk00000003/sig00000634 , \blk00000003/sig00000635 }), + .M({\NLW_blk00000003/blk0000010a_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000109 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000109_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000109_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000818 , \blk00000003/sig00000819 , \blk00000003/sig0000081a , +\blk00000003/sig0000081b , \blk00000003/sig0000081c , \blk00000003/sig0000081d , \blk00000003/sig0000081e , \blk00000003/sig0000081f , +\blk00000003/sig00000820 , \blk00000003/sig00000821 , \blk00000003/sig00000822 , \blk00000003/sig00000823 , \blk00000003/sig00000824 , +\blk00000003/sig00000825 , \blk00000003/sig00000826 , \blk00000003/sig00000827 }), + .BCOUT({\NLW_blk00000003/blk00000109_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000109_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000109_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000109_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000109_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000109_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000109_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000109_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000109_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000007e8 , \blk00000003/sig000007e9 , \blk00000003/sig000007ea , \blk00000003/sig000007eb , \blk00000003/sig000007ec , +\blk00000003/sig000007ed , \blk00000003/sig000007ee , \blk00000003/sig000007ef , \blk00000003/sig000007f0 , \blk00000003/sig000007f1 , +\blk00000003/sig000007f2 , \blk00000003/sig000007f3 , \blk00000003/sig000007f4 , \blk00000003/sig000007f5 , \blk00000003/sig000007f6 , +\blk00000003/sig000007f7 , \blk00000003/sig000007f8 , \blk00000003/sig000007f9 , \blk00000003/sig000007fa , \blk00000003/sig000007fb , +\blk00000003/sig000007fc , \blk00000003/sig000007fd , \blk00000003/sig000007fe , \blk00000003/sig000007ff , \blk00000003/sig00000800 , +\blk00000003/sig00000801 , \blk00000003/sig00000802 , \blk00000003/sig00000803 , \blk00000003/sig00000804 , \blk00000003/sig00000805 , +\blk00000003/sig00000806 , \blk00000003/sig00000807 , \blk00000003/sig00000808 , \blk00000003/sig00000809 , \blk00000003/sig0000080a , +\blk00000003/sig0000080b , \blk00000003/sig0000080c , \blk00000003/sig0000080d , \blk00000003/sig0000080e , \blk00000003/sig0000080f , +\blk00000003/sig00000810 , \blk00000003/sig00000811 , \blk00000003/sig00000812 , \blk00000003/sig00000813 , \blk00000003/sig00000814 , +\blk00000003/sig00000815 , \blk00000003/sig00000816 , \blk00000003/sig00000817 }), + .C({\NLW_blk00000003/blk00000109_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000109_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000828 , \blk00000003/sig00000829 , \blk00000003/sig0000082a , +\blk00000003/sig0000082b , \blk00000003/sig0000082c , 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\blk00000003/sig000005df , \blk00000003/sig000005e0 , +\blk00000003/sig000005e1 , \blk00000003/sig000005e2 , \blk00000003/sig000005e3 }), + .M({\NLW_blk00000003/blk00000109_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000108 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000108_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000108_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000007c8 , \blk00000003/sig000007c9 , \blk00000003/sig000007ca , +\blk00000003/sig000007cb , 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+\NLW_blk00000003/blk00000108_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000108_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000108_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000108_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000108_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000108_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig0000042e , \blk00000003/sig0000042f , \blk00000003/sig00000430 , \blk00000003/sig00000431 , \blk00000003/sig00000432 , +\blk00000003/sig00000433 , \blk00000003/sig00000434 , \blk00000003/sig00000435 , \blk00000003/sig00000436 , \blk00000003/sig00000437 , +\blk00000003/sig00000438 , \blk00000003/sig00000439 , \blk00000003/sig0000043a , \blk00000003/sig0000043b , \blk00000003/sig0000043c , +\blk00000003/sig0000043d , \blk00000003/sig0000043e , \blk00000003/sig0000043f , \blk00000003/sig00000440 , \blk00000003/sig00000441 , +\blk00000003/sig00000442 , \blk00000003/sig00000443 , \blk00000003/sig00000444 , \blk00000003/sig00000445 , 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\NLW_blk00000003/blk00000108_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000108_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000108_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000108_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000108_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000108_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000108_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<22>_UNCONNECTED , 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\blk00000003/sig00000590 , \blk00000003/sig00000591 }), + .M({\NLW_blk00000003/blk00000108_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000107 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000107_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000107_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000778 , \blk00000003/sig00000779 , \blk00000003/sig0000077a , +\blk00000003/sig0000077b , \blk00000003/sig0000077c , \blk00000003/sig0000077d , \blk00000003/sig0000077e , \blk00000003/sig0000077f , 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+\NLW_blk00000003/blk00000107_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000788 , \blk00000003/sig00000789 , \blk00000003/sig0000078a , \blk00000003/sig0000078b , \blk00000003/sig0000078c , +\blk00000003/sig0000078d , \blk00000003/sig0000078e , \blk00000003/sig0000078f , \blk00000003/sig00000790 , \blk00000003/sig00000791 , +\blk00000003/sig00000792 , \blk00000003/sig00000793 , \blk00000003/sig00000794 , \blk00000003/sig00000795 , \blk00000003/sig00000796 , +\blk00000003/sig00000797 , \blk00000003/sig00000798 , \blk00000003/sig00000799 , \blk00000003/sig0000079a , \blk00000003/sig0000079b , +\blk00000003/sig0000079c , \blk00000003/sig0000079d , \blk00000003/sig0000079e , \blk00000003/sig0000079f , \blk00000003/sig000007a0 , +\blk00000003/sig000007a1 , \blk00000003/sig000007a2 , \blk00000003/sig000007a3 , \blk00000003/sig000007a4 , \blk00000003/sig000007a5 , +\blk00000003/sig000007a6 , \blk00000003/sig000007a7 , \blk00000003/sig000007a8 , \blk00000003/sig000007a9 , \blk00000003/sig000007aa , +\blk00000003/sig000007ab , \blk00000003/sig000007ac , \blk00000003/sig000007ad , \blk00000003/sig000007ae , \blk00000003/sig000007af , +\blk00000003/sig000007b0 , \blk00000003/sig000007b1 , \blk00000003/sig000007b2 , \blk00000003/sig000007b3 , \blk00000003/sig000007b4 , +\blk00000003/sig000007b5 , \blk00000003/sig000007b6 , \blk00000003/sig000007b7 }), + .C({\NLW_blk00000003/blk00000107_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000107_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000007b8 , \blk00000003/sig000007b9 , \blk00000003/sig000007ba , +\blk00000003/sig000007bb , \blk00000003/sig000007bc , \blk00000003/sig000007bd , \blk00000003/sig000007be , \blk00000003/sig000007bf , +\blk00000003/sig000007c0 , \blk00000003/sig000007c1 , \blk00000003/sig000007c2 , \blk00000003/sig000007c3 , \blk00000003/sig000007c4 , +\blk00000003/sig000007c5 , \blk00000003/sig000007c6 , \blk00000003/sig000007c7 }), + .PCOUT({\blk00000003/sig000001d2 , \blk00000003/sig000001d3 , \blk00000003/sig000001d4 , \blk00000003/sig000001d5 , \blk00000003/sig000001d6 , +\blk00000003/sig000001d7 , \blk00000003/sig000001d8 , \blk00000003/sig000001d9 , \blk00000003/sig000001da , \blk00000003/sig000001db , +\blk00000003/sig000001dc , \blk00000003/sig000001dd , \blk00000003/sig000001de , \blk00000003/sig000001df , \blk00000003/sig000001e0 , +\blk00000003/sig000001e1 , \blk00000003/sig000001e2 , \blk00000003/sig000001e3 , \blk00000003/sig000001e4 , \blk00000003/sig000001e5 , +\blk00000003/sig000001e6 , \blk00000003/sig000001e7 , \blk00000003/sig000001e8 , \blk00000003/sig000001e9 , \blk00000003/sig000001ea , +\blk00000003/sig000001eb , \blk00000003/sig000001ec , \blk00000003/sig000001ed , \blk00000003/sig000001ee , \blk00000003/sig000001ef , +\blk00000003/sig000001f0 , \blk00000003/sig000001f1 , \blk00000003/sig000001f2 , \blk00000003/sig000001f3 , \blk00000003/sig000001f4 , +\blk00000003/sig000001f5 , \blk00000003/sig000001f6 , \blk00000003/sig000001f7 , \blk00000003/sig000001f8 , \blk00000003/sig000001f9 , +\blk00000003/sig000001fa , \blk00000003/sig000001fb , \blk00000003/sig000001fc , \blk00000003/sig000001fd , \blk00000003/sig000001fe , +\blk00000003/sig000001ff , \blk00000003/sig00000200 , \blk00000003/sig00000201 }), + .A({\blk00000003/sig000004ee , \blk00000003/sig000004ef , \blk00000003/sig000004f0 , \blk00000003/sig000004f1 , \blk00000003/sig000004f2 , +\blk00000003/sig000004f3 , \blk00000003/sig000004f4 , \blk00000003/sig000004f5 , \blk00000003/sig000004f6 , \blk00000003/sig000004f7 , +\blk00000003/sig000004f8 , \blk00000003/sig000004f9 , \blk00000003/sig000004fa , \blk00000003/sig000004fb , \blk00000003/sig000004fc , +\blk00000003/sig000004fd , \blk00000003/sig000004fe , \blk00000003/sig000004ff }), + .M({\NLW_blk00000003/blk00000107_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000106 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000106_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000106_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000728 , \blk00000003/sig00000729 , \blk00000003/sig0000072a , +\blk00000003/sig0000072b , \blk00000003/sig0000072c , \blk00000003/sig0000072d , \blk00000003/sig0000072e , \blk00000003/sig0000072f , +\blk00000003/sig00000730 , \blk00000003/sig00000731 , \blk00000003/sig00000732 , \blk00000003/sig00000733 , \blk00000003/sig00000734 , +\blk00000003/sig00000735 , \blk00000003/sig00000736 , \blk00000003/sig00000737 }), + .BCOUT({\NLW_blk00000003/blk00000106_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000738 , \blk00000003/sig00000739 , \blk00000003/sig0000073a , \blk00000003/sig0000073b , \blk00000003/sig0000073c , +\blk00000003/sig0000073d , \blk00000003/sig0000073e , \blk00000003/sig0000073f , \blk00000003/sig00000740 , \blk00000003/sig00000741 , +\blk00000003/sig00000742 , \blk00000003/sig00000743 , \blk00000003/sig00000744 , \blk00000003/sig00000745 , \blk00000003/sig00000746 , +\blk00000003/sig00000747 , \blk00000003/sig00000748 , \blk00000003/sig00000749 , \blk00000003/sig0000074a , \blk00000003/sig0000074b , +\blk00000003/sig0000074c , \blk00000003/sig0000074d , \blk00000003/sig0000074e , \blk00000003/sig0000074f , \blk00000003/sig00000750 , +\blk00000003/sig00000751 , \blk00000003/sig00000752 , \blk00000003/sig00000753 , \blk00000003/sig00000754 , \blk00000003/sig00000755 , +\blk00000003/sig00000756 , \blk00000003/sig00000757 , \blk00000003/sig00000758 , \blk00000003/sig00000759 , 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\NLW_blk00000003/blk00000106_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000106_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000768 , \blk00000003/sig00000769 , \blk00000003/sig0000076a , +\blk00000003/sig0000076b , \blk00000003/sig0000076c , \blk00000003/sig0000076d , \blk00000003/sig0000076e , \blk00000003/sig0000076f , +\blk00000003/sig00000770 , \blk00000003/sig00000771 , \blk00000003/sig00000772 , \blk00000003/sig00000773 , \blk00000003/sig00000774 , +\blk00000003/sig00000775 , \blk00000003/sig00000776 , \blk00000003/sig00000777 }), + .PCOUT({\blk00000003/sig0000025a , \blk00000003/sig0000025b , \blk00000003/sig0000025c , \blk00000003/sig0000025d , \blk00000003/sig0000025e , +\blk00000003/sig0000025f , \blk00000003/sig00000260 , \blk00000003/sig00000261 , \blk00000003/sig00000262 , \blk00000003/sig00000263 , +\blk00000003/sig00000264 , \blk00000003/sig00000265 , \blk00000003/sig00000266 , \blk00000003/sig00000267 , \blk00000003/sig00000268 , +\blk00000003/sig00000269 , \blk00000003/sig0000026a , \blk00000003/sig0000026b , \blk00000003/sig0000026c , \blk00000003/sig0000026d , +\blk00000003/sig0000026e , \blk00000003/sig0000026f , \blk00000003/sig00000270 , \blk00000003/sig00000271 , \blk00000003/sig00000272 , +\blk00000003/sig00000273 , \blk00000003/sig00000274 , \blk00000003/sig00000275 , \blk00000003/sig00000276 , \blk00000003/sig00000277 , +\blk00000003/sig00000278 , \blk00000003/sig00000279 , \blk00000003/sig0000027a , \blk00000003/sig0000027b , \blk00000003/sig0000027c , +\blk00000003/sig0000027d , \blk00000003/sig0000027e , \blk00000003/sig0000027f , \blk00000003/sig00000280 , \blk00000003/sig00000281 , +\blk00000003/sig00000282 , \blk00000003/sig00000283 , \blk00000003/sig00000284 , \blk00000003/sig00000285 , \blk00000003/sig00000286 , +\blk00000003/sig00000287 , \blk00000003/sig00000288 , \blk00000003/sig00000289 }), + .A({\blk00000003/sig000004ee , \blk00000003/sig000004ef , \blk00000003/sig000004f0 , \blk00000003/sig000004f1 , \blk00000003/sig000004f2 , +\blk00000003/sig000004f3 , \blk00000003/sig000004f4 , \blk00000003/sig000004f5 , \blk00000003/sig000004f6 , \blk00000003/sig000004f7 , +\blk00000003/sig000004f8 , \blk00000003/sig000004f9 , \blk00000003/sig000004fa , \blk00000003/sig000004fb , \blk00000003/sig000004fc , +\blk00000003/sig000004fd , \blk00000003/sig000004fe , \blk00000003/sig000004ff }), + .M({\NLW_blk00000003/blk00000106_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000105 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000105_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000105_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000718 , \blk00000003/sig00000718 , \blk00000003/sig00000718 , \blk00000003/sig00000718 , \blk00000003/sig00000718 , +\blk00000003/sig00000718 , \blk00000003/sig00000718 , \blk00000003/sig00000718 , \blk00000003/sig00000718 , \blk00000003/sig00000718 , +\blk00000003/sig00000718 , \blk00000003/sig00000719 , \blk00000003/sig0000071a , \blk00000003/sig0000071b , \blk00000003/sig0000071c , +\blk00000003/sig0000071d , \blk00000003/sig0000071e , \blk00000003/sig0000071f }), + .BCOUT({\NLW_blk00000003/blk00000105_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000006e8 , \blk00000003/sig000006e9 , \blk00000003/sig000006ea , \blk00000003/sig000006eb , \blk00000003/sig000006ec , +\blk00000003/sig000006ed , \blk00000003/sig000006ee , \blk00000003/sig000006ef , \blk00000003/sig000006f0 , \blk00000003/sig000006f1 , +\blk00000003/sig000006f2 , \blk00000003/sig000006f3 , \blk00000003/sig000006f4 , \blk00000003/sig000006f5 , \blk00000003/sig000006f6 , +\blk00000003/sig000006f7 , \blk00000003/sig000006f8 , \blk00000003/sig000006f9 , \blk00000003/sig000006fa , \blk00000003/sig000006fb , +\blk00000003/sig000006fc , \blk00000003/sig000006fd , \blk00000003/sig000006fe , \blk00000003/sig000006ff , \blk00000003/sig00000700 , +\blk00000003/sig00000701 , \blk00000003/sig00000702 , \blk00000003/sig00000703 , \blk00000003/sig00000704 , \blk00000003/sig00000705 , +\blk00000003/sig00000706 , \blk00000003/sig00000707 , \blk00000003/sig00000708 , \blk00000003/sig00000709 , \blk00000003/sig0000070a , +\blk00000003/sig0000070b , \blk00000003/sig0000070c , \blk00000003/sig0000070d , \blk00000003/sig0000070e , \blk00000003/sig0000070f , +\blk00000003/sig00000710 , \blk00000003/sig00000711 , \blk00000003/sig00000712 , \blk00000003/sig00000713 , \blk00000003/sig00000714 , +\blk00000003/sig00000715 , \blk00000003/sig00000716 , \blk00000003/sig00000717 }), + .C({\NLW_blk00000003/blk00000105_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000105_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000720 , \blk00000003/sig00000720 , \blk00000003/sig00000720 , \blk00000003/sig00000720 , \blk00000003/sig00000720 , +\blk00000003/sig00000720 , \blk00000003/sig00000720 , \blk00000003/sig00000720 , \blk00000003/sig00000720 , \blk00000003/sig00000720 , +\blk00000003/sig00000720 , \blk00000003/sig00000721 , \blk00000003/sig00000722 , \blk00000003/sig00000723 , \blk00000003/sig00000724 , +\blk00000003/sig00000725 , \blk00000003/sig00000726 , \blk00000003/sig00000727 }), + .PCOUT({\blk00000003/sig00000508 , \blk00000003/sig00000509 , \blk00000003/sig0000050a , \blk00000003/sig0000050b , \blk00000003/sig0000050c , +\blk00000003/sig0000050d , \blk00000003/sig0000050e , \blk00000003/sig0000050f , \blk00000003/sig00000510 , \blk00000003/sig00000511 , +\blk00000003/sig00000512 , \blk00000003/sig00000513 , \blk00000003/sig00000514 , \blk00000003/sig00000515 , \blk00000003/sig00000516 , +\blk00000003/sig00000517 , \blk00000003/sig00000518 , \blk00000003/sig00000519 , \blk00000003/sig0000051a , \blk00000003/sig0000051b , +\blk00000003/sig0000051c , \blk00000003/sig0000051d , \blk00000003/sig0000051e , \blk00000003/sig0000051f , \blk00000003/sig00000520 , +\blk00000003/sig00000521 , \blk00000003/sig00000522 , \blk00000003/sig00000523 , \blk00000003/sig00000524 , \blk00000003/sig00000525 , +\blk00000003/sig00000526 , \blk00000003/sig00000527 , \blk00000003/sig00000528 , \blk00000003/sig00000529 , \blk00000003/sig0000052a , +\blk00000003/sig0000052b , \blk00000003/sig0000052c , \blk00000003/sig0000052d , \blk00000003/sig0000052e , \blk00000003/sig0000052f , +\blk00000003/sig00000530 , \blk00000003/sig00000531 , \blk00000003/sig00000532 , \blk00000003/sig00000533 , \blk00000003/sig00000534 , +\blk00000003/sig00000535 , \blk00000003/sig00000536 , \blk00000003/sig00000537 }), + .A({\blk00000003/sig00000646 , \blk00000003/sig00000647 , \blk00000003/sig00000648 , \blk00000003/sig00000649 , \blk00000003/sig0000064a , +\blk00000003/sig0000064b , \blk00000003/sig0000064c , \blk00000003/sig0000064d , \blk00000003/sig0000064e , \blk00000003/sig0000064f , +\blk00000003/sig00000650 , \blk00000003/sig00000651 , \blk00000003/sig00000652 , \blk00000003/sig00000653 , \blk00000003/sig00000654 , +\blk00000003/sig00000655 , \blk00000003/sig00000656 , \blk00000003/sig00000657 }), + .M({\NLW_blk00000003/blk00000105_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000104 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000104_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000104_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig000006d8 , \blk00000003/sig000006d8 , \blk00000003/sig000006d8 , \blk00000003/sig000006d8 , \blk00000003/sig000006d8 , +\blk00000003/sig000006d8 , \blk00000003/sig000006d8 , \blk00000003/sig000006d8 , \blk00000003/sig000006d8 , \blk00000003/sig000006d8 , +\blk00000003/sig000006d8 , \blk00000003/sig000006d9 , \blk00000003/sig000006da , \blk00000003/sig000006db , \blk00000003/sig000006dc , +\blk00000003/sig000006dd , \blk00000003/sig000006de , \blk00000003/sig000006df }), + .BCOUT({\NLW_blk00000003/blk00000104_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000006a8 , \blk00000003/sig000006a9 , \blk00000003/sig000006aa , \blk00000003/sig000006ab , \blk00000003/sig000006ac , +\blk00000003/sig000006ad , \blk00000003/sig000006ae , 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\blk00000003/sig000006d3 , \blk00000003/sig000006d4 , +\blk00000003/sig000006d5 , \blk00000003/sig000006d6 , \blk00000003/sig000006d7 }), + .C({\NLW_blk00000003/blk00000104_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000104_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig000006e0 , \blk00000003/sig000006e0 , \blk00000003/sig000006e0 , \blk00000003/sig000006e0 , \blk00000003/sig000006e0 , +\blk00000003/sig000006e0 , \blk00000003/sig000006e0 , \blk00000003/sig000006e0 , \blk00000003/sig000006e0 , \blk00000003/sig000006e0 , +\blk00000003/sig000006e0 , \blk00000003/sig000006e1 , \blk00000003/sig000006e2 , \blk00000003/sig000006e3 , \blk00000003/sig000006e4 , +\blk00000003/sig000006e5 , \blk00000003/sig000006e6 , \blk00000003/sig000006e7 }), + .PCOUT({\blk00000003/sig000006e8 , \blk00000003/sig000006e9 , \blk00000003/sig000006ea , \blk00000003/sig000006eb , \blk00000003/sig000006ec , +\blk00000003/sig000006ed , \blk00000003/sig000006ee , \blk00000003/sig000006ef , \blk00000003/sig000006f0 , \blk00000003/sig000006f1 , +\blk00000003/sig000006f2 , \blk00000003/sig000006f3 , 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.A({\blk00000003/sig00000624 , \blk00000003/sig00000625 , \blk00000003/sig00000626 , \blk00000003/sig00000627 , \blk00000003/sig00000628 , +\blk00000003/sig00000629 , \blk00000003/sig0000062a , \blk00000003/sig0000062b , \blk00000003/sig0000062c , \blk00000003/sig0000062d , +\blk00000003/sig0000062e , \blk00000003/sig0000062f , \blk00000003/sig00000630 , \blk00000003/sig00000631 , \blk00000003/sig00000632 , +\blk00000003/sig00000633 , \blk00000003/sig00000634 , \blk00000003/sig00000635 }), + .M({\NLW_blk00000003/blk00000104_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000103 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000103_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000103_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000698 , \blk00000003/sig00000698 , \blk00000003/sig00000698 , \blk00000003/sig00000698 , \blk00000003/sig00000698 , +\blk00000003/sig00000698 , \blk00000003/sig00000698 , \blk00000003/sig00000698 , \blk00000003/sig00000698 , \blk00000003/sig00000698 , +\blk00000003/sig00000698 , \blk00000003/sig00000699 , \blk00000003/sig0000069a , \blk00000003/sig0000069b , \blk00000003/sig0000069c , +\blk00000003/sig0000069d , \blk00000003/sig0000069e , \blk00000003/sig0000069f }), + .BCOUT({\NLW_blk00000003/blk00000103_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000103_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000103_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000103_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000103_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000103_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000103_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000103_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000103_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000668 , \blk00000003/sig00000669 , \blk00000003/sig0000066a , \blk00000003/sig0000066b , \blk00000003/sig0000066c , +\blk00000003/sig0000066d , \blk00000003/sig0000066e , \blk00000003/sig0000066f , \blk00000003/sig00000670 , \blk00000003/sig00000671 , +\blk00000003/sig00000672 , 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\blk00000003/sig00000697 }), + .C({\NLW_blk00000003/blk00000103_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<9>_UNCONNECTED , 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\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig000006a0 , \blk00000003/sig000006a0 , \blk00000003/sig000006a0 , \blk00000003/sig000006a0 , \blk00000003/sig000006a0 , +\blk00000003/sig000006a0 , \blk00000003/sig000006a0 , \blk00000003/sig000006a0 , \blk00000003/sig000006a0 , \blk00000003/sig000006a0 , +\blk00000003/sig000006a0 , \blk00000003/sig000006a1 , \blk00000003/sig000006a2 , \blk00000003/sig000006a3 , \blk00000003/sig000006a4 , +\blk00000003/sig000006a5 , \blk00000003/sig000006a6 , \blk00000003/sig000006a7 }), + .PCOUT({\blk00000003/sig000006a8 , \blk00000003/sig000006a9 , \blk00000003/sig000006aa , \blk00000003/sig000006ab , \blk00000003/sig000006ac , +\blk00000003/sig000006ad , \blk00000003/sig000006ae , \blk00000003/sig000006af , \blk00000003/sig000006b0 , \blk00000003/sig000006b1 , +\blk00000003/sig000006b2 , \blk00000003/sig000006b3 , \blk00000003/sig000006b4 , \blk00000003/sig000006b5 , \blk00000003/sig000006b6 , +\blk00000003/sig000006b7 , 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.RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000658 , \blk00000003/sig00000658 , \blk00000003/sig00000658 , \blk00000003/sig00000658 , \blk00000003/sig00000658 , +\blk00000003/sig00000658 , \blk00000003/sig00000658 , \blk00000003/sig00000658 , \blk00000003/sig00000658 , \blk00000003/sig00000658 , +\blk00000003/sig00000658 , \blk00000003/sig00000659 , \blk00000003/sig0000065a , \blk00000003/sig0000065b , \blk00000003/sig0000065c , +\blk00000003/sig0000065d , \blk00000003/sig0000065e , \blk00000003/sig0000065f }), + .BCOUT({\NLW_blk00000003/blk00000102_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000102_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000102_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000102_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000102_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000102_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000102_BCOUT<11>_UNCONNECTED , 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\NLW_blk00000003/blk00000102_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000660 , \blk00000003/sig00000660 , \blk00000003/sig00000660 , \blk00000003/sig00000660 , \blk00000003/sig00000660 , +\blk00000003/sig00000660 , \blk00000003/sig00000660 , \blk00000003/sig00000660 , \blk00000003/sig00000660 , \blk00000003/sig00000660 , +\blk00000003/sig00000660 , \blk00000003/sig00000661 , \blk00000003/sig00000662 , \blk00000003/sig00000663 , \blk00000003/sig00000664 , +\blk00000003/sig00000665 , \blk00000003/sig00000666 , \blk00000003/sig00000667 }), + .PCOUT({\blk00000003/sig00000668 , \blk00000003/sig00000669 , \blk00000003/sig0000066a , \blk00000003/sig0000066b , \blk00000003/sig0000066c , +\blk00000003/sig0000066d , \blk00000003/sig0000066e , \blk00000003/sig0000066f , \blk00000003/sig00000670 , \blk00000003/sig00000671 , +\blk00000003/sig00000672 , \blk00000003/sig00000673 , \blk00000003/sig00000674 , \blk00000003/sig00000675 , \blk00000003/sig00000676 , +\blk00000003/sig00000677 , \blk00000003/sig00000678 , \blk00000003/sig00000679 , \blk00000003/sig0000067a , \blk00000003/sig0000067b , +\blk00000003/sig0000067c , \blk00000003/sig0000067d , \blk00000003/sig0000067e , \blk00000003/sig0000067f , \blk00000003/sig00000680 , +\blk00000003/sig00000681 , \blk00000003/sig00000682 , \blk00000003/sig00000683 , \blk00000003/sig00000684 , \blk00000003/sig00000685 , +\blk00000003/sig00000686 , \blk00000003/sig00000687 , \blk00000003/sig00000688 , \blk00000003/sig00000689 , \blk00000003/sig0000068a , +\blk00000003/sig0000068b , \blk00000003/sig0000068c , \blk00000003/sig0000068d , \blk00000003/sig0000068e , \blk00000003/sig0000068f , +\blk00000003/sig00000690 , \blk00000003/sig00000691 , \blk00000003/sig00000692 , \blk00000003/sig00000693 , \blk00000003/sig00000694 , +\blk00000003/sig00000695 , \blk00000003/sig00000696 , \blk00000003/sig00000697 }), + .A({\blk00000003/sig00000580 , \blk00000003/sig00000581 , \blk00000003/sig00000582 , \blk00000003/sig00000583 , \blk00000003/sig00000584 , +\blk00000003/sig00000585 , \blk00000003/sig00000586 , \blk00000003/sig00000587 , \blk00000003/sig00000588 , \blk00000003/sig00000589 , +\blk00000003/sig0000058a , \blk00000003/sig0000058b , \blk00000003/sig0000058c , \blk00000003/sig0000058d , \blk00000003/sig0000058e , +\blk00000003/sig0000058f , \blk00000003/sig00000590 , \blk00000003/sig00000591 }), + .M({\NLW_blk00000003/blk00000102_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000101 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000101_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000101_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000636 , \blk00000003/sig00000636 , \blk00000003/sig00000636 , \blk00000003/sig00000636 , \blk00000003/sig00000636 , +\blk00000003/sig00000636 , \blk00000003/sig00000636 , \blk00000003/sig00000636 , \blk00000003/sig00000636 , \blk00000003/sig00000636 , +\blk00000003/sig00000636 , \blk00000003/sig00000637 , \blk00000003/sig00000638 , \blk00000003/sig00000639 , \blk00000003/sig0000063a , +\blk00000003/sig0000063b , \blk00000003/sig0000063c , \blk00000003/sig0000063d }), + .BCOUT({\NLW_blk00000003/blk00000101_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000101_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000101_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000101_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000101_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000101_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000101_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000101_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000101_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000005f4 , \blk00000003/sig000005f5 , \blk00000003/sig000005f6 , \blk00000003/sig000005f7 , \blk00000003/sig000005f8 , +\blk00000003/sig000005f9 , \blk00000003/sig000005fa , \blk00000003/sig000005fb , \blk00000003/sig000005fc , \blk00000003/sig000005fd , +\blk00000003/sig000005fe , \blk00000003/sig000005ff , \blk00000003/sig00000600 , \blk00000003/sig00000601 , \blk00000003/sig00000602 , +\blk00000003/sig00000603 , \blk00000003/sig00000604 , \blk00000003/sig00000605 , \blk00000003/sig00000606 , \blk00000003/sig00000607 , +\blk00000003/sig00000608 , \blk00000003/sig00000609 , \blk00000003/sig0000060a , \blk00000003/sig0000060b , \blk00000003/sig0000060c , +\blk00000003/sig0000060d , \blk00000003/sig0000060e , \blk00000003/sig0000060f , \blk00000003/sig00000610 , \blk00000003/sig00000611 , +\blk00000003/sig00000612 , \blk00000003/sig00000613 , \blk00000003/sig00000614 , \blk00000003/sig00000615 , \blk00000003/sig00000616 , +\blk00000003/sig00000617 , \blk00000003/sig00000618 , \blk00000003/sig00000619 , \blk00000003/sig0000061a , \blk00000003/sig0000061b , +\blk00000003/sig0000061c , \blk00000003/sig0000061d , \blk00000003/sig0000061e , \blk00000003/sig0000061f , \blk00000003/sig00000620 , +\blk00000003/sig00000621 , \blk00000003/sig00000622 , \blk00000003/sig00000623 }), + .C({\NLW_blk00000003/blk00000101_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000101_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig0000063e , \blk00000003/sig0000063e , \blk00000003/sig0000063e , \blk00000003/sig0000063e , \blk00000003/sig0000063e , +\blk00000003/sig0000063e , \blk00000003/sig0000063e , \blk00000003/sig0000063e , \blk00000003/sig0000063e , \blk00000003/sig0000063e , +\blk00000003/sig0000063e , \blk00000003/sig0000063f , \blk00000003/sig00000640 , \blk00000003/sig00000641 , \blk00000003/sig00000642 , +\blk00000003/sig00000643 , \blk00000003/sig00000644 , \blk00000003/sig00000645 }), + .PCOUT({\blk00000003/sig000004b6 , \blk00000003/sig000004b7 , \blk00000003/sig000004b8 , \blk00000003/sig000004b9 , \blk00000003/sig000004ba , +\blk00000003/sig000004bb , \blk00000003/sig000004bc , \blk00000003/sig000004bd , \blk00000003/sig000004be , \blk00000003/sig000004bf , +\blk00000003/sig000004c0 , \blk00000003/sig000004c1 , \blk00000003/sig000004c2 , \blk00000003/sig000004c3 , \blk00000003/sig000004c4 , +\blk00000003/sig000004c5 , \blk00000003/sig000004c6 , \blk00000003/sig000004c7 , \blk00000003/sig000004c8 , \blk00000003/sig000004c9 , +\blk00000003/sig000004ca , \blk00000003/sig000004cb , \blk00000003/sig000004cc , \blk00000003/sig000004cd , \blk00000003/sig000004ce , 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\blk00000003/sig0000056c , \blk00000003/sig0000056d , +\blk00000003/sig0000056e , \blk00000003/sig0000056f , \blk00000003/sig00000570 , \blk00000003/sig00000571 , \blk00000003/sig00000572 , +\blk00000003/sig00000573 , \blk00000003/sig00000574 , \blk00000003/sig00000575 , \blk00000003/sig00000576 , \blk00000003/sig00000577 , +\blk00000003/sig00000578 , \blk00000003/sig00000579 , \blk00000003/sig0000057a , \blk00000003/sig0000057b , \blk00000003/sig0000057c , +\blk00000003/sig0000057d , \blk00000003/sig0000057e , \blk00000003/sig0000057f }), + .C({\NLW_blk00000003/blk000000ff_C<47>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<46>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<45>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<44>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<43>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<42>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<41>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<40>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<39>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<38>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<37>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<36>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<35>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<34>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<33>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<32>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<31>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<30>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<29>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<27>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<26>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<25>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<24>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<23>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<21>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<20>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<19>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<18>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<17>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<15>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<14>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<13>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<12>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<11>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<9>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<8>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<7>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<6>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<5>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<3>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<2>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<1>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk000000ff_P<47>_UNCONNECTED , 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\NLW_blk00000003/blk000000ff_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<7>_UNCONNECTED , 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\blk00000003/sig000005a0 , \blk00000003/sig000005a1 }), + .PCOUT({\blk00000003/sig000005a2 , \blk00000003/sig000005a3 , \blk00000003/sig000005a4 , \blk00000003/sig000005a5 , \blk00000003/sig000005a6 , +\blk00000003/sig000005a7 , \blk00000003/sig000005a8 , \blk00000003/sig000005a9 , \blk00000003/sig000005aa , \blk00000003/sig000005ab , +\blk00000003/sig000005ac , \blk00000003/sig000005ad , \blk00000003/sig000005ae , \blk00000003/sig000005af , \blk00000003/sig000005b0 , +\blk00000003/sig000005b1 , \blk00000003/sig000005b2 , \blk00000003/sig000005b3 , \blk00000003/sig000005b4 , \blk00000003/sig000005b5 , +\blk00000003/sig000005b6 , \blk00000003/sig000005b7 , \blk00000003/sig000005b8 , \blk00000003/sig000005b9 , \blk00000003/sig000005ba , +\blk00000003/sig000005bb , \blk00000003/sig000005bc , \blk00000003/sig000005bd , \blk00000003/sig000005be , \blk00000003/sig000005bf , +\blk00000003/sig000005c0 , \blk00000003/sig000005c1 , \blk00000003/sig000005c2 , \blk00000003/sig000005c3 , \blk00000003/sig000005c4 , +\blk00000003/sig000005c5 , \blk00000003/sig000005c6 , \blk00000003/sig000005c7 , \blk00000003/sig000005c8 , \blk00000003/sig000005c9 , +\blk00000003/sig000005ca , \blk00000003/sig000005cb , \blk00000003/sig000005cc , \blk00000003/sig000005cd , \blk00000003/sig000005ce , +\blk00000003/sig000005cf , \blk00000003/sig000005d0 , \blk00000003/sig000005d1 }), + .A({\blk00000003/sig000005d2 , \blk00000003/sig000005d3 , \blk00000003/sig000005d4 , \blk00000003/sig000005d5 , \blk00000003/sig000005d6 , +\blk00000003/sig000005d7 , \blk00000003/sig000005d8 , \blk00000003/sig000005d9 , \blk00000003/sig000005da , \blk00000003/sig000005db , +\blk00000003/sig000005dc , \blk00000003/sig000005dd , \blk00000003/sig000005de , \blk00000003/sig000005df , \blk00000003/sig000005e0 , +\blk00000003/sig000005e1 , \blk00000003/sig000005e2 , \blk00000003/sig000005e3 }), + .M({\NLW_blk00000003/blk000000ff_M<35>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<34>_UNCONNECTED , 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\NLW_blk00000003/blk000000ff_M<13>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_M<12>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<11>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_M<9>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<8>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<7>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_M<6>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<5>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_M<3>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<2>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<1>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk000000fe ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk000000fe_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk000000fe_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000540 , \blk00000003/sig00000540 , \blk00000003/sig00000540 , \blk00000003/sig00000540 , \blk00000003/sig00000540 , +\blk00000003/sig00000540 , \blk00000003/sig00000540 , \blk00000003/sig00000540 , \blk00000003/sig00000540 , \blk00000003/sig00000540 , +\blk00000003/sig00000540 , \blk00000003/sig00000541 , \blk00000003/sig00000542 , \blk00000003/sig00000543 , \blk00000003/sig00000544 , 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\NLW_blk00000003/blk000000fe_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig0000038c , \blk00000003/sig0000038d , \blk00000003/sig0000038e , \blk00000003/sig0000038f , \blk00000003/sig00000390 , +\blk00000003/sig00000391 , \blk00000003/sig00000392 , \blk00000003/sig00000393 , \blk00000003/sig00000394 , \blk00000003/sig00000395 , +\blk00000003/sig00000396 , \blk00000003/sig00000397 , \blk00000003/sig00000398 , \blk00000003/sig00000399 , \blk00000003/sig0000039a , +\blk00000003/sig0000039b , \blk00000003/sig0000039c , \blk00000003/sig0000039d , \blk00000003/sig0000039e , \blk00000003/sig0000039f , +\blk00000003/sig000003a0 , \blk00000003/sig000003a1 , \blk00000003/sig000003a2 , \blk00000003/sig000003a3 , \blk00000003/sig000003a4 , +\blk00000003/sig000003a5 , \blk00000003/sig000003a6 , \blk00000003/sig000003a7 , \blk00000003/sig000003a8 , \blk00000003/sig000003a9 , +\blk00000003/sig000003aa , \blk00000003/sig000003ab , \blk00000003/sig000003ac , \blk00000003/sig000003ad , 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+\NLW_blk00000003/blk000000fe_C<15>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<14>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_C<12>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<11>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_C<9>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<8>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_C<6>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<5>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_C<3>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<2>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk000000fe_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000548 , \blk00000003/sig00000548 , \blk00000003/sig00000548 , \blk00000003/sig00000548 , \blk00000003/sig00000548 , +\blk00000003/sig00000548 , \blk00000003/sig00000548 , \blk00000003/sig00000548 , \blk00000003/sig00000548 , \blk00000003/sig00000548 , +\blk00000003/sig00000548 , \blk00000003/sig00000549 , \blk00000003/sig0000054a , \blk00000003/sig0000054b , \blk00000003/sig0000054c , +\blk00000003/sig0000054d , \blk00000003/sig0000054e , \blk00000003/sig0000054f }), + .PCOUT({\blk00000003/sig00000550 , \blk00000003/sig00000551 , \blk00000003/sig00000552 , \blk00000003/sig00000553 , \blk00000003/sig00000554 , +\blk00000003/sig00000555 , \blk00000003/sig00000556 , \blk00000003/sig00000557 , \blk00000003/sig00000558 , \blk00000003/sig00000559 , +\blk00000003/sig0000055a , \blk00000003/sig0000055b , \blk00000003/sig0000055c , \blk00000003/sig0000055d , \blk00000003/sig0000055e , +\blk00000003/sig0000055f , \blk00000003/sig00000560 , \blk00000003/sig00000561 , \blk00000003/sig00000562 , \blk00000003/sig00000563 , +\blk00000003/sig00000564 , \blk00000003/sig00000565 , \blk00000003/sig00000566 , \blk00000003/sig00000567 , \blk00000003/sig00000568 , +\blk00000003/sig00000569 , \blk00000003/sig0000056a , \blk00000003/sig0000056b , \blk00000003/sig0000056c , \blk00000003/sig0000056d , +\blk00000003/sig0000056e , \blk00000003/sig0000056f , \blk00000003/sig00000570 , \blk00000003/sig00000571 , \blk00000003/sig00000572 , +\blk00000003/sig00000573 , \blk00000003/sig00000574 , \blk00000003/sig00000575 , \blk00000003/sig00000576 , \blk00000003/sig00000577 , +\blk00000003/sig00000578 , \blk00000003/sig00000579 , \blk00000003/sig0000057a , \blk00000003/sig0000057b , \blk00000003/sig0000057c , +\blk00000003/sig0000057d , \blk00000003/sig0000057e , \blk00000003/sig0000057f }), + .A({\blk00000003/sig00000580 , \blk00000003/sig00000581 , \blk00000003/sig00000582 , \blk00000003/sig00000583 , \blk00000003/sig00000584 , +\blk00000003/sig00000585 , \blk00000003/sig00000586 , \blk00000003/sig00000587 , \blk00000003/sig00000588 , \blk00000003/sig00000589 , +\blk00000003/sig0000058a , \blk00000003/sig0000058b , \blk00000003/sig0000058c , \blk00000003/sig0000058d , \blk00000003/sig0000058e , +\blk00000003/sig0000058f , \blk00000003/sig00000590 , \blk00000003/sig00000591 }), + .M({\NLW_blk00000003/blk000000fe_M<35>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<33>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<32>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<30>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<29>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<27>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<26>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<24>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<23>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<21>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<20>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<18>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<17>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<15>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<14>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<12>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<11>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<9>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<8>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<6>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<5>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<3>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<2>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk000000fd ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk000000fd_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk000000fd_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000500 , \blk00000003/sig00000500 , \blk00000003/sig00000500 , \blk00000003/sig00000500 , \blk00000003/sig00000500 , +\blk00000003/sig00000500 , \blk00000003/sig00000500 , \blk00000003/sig00000500 , \blk00000003/sig00000500 , \blk00000003/sig00000500 , +\blk00000003/sig00000500 , \blk00000003/sig00000501 , \blk00000003/sig00000502 , \blk00000003/sig00000503 , \blk00000003/sig00000504 , +\blk00000003/sig00000505 , \blk00000003/sig00000506 , \blk00000003/sig00000507 }), + .BCOUT({\NLW_blk00000003/blk000000fd_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000508 , \blk00000003/sig00000509 , \blk00000003/sig0000050a , \blk00000003/sig0000050b , \blk00000003/sig0000050c , +\blk00000003/sig0000050d , \blk00000003/sig0000050e , \blk00000003/sig0000050f , \blk00000003/sig00000510 , \blk00000003/sig00000511 , +\blk00000003/sig00000512 , \blk00000003/sig00000513 , \blk00000003/sig00000514 , \blk00000003/sig00000515 , \blk00000003/sig00000516 , +\blk00000003/sig00000517 , \blk00000003/sig00000518 , \blk00000003/sig00000519 , \blk00000003/sig0000051a , \blk00000003/sig0000051b , +\blk00000003/sig0000051c , \blk00000003/sig0000051d , \blk00000003/sig0000051e , \blk00000003/sig0000051f , \blk00000003/sig00000520 , +\blk00000003/sig00000521 , \blk00000003/sig00000522 , \blk00000003/sig00000523 , \blk00000003/sig00000524 , \blk00000003/sig00000525 , +\blk00000003/sig00000526 , \blk00000003/sig00000527 , \blk00000003/sig00000528 , \blk00000003/sig00000529 , \blk00000003/sig0000052a , +\blk00000003/sig0000052b , \blk00000003/sig0000052c , \blk00000003/sig0000052d , \blk00000003/sig0000052e , \blk00000003/sig0000052f , +\blk00000003/sig00000530 , \blk00000003/sig00000531 , \blk00000003/sig00000532 , \blk00000003/sig00000533 , \blk00000003/sig00000534 , +\blk00000003/sig00000535 , \blk00000003/sig00000536 , \blk00000003/sig00000537 }), + .C({\NLW_blk00000003/blk000000fd_C<47>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<46>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<45>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<44>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<43>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<42>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<41>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<40>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<39>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<38>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<37>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<36>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<35>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<33>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<32>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<30>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<29>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<27>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<26>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<24>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<23>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<21>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<20>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<18>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<17>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<15>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<14>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<13>_UNCONNECTED , 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\NLW_blk00000003/blk000000fd_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000538 , \blk00000003/sig00000538 , \blk00000003/sig00000538 , \blk00000003/sig00000538 , \blk00000003/sig00000538 , +\blk00000003/sig00000538 , \blk00000003/sig00000538 , \blk00000003/sig00000538 , \blk00000003/sig00000538 , \blk00000003/sig00000538 , +\blk00000003/sig00000538 , \blk00000003/sig00000539 , \blk00000003/sig0000053a , \blk00000003/sig0000053b , \blk00000003/sig0000053c , +\blk00000003/sig0000053d , \blk00000003/sig0000053e , \blk00000003/sig0000053f }), + .PCOUT({\blk00000003/sig00000180 , \blk00000003/sig00000181 , \blk00000003/sig00000182 , \blk00000003/sig00000183 , \blk00000003/sig00000184 , +\blk00000003/sig00000185 , \blk00000003/sig00000186 , \blk00000003/sig00000187 , \blk00000003/sig00000188 , \blk00000003/sig00000189 , +\blk00000003/sig0000018a , \blk00000003/sig0000018b , \blk00000003/sig0000018c , \blk00000003/sig0000018d , \blk00000003/sig0000018e , +\blk00000003/sig0000018f , \blk00000003/sig00000190 , \blk00000003/sig00000191 , \blk00000003/sig00000192 , \blk00000003/sig00000193 , +\blk00000003/sig00000194 , \blk00000003/sig00000195 , \blk00000003/sig00000196 , \blk00000003/sig00000197 , \blk00000003/sig00000198 , +\blk00000003/sig00000199 , \blk00000003/sig0000019a , \blk00000003/sig0000019b , \blk00000003/sig0000019c , \blk00000003/sig0000019d , +\blk00000003/sig0000019e , \blk00000003/sig0000019f , \blk00000003/sig000001a0 , \blk00000003/sig000001a1 , \blk00000003/sig000001a2 , +\blk00000003/sig000001a3 , \blk00000003/sig000001a4 , \blk00000003/sig000001a5 , \blk00000003/sig000001a6 , \blk00000003/sig000001a7 , +\blk00000003/sig000001a8 , \blk00000003/sig000001a9 , \blk00000003/sig000001aa , \blk00000003/sig000001ab , \blk00000003/sig000001ac , +\blk00000003/sig000001ad , \blk00000003/sig000001ae , \blk00000003/sig000001af }), + .A({\blk00000003/sig000004ee , \blk00000003/sig000004ef , \blk00000003/sig000004f0 , \blk00000003/sig000004f1 , \blk00000003/sig000004f2 , +\blk00000003/sig000004f3 , \blk00000003/sig000004f4 , \blk00000003/sig000004f5 , \blk00000003/sig000004f6 , \blk00000003/sig000004f7 , +\blk00000003/sig000004f8 , \blk00000003/sig000004f9 , \blk00000003/sig000004fa , \blk00000003/sig000004fb , \blk00000003/sig000004fc , +\blk00000003/sig000004fd , \blk00000003/sig000004fe , \blk00000003/sig000004ff }), + .M({\NLW_blk00000003/blk000000fd_M<35>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_M<33>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<32>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_M<30>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<29>_UNCONNECTED , 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\NLW_blk00000003/blk000000fd_M<8>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_M<6>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<5>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_M<3>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<2>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk000000fc ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk000000fc_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk000000fc_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig000004ae , \blk00000003/sig000004ae , \blk00000003/sig000004ae , \blk00000003/sig000004ae , \blk00000003/sig000004ae , +\blk00000003/sig000004ae , \blk00000003/sig000004ae , \blk00000003/sig000004ae , \blk00000003/sig000004ae , \blk00000003/sig000004ae , +\blk00000003/sig000004ae , \blk00000003/sig000004af , \blk00000003/sig000004b0 , \blk00000003/sig000004b1 , \blk00000003/sig000004b2 , +\blk00000003/sig000004b3 , \blk00000003/sig000004b4 , \blk00000003/sig000004b5 }), + .BCOUT({\NLW_blk00000003/blk000000fc_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000004b6 , \blk00000003/sig000004b7 , \blk00000003/sig000004b8 , \blk00000003/sig000004b9 , \blk00000003/sig000004ba , +\blk00000003/sig000004bb , \blk00000003/sig000004bc , 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\blk00000003/sig000004e1 , \blk00000003/sig000004e2 , +\blk00000003/sig000004e3 , \blk00000003/sig000004e4 , \blk00000003/sig000004e5 }), + .C({\NLW_blk00000003/blk000000fc_C<47>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<46>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<45>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<44>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<43>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<42>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<41>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<40>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<39>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<38>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<37>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<36>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<35>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<33>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<32>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<30>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<29>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<27>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<26>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<24>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<23>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<21>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<20>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<18>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<17>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<15>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<14>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<12>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<11>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<9>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<8>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<6>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<5>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<3>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<2>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk000000fc_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<39>_UNCONNECTED , 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\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig000004e6 , \blk00000003/sig000004e6 , \blk00000003/sig000004e6 , \blk00000003/sig000004e6 , \blk00000003/sig000004e6 , +\blk00000003/sig000004e6 , \blk00000003/sig000004e6 , \blk00000003/sig000004e6 , \blk00000003/sig000004e6 , \blk00000003/sig000004e6 , +\blk00000003/sig000004e6 , \blk00000003/sig000004e7 , \blk00000003/sig000004e8 , \blk00000003/sig000004e9 , \blk00000003/sig000004ea , +\blk00000003/sig000004eb , \blk00000003/sig000004ec , \blk00000003/sig000004ed }), + .PCOUT({\blk00000003/sig0000021a , \blk00000003/sig0000021b , \blk00000003/sig0000021c , \blk00000003/sig0000021d , \blk00000003/sig0000021e , +\blk00000003/sig0000021f , \blk00000003/sig00000220 , \blk00000003/sig00000221 , \blk00000003/sig00000222 , \blk00000003/sig00000223 , +\blk00000003/sig00000224 , \blk00000003/sig00000225 , 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.A({\blk00000003/sig000004ee , \blk00000003/sig000004ef , \blk00000003/sig000004f0 , \blk00000003/sig000004f1 , \blk00000003/sig000004f2 , +\blk00000003/sig000004f3 , \blk00000003/sig000004f4 , \blk00000003/sig000004f5 , \blk00000003/sig000004f6 , \blk00000003/sig000004f7 , +\blk00000003/sig000004f8 , \blk00000003/sig000004f9 , \blk00000003/sig000004fa , \blk00000003/sig000004fb , \blk00000003/sig000004fc , +\blk00000003/sig000004fd , \blk00000003/sig000004fe , \blk00000003/sig000004ff }), + .M({\NLW_blk00000003/blk000000fc_M<35>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_M<33>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<32>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_M<30>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<29>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_M<27>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<26>_UNCONNECTED , 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\NLW_blk00000003/blk000000fc_M<5>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_M<3>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<2>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk000000fb ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk000000fb_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk000000fb_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig0000045e , \blk00000003/sig0000045f , \blk00000003/sig00000460 , +\blk00000003/sig00000461 , \blk00000003/sig00000462 , \blk00000003/sig00000463 , \blk00000003/sig00000464 , \blk00000003/sig00000465 , +\blk00000003/sig00000466 , \blk00000003/sig00000467 , \blk00000003/sig00000468 , \blk00000003/sig00000469 , \blk00000003/sig0000046a , +\blk00000003/sig0000046b , \blk00000003/sig0000046c , \blk00000003/sig0000046d }), + .BCOUT({\NLW_blk00000003/blk000000fb_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<13>_UNCONNECTED , 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\NLW_blk00000003/blk000000fa_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig0000041e , \blk00000003/sig0000041f , \blk00000003/sig00000420 , +\blk00000003/sig00000421 , \blk00000003/sig00000422 , \blk00000003/sig00000423 , \blk00000003/sig00000424 , \blk00000003/sig00000425 , +\blk00000003/sig00000426 , \blk00000003/sig00000427 , \blk00000003/sig00000428 , \blk00000003/sig00000429 , \blk00000003/sig0000042a , +\blk00000003/sig0000042b , \blk00000003/sig0000042c , \blk00000003/sig0000042d }), + .PCOUT({\blk00000003/sig0000042e , \blk00000003/sig0000042f , \blk00000003/sig00000430 , \blk00000003/sig00000431 , \blk00000003/sig00000432 , +\blk00000003/sig00000433 , \blk00000003/sig00000434 , \blk00000003/sig00000435 , \blk00000003/sig00000436 , \blk00000003/sig00000437 , +\blk00000003/sig00000438 , \blk00000003/sig00000439 , \blk00000003/sig0000043a , \blk00000003/sig0000043b , \blk00000003/sig0000043c , +\blk00000003/sig0000043d , \blk00000003/sig0000043e , \blk00000003/sig0000043f , \blk00000003/sig00000440 , \blk00000003/sig00000441 , +\blk00000003/sig00000442 , \blk00000003/sig00000443 , \blk00000003/sig00000444 , \blk00000003/sig00000445 , \blk00000003/sig00000446 , +\blk00000003/sig00000447 , \blk00000003/sig00000448 , \blk00000003/sig00000449 , \blk00000003/sig0000044a , \blk00000003/sig0000044b , +\blk00000003/sig0000044c , \blk00000003/sig0000044d , \blk00000003/sig0000044e , \blk00000003/sig0000044f , \blk00000003/sig00000450 , +\blk00000003/sig00000451 , \blk00000003/sig00000452 , \blk00000003/sig00000453 , \blk00000003/sig00000454 , \blk00000003/sig00000455 , +\blk00000003/sig00000456 , \blk00000003/sig00000457 , \blk00000003/sig00000458 , \blk00000003/sig00000459 , \blk00000003/sig0000045a , +\blk00000003/sig0000045b , \blk00000003/sig0000045c , \blk00000003/sig0000045d }), + .A({\blk00000003/sig000003bc , \blk00000003/sig000003bd , \blk00000003/sig000003be , \blk00000003/sig000003bf , \blk00000003/sig000003c0 , +\blk00000003/sig000003c1 , \blk00000003/sig000003c2 , \blk00000003/sig000003c3 , \blk00000003/sig000003c4 , \blk00000003/sig000003c5 , +\blk00000003/sig000003c6 , \blk00000003/sig000003c7 , \blk00000003/sig000003c8 , \blk00000003/sig000003c9 , \blk00000003/sig000003ca , +\blk00000003/sig000003cb , \blk00000003/sig000003cc , \blk00000003/sig000003cd }), + .M({\NLW_blk00000003/blk000000fa_M<35>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<33>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<32>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<30>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<29>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<27>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<26>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<24>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<23>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<21>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<20>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<18>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<17>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<15>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<14>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<12>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<11>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<9>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<8>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<6>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<5>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<3>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<2>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk000000f9 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk000000f9_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk000000f9_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig000003ce , \blk00000003/sig000003ce , \blk00000003/sig000003ce , \blk00000003/sig000003ce , \blk00000003/sig000003ce , +\blk00000003/sig000003ce , \blk00000003/sig000003ce , \blk00000003/sig000003ce , \blk00000003/sig000003ce , \blk00000003/sig000003ce , +\blk00000003/sig000003ce , \blk00000003/sig000003cf , \blk00000003/sig000003d0 , \blk00000003/sig000003d1 , \blk00000003/sig000003d2 , +\blk00000003/sig000003d3 , \blk00000003/sig000003d4 , \blk00000003/sig000003d5 }), + .BCOUT({\NLW_blk00000003/blk000000f9_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\NLW_blk00000003/blk000000f9_C<47>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<45>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<44>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<42>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<41>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<39>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<38>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<36>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<35>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<33>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<32>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<30>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<29>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<27>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<26>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<24>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<23>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<21>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<20>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<18>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<17>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<15>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<14>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<12>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<11>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<9>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<8>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<6>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<5>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<3>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<2>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk000000f9_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig000003d6 , \blk00000003/sig000003d6 , \blk00000003/sig000003d6 , \blk00000003/sig000003d6 , \blk00000003/sig000003d6 , +\blk00000003/sig000003d6 , \blk00000003/sig000003d6 , \blk00000003/sig000003d6 , \blk00000003/sig000003d6 , \blk00000003/sig000003d6 , +\blk00000003/sig000003d6 , \blk00000003/sig000003d7 , \blk00000003/sig000003d8 , \blk00000003/sig000003d9 , \blk00000003/sig000003da , +\blk00000003/sig000003db , \blk00000003/sig000003dc , \blk00000003/sig000003dd }), + .PCOUT({\blk00000003/sig000003de , \blk00000003/sig000003df , \blk00000003/sig000003e0 , \blk00000003/sig000003e1 , \blk00000003/sig000003e2 , +\blk00000003/sig000003e3 , \blk00000003/sig000003e4 , \blk00000003/sig000003e5 , \blk00000003/sig000003e6 , \blk00000003/sig000003e7 , +\blk00000003/sig000003e8 , \blk00000003/sig000003e9 , \blk00000003/sig000003ea , \blk00000003/sig000003eb , \blk00000003/sig000003ec , +\blk00000003/sig000003ed , \blk00000003/sig000003ee , \blk00000003/sig000003ef , \blk00000003/sig000003f0 , \blk00000003/sig000003f1 , +\blk00000003/sig000003f2 , \blk00000003/sig000003f3 , \blk00000003/sig000003f4 , \blk00000003/sig000003f5 , \blk00000003/sig000003f6 , +\blk00000003/sig000003f7 , \blk00000003/sig000003f8 , \blk00000003/sig000003f9 , \blk00000003/sig000003fa , \blk00000003/sig000003fb , +\blk00000003/sig000003fc , \blk00000003/sig000003fd , \blk00000003/sig000003fe , \blk00000003/sig000003ff , \blk00000003/sig00000400 , +\blk00000003/sig00000401 , \blk00000003/sig00000402 , \blk00000003/sig00000403 , \blk00000003/sig00000404 , \blk00000003/sig00000405 , +\blk00000003/sig00000406 , \blk00000003/sig00000407 , \blk00000003/sig00000408 , \blk00000003/sig00000409 , \blk00000003/sig0000040a , +\blk00000003/sig0000040b , \blk00000003/sig0000040c , \blk00000003/sig0000040d }), + .A({\blk00000003/sig000003bc , \blk00000003/sig000003bd , \blk00000003/sig000003be , \blk00000003/sig000003bf , \blk00000003/sig000003c0 , +\blk00000003/sig000003c1 , \blk00000003/sig000003c2 , \blk00000003/sig000003c3 , \blk00000003/sig000003c4 , \blk00000003/sig000003c5 , +\blk00000003/sig000003c6 , \blk00000003/sig000003c7 , \blk00000003/sig000003c8 , \blk00000003/sig000003c9 , \blk00000003/sig000003ca , +\blk00000003/sig000003cb , \blk00000003/sig000003cc , \blk00000003/sig000003cd }), + .M({\NLW_blk00000003/blk000000f9_M<35>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<33>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<32>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<30>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<29>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<27>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<26>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<24>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<23>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<21>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<20>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<18>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<17>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<15>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<14>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<12>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<11>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<9>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<8>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<6>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<5>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<3>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<2>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk000000f8 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk000000f8_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk000000f8_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig0000037c , \blk00000003/sig0000037c , \blk00000003/sig0000037c , \blk00000003/sig0000037c , \blk00000003/sig0000037c , +\blk00000003/sig0000037c , \blk00000003/sig0000037c , \blk00000003/sig0000037c , \blk00000003/sig0000037c , \blk00000003/sig0000037c , +\blk00000003/sig0000037c , \blk00000003/sig0000037d , \blk00000003/sig0000037e , \blk00000003/sig0000037f , \blk00000003/sig00000380 , +\blk00000003/sig00000381 , \blk00000003/sig00000382 , \blk00000003/sig00000383 }), + .BCOUT({\NLW_blk00000003/blk000000f8_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\NLW_blk00000003/blk000000f8_C<47>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<45>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<44>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<42>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<41>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<39>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<38>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<36>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<35>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<33>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<32>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<30>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<29>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<27>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<26>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<24>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<23>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<21>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<20>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<18>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<17>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<15>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<14>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<12>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<11>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<9>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<8>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<6>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<5>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<3>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<2>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk000000f8_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000384 , \blk00000003/sig00000384 , \blk00000003/sig00000384 , \blk00000003/sig00000384 , \blk00000003/sig00000384 , +\blk00000003/sig00000384 , \blk00000003/sig00000384 , \blk00000003/sig00000384 , \blk00000003/sig00000384 , \blk00000003/sig00000384 , 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\blk00000003/sig000003a8 , \blk00000003/sig000003a9 , +\blk00000003/sig000003aa , \blk00000003/sig000003ab , \blk00000003/sig000003ac , \blk00000003/sig000003ad , \blk00000003/sig000003ae , +\blk00000003/sig000003af , \blk00000003/sig000003b0 , \blk00000003/sig000003b1 , \blk00000003/sig000003b2 , \blk00000003/sig000003b3 , +\blk00000003/sig000003b4 , \blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , \blk00000003/sig000003b8 , +\blk00000003/sig000003b9 , \blk00000003/sig000003ba , \blk00000003/sig000003bb }), + .A({\blk00000003/sig000003bc , \blk00000003/sig000003bd , \blk00000003/sig000003be , \blk00000003/sig000003bf , \blk00000003/sig000003c0 , +\blk00000003/sig000003c1 , \blk00000003/sig000003c2 , \blk00000003/sig000003c3 , \blk00000003/sig000003c4 , \blk00000003/sig000003c5 , +\blk00000003/sig000003c6 , \blk00000003/sig000003c7 , \blk00000003/sig000003c8 , \blk00000003/sig000003c9 , \blk00000003/sig000003ca , +\blk00000003/sig000003cb , \blk00000003/sig000003cc , \blk00000003/sig000003cd }), + .M({\NLW_blk00000003/blk000000f8_M<35>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<33>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<32>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<30>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<29>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<27>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<26>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<24>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<23>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<21>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<20>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<18>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<17>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<15>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<14>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<12>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<11>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<9>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<8>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<6>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<5>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<3>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<2>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<0>_UNCONNECTED }) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029f ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000037b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000379 ), + .Q(\blk00000003/sig0000037a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000378 ), + .Q(\blk00000003/sig00000374 ) + ); + XORCY \blk00000003/blk000000f4 ( + .CI(\blk00000003/sig00000374 ), + .LI(\blk00000003/sig00000376 ), + .O(\blk00000003/sig00000377 ) + ); + MUXCY_D \blk00000003/blk000000f3 ( + .CI(\blk00000003/sig00000374 ), + .DI(\blk00000003/sig00000375 ), + .S(\blk00000003/sig00000376 ), + .O(\NLW_blk00000003/blk000000f3_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000f3_LO_UNCONNECTED ) + ); + FDE \blk00000003/blk000000f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000372 ), + .Q(\blk00000003/sig00000373 ) + ); + XORCY \blk00000003/blk000000f1 ( + .CI(\blk00000003/sig0000036e ), + .LI(\blk00000003/sig00000370 ), + .O(\blk00000003/sig00000371 ) + ); + MUXCY_D \blk00000003/blk000000f0 ( + .CI(\blk00000003/sig0000036e ), + .DI(\blk00000003/sig0000036f ), + .S(\blk00000003/sig00000370 ), + .O(\NLW_blk00000003/blk000000f0_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000f0_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000ef ( + .CI(\blk00000003/sig00000049 ), + .DI(NlwRenamedSig_OI_rfd), + .S(\blk00000003/sig0000036d ), + .O(\blk00000003/sig0000036e ) + ); + XORCY \blk00000003/blk000000ee ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig0000036b ), + .O(\blk00000003/sig0000036c ) + ); + MUXCY_D \blk00000003/blk000000ed ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig0000036a ), + .S(\blk00000003/sig0000036b ), + .O(\NLW_blk00000003/blk000000ed_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000ed_LO_UNCONNECTED ) + ); + MUXCY_L \blk00000003/blk000000ec ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000369 ), + .S(\blk00000003/sig00000363 ), + .LO(\blk00000003/sig00000365 ) + ); + MUXCY_D \blk00000003/blk000000eb ( + .CI(\blk00000003/sig00000365 ), + .DI(\blk00000003/sig00000368 ), + .S(\blk00000003/sig00000366 ), + .O(\NLW_blk00000003/blk000000eb_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000eb_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000ea ( + .CI(\blk00000003/sig00000365 ), + .LI(\blk00000003/sig00000366 ), + .O(\blk00000003/sig00000367 ) + ); + XORCY \blk00000003/blk000000e9 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000363 ), + .O(\blk00000003/sig00000364 ) + ); + MUXCY_L \blk00000003/blk000000e8 ( + .CI(\blk00000003/sig0000035c ), + .DI(\blk00000003/sig000002ba ), + .S(\blk00000003/sig0000035d ), + .LO(\blk00000003/sig0000035f ) + ); + MUXCY_D \blk00000003/blk000000e7 ( + .CI(\blk00000003/sig0000035f ), + .DI(\blk00000003/sig000002b9 ), + .S(\blk00000003/sig00000360 ), + .O(\NLW_blk00000003/blk000000e7_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000e7_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000e6 ( + .CI(\blk00000003/sig00000049 ), + .DI(NlwRenamedSig_OI_rfd), + .S(\blk00000003/sig00000362 ), + .O(\blk00000003/sig0000035c ) + ); + XORCY \blk00000003/blk000000e5 ( + .CI(\blk00000003/sig0000035f ), + .LI(\blk00000003/sig00000360 ), + .O(\blk00000003/sig00000361 ) + ); + XORCY \blk00000003/blk000000e4 ( + .CI(\blk00000003/sig0000035c ), + .LI(\blk00000003/sig0000035d ), + .O(\blk00000003/sig0000035e ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000034d ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002f2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000034c ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002ef ) + ); + MUXCY_D \blk00000003/blk000000e1 ( + .CI(\blk00000003/sig000002ef ), + .DI(\blk00000003/sig0000035a ), + .S(\blk00000003/sig0000035b ), + .O(\blk00000003/sig00000357 ), + .LO(\NLW_blk00000003/blk000000e1_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000e0 ( + .CI(\blk00000003/sig00000357 ), + .DI(\blk00000003/sig00000358 ), + .S(\blk00000003/sig00000359 ), + .O(\blk00000003/sig00000355 ), + .LO(\NLW_blk00000003/blk000000e0_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000df ( + .CI(\blk00000003/sig00000355 ), + .DI(\blk00000003/sig0000034b ), + .S(\blk00000003/sig00000356 ), + .O(\blk00000003/sig00000352 ), + .LO(\NLW_blk00000003/blk000000df_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000de ( + .CI(\blk00000003/sig00000352 ), + .DI(\blk00000003/sig00000353 ), + .S(\blk00000003/sig00000354 ), + .O(\blk00000003/sig00000350 ), + .LO(\NLW_blk00000003/blk000000de_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000dd ( + .CI(\blk00000003/sig00000350 ), + .DI(\blk00000003/sig0000031e ), + .S(\blk00000003/sig00000351 ), + .O(\blk00000003/sig0000034e ), + .LO(\NLW_blk00000003/blk000000dd_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000dc ( + .CI(\blk00000003/sig0000034e ), + .DI(\blk00000003/sig000002ec ), + .S(\blk00000003/sig0000034f ), + .O(\NLW_blk00000003/blk000000dc_O_UNCONNECTED ), + .LO(\blk00000003/sig0000034c ) + ); + XORCY \blk00000003/blk000000db ( + .CI(\blk00000003/sig0000034c ), + .LI(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig0000034d ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000da ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000033b ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000034b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000033a ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000029f ) + ); + MUXCY_D \blk00000003/blk000000d8 ( + .CI(\blk00000003/sig0000029f ), + .DI(\blk00000003/sig00000349 ), + .S(\blk00000003/sig0000034a ), + .O(\blk00000003/sig00000347 ), + .LO(\NLW_blk00000003/blk000000d8_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d7 ( + .CI(\blk00000003/sig00000347 ), + .DI(\blk00000003/sig000002a0 ), + .S(\blk00000003/sig00000348 ), + .O(\blk00000003/sig00000345 ), + .LO(\NLW_blk00000003/blk000000d7_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d6 ( + .CI(\blk00000003/sig00000345 ), + .DI(\blk00000003/sig0000029f ), + .S(\blk00000003/sig00000346 ), + .O(\blk00000003/sig00000342 ), + .LO(\NLW_blk00000003/blk000000d6_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d5 ( + .CI(\blk00000003/sig00000342 ), + .DI(\blk00000003/sig00000343 ), + .S(\blk00000003/sig00000344 ), + .O(\blk00000003/sig00000340 ), + .LO(\NLW_blk00000003/blk000000d5_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d4 ( + .CI(\blk00000003/sig00000340 ), + .DI(\blk00000003/sig000002f2 ), + .S(\blk00000003/sig00000341 ), + .O(\blk00000003/sig0000033c ), + .LO(\NLW_blk00000003/blk000000d4_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d3 ( + .CI(\blk00000003/sig0000033e ), + .DI(\blk00000003/sig000002f2 ), + .S(\blk00000003/sig0000033f ), + .O(\NLW_blk00000003/blk000000d3_O_UNCONNECTED ), + .LO(\blk00000003/sig0000033a ) + ); + MUXCY_D \blk00000003/blk000000d2 ( + .CI(\blk00000003/sig0000033c ), + .DI(\blk00000003/sig00000313 ), + .S(\blk00000003/sig0000033d ), + .O(\blk00000003/sig0000033e ), + .LO(\NLW_blk00000003/blk000000d2_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000d1 ( + .CI(\blk00000003/sig0000033a ), + .LI(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig0000033b ) + ); + FDE \blk00000003/blk000000d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000338 ), + .Q(\blk00000003/sig00000339 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ef ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000337 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000324 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000333 ) + ); + XORCY \blk00000003/blk000000cd ( + .CI(\blk00000003/sig00000333 ), + .LI(\blk00000003/sig00000335 ), + .O(\blk00000003/sig00000336 ) + ); + MUXCY_D \blk00000003/blk000000cc ( + .CI(\blk00000003/sig00000333 ), + .DI(\blk00000003/sig00000334 ), + .S(\blk00000003/sig00000335 ), + .O(\NLW_blk00000003/blk000000cc_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000cc_LO_UNCONNECTED ) + ); + MUXCY_L \blk00000003/blk000000cb ( + .CI(\blk00000003/sig00000326 ), + .DI(\blk00000003/sig00000332 ), + .S(\blk00000003/sig00000327 ), + .LO(\blk00000003/sig0000032c ) + ); + MUXCY_L \blk00000003/blk000000ca ( + .CI(\blk00000003/sig0000032c ), + .DI(\blk00000003/sig00000331 ), + .S(\blk00000003/sig0000032d ), + .LO(\blk00000003/sig00000329 ) + ); + MUXCY_D \blk00000003/blk000000c9 ( + .CI(\blk00000003/sig00000329 ), + .DI(\blk00000003/sig00000330 ), + .S(\blk00000003/sig0000032a ), + .O(\NLW_blk00000003/blk000000c9_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000c9_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000c8 ( + .CI(\blk00000003/sig00000049 ), + .DI(NlwRenamedSig_OI_rfd), + .S(\blk00000003/sig0000032f ), + .O(\blk00000003/sig00000326 ) + ); + XORCY \blk00000003/blk000000c7 ( + .CI(\blk00000003/sig0000032c ), + .LI(\blk00000003/sig0000032d ), + .O(\blk00000003/sig0000032e ) + ); + XORCY \blk00000003/blk000000c6 ( + .CI(\blk00000003/sig00000329 ), + .LI(\blk00000003/sig0000032a ), + .O(\blk00000003/sig0000032b ) + ); + XORCY \blk00000003/blk000000c5 ( + .CI(\blk00000003/sig00000326 ), + .LI(\blk00000003/sig00000327 ), + .O(\blk00000003/sig00000328 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c4 ( + .C(clk), + .CE(ce), + .D(coef_ld), + .Q(\blk00000003/sig00000325 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c3 ( + .C(clk), + .CE(ce), + .D(coef_we), + .Q(\blk00000003/sig00000324 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b0 ), + .Q(\blk00000003/sig00000318 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000323 ), + .Q(\blk00000003/sig0000030b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000321 ), + .Q(\blk00000003/sig00000322 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000320 ), + .Q(\blk00000003/sig00000309 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000031f ), + .Q(\blk00000003/sig00000316 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000031d ), + .Q(\blk00000003/sig0000031e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000031b ), + .Q(\blk00000003/sig0000031c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000319 ), + .Q(\blk00000003/sig0000031a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000318 ), + .Q(\blk00000003/sig00000314 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000316 ), + .Q(\blk00000003/sig00000317 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000314 ), + .Q(\blk00000003/sig00000315 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ee ), + .Q(\blk00000003/sig00000313 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000030e ), + .Q(\blk00000003/sig00000312 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000308 ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000b5_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000305 ), + .R(coef_ld), + .Q(\blk00000003/sig00000302 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000300 ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000b3_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002fb ), + .R(coef_ld), + .Q(\blk00000003/sig000002f8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ef ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000311 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000030f ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000310 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000af ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000030d ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000030e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000030b ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000030c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000309 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000030a ) + ); + XORCY \blk00000003/blk000000ac ( + .CI(\blk00000003/sig00000307 ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000308 ) + ); + MUXCY \blk00000003/blk000000ab ( + .CI(\blk00000003/sig00000307 ), + .DI(\blk00000003/sig00000049 ), + .S(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig000002fd ) + ); + MUXCY_D \blk00000003/blk000000aa ( + .CI(coef_we), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000306 ), + .O(\blk00000003/sig00000307 ), + .LO(\NLW_blk00000003/blk000000aa_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000a9 ( + .CI(\blk00000003/sig00000303 ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000305 ) + ); + MUXCY \blk00000003/blk000000a8 ( + .CI(\blk00000003/sig00000303 ), + .DI(\blk00000003/sig00000049 ), + .S(NlwRenamedSig_OI_rfd), + .O(\NLW_blk00000003/blk000000a8_O_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000a7 ( + .CI(NlwRenamedSig_OI_rfd), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000304 ), + .O(\blk00000003/sig00000301 ), + .LO(\NLW_blk00000003/blk000000a7_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000a6 ( + .CI(\blk00000003/sig00000301 ), + .DI(\blk00000003/sig00000302 ), + .S(coef_we), + .O(\blk00000003/sig00000303 ), + .LO(\NLW_blk00000003/blk000000a6_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000a5 ( + .CI(\blk00000003/sig000002ff ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000300 ) + ); + MUXCY \blk00000003/blk000000a4 ( + .CI(\blk00000003/sig000002ff ), + .DI(\blk00000003/sig00000049 ), + .S(NlwRenamedSig_OI_rfd), + .O(\NLW_blk00000003/blk000000a4_O_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000a3 ( + .CI(\blk00000003/sig000002fd ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000002fe ), + .O(\blk00000003/sig000002ff ), + .LO(\NLW_blk00000003/blk000000a3_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000a2 ( + .CI(NlwRenamedSig_OI_rfd), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000002fc ), + .O(\blk00000003/sig000002f7 ), + .LO(\NLW_blk00000003/blk000000a2_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000a1 ( + .CI(\blk00000003/sig000002fa ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig000002fb ) + ); + MUXCY \blk00000003/blk000000a0 ( + .CI(\blk00000003/sig000002fa ), + .DI(\blk00000003/sig00000049 ), + .S(NlwRenamedSig_OI_rfd), + .O(\NLW_blk00000003/blk000000a0_O_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk0000009f ( + .CI(\blk00000003/sig000002f7 ), + .DI(\blk00000003/sig000002f8 ), + .S(\blk00000003/sig000002f9 ), + .O(\blk00000003/sig000002fa ), + .LO(\NLW_blk00000003/blk0000009f_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000009e ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000002f5 ), + .O(\blk00000003/sig000002f6 ) + ); + MUXCY_D \blk00000003/blk0000009d ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000002f4 ), + .S(\blk00000003/sig000002f5 ), + .O(\NLW_blk00000003/blk0000009d_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk0000009d_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000009c ( + .CI(\blk00000003/sig000002ed ), + .LI(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig000002eb ) + ); + MUXCY_D \blk00000003/blk0000009b ( + .CI(\blk00000003/sig000002f1 ), + .DI(\blk00000003/sig000002f2 ), + .S(\blk00000003/sig000002f3 ), + .O(\NLW_blk00000003/blk0000009b_O_UNCONNECTED ), + .LO(\blk00000003/sig000002ed ) + ); + MUXCY_D \blk00000003/blk0000009a ( + .CI(\blk00000003/sig000002ee ), + .DI(\blk00000003/sig000002ef ), + .S(\blk00000003/sig000002f0 ), + .O(\blk00000003/sig000002f1 ), + .LO(\NLW_blk00000003/blk0000009a_LO_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000099 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ed ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002ee ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000098 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002eb ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002ec ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b7 ), + .R(sclr), + .Q(\blk00000003/sig000002b6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000033 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b6 ), + .R(sclr), + .Q(\blk00000003/sig000002b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000032 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b5 ), + .R(\blk00000003/sig000002ae ), + .Q(data_valid) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000031 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b3 ), + .R(sclr), + .Q(\blk00000003/sig000002b4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000030 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b1 ), + .R(sclr), + .Q(\blk00000003/sig000002b2 ) + ); + FDRE \blk00000003/blk0000002f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002af ), + .R(sclr), + .Q(\blk00000003/sig000002b0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ad ), + .R(\blk00000003/sig000002ae ), + .Q(rdy) + ); + FDRE \blk00000003/blk0000002d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ab ), + .R(sclr), + .Q(\blk00000003/sig000002ac ) + ); + FDSE \blk00000003/blk0000002c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a9 ), + .S(sclr), + .Q(\blk00000003/sig000002aa ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029b ), + .R(sclr), + .Q(\blk00000003/sig000002a8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a7 ), + .R(sclr), + .Q(\blk00000003/sig0000029c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000029 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a5 ), + .R(sclr), + .Q(\blk00000003/sig000002a6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000028 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a3 ), + .R(sclr), + .Q(\blk00000003/sig000002a4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000027 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a1 ), + .R(sclr), + .Q(\NLW_blk00000003/blk00000027_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000026 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a1 ), + .R(sclr), + .Q(\blk00000003/sig000002a2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000025 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029f ), + .Q(\blk00000003/sig000002a0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000024 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000176 ), + .R(sclr), + .Q(\blk00000003/sig00000173 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000023 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000170 ), + .R(sclr), + .Q(\NLW_blk00000003/blk00000023_Q_UNCONNECTED ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000022 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000171 ), + .S(sclr), + .Q(\blk00000003/sig0000029e ) + ); + MUXCY_D \blk00000003/blk00000021 ( + .CI(\blk00000003/sig0000029c ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000029d ), + .O(\blk00000003/sig0000029a ), + .LO(\NLW_blk00000003/blk00000021_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk00000020 ( + .CI(\blk00000003/sig0000029a ), + .DI(\blk00000003/sig00000049 ), + .S(NlwRenamedSig_OI_rfd), + .O(\NLW_blk00000003/blk00000020_O_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000001f ( + .CI(\blk00000003/sig0000029a ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig0000029b ) + ); + DSP48A1 #( + .A0REG ( 1 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000001e ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000001e_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000001e_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig0000024a , \blk00000003/sig0000024b , \blk00000003/sig0000024c , +\blk00000003/sig0000024d , \blk00000003/sig0000024e , \blk00000003/sig0000024f , \blk00000003/sig00000250 , \blk00000003/sig00000251 , +\blk00000003/sig00000252 , \blk00000003/sig00000253 , \blk00000003/sig00000254 , \blk00000003/sig00000255 , \blk00000003/sig00000256 , +\blk00000003/sig00000257 , \blk00000003/sig00000258 , \blk00000003/sig00000259 }), + .BCOUT({\NLW_blk00000003/blk0000001e_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig0000025a , \blk00000003/sig0000025b , \blk00000003/sig0000025c , \blk00000003/sig0000025d , \blk00000003/sig0000025e , +\blk00000003/sig0000025f , \blk00000003/sig00000260 , \blk00000003/sig00000261 , \blk00000003/sig00000262 , \blk00000003/sig00000263 , +\blk00000003/sig00000264 , \blk00000003/sig00000265 , \blk00000003/sig00000266 , \blk00000003/sig00000267 , \blk00000003/sig00000268 , +\blk00000003/sig00000269 , \blk00000003/sig0000026a , \blk00000003/sig0000026b , \blk00000003/sig0000026c , \blk00000003/sig0000026d , +\blk00000003/sig0000026e , \blk00000003/sig0000026f , \blk00000003/sig00000270 , \blk00000003/sig00000271 , \blk00000003/sig00000272 , +\blk00000003/sig00000273 , \blk00000003/sig00000274 , \blk00000003/sig00000275 , \blk00000003/sig00000276 , \blk00000003/sig00000277 , +\blk00000003/sig00000278 , \blk00000003/sig00000279 , \blk00000003/sig0000027a , \blk00000003/sig0000027b , \blk00000003/sig0000027c , +\blk00000003/sig0000027d , \blk00000003/sig0000027e , \blk00000003/sig0000027f , \blk00000003/sig00000280 , \blk00000003/sig00000281 , +\blk00000003/sig00000282 , \blk00000003/sig00000283 , \blk00000003/sig00000284 , \blk00000003/sig00000285 , \blk00000003/sig00000286 , +\blk00000003/sig00000287 , \blk00000003/sig00000288 , \blk00000003/sig00000289 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk0000001e_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000001e_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000001e_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000001e_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000001e_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000001e_P<40>_UNCONNECTED , +\blk00000003/sig00000152 , \blk00000003/sig00000153 , \blk00000003/sig00000154 , \blk00000003/sig00000155 , \blk00000003/sig00000156 , +\blk00000003/sig00000157 , \blk00000003/sig00000102 , \blk00000003/sig00000103 , \blk00000003/sig00000104 , \blk00000003/sig00000105 , +\blk00000003/sig00000106 , \blk00000003/sig00000107 , \blk00000003/sig00000108 , \blk00000003/sig00000109 , \blk00000003/sig0000010a , +\blk00000003/sig0000010b , \blk00000003/sig0000010c , \blk00000003/sig0000010d , \blk00000003/sig0000010e , \blk00000003/sig0000010f , +\blk00000003/sig00000110 , \blk00000003/sig00000111 , \blk00000003/sig00000112 , \blk00000003/sig00000113 , \blk00000003/sig0000028a , +\blk00000003/sig0000028b , \blk00000003/sig0000028c , \blk00000003/sig0000028d , \blk00000003/sig0000028e , \blk00000003/sig0000028f , +\blk00000003/sig00000290 , \blk00000003/sig00000291 , \blk00000003/sig00000292 , \blk00000003/sig00000293 , \blk00000003/sig00000294 , +\blk00000003/sig00000295 , \blk00000003/sig00000296 , \blk00000003/sig00000297 , \blk00000003/sig00000298 , \blk00000003/sig00000299 }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000165 , \blk00000003/sig00000167 , \blk00000003/sig00000169 }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .PCOUT({\NLW_blk00000003/blk0000001e_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig000001b0 , \blk00000003/sig000001b1 , \blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , +\blk00000003/sig000001b5 , \blk00000003/sig000001b6 , \blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 , +\blk00000003/sig000001ba , \blk00000003/sig000001bb , \blk00000003/sig000001bc , \blk00000003/sig000001bd , \blk00000003/sig000001be , +\blk00000003/sig000001bf , \blk00000003/sig000001c0 , \blk00000003/sig000001c1 }), + .M({\NLW_blk00000003/blk0000001e_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 1 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000001d ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000001d_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000001d_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000212 , \blk00000003/sig00000212 , \blk00000003/sig00000212 , \blk00000003/sig00000212 , \blk00000003/sig00000212 , +\blk00000003/sig00000212 , \blk00000003/sig00000212 , \blk00000003/sig00000212 , \blk00000003/sig00000212 , \blk00000003/sig00000212 , +\blk00000003/sig00000212 , \blk00000003/sig00000213 , \blk00000003/sig00000214 , \blk00000003/sig00000215 , \blk00000003/sig00000216 , +\blk00000003/sig00000217 , \blk00000003/sig00000218 , \blk00000003/sig00000219 }), + .BCOUT({\NLW_blk00000003/blk0000001d_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig0000021a , \blk00000003/sig0000021b , \blk00000003/sig0000021c , \blk00000003/sig0000021d , \blk00000003/sig0000021e , +\blk00000003/sig0000021f , \blk00000003/sig00000220 , \blk00000003/sig00000221 , \blk00000003/sig00000222 , \blk00000003/sig00000223 , +\blk00000003/sig00000224 , \blk00000003/sig00000225 , \blk00000003/sig00000226 , \blk00000003/sig00000227 , \blk00000003/sig00000228 , +\blk00000003/sig00000229 , \blk00000003/sig0000022a , \blk00000003/sig0000022b , \blk00000003/sig0000022c , \blk00000003/sig0000022d , +\blk00000003/sig0000022e , \blk00000003/sig0000022f , \blk00000003/sig00000230 , \blk00000003/sig00000231 , \blk00000003/sig00000232 , +\blk00000003/sig00000233 , \blk00000003/sig00000234 , \blk00000003/sig00000235 , \blk00000003/sig00000236 , \blk00000003/sig00000237 , +\blk00000003/sig00000238 , \blk00000003/sig00000239 , \blk00000003/sig0000023a , \blk00000003/sig0000023b , \blk00000003/sig0000023c , +\blk00000003/sig0000023d , \blk00000003/sig0000023e , \blk00000003/sig0000023f , \blk00000003/sig00000240 , \blk00000003/sig00000241 , +\blk00000003/sig00000242 , \blk00000003/sig00000243 , \blk00000003/sig00000244 , \blk00000003/sig00000245 , \blk00000003/sig00000246 , +\blk00000003/sig00000247 , \blk00000003/sig00000248 , \blk00000003/sig00000249 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk0000001d_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<31>_UNCONNECTED , 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+\blk00000003/sig00000165 , \blk00000003/sig00000167 , \blk00000003/sig00000169 }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .PCOUT({\NLW_blk00000003/blk0000001d_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig000001b0 , \blk00000003/sig000001b1 , \blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , +\blk00000003/sig000001b5 , \blk00000003/sig000001b6 , \blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 , +\blk00000003/sig000001ba , \blk00000003/sig000001bb , \blk00000003/sig000001bc , \blk00000003/sig000001bd , \blk00000003/sig000001be , +\blk00000003/sig000001bf , \blk00000003/sig000001c0 , \blk00000003/sig000001c1 }), + .M({\NLW_blk00000003/blk0000001d_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 1 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000001c ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000001c_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000001c_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000001c2 , \blk00000003/sig000001c3 , \blk00000003/sig000001c4 , +\blk00000003/sig000001c5 , \blk00000003/sig000001c6 , \blk00000003/sig000001c7 , \blk00000003/sig000001c8 , \blk00000003/sig000001c9 , +\blk00000003/sig000001ca , \blk00000003/sig000001cb , \blk00000003/sig000001cc , \blk00000003/sig000001cd , \blk00000003/sig000001ce , +\blk00000003/sig000001cf , \blk00000003/sig000001d0 , \blk00000003/sig000001d1 }), + .BCOUT({\NLW_blk00000003/blk0000001c_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000001d2 , 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\blk00000003/sig000001f7 , \blk00000003/sig000001f8 , \blk00000003/sig000001f9 , +\blk00000003/sig000001fa , \blk00000003/sig000001fb , \blk00000003/sig000001fc , \blk00000003/sig000001fd , \blk00000003/sig000001fe , +\blk00000003/sig000001ff , \blk00000003/sig00000200 , \blk00000003/sig00000201 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , 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\NLW_blk00000003/blk0000001c_P<40>_UNCONNECTED , +\blk00000003/sig000000fc , \blk00000003/sig000000fd , \blk00000003/sig000000fe , \blk00000003/sig000000ff , \blk00000003/sig00000100 , +\blk00000003/sig00000101 , \blk00000003/sig000000ac , \blk00000003/sig000000ad , \blk00000003/sig000000ae , \blk00000003/sig000000af , +\blk00000003/sig000000b0 , \blk00000003/sig000000b1 , \blk00000003/sig000000b2 , \blk00000003/sig000000b3 , \blk00000003/sig000000b4 , +\blk00000003/sig000000b5 , \blk00000003/sig000000b6 , \blk00000003/sig000000b7 , \blk00000003/sig000000b8 , \blk00000003/sig000000b9 , +\blk00000003/sig000000ba , \blk00000003/sig000000bb , \blk00000003/sig000000bc , \blk00000003/sig000000bd , \blk00000003/sig00000202 , +\blk00000003/sig00000203 , \blk00000003/sig00000204 , \blk00000003/sig00000205 , \blk00000003/sig00000206 , \blk00000003/sig00000207 , +\blk00000003/sig00000208 , \blk00000003/sig00000209 , \blk00000003/sig0000020a , \blk00000003/sig0000020b , \blk00000003/sig0000020c , +\blk00000003/sig0000020d , \blk00000003/sig0000020e , \blk00000003/sig0000020f , \blk00000003/sig00000210 , \blk00000003/sig00000211 }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000165 , \blk00000003/sig00000167 , \blk00000003/sig00000169 }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .PCOUT({\NLW_blk00000003/blk0000001c_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<46>_UNCONNECTED , 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+\NLW_blk00000003/blk0000001c_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig000001b0 , \blk00000003/sig000001b1 , \blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , +\blk00000003/sig000001b5 , \blk00000003/sig000001b6 , \blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 , +\blk00000003/sig000001ba , \blk00000003/sig000001bb , \blk00000003/sig000001bc , \blk00000003/sig000001bd , \blk00000003/sig000001be , +\blk00000003/sig000001bf , \blk00000003/sig000001c0 , \blk00000003/sig000001c1 }), + .M({\NLW_blk00000003/blk0000001c_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 1 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000001b ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000001b_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000001b_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000178 , \blk00000003/sig00000178 , \blk00000003/sig00000178 , \blk00000003/sig00000178 , \blk00000003/sig00000178 , +\blk00000003/sig00000178 , \blk00000003/sig00000178 , \blk00000003/sig00000178 , \blk00000003/sig00000178 , \blk00000003/sig00000178 , +\blk00000003/sig00000178 , \blk00000003/sig00000179 , \blk00000003/sig0000017a , \blk00000003/sig0000017b , \blk00000003/sig0000017c , +\blk00000003/sig0000017d , \blk00000003/sig0000017e , \blk00000003/sig0000017f }), + .BCOUT({\NLW_blk00000003/blk0000001b_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000180 , \blk00000003/sig00000181 , \blk00000003/sig00000182 , \blk00000003/sig00000183 , \blk00000003/sig00000184 , +\blk00000003/sig00000185 , \blk00000003/sig00000186 , \blk00000003/sig00000187 , \blk00000003/sig00000188 , \blk00000003/sig00000189 , +\blk00000003/sig0000018a , \blk00000003/sig0000018b , \blk00000003/sig0000018c , \blk00000003/sig0000018d , \blk00000003/sig0000018e , +\blk00000003/sig0000018f , \blk00000003/sig00000190 , \blk00000003/sig00000191 , \blk00000003/sig00000192 , \blk00000003/sig00000193 , +\blk00000003/sig00000194 , \blk00000003/sig00000195 , \blk00000003/sig00000196 , \blk00000003/sig00000197 , \blk00000003/sig00000198 , +\blk00000003/sig00000199 , \blk00000003/sig0000019a , \blk00000003/sig0000019b , \blk00000003/sig0000019c , \blk00000003/sig0000019d , +\blk00000003/sig0000019e , \blk00000003/sig0000019f , \blk00000003/sig000001a0 , \blk00000003/sig000001a1 , \blk00000003/sig000001a2 , +\blk00000003/sig000001a3 , \blk00000003/sig000001a4 , \blk00000003/sig000001a5 , \blk00000003/sig000001a6 , \blk00000003/sig000001a7 , +\blk00000003/sig000001a8 , \blk00000003/sig000001a9 , \blk00000003/sig000001aa , \blk00000003/sig000001ab , \blk00000003/sig000001ac , +\blk00000003/sig000001ad , \blk00000003/sig000001ae , \blk00000003/sig000001af }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk0000001b_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<31>_UNCONNECTED , +\blk00000003/sig000000be , \blk00000003/sig000000bf , \blk00000003/sig000000c0 , \blk00000003/sig000000c1 , \blk00000003/sig000000c2 , +\blk00000003/sig000000c3 , \blk00000003/sig000000c4 , \blk00000003/sig000000c5 , \blk00000003/sig000000c6 , \blk00000003/sig000000c7 , +\blk00000003/sig000000c8 , \blk00000003/sig000000c9 , \blk00000003/sig000000ca , \blk00000003/sig000000cb , \blk00000003/sig000000cc , +\blk00000003/sig000000cd , \blk00000003/sig000000ce , \blk00000003/sig000000cf , \blk00000003/sig000000d0 , \blk00000003/sig000000d1 , +\blk00000003/sig000000d2 , \blk00000003/sig000000d3 , \blk00000003/sig000000d4 , \blk00000003/sig000000d5 , \blk00000003/sig000000d6 , +\blk00000003/sig000000d7 , \blk00000003/sig000000d8 , \blk00000003/sig000000d9 , \blk00000003/sig000000da , \blk00000003/sig000000db , +\blk00000003/sig000000dc }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000165 , \blk00000003/sig00000167 , \blk00000003/sig00000169 }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .PCOUT({\NLW_blk00000003/blk0000001b_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig000001b0 , \blk00000003/sig000001b1 , \blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , +\blk00000003/sig000001b5 , \blk00000003/sig000001b6 , \blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 , +\blk00000003/sig000001ba , \blk00000003/sig000001bb , \blk00000003/sig000001bc , \blk00000003/sig000001bd , \blk00000003/sig000001be , +\blk00000003/sig000001bf , \blk00000003/sig000001c0 , \blk00000003/sig000001c1 }), + .M({\NLW_blk00000003/blk0000001b_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<0>_UNCONNECTED }) + ); + MUXCY_D \blk00000003/blk0000001a ( + .CI(NlwRenamedSig_OI_rfd), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000177 ), + .O(\blk00000003/sig00000172 ), + .LO(\NLW_blk00000003/blk0000001a_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000019 ( + .CI(\blk00000003/sig00000175 ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000176 ) + ); + MUXCY \blk00000003/blk00000018 ( + .CI(\blk00000003/sig00000175 ), + .DI(\blk00000003/sig00000049 ), + .S(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig0000016a ) + ); + MUXCY_D \blk00000003/blk00000017 ( + .CI(\blk00000003/sig00000172 ), + .DI(\blk00000003/sig00000173 ), + .S(\blk00000003/sig00000174 ), + .O(\blk00000003/sig00000175 ), + .LO(\NLW_blk00000003/blk00000017_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000016 ( + .CI(\blk00000003/sig00000170 ), + .LI(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig00000171 ) + ); + MUXCY_D \blk00000003/blk00000015 ( + .CI(\blk00000003/sig0000016d ), + .DI(\blk00000003/sig0000016e ), + .S(\blk00000003/sig0000016f ), + .O(\NLW_blk00000003/blk00000015_O_UNCONNECTED ), + .LO(\blk00000003/sig00000170 ) + ); + MUXCY_D \blk00000003/blk00000014 ( + .CI(\blk00000003/sig0000016a ), + .DI(\blk00000003/sig0000016b ), + .S(\blk00000003/sig0000016c ), + .O(\blk00000003/sig0000016d ), + .LO(\NLW_blk00000003/blk00000014_LO_UNCONNECTED ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000013 ( + .C(clk), + .D(\blk00000003/sig00000168 ), + .Q(\blk00000003/sig00000169 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000012 ( + .C(clk), + .D(\blk00000003/sig00000166 ), + .Q(\blk00000003/sig00000167 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000011 ( + .C(clk), + .D(\blk00000003/sig00000164 ), + .Q(\blk00000003/sig00000165 ) + ); + XORCY \blk00000003/blk00000010 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000162 ), + .O(\blk00000003/sig00000163 ) + ); + MUXCY_D \blk00000003/blk0000000f ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000161 ), + .S(\blk00000003/sig00000162 ), + .O(\NLW_blk00000003/blk0000000f_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk0000000f_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk0000000e ( + .CI(\blk00000003/sig0000015c ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000160 ), + .O(\NLW_blk00000003/blk0000000e_O_UNCONNECTED ), + .LO(\blk00000003/sig0000015e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000000d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000015e ), + .R(sclr), + .Q(\blk00000003/sig0000015f ) + ); + MUXCY_D \blk00000003/blk0000000c ( + .CI(NlwRenamedSig_OI_rfd), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000015d ), + .O(\blk00000003/sig0000015a ), + .LO(\NLW_blk00000003/blk0000000c_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000000b ( + .CI(\blk00000003/sig0000015b ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000158 ) + ); + MUXCY \blk00000003/blk0000000a ( + .CI(\blk00000003/sig0000015b ), + .DI(\blk00000003/sig00000049 ), + .S(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig0000015c ) + ); + MUXCY_D \blk00000003/blk00000009 ( + .CI(\blk00000003/sig0000015a ), + .DI(\blk00000003/sig00000159 ), + .S(nd), + .O(\blk00000003/sig0000015b ), + .LO(\NLW_blk00000003/blk00000009_LO_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000008 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000158 ), + .R(sclr), + .Q(\blk00000003/sig00000159 ) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 0 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000007 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000007_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000007_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000102 , \blk00000003/sig00000103 , \blk00000003/sig00000104 , \blk00000003/sig00000105 , \blk00000003/sig00000106 , +\blk00000003/sig00000107 , \blk00000003/sig00000108 , \blk00000003/sig00000109 , \blk00000003/sig0000010a , \blk00000003/sig0000010b , +\blk00000003/sig0000010c , \blk00000003/sig0000010d , \blk00000003/sig0000010e , \blk00000003/sig0000010f , \blk00000003/sig00000110 , +\blk00000003/sig00000111 , \blk00000003/sig00000112 , \blk00000003/sig00000113 }), + .BCOUT({\NLW_blk00000003/blk00000007_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , +\blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , +\blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , +\blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000115 , \blk00000003/sig00000116 , +\blk00000003/sig00000117 , \blk00000003/sig00000118 , \blk00000003/sig00000119 , \blk00000003/sig0000011a , \blk00000003/sig0000011b , +\blk00000003/sig0000011c , \blk00000003/sig0000011d , \blk00000003/sig0000011e , \blk00000003/sig0000011f , \blk00000003/sig00000120 , +\blk00000003/sig00000121 , \blk00000003/sig00000122 , \blk00000003/sig00000123 , \blk00000003/sig00000124 , \blk00000003/sig00000125 , +\blk00000003/sig00000126 , \blk00000003/sig00000127 , \blk00000003/sig00000128 , \blk00000003/sig00000129 , \blk00000003/sig0000012a , +\blk00000003/sig0000012b , \blk00000003/sig0000012c , \blk00000003/sig0000012d , \blk00000003/sig0000012e , \blk00000003/sig0000012f , +\blk00000003/sig00000130 , \blk00000003/sig00000131 , \blk00000003/sig00000132 }), + .P({\NLW_blk00000003/blk00000007_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000007_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000007_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000007_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000007_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000007_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<31>_UNCONNECTED , +\blk00000003/sig00000133 , \blk00000003/sig00000134 , \blk00000003/sig00000135 , \blk00000003/sig00000136 , \blk00000003/sig00000137 , +\blk00000003/sig00000138 , \blk00000003/sig00000139 , \blk00000003/sig0000013a , \blk00000003/sig0000013b , \blk00000003/sig0000013c , +\blk00000003/sig0000013d , \blk00000003/sig0000013e , \blk00000003/sig0000013f , \blk00000003/sig00000140 , \blk00000003/sig00000141 , +\blk00000003/sig00000142 , \blk00000003/sig00000143 , \blk00000003/sig00000144 , \blk00000003/sig00000145 , \blk00000003/sig00000146 , +\blk00000003/sig00000147 , \blk00000003/sig00000148 , \blk00000003/sig00000149 , \blk00000003/sig0000014a , \blk00000003/sig0000014b , +\blk00000003/sig0000014c , \blk00000003/sig0000014d , \blk00000003/sig0000014e , \blk00000003/sig0000014f , \blk00000003/sig00000150 , +\blk00000003/sig00000151 }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +NlwRenamedSig_OI_rfd, NlwRenamedSig_OI_rfd, NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , +\blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , +\blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , +\blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 }), + .PCOUT({\NLW_blk00000003/blk00000007_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , +\blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , +\blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000153 , \blk00000003/sig00000154 , +\blk00000003/sig00000155 , \blk00000003/sig00000156 , \blk00000003/sig00000157 }), + .M({\NLW_blk00000003/blk00000007_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 0 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000006 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000006_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000006_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig000000ac , \blk00000003/sig000000ad , \blk00000003/sig000000ae , \blk00000003/sig000000af , \blk00000003/sig000000b0 , +\blk00000003/sig000000b1 , \blk00000003/sig000000b2 , \blk00000003/sig000000b3 , \blk00000003/sig000000b4 , \blk00000003/sig000000b5 , +\blk00000003/sig000000b6 , \blk00000003/sig000000b7 , \blk00000003/sig000000b8 , \blk00000003/sig000000b9 , \blk00000003/sig000000ba , +\blk00000003/sig000000bb , \blk00000003/sig000000bc , \blk00000003/sig000000bd }), + .BCOUT({\NLW_blk00000003/blk00000006_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , +\blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , +\blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , +\blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000bf , \blk00000003/sig000000c0 , +\blk00000003/sig000000c1 , \blk00000003/sig000000c2 , \blk00000003/sig000000c3 , \blk00000003/sig000000c4 , \blk00000003/sig000000c5 , +\blk00000003/sig000000c6 , \blk00000003/sig000000c7 , \blk00000003/sig000000c8 , \blk00000003/sig000000c9 , \blk00000003/sig000000ca , +\blk00000003/sig000000cb , \blk00000003/sig000000cc , \blk00000003/sig000000cd , \blk00000003/sig000000ce , \blk00000003/sig000000cf , +\blk00000003/sig000000d0 , \blk00000003/sig000000d1 , \blk00000003/sig000000d2 , \blk00000003/sig000000d3 , \blk00000003/sig000000d4 , +\blk00000003/sig000000d5 , \blk00000003/sig000000d6 , \blk00000003/sig000000d7 , \blk00000003/sig000000d8 , \blk00000003/sig000000d9 , +\blk00000003/sig000000da , \blk00000003/sig000000db , \blk00000003/sig000000dc }), + .P({\NLW_blk00000003/blk00000006_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000006_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000006_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000006_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000006_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000006_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<31>_UNCONNECTED , +\blk00000003/sig000000dd , \blk00000003/sig000000de , \blk00000003/sig000000df , \blk00000003/sig000000e0 , \blk00000003/sig000000e1 , +\blk00000003/sig000000e2 , \blk00000003/sig000000e3 , \blk00000003/sig000000e4 , \blk00000003/sig000000e5 , \blk00000003/sig000000e6 , +\blk00000003/sig000000e7 , \blk00000003/sig000000e8 , \blk00000003/sig000000e9 , \blk00000003/sig000000ea , \blk00000003/sig000000eb , +\blk00000003/sig000000ec , \blk00000003/sig000000ed , \blk00000003/sig000000ee , \blk00000003/sig000000ef , \blk00000003/sig000000f0 , +\blk00000003/sig000000f1 , \blk00000003/sig000000f2 , \blk00000003/sig000000f3 , \blk00000003/sig000000f4 , \blk00000003/sig000000f5 , +\blk00000003/sig000000f6 , \blk00000003/sig000000f7 , \blk00000003/sig000000f8 , \blk00000003/sig000000f9 , \blk00000003/sig000000fa , +\blk00000003/sig000000fb }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +NlwRenamedSig_OI_rfd, NlwRenamedSig_OI_rfd, NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , +\blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , +\blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , +\blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc }), + .PCOUT({\NLW_blk00000003/blk00000006_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , +\blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , +\blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fd , \blk00000003/sig000000fe , +\blk00000003/sig000000ff , \blk00000003/sig00000100 , \blk00000003/sig00000101 }), + .M({\NLW_blk00000003/blk00000006_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<0>_UNCONNECTED }) + ); + VCC \blk00000003/blk00000005 ( + .P(NlwRenamedSig_OI_rfd) + ); + GND \blk00000003/blk00000004 ( + .G(\blk00000003/sig00000049 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000035/blk00000097 ( + .I0(nd), + .I1(ce), + .O(\blk00000003/blk00000035/sig00000f29 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000096 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[22]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000096_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f27 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000095 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[21]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000095_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f26 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000094 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[23]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000094_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f28 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000093 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[19]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000093_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f24 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000092 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[18]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000092_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f23 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000091 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[20]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000091_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f25 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000090 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[16]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000090_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f21 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000008f ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[15]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000008f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f20 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000008e ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[17]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000008e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f22 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000008d ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[13]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000008d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f1e ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000008c ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[12]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000008c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f1d ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000008b ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[14]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000008b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f1f ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000008a ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[10]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000008a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f1b ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000089 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[9]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000089_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f1a ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000088 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[11]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000088_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f1c ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000087 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[7]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000087_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f18 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000086 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[6]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000086_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f17 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000085 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[8]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000085_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f19 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000084 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[4]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000084_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f15 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000083 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[3]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000083_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f14 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000082 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[5]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000082_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f16 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000081 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[1]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000081_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f12 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000080 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[0]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000080_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f11 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000007f ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[2]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000007f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f13 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000007e ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[22]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000007e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f0f ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000007d ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[21]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000007d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f0e ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000007c ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[23]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000007c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f10 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000007b ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[19]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000007b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f0c ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000007a ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[18]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000007a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f0b ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000079 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[20]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000079_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f0d ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000078 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[16]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000078_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f09 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000077 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[15]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000077_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f08 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000076 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[17]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000076_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f0a ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000075 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[13]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000075_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f06 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000074 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[12]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000074_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f05 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000073 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[14]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000073_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f07 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000072 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[10]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000072_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f03 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000071 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[9]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000071_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f02 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000070 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[11]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000070_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f04 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000006f ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[7]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000006f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f00 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000006e ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[6]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000006e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000eff ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000006d ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[8]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000006d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f01 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000006c ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[4]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000006c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000efd ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000006b ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[3]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000006b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000efc ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000006a ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[5]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000006a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000efe ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000069 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[1]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000069_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000efa ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000068 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[0]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000068_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000ef9 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000067 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[2]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000067_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000efb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000066 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f28 ), + .Q(\blk00000003/sig000002bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000065 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f27 ), + .Q(\blk00000003/sig000002bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000064 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f26 ), + .Q(\blk00000003/sig000002bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000063 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f25 ), + .Q(\blk00000003/sig000002be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000062 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f24 ), + .Q(\blk00000003/sig000002bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000061 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f23 ), + .Q(\blk00000003/sig000002c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000060 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f22 ), + .Q(\blk00000003/sig000002c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000005f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f21 ), + .Q(\blk00000003/sig000002c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000005e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f20 ), + .Q(\blk00000003/sig000002c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000005d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f1f ), + .Q(\blk00000003/sig000002c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000005c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f1e ), + .Q(\blk00000003/sig000002c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000005b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f1d ), + .Q(\blk00000003/sig000002c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000005a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f1c ), + .Q(\blk00000003/sig000002c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000059 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f1b ), + .Q(\blk00000003/sig000002c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000058 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f1a ), + .Q(\blk00000003/sig000002c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000057 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f19 ), + .Q(\blk00000003/sig000002ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000056 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f18 ), + .Q(\blk00000003/sig000002cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000055 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f17 ), + .Q(\blk00000003/sig000002cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000054 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f16 ), + .Q(\blk00000003/sig000002cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000053 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f15 ), + .Q(\blk00000003/sig000002ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000052 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f14 ), + .Q(\blk00000003/sig000002cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000051 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f13 ), + .Q(\blk00000003/sig000002d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000050 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f12 ), + .Q(\blk00000003/sig000002d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000004f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f11 ), + .Q(\blk00000003/sig000002d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000004e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f10 ), + .Q(\blk00000003/sig000002d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000004d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f0f ), + .Q(\blk00000003/sig000002d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000004c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f0e ), + .Q(\blk00000003/sig000002d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000004b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f0d ), + .Q(\blk00000003/sig000002d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000004a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f0c ), + .Q(\blk00000003/sig000002d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000049 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f0b ), + .Q(\blk00000003/sig000002d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000048 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f0a ), + .Q(\blk00000003/sig000002d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000047 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f09 ), + .Q(\blk00000003/sig000002da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000046 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f08 ), + .Q(\blk00000003/sig000002db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000045 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f07 ), + .Q(\blk00000003/sig000002dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000044 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f06 ), + .Q(\blk00000003/sig000002dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000043 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f05 ), + .Q(\blk00000003/sig000002de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000042 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f04 ), + .Q(\blk00000003/sig000002df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000041 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f03 ), + .Q(\blk00000003/sig000002e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000040 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f02 ), + .Q(\blk00000003/sig000002e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000003f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f01 ), + .Q(\blk00000003/sig000002e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000003e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f00 ), + .Q(\blk00000003/sig000002e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000003d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000eff ), + .Q(\blk00000003/sig000002e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000003c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000efe ), + .Q(\blk00000003/sig000002e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000003b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000efd ), + .Q(\blk00000003/sig000002e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000003a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000efc ), + .Q(\blk00000003/sig000002e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000039 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000efb ), + .Q(\blk00000003/sig000002e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000038 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000efa ), + .Q(\blk00000003/sig000002e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000037 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000ef9 ), + .Q(\blk00000003/sig000002ea ) + ); + GND \blk00000003/blk00000035/blk00000036 ( + .G(\blk00000003/blk00000035/sig00000ef8 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000013d/blk0000015f ( + .I0(\blk00000003/sig000009fa ), + .I1(ce), + .O(\blk00000003/blk0000013d/sig00000f5f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk0000015e ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008c8 ), + .Q(\blk00000003/blk0000013d/sig00000f5e ), + .Q15(\NLW_blk00000003/blk0000013d/blk0000015e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk0000015d ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008c9 ), + .Q(\blk00000003/blk0000013d/sig00000f5d ), + .Q15(\NLW_blk00000003/blk0000013d/blk0000015d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk0000015c ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008ca ), + .Q(\blk00000003/blk0000013d/sig00000f5c ), + .Q15(\NLW_blk00000003/blk0000013d/blk0000015c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk0000015b ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008cb ), + .Q(\blk00000003/blk0000013d/sig00000f5b ), + .Q15(\NLW_blk00000003/blk0000013d/blk0000015b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk0000015a ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008cc ), + .Q(\blk00000003/blk0000013d/sig00000f5a ), + .Q15(\NLW_blk00000003/blk0000013d/blk0000015a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000159 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008cd ), + .Q(\blk00000003/blk0000013d/sig00000f59 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000159_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000158 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008ce ), + .Q(\blk00000003/blk0000013d/sig00000f58 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000158_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000157 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008cf ), + .Q(\blk00000003/blk0000013d/sig00000f57 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000157_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000156 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008d0 ), + .Q(\blk00000003/blk0000013d/sig00000f56 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000156_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000155 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008d1 ), + .Q(\blk00000003/blk0000013d/sig00000f55 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000155_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000154 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008d2 ), + .Q(\blk00000003/blk0000013d/sig00000f54 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000154_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000153 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008d3 ), + .Q(\blk00000003/blk0000013d/sig00000f53 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000153_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000152 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008d4 ), + .Q(\blk00000003/blk0000013d/sig00000f52 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000152_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000151 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008d5 ), + .Q(\blk00000003/blk0000013d/sig00000f51 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000151_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000150 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008d6 ), + .Q(\blk00000003/blk0000013d/sig00000f50 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000150_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk0000014f ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008d7 ), + .Q(\blk00000003/blk0000013d/sig00000f4f ), + .Q15(\NLW_blk00000003/blk0000013d/blk0000014f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk0000014e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f5e ), + .Q(\blk00000003/sig00000768 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk0000014d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f5d ), + .Q(\blk00000003/sig00000769 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk0000014c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f5c ), + .Q(\blk00000003/sig0000076a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk0000014b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f5b ), + .Q(\blk00000003/sig0000076b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk0000014a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f5a ), + .Q(\blk00000003/sig0000076c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000149 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f59 ), + .Q(\blk00000003/sig0000076d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000148 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f58 ), + .Q(\blk00000003/sig0000076e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000147 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f57 ), + .Q(\blk00000003/sig0000076f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000146 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f56 ), + .Q(\blk00000003/sig00000770 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000145 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f55 ), + .Q(\blk00000003/sig00000771 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000144 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f54 ), + .Q(\blk00000003/sig00000772 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000143 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f53 ), + .Q(\blk00000003/sig00000773 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000142 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f52 ), + .Q(\blk00000003/sig00000774 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000141 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f51 ), + .Q(\blk00000003/sig00000775 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000140 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f50 ), + .Q(\blk00000003/sig00000776 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk0000013f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f4f ), + .Q(\blk00000003/sig00000777 ) + ); + GND \blk00000003/blk0000013d/blk0000013e ( + .G(\blk00000003/blk0000013d/sig00000f4e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000160/blk00000182 ( + .I0(\blk00000003/sig000009f8 ), + .I1(ce), + .O(\blk00000003/blk00000160/sig00000f95 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000181 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a17 ), + .Q(\blk00000003/blk00000160/sig00000f94 ), + .Q15(\NLW_blk00000003/blk00000160/blk00000181_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000180 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a18 ), + .Q(\blk00000003/blk00000160/sig00000f93 ), + .Q15(\NLW_blk00000003/blk00000160/blk00000180_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk0000017f ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a19 ), + .Q(\blk00000003/blk00000160/sig00000f92 ), + .Q15(\NLW_blk00000003/blk00000160/blk0000017f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk0000017e ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a1a ), + .Q(\blk00000003/blk00000160/sig00000f91 ), + .Q15(\NLW_blk00000003/blk00000160/blk0000017e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk0000017d ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a1b ), + .Q(\blk00000003/blk00000160/sig00000f90 ), + .Q15(\NLW_blk00000003/blk00000160/blk0000017d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk0000017c ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a1c ), + .Q(\blk00000003/blk00000160/sig00000f8f ), + .Q15(\NLW_blk00000003/blk00000160/blk0000017c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk0000017b ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a1d ), + .Q(\blk00000003/blk00000160/sig00000f8e ), + .Q15(\NLW_blk00000003/blk00000160/blk0000017b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk0000017a ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a1e ), + .Q(\blk00000003/blk00000160/sig00000f8d ), + .Q15(\NLW_blk00000003/blk00000160/blk0000017a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000179 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a1f ), + .Q(\blk00000003/blk00000160/sig00000f8c ), + .Q15(\NLW_blk00000003/blk00000160/blk00000179_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000178 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a20 ), + .Q(\blk00000003/blk00000160/sig00000f8b ), + .Q15(\NLW_blk00000003/blk00000160/blk00000178_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000177 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a21 ), + .Q(\blk00000003/blk00000160/sig00000f8a ), + .Q15(\NLW_blk00000003/blk00000160/blk00000177_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000176 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a22 ), + .Q(\blk00000003/blk00000160/sig00000f89 ), + .Q15(\NLW_blk00000003/blk00000160/blk00000176_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000175 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a23 ), + .Q(\blk00000003/blk00000160/sig00000f88 ), + .Q15(\NLW_blk00000003/blk00000160/blk00000175_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000174 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a24 ), + .Q(\blk00000003/blk00000160/sig00000f87 ), + .Q15(\NLW_blk00000003/blk00000160/blk00000174_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000173 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a25 ), + .Q(\blk00000003/blk00000160/sig00000f86 ), + .Q15(\NLW_blk00000003/blk00000160/blk00000173_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000172 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a26 ), + .Q(\blk00000003/blk00000160/sig00000f85 ), + .Q15(\NLW_blk00000003/blk00000160/blk00000172_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000171 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f94 ), + .Q(\blk00000003/sig00000728 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000170 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f93 ), + .Q(\blk00000003/sig00000729 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk0000016f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f92 ), + .Q(\blk00000003/sig0000072a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk0000016e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f91 ), + .Q(\blk00000003/sig0000072b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk0000016d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f90 ), + .Q(\blk00000003/sig0000072c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk0000016c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f8f ), + .Q(\blk00000003/sig0000072d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk0000016b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f8e ), + .Q(\blk00000003/sig0000072e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk0000016a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f8d ), + .Q(\blk00000003/sig0000072f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000169 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f8c ), + .Q(\blk00000003/sig00000730 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000168 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f8b ), + .Q(\blk00000003/sig00000731 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000167 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f8a ), + .Q(\blk00000003/sig00000732 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000166 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f89 ), + .Q(\blk00000003/sig00000733 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000165 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f88 ), + .Q(\blk00000003/sig00000734 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000164 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f87 ), + .Q(\blk00000003/sig00000735 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000163 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f86 ), + .Q(\blk00000003/sig00000736 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000162 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f85 ), + .Q(\blk00000003/sig00000737 ) + ); + GND \blk00000003/blk00000160/blk00000161 ( + .G(\blk00000003/blk00000160/sig00000f84 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000183/blk000001a5 ( + .I0(\blk00000003/sig000009fa ), + .I1(ce), + .O(\blk00000003/blk00000183/sig00000fcb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk000001a4 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009d8 ), + .Q(\blk00000003/blk00000183/sig00000fca ), + .Q15(\NLW_blk00000003/blk00000183/blk000001a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk000001a3 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009d9 ), + .Q(\blk00000003/blk00000183/sig00000fc9 ), + .Q15(\NLW_blk00000003/blk00000183/blk000001a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk000001a2 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009da ), + .Q(\blk00000003/blk00000183/sig00000fc8 ), + .Q15(\NLW_blk00000003/blk00000183/blk000001a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk000001a1 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009db ), + .Q(\blk00000003/blk00000183/sig00000fc7 ), + .Q15(\NLW_blk00000003/blk00000183/blk000001a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk000001a0 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009dc ), + .Q(\blk00000003/blk00000183/sig00000fc6 ), + .Q15(\NLW_blk00000003/blk00000183/blk000001a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk0000019f ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009dd ), + .Q(\blk00000003/blk00000183/sig00000fc5 ), + .Q15(\NLW_blk00000003/blk00000183/blk0000019f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk0000019e ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009de ), + .Q(\blk00000003/blk00000183/sig00000fc4 ), + .Q15(\NLW_blk00000003/blk00000183/blk0000019e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk0000019d ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009df ), + .Q(\blk00000003/blk00000183/sig00000fc3 ), + .Q15(\NLW_blk00000003/blk00000183/blk0000019d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk0000019c ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009e0 ), + .Q(\blk00000003/blk00000183/sig00000fc2 ), + .Q15(\NLW_blk00000003/blk00000183/blk0000019c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk0000019b ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009e1 ), + .Q(\blk00000003/blk00000183/sig00000fc1 ), + .Q15(\NLW_blk00000003/blk00000183/blk0000019b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk0000019a ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009e2 ), + .Q(\blk00000003/blk00000183/sig00000fc0 ), + .Q15(\NLW_blk00000003/blk00000183/blk0000019a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk00000199 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009e3 ), + .Q(\blk00000003/blk00000183/sig00000fbf ), + .Q15(\NLW_blk00000003/blk00000183/blk00000199_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk00000198 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009e4 ), + .Q(\blk00000003/blk00000183/sig00000fbe ), + .Q15(\NLW_blk00000003/blk00000183/blk00000198_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk00000197 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009e5 ), + .Q(\blk00000003/blk00000183/sig00000fbd ), + .Q15(\NLW_blk00000003/blk00000183/blk00000197_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk00000196 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009e6 ), + .Q(\blk00000003/blk00000183/sig00000fbc ), + .Q15(\NLW_blk00000003/blk00000183/blk00000196_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk00000195 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009e7 ), + .Q(\blk00000003/blk00000183/sig00000fbb ), + .Q15(\NLW_blk00000003/blk00000183/blk00000195_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000194 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fca ), + .Q(\blk00000003/sig000007b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000193 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc9 ), + .Q(\blk00000003/sig000007b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000192 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc8 ), + .Q(\blk00000003/sig000007ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000191 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc7 ), + .Q(\blk00000003/sig000007bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000190 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc6 ), + .Q(\blk00000003/sig000007bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk0000018f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc5 ), + .Q(\blk00000003/sig000007bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk0000018e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc4 ), + .Q(\blk00000003/sig000007be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk0000018d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc3 ), + .Q(\blk00000003/sig000007bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk0000018c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc2 ), + .Q(\blk00000003/sig000007c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk0000018b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc1 ), + .Q(\blk00000003/sig000007c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk0000018a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc0 ), + .Q(\blk00000003/sig000007c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000189 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fbf ), + .Q(\blk00000003/sig000007c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000188 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fbe ), + .Q(\blk00000003/sig000007c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000187 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fbd ), + .Q(\blk00000003/sig000007c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000186 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fbc ), + .Q(\blk00000003/sig000007c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000185 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fbb ), + .Q(\blk00000003/sig000007c7 ) + ); + GND \blk00000003/blk00000183/blk00000184 ( + .G(\blk00000003/blk00000183/sig00000fba ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001a6/blk000001c8 ( + .I0(\blk00000003/sig000009f8 ), + .I1(ce), + .O(\blk00000003/blk000001a6/sig00001001 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001c7 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a27 ), + .Q(\blk00000003/blk000001a6/sig00001000 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001c7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001c6 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a28 ), + .Q(\blk00000003/blk000001a6/sig00000fff ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001c6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001c5 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a29 ), + .Q(\blk00000003/blk000001a6/sig00000ffe ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001c5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001c4 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a2a ), + .Q(\blk00000003/blk000001a6/sig00000ffd ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001c4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001c3 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a2b ), + .Q(\blk00000003/blk000001a6/sig00000ffc ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001c3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001c2 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a2c ), + .Q(\blk00000003/blk000001a6/sig00000ffb ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001c2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001c1 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a2d ), + .Q(\blk00000003/blk000001a6/sig00000ffa ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001c1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001c0 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a2e ), + .Q(\blk00000003/blk000001a6/sig00000ff9 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001c0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001bf ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a2f ), + .Q(\blk00000003/blk000001a6/sig00000ff8 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001bf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001be ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a30 ), + .Q(\blk00000003/blk000001a6/sig00000ff7 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001be_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001bd ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a31 ), + .Q(\blk00000003/blk000001a6/sig00000ff6 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001bd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001bc ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a32 ), + .Q(\blk00000003/blk000001a6/sig00000ff5 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001bc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001bb ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a33 ), + .Q(\blk00000003/blk000001a6/sig00000ff4 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001bb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001ba ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a34 ), + .Q(\blk00000003/blk000001a6/sig00000ff3 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001ba_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001b9 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a35 ), + .Q(\blk00000003/blk000001a6/sig00000ff2 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001b9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001b8 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a36 ), + .Q(\blk00000003/blk000001a6/sig00000ff1 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001b8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00001000 ), + .Q(\blk00000003/sig00000778 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000fff ), + .Q(\blk00000003/sig00000779 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ffe ), + .Q(\blk00000003/sig0000077a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ffd ), + .Q(\blk00000003/sig0000077b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ffc ), + .Q(\blk00000003/sig0000077c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ffb ), + .Q(\blk00000003/sig0000077d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ffa ), + .Q(\blk00000003/sig0000077e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff9 ), + .Q(\blk00000003/sig0000077f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001af ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff8 ), + .Q(\blk00000003/sig00000780 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff7 ), + .Q(\blk00000003/sig00000781 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff6 ), + .Q(\blk00000003/sig00000782 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff5 ), + .Q(\blk00000003/sig00000783 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff4 ), + .Q(\blk00000003/sig00000784 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff3 ), + .Q(\blk00000003/sig00000785 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff2 ), + .Q(\blk00000003/sig00000786 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff1 ), + .Q(\blk00000003/sig00000787 ) + ); + GND \blk00000003/blk000001a6/blk000001a7 ( + .G(\blk00000003/blk000001a6/sig00000ff0 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001c9/blk000001eb ( + .I0(\blk00000003/sig000009f9 ), + .I1(ce), + .O(\blk00000003/blk000001c9/sig00001037 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001ea ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000878 ), + .Q(\blk00000003/blk000001c9/sig00001036 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001ea_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e9 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000879 ), + .Q(\blk00000003/blk000001c9/sig00001035 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e8 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig0000087a ), + .Q(\blk00000003/blk000001c9/sig00001034 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e7 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig0000087b ), + .Q(\blk00000003/blk000001c9/sig00001033 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e6 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig0000087c ), + .Q(\blk00000003/blk000001c9/sig00001032 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e5 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig0000087d ), + .Q(\blk00000003/blk000001c9/sig00001031 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e4 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig0000087e ), + .Q(\blk00000003/blk000001c9/sig00001030 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e3 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig0000087f ), + .Q(\blk00000003/blk000001c9/sig0000102f ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e2 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000880 ), + .Q(\blk00000003/blk000001c9/sig0000102e ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e1 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000881 ), + .Q(\blk00000003/blk000001c9/sig0000102d ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e0 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000882 ), + .Q(\blk00000003/blk000001c9/sig0000102c ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001df ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000883 ), + .Q(\blk00000003/blk000001c9/sig0000102b ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001de ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000884 ), + .Q(\blk00000003/blk000001c9/sig0000102a ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001dd ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000885 ), + .Q(\blk00000003/blk000001c9/sig00001029 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001dc ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000886 ), + .Q(\blk00000003/blk000001c9/sig00001028 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001db ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000887 ), + .Q(\blk00000003/blk000001c9/sig00001027 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001db_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001da ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001036 ), + .Q(\blk00000003/sig000008c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001035 ), + .Q(\blk00000003/sig000008c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001034 ), + .Q(\blk00000003/sig000008ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001033 ), + .Q(\blk00000003/sig000008cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001032 ), + .Q(\blk00000003/sig000008cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001031 ), + .Q(\blk00000003/sig000008cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001030 ), + .Q(\blk00000003/sig000008ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig0000102f ), + .Q(\blk00000003/sig000008cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig0000102e ), + .Q(\blk00000003/sig000008d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig0000102d ), + .Q(\blk00000003/sig000008d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig0000102c ), + .Q(\blk00000003/sig000008d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig0000102b ), + .Q(\blk00000003/sig000008d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig0000102a ), + .Q(\blk00000003/sig000008d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001029 ), + .Q(\blk00000003/sig000008d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001028 ), + .Q(\blk00000003/sig000008d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001027 ), + .Q(\blk00000003/sig000008d7 ) + ); + GND \blk00000003/blk000001c9/blk000001ca ( + .G(\blk00000003/blk000001c9/sig00001026 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001ec/blk0000020e ( + .I0(\blk00000003/sig000009f7 ), + .I1(ce), + .O(\blk00000003/blk000001ec/sig0000106d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020d ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a37 ), + .Q(\blk00000003/blk000001ec/sig0000106c ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020c ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a38 ), + .Q(\blk00000003/blk000001ec/sig0000106b ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020b ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a39 ), + .Q(\blk00000003/blk000001ec/sig0000106a ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020a ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a3a ), + .Q(\blk00000003/blk000001ec/sig00001069 ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000209 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a3b ), + .Q(\blk00000003/blk000001ec/sig00001068 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000209_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000208 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a3c ), + .Q(\blk00000003/blk000001ec/sig00001067 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000208_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000207 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a3d ), + .Q(\blk00000003/blk000001ec/sig00001066 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000207_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000206 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a3e ), + .Q(\blk00000003/blk000001ec/sig00001065 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000206_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000205 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a3f ), + .Q(\blk00000003/blk000001ec/sig00001064 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000205_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000204 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a40 ), + .Q(\blk00000003/blk000001ec/sig00001063 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000204_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000203 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a41 ), + .Q(\blk00000003/blk000001ec/sig00001062 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000203_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000202 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a42 ), + .Q(\blk00000003/blk000001ec/sig00001061 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000202_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000201 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a43 ), + .Q(\blk00000003/blk000001ec/sig00001060 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000201_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000200 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a44 ), + .Q(\blk00000003/blk000001ec/sig0000105f ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000200_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk000001ff ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a45 ), + .Q(\blk00000003/blk000001ec/sig0000105e ), + .Q15(\NLW_blk00000003/blk000001ec/blk000001ff_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk000001fe ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a46 ), + .Q(\blk00000003/blk000001ec/sig0000105d ), + .Q15(\NLW_blk00000003/blk000001ec/blk000001fe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig0000106c ), + .Q(\blk00000003/sig000008b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig0000106b ), + .Q(\blk00000003/sig000008b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig0000106a ), + .Q(\blk00000003/sig000008ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001069 ), + .Q(\blk00000003/sig000008bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001068 ), + .Q(\blk00000003/sig000008bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001067 ), + .Q(\blk00000003/sig000008bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001066 ), + .Q(\blk00000003/sig000008be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001065 ), + .Q(\blk00000003/sig000008bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001064 ), + .Q(\blk00000003/sig000008c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001063 ), + .Q(\blk00000003/sig000008c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001062 ), + .Q(\blk00000003/sig000008c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001061 ), + .Q(\blk00000003/sig000008c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001060 ), + .Q(\blk00000003/sig000008c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig0000105f ), + .Q(\blk00000003/sig000008c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig0000105e ), + .Q(\blk00000003/sig000008c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig0000105d ), + .Q(\blk00000003/sig000008c7 ) + ); + GND \blk00000003/blk000001ec/blk000001ed ( + .G(\blk00000003/blk000001ec/sig0000105c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000020f/blk00000231 ( + .I0(\blk00000003/sig000009f9 ), + .I1(ce), + .O(\blk00000003/blk0000020f/sig000010a3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000230 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000988 ), + .Q(\blk00000003/blk0000020f/sig000010a2 ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000230_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk0000022f ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000989 ), + .Q(\blk00000003/blk0000020f/sig000010a1 ), + .Q15(\NLW_blk00000003/blk0000020f/blk0000022f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk0000022e ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig0000098a ), + .Q(\blk00000003/blk0000020f/sig000010a0 ), + .Q15(\NLW_blk00000003/blk0000020f/blk0000022e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk0000022d ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig0000098b ), + .Q(\blk00000003/blk0000020f/sig0000109f ), + .Q15(\NLW_blk00000003/blk0000020f/blk0000022d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk0000022c ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig0000098c ), + .Q(\blk00000003/blk0000020f/sig0000109e ), + .Q15(\NLW_blk00000003/blk0000020f/blk0000022c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk0000022b ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig0000098d ), + .Q(\blk00000003/blk0000020f/sig0000109d ), + .Q15(\NLW_blk00000003/blk0000020f/blk0000022b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk0000022a ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig0000098e ), + .Q(\blk00000003/blk0000020f/sig0000109c ), + .Q15(\NLW_blk00000003/blk0000020f/blk0000022a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000229 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig0000098f ), + .Q(\blk00000003/blk0000020f/sig0000109b ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000229_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000228 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000990 ), + .Q(\blk00000003/blk0000020f/sig0000109a ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000228_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000227 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000991 ), + .Q(\blk00000003/blk0000020f/sig00001099 ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000227_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000226 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000992 ), + .Q(\blk00000003/blk0000020f/sig00001098 ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000226_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000225 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000993 ), + .Q(\blk00000003/blk0000020f/sig00001097 ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000225_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000224 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000994 ), + .Q(\blk00000003/blk0000020f/sig00001096 ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000224_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000223 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000995 ), + .Q(\blk00000003/blk0000020f/sig00001095 ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000223_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000222 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000996 ), + .Q(\blk00000003/blk0000020f/sig00001094 ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000222_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000221 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000997 ), + .Q(\blk00000003/blk0000020f/sig00001093 ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000221_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000220 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig000010a2 ), + .Q(\blk00000003/sig000009d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk0000021f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig000010a1 ), + .Q(\blk00000003/sig000009d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk0000021e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig000010a0 ), + .Q(\blk00000003/sig000009da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk0000021d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig0000109f ), + .Q(\blk00000003/sig000009db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk0000021c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig0000109e ), + .Q(\blk00000003/sig000009dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk0000021b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig0000109d ), + .Q(\blk00000003/sig000009dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk0000021a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig0000109c ), + .Q(\blk00000003/sig000009de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000219 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig0000109b ), + .Q(\blk00000003/sig000009df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000218 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig0000109a ), + .Q(\blk00000003/sig000009e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000217 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig00001099 ), + .Q(\blk00000003/sig000009e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000216 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig00001098 ), + .Q(\blk00000003/sig000009e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000215 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig00001097 ), + .Q(\blk00000003/sig000009e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000214 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig00001096 ), + .Q(\blk00000003/sig000009e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000213 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig00001095 ), + .Q(\blk00000003/sig000009e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000212 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig00001094 ), + .Q(\blk00000003/sig000009e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000211 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig00001093 ), + .Q(\blk00000003/sig000009e7 ) + ); + GND \blk00000003/blk0000020f/blk00000210 ( + .G(\blk00000003/blk0000020f/sig00001092 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000232/blk00000254 ( + .I0(\blk00000003/sig000009f7 ), + .I1(ce), + .O(\blk00000003/blk00000232/sig000010d9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000253 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a47 ), + .Q(\blk00000003/blk00000232/sig000010d8 ), + .Q15(\NLW_blk00000003/blk00000232/blk00000253_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000252 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a48 ), + .Q(\blk00000003/blk00000232/sig000010d7 ), + .Q15(\NLW_blk00000003/blk00000232/blk00000252_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000251 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a49 ), + .Q(\blk00000003/blk00000232/sig000010d6 ), + .Q15(\NLW_blk00000003/blk00000232/blk00000251_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000250 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a4a ), + .Q(\blk00000003/blk00000232/sig000010d5 ), + .Q15(\NLW_blk00000003/blk00000232/blk00000250_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk0000024f ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a4b ), + .Q(\blk00000003/blk00000232/sig000010d4 ), + .Q15(\NLW_blk00000003/blk00000232/blk0000024f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk0000024e ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a4c ), + .Q(\blk00000003/blk00000232/sig000010d3 ), + .Q15(\NLW_blk00000003/blk00000232/blk0000024e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk0000024d ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a4d ), + .Q(\blk00000003/blk00000232/sig000010d2 ), + .Q15(\NLW_blk00000003/blk00000232/blk0000024d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk0000024c ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a4e ), + .Q(\blk00000003/blk00000232/sig000010d1 ), + .Q15(\NLW_blk00000003/blk00000232/blk0000024c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk0000024b ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a4f ), + .Q(\blk00000003/blk00000232/sig000010d0 ), + .Q15(\NLW_blk00000003/blk00000232/blk0000024b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk0000024a ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a50 ), + .Q(\blk00000003/blk00000232/sig000010cf ), + .Q15(\NLW_blk00000003/blk00000232/blk0000024a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000249 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a51 ), + .Q(\blk00000003/blk00000232/sig000010ce ), + .Q15(\NLW_blk00000003/blk00000232/blk00000249_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000248 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a52 ), + .Q(\blk00000003/blk00000232/sig000010cd ), + .Q15(\NLW_blk00000003/blk00000232/blk00000248_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000247 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a53 ), + .Q(\blk00000003/blk00000232/sig000010cc ), + .Q15(\NLW_blk00000003/blk00000232/blk00000247_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000246 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a54 ), + .Q(\blk00000003/blk00000232/sig000010cb ), + .Q15(\NLW_blk00000003/blk00000232/blk00000246_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000245 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a55 ), + .Q(\blk00000003/blk00000232/sig000010ca ), + .Q15(\NLW_blk00000003/blk00000232/blk00000245_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000244 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a56 ), + .Q(\blk00000003/blk00000232/sig000010c9 ), + .Q15(\NLW_blk00000003/blk00000232/blk00000244_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000243 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d8 ), + .Q(\blk00000003/sig000009c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000242 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d7 ), + .Q(\blk00000003/sig000009c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000241 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d6 ), + .Q(\blk00000003/sig000009ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000240 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d5 ), + .Q(\blk00000003/sig000009cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk0000023f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d4 ), + .Q(\blk00000003/sig000009cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk0000023e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d3 ), + .Q(\blk00000003/sig000009cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk0000023d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d2 ), + .Q(\blk00000003/sig000009ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk0000023c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d1 ), + .Q(\blk00000003/sig000009cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk0000023b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d0 ), + .Q(\blk00000003/sig000009d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk0000023a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010cf ), + .Q(\blk00000003/sig000009d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000239 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010ce ), + .Q(\blk00000003/sig000009d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000238 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010cd ), + .Q(\blk00000003/sig000009d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000237 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010cc ), + .Q(\blk00000003/sig000009d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000236 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010cb ), + .Q(\blk00000003/sig000009d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000235 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010ca ), + .Q(\blk00000003/sig000009d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000234 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010c9 ), + .Q(\blk00000003/sig000009d7 ) + ); + GND \blk00000003/blk00000232/blk00000233 ( + .G(\blk00000003/blk00000232/sig000010c8 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000255/blk00000277 ( + .I0(\blk00000003/sig00000a06 ), + .I1(ce), + .O(\blk00000003/blk00000255/sig0000110f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000276 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000828 ), + .Q(\blk00000003/blk00000255/sig0000110e ), + .Q15(\NLW_blk00000003/blk00000255/blk00000276_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000275 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000829 ), + .Q(\blk00000003/blk00000255/sig0000110d ), + .Q15(\NLW_blk00000003/blk00000255/blk00000275_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000274 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig0000082a ), + .Q(\blk00000003/blk00000255/sig0000110c ), + .Q15(\NLW_blk00000003/blk00000255/blk00000274_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000273 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig0000082b ), + .Q(\blk00000003/blk00000255/sig0000110b ), + .Q15(\NLW_blk00000003/blk00000255/blk00000273_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000272 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig0000082c ), + .Q(\blk00000003/blk00000255/sig0000110a ), + .Q15(\NLW_blk00000003/blk00000255/blk00000272_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000271 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig0000082d ), + .Q(\blk00000003/blk00000255/sig00001109 ), + .Q15(\NLW_blk00000003/blk00000255/blk00000271_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000270 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig0000082e ), + .Q(\blk00000003/blk00000255/sig00001108 ), + .Q15(\NLW_blk00000003/blk00000255/blk00000270_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk0000026f ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig0000082f ), + .Q(\blk00000003/blk00000255/sig00001107 ), + .Q15(\NLW_blk00000003/blk00000255/blk0000026f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk0000026e ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000830 ), + .Q(\blk00000003/blk00000255/sig00001106 ), + .Q15(\NLW_blk00000003/blk00000255/blk0000026e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk0000026d ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000831 ), + .Q(\blk00000003/blk00000255/sig00001105 ), + .Q15(\NLW_blk00000003/blk00000255/blk0000026d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk0000026c ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000832 ), + .Q(\blk00000003/blk00000255/sig00001104 ), + .Q15(\NLW_blk00000003/blk00000255/blk0000026c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk0000026b ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000833 ), + .Q(\blk00000003/blk00000255/sig00001103 ), + .Q15(\NLW_blk00000003/blk00000255/blk0000026b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk0000026a ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000834 ), + .Q(\blk00000003/blk00000255/sig00001102 ), + .Q15(\NLW_blk00000003/blk00000255/blk0000026a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000269 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000835 ), + .Q(\blk00000003/blk00000255/sig00001101 ), + .Q15(\NLW_blk00000003/blk00000255/blk00000269_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000268 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000836 ), + .Q(\blk00000003/blk00000255/sig00001100 ), + .Q15(\NLW_blk00000003/blk00000255/blk00000268_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000267 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000837 ), + .Q(\blk00000003/blk00000255/sig000010ff ), + .Q15(\NLW_blk00000003/blk00000255/blk00000267_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000266 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig0000110e ), + .Q(\blk00000003/sig00000878 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000265 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig0000110d ), + .Q(\blk00000003/sig00000879 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000264 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig0000110c ), + .Q(\blk00000003/sig0000087a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000263 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig0000110b ), + .Q(\blk00000003/sig0000087b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000262 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig0000110a ), + .Q(\blk00000003/sig0000087c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000261 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001109 ), + .Q(\blk00000003/sig0000087d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000260 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001108 ), + .Q(\blk00000003/sig0000087e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk0000025f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001107 ), + .Q(\blk00000003/sig0000087f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk0000025e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001106 ), + .Q(\blk00000003/sig00000880 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk0000025d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001105 ), + .Q(\blk00000003/sig00000881 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk0000025c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001104 ), + .Q(\blk00000003/sig00000882 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk0000025b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001103 ), + .Q(\blk00000003/sig00000883 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk0000025a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001102 ), + .Q(\blk00000003/sig00000884 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000259 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001101 ), + .Q(\blk00000003/sig00000885 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000258 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001100 ), + .Q(\blk00000003/sig00000886 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000257 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig000010ff ), + .Q(\blk00000003/sig00000887 ) + ); + GND \blk00000003/blk00000255/blk00000256 ( + .G(\blk00000003/blk00000255/sig000010fe ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000278/blk0000029a ( + .I0(\blk00000003/sig00000a03 ), + .I1(ce), + .O(\blk00000003/blk00000278/sig00001145 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000299 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a57 ), + .Q(\blk00000003/blk00000278/sig00001144 ), + .Q15(\NLW_blk00000003/blk00000278/blk00000299_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000298 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a58 ), + .Q(\blk00000003/blk00000278/sig00001143 ), + .Q15(\NLW_blk00000003/blk00000278/blk00000298_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000297 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a59 ), + .Q(\blk00000003/blk00000278/sig00001142 ), + .Q15(\NLW_blk00000003/blk00000278/blk00000297_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000296 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a5a ), + .Q(\blk00000003/blk00000278/sig00001141 ), + .Q15(\NLW_blk00000003/blk00000278/blk00000296_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000295 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a5b ), + .Q(\blk00000003/blk00000278/sig00001140 ), + .Q15(\NLW_blk00000003/blk00000278/blk00000295_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000294 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a5c ), + .Q(\blk00000003/blk00000278/sig0000113f ), + .Q15(\NLW_blk00000003/blk00000278/blk00000294_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000293 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a5d ), + .Q(\blk00000003/blk00000278/sig0000113e ), + .Q15(\NLW_blk00000003/blk00000278/blk00000293_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000292 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a5e ), + .Q(\blk00000003/blk00000278/sig0000113d ), + .Q15(\NLW_blk00000003/blk00000278/blk00000292_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000291 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a5f ), + .Q(\blk00000003/blk00000278/sig0000113c ), + .Q15(\NLW_blk00000003/blk00000278/blk00000291_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000290 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a60 ), + .Q(\blk00000003/blk00000278/sig0000113b ), + .Q15(\NLW_blk00000003/blk00000278/blk00000290_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk0000028f ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a61 ), + .Q(\blk00000003/blk00000278/sig0000113a ), + .Q15(\NLW_blk00000003/blk00000278/blk0000028f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk0000028e ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a62 ), + .Q(\blk00000003/blk00000278/sig00001139 ), + .Q15(\NLW_blk00000003/blk00000278/blk0000028e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk0000028d ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a63 ), + .Q(\blk00000003/blk00000278/sig00001138 ), + .Q15(\NLW_blk00000003/blk00000278/blk0000028d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk0000028c ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a64 ), + .Q(\blk00000003/blk00000278/sig00001137 ), + .Q15(\NLW_blk00000003/blk00000278/blk0000028c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk0000028b ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a65 ), + .Q(\blk00000003/blk00000278/sig00001136 ), + .Q15(\NLW_blk00000003/blk00000278/blk0000028b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk0000028a ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a66 ), + .Q(\blk00000003/blk00000278/sig00001135 ), + .Q15(\NLW_blk00000003/blk00000278/blk0000028a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000289 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001144 ), + .Q(\blk00000003/sig00000868 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000288 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001143 ), + .Q(\blk00000003/sig00000869 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000287 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001142 ), + .Q(\blk00000003/sig0000086a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000286 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001141 ), + .Q(\blk00000003/sig0000086b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000285 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001140 ), + .Q(\blk00000003/sig0000086c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000284 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig0000113f ), + .Q(\blk00000003/sig0000086d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000283 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig0000113e ), + .Q(\blk00000003/sig0000086e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000282 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig0000113d ), + .Q(\blk00000003/sig0000086f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000281 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig0000113c ), + .Q(\blk00000003/sig00000870 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000280 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig0000113b ), + .Q(\blk00000003/sig00000871 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk0000027f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig0000113a ), + .Q(\blk00000003/sig00000872 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk0000027e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001139 ), + .Q(\blk00000003/sig00000873 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk0000027d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001138 ), + .Q(\blk00000003/sig00000874 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk0000027c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001137 ), + .Q(\blk00000003/sig00000875 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk0000027b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001136 ), + .Q(\blk00000003/sig00000876 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk0000027a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001135 ), + .Q(\blk00000003/sig00000877 ) + ); + GND \blk00000003/blk00000278/blk00000279 ( + .G(\blk00000003/blk00000278/sig00001134 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000029b/blk000002bd ( + .I0(\blk00000003/sig00000a06 ), + .I1(ce), + .O(\blk00000003/blk0000029b/sig0000117b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002bc ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000938 ), + .Q(\blk00000003/blk0000029b/sig0000117a ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002bc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002bb ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000939 ), + .Q(\blk00000003/blk0000029b/sig00001179 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002bb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002ba ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig0000093a ), + .Q(\blk00000003/blk0000029b/sig00001178 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002ba_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b9 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig0000093b ), + .Q(\blk00000003/blk0000029b/sig00001177 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b8 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig0000093c ), + .Q(\blk00000003/blk0000029b/sig00001176 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b7 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig0000093d ), + .Q(\blk00000003/blk0000029b/sig00001175 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b6 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig0000093e ), + .Q(\blk00000003/blk0000029b/sig00001174 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b5 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig0000093f ), + .Q(\blk00000003/blk0000029b/sig00001173 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b4 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000940 ), + .Q(\blk00000003/blk0000029b/sig00001172 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b3 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000941 ), + .Q(\blk00000003/blk0000029b/sig00001171 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b2 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000942 ), + .Q(\blk00000003/blk0000029b/sig00001170 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b1 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000943 ), + .Q(\blk00000003/blk0000029b/sig0000116f ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b0 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000944 ), + .Q(\blk00000003/blk0000029b/sig0000116e ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002af ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000945 ), + .Q(\blk00000003/blk0000029b/sig0000116d ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002ae ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000946 ), + .Q(\blk00000003/blk0000029b/sig0000116c ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002ad ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000947 ), + .Q(\blk00000003/blk0000029b/sig0000116b ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002ad_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig0000117a ), + .Q(\blk00000003/sig00000988 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001179 ), + .Q(\blk00000003/sig00000989 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001178 ), + .Q(\blk00000003/sig0000098a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001177 ), + .Q(\blk00000003/sig0000098b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001176 ), + .Q(\blk00000003/sig0000098c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001175 ), + .Q(\blk00000003/sig0000098d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001174 ), + .Q(\blk00000003/sig0000098e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001173 ), + .Q(\blk00000003/sig0000098f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001172 ), + .Q(\blk00000003/sig00000990 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001171 ), + .Q(\blk00000003/sig00000991 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001170 ), + .Q(\blk00000003/sig00000992 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig0000116f ), + .Q(\blk00000003/sig00000993 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig0000116e ), + .Q(\blk00000003/sig00000994 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk0000029f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig0000116d ), + .Q(\blk00000003/sig00000995 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk0000029e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig0000116c ), + .Q(\blk00000003/sig00000996 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk0000029d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig0000116b ), + .Q(\blk00000003/sig00000997 ) + ); + GND \blk00000003/blk0000029b/blk0000029c ( + .G(\blk00000003/blk0000029b/sig0000116a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002be/blk000002e0 ( + .I0(\blk00000003/sig00000a03 ), + .I1(ce), + .O(\blk00000003/blk000002be/sig000011b1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002df ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a67 ), + .Q(\blk00000003/blk000002be/sig000011b0 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002de ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a68 ), + .Q(\blk00000003/blk000002be/sig000011af ), + .Q15(\NLW_blk00000003/blk000002be/blk000002de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002dd ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a69 ), + .Q(\blk00000003/blk000002be/sig000011ae ), + .Q15(\NLW_blk00000003/blk000002be/blk000002dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002dc ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a6a ), + .Q(\blk00000003/blk000002be/sig000011ad ), + .Q15(\NLW_blk00000003/blk000002be/blk000002dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002db ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a6b ), + .Q(\blk00000003/blk000002be/sig000011ac ), + .Q15(\NLW_blk00000003/blk000002be/blk000002db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002da ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a6c ), + .Q(\blk00000003/blk000002be/sig000011ab ), + .Q15(\NLW_blk00000003/blk000002be/blk000002da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d9 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a6d ), + .Q(\blk00000003/blk000002be/sig000011aa ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d8 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a6e ), + .Q(\blk00000003/blk000002be/sig000011a9 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d7 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a6f ), + .Q(\blk00000003/blk000002be/sig000011a8 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d6 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a70 ), + .Q(\blk00000003/blk000002be/sig000011a7 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d5 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a71 ), + .Q(\blk00000003/blk000002be/sig000011a6 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d4 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a72 ), + .Q(\blk00000003/blk000002be/sig000011a5 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d3 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a73 ), + .Q(\blk00000003/blk000002be/sig000011a4 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d2 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a74 ), + .Q(\blk00000003/blk000002be/sig000011a3 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d1 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a75 ), + .Q(\blk00000003/blk000002be/sig000011a2 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d0 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a76 ), + .Q(\blk00000003/blk000002be/sig000011a1 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011b0 ), + .Q(\blk00000003/sig00000978 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011af ), + .Q(\blk00000003/sig00000979 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011ae ), + .Q(\blk00000003/sig0000097a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011ad ), + .Q(\blk00000003/sig0000097b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011ac ), + .Q(\blk00000003/sig0000097c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011ab ), + .Q(\blk00000003/sig0000097d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011aa ), + .Q(\blk00000003/sig0000097e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a9 ), + .Q(\blk00000003/sig0000097f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a8 ), + .Q(\blk00000003/sig00000980 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a7 ), + .Q(\blk00000003/sig00000981 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a6 ), + .Q(\blk00000003/sig00000982 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a5 ), + .Q(\blk00000003/sig00000983 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a4 ), + .Q(\blk00000003/sig00000984 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a3 ), + .Q(\blk00000003/sig00000985 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a2 ), + .Q(\blk00000003/sig00000986 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a1 ), + .Q(\blk00000003/sig00000987 ) + ); + GND \blk00000003/blk000002be/blk000002bf ( + .G(\blk00000003/blk000002be/sig000011a0 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002e1/blk00000303 ( + .I0(\blk00000003/sig00000a09 ), + .I1(ce), + .O(\blk00000003/blk000002e1/sig000011e7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk00000302 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007d8 ), + .Q(\blk00000003/blk000002e1/sig000011e6 ), + .Q15(\NLW_blk00000003/blk000002e1/blk00000302_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk00000301 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007d9 ), + .Q(\blk00000003/blk000002e1/sig000011e5 ), + .Q15(\NLW_blk00000003/blk000002e1/blk00000301_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk00000300 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007da ), + .Q(\blk00000003/blk000002e1/sig000011e4 ), + .Q15(\NLW_blk00000003/blk000002e1/blk00000300_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002ff ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007db ), + .Q(\blk00000003/blk000002e1/sig000011e3 ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002ff_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002fe ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007dc ), + .Q(\blk00000003/blk000002e1/sig000011e2 ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002fe_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002fd ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007dd ), + .Q(\blk00000003/blk000002e1/sig000011e1 ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002fd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002fc ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007de ), + .Q(\blk00000003/blk000002e1/sig000011e0 ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002fc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002fb ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007df ), + .Q(\blk00000003/blk000002e1/sig000011df ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002fb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002fa ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007e0 ), + .Q(\blk00000003/blk000002e1/sig000011de ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002fa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002f9 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007e1 ), + .Q(\blk00000003/blk000002e1/sig000011dd ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002f9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002f8 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007e2 ), + .Q(\blk00000003/blk000002e1/sig000011dc ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002f8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002f7 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007e3 ), + .Q(\blk00000003/blk000002e1/sig000011db ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002f7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002f6 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007e4 ), + .Q(\blk00000003/blk000002e1/sig000011da ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002f6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002f5 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007e5 ), + .Q(\blk00000003/blk000002e1/sig000011d9 ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002f5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002f4 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007e6 ), + .Q(\blk00000003/blk000002e1/sig000011d8 ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002f4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002f3 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007e7 ), + .Q(\blk00000003/blk000002e1/sig000011d7 ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002f3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011e6 ), + .Q(\blk00000003/sig00000828 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011e5 ), + .Q(\blk00000003/sig00000829 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011e4 ), + .Q(\blk00000003/sig0000082a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011e3 ), + .Q(\blk00000003/sig0000082b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011e2 ), + .Q(\blk00000003/sig0000082c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011e1 ), + .Q(\blk00000003/sig0000082d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011e0 ), + .Q(\blk00000003/sig0000082e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011df ), + .Q(\blk00000003/sig0000082f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011de ), + .Q(\blk00000003/sig00000830 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011dd ), + .Q(\blk00000003/sig00000831 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011dc ), + .Q(\blk00000003/sig00000832 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011db ), + .Q(\blk00000003/sig00000833 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011da ), + .Q(\blk00000003/sig00000834 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011d9 ), + .Q(\blk00000003/sig00000835 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011d8 ), + .Q(\blk00000003/sig00000836 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011d7 ), + .Q(\blk00000003/sig00000837 ) + ); + GND \blk00000003/blk000002e1/blk000002e2 ( + .G(\blk00000003/blk000002e1/sig000011d6 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000304/blk00000326 ( + .I0(\blk00000003/sig00000a0a ), + .I1(ce), + .O(\blk00000003/blk00000304/sig0000121d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000325 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a77 ), + .Q(\blk00000003/blk00000304/sig0000121c ), + .Q15(\NLW_blk00000003/blk00000304/blk00000325_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000324 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a78 ), + .Q(\blk00000003/blk00000304/sig0000121b ), + .Q15(\NLW_blk00000003/blk00000304/blk00000324_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000323 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a79 ), + .Q(\blk00000003/blk00000304/sig0000121a ), + .Q15(\NLW_blk00000003/blk00000304/blk00000323_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000322 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a7a ), + .Q(\blk00000003/blk00000304/sig00001219 ), + .Q15(\NLW_blk00000003/blk00000304/blk00000322_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000321 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a7b ), + .Q(\blk00000003/blk00000304/sig00001218 ), + .Q15(\NLW_blk00000003/blk00000304/blk00000321_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000320 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a7c ), + .Q(\blk00000003/blk00000304/sig00001217 ), + .Q15(\NLW_blk00000003/blk00000304/blk00000320_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk0000031f ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a7d ), + .Q(\blk00000003/blk00000304/sig00001216 ), + .Q15(\NLW_blk00000003/blk00000304/blk0000031f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk0000031e ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a7e ), + .Q(\blk00000003/blk00000304/sig00001215 ), + .Q15(\NLW_blk00000003/blk00000304/blk0000031e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk0000031d ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a7f ), + .Q(\blk00000003/blk00000304/sig00001214 ), + .Q15(\NLW_blk00000003/blk00000304/blk0000031d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk0000031c ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a80 ), + .Q(\blk00000003/blk00000304/sig00001213 ), + .Q15(\NLW_blk00000003/blk00000304/blk0000031c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk0000031b ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a81 ), + .Q(\blk00000003/blk00000304/sig00001212 ), + .Q15(\NLW_blk00000003/blk00000304/blk0000031b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk0000031a ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a82 ), + .Q(\blk00000003/blk00000304/sig00001211 ), + .Q15(\NLW_blk00000003/blk00000304/blk0000031a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000319 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a83 ), + .Q(\blk00000003/blk00000304/sig00001210 ), + .Q15(\NLW_blk00000003/blk00000304/blk00000319_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000318 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a84 ), + .Q(\blk00000003/blk00000304/sig0000120f ), + .Q15(\NLW_blk00000003/blk00000304/blk00000318_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000317 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a85 ), + .Q(\blk00000003/blk00000304/sig0000120e ), + .Q15(\NLW_blk00000003/blk00000304/blk00000317_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000316 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a86 ), + .Q(\blk00000003/blk00000304/sig0000120d ), + .Q15(\NLW_blk00000003/blk00000304/blk00000316_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000315 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig0000121c ), + .Q(\blk00000003/sig00000818 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000314 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig0000121b ), + .Q(\blk00000003/sig00000819 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000313 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig0000121a ), + .Q(\blk00000003/sig0000081a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000312 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001219 ), + .Q(\blk00000003/sig0000081b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000311 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001218 ), + .Q(\blk00000003/sig0000081c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000310 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001217 ), + .Q(\blk00000003/sig0000081d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk0000030f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001216 ), + .Q(\blk00000003/sig0000081e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk0000030e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001215 ), + .Q(\blk00000003/sig0000081f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk0000030d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001214 ), + .Q(\blk00000003/sig00000820 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk0000030c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001213 ), + .Q(\blk00000003/sig00000821 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk0000030b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001212 ), + .Q(\blk00000003/sig00000822 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk0000030a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001211 ), + .Q(\blk00000003/sig00000823 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000309 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001210 ), + .Q(\blk00000003/sig00000824 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000308 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig0000120f ), + .Q(\blk00000003/sig00000825 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000307 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig0000120e ), + .Q(\blk00000003/sig00000826 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000306 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig0000120d ), + .Q(\blk00000003/sig00000827 ) + ); + GND \blk00000003/blk00000304/blk00000305 ( + .G(\blk00000003/blk00000304/sig0000120c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000327/blk00000349 ( + .I0(\blk00000003/sig00000a09 ), + .I1(ce), + .O(\blk00000003/blk00000327/sig00001253 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000348 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008e8 ), + .Q(\blk00000003/blk00000327/sig00001252 ), + .Q15(\NLW_blk00000003/blk00000327/blk00000348_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000347 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008e9 ), + .Q(\blk00000003/blk00000327/sig00001251 ), + .Q15(\NLW_blk00000003/blk00000327/blk00000347_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000346 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008ea ), + .Q(\blk00000003/blk00000327/sig00001250 ), + .Q15(\NLW_blk00000003/blk00000327/blk00000346_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000345 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008eb ), + .Q(\blk00000003/blk00000327/sig0000124f ), + .Q15(\NLW_blk00000003/blk00000327/blk00000345_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000344 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008ec ), + .Q(\blk00000003/blk00000327/sig0000124e ), + .Q15(\NLW_blk00000003/blk00000327/blk00000344_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000343 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008ed ), + .Q(\blk00000003/blk00000327/sig0000124d ), + .Q15(\NLW_blk00000003/blk00000327/blk00000343_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000342 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008ee ), + .Q(\blk00000003/blk00000327/sig0000124c ), + .Q15(\NLW_blk00000003/blk00000327/blk00000342_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000341 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008ef ), + .Q(\blk00000003/blk00000327/sig0000124b ), + .Q15(\NLW_blk00000003/blk00000327/blk00000341_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000340 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008f0 ), + .Q(\blk00000003/blk00000327/sig0000124a ), + .Q15(\NLW_blk00000003/blk00000327/blk00000340_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk0000033f ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008f1 ), + .Q(\blk00000003/blk00000327/sig00001249 ), + .Q15(\NLW_blk00000003/blk00000327/blk0000033f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk0000033e ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008f2 ), + .Q(\blk00000003/blk00000327/sig00001248 ), + .Q15(\NLW_blk00000003/blk00000327/blk0000033e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk0000033d ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008f3 ), + .Q(\blk00000003/blk00000327/sig00001247 ), + .Q15(\NLW_blk00000003/blk00000327/blk0000033d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk0000033c ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008f4 ), + .Q(\blk00000003/blk00000327/sig00001246 ), + .Q15(\NLW_blk00000003/blk00000327/blk0000033c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk0000033b ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008f5 ), + .Q(\blk00000003/blk00000327/sig00001245 ), + .Q15(\NLW_blk00000003/blk00000327/blk0000033b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk0000033a ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008f6 ), + .Q(\blk00000003/blk00000327/sig00001244 ), + .Q15(\NLW_blk00000003/blk00000327/blk0000033a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000339 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008f7 ), + .Q(\blk00000003/blk00000327/sig00001243 ), + .Q15(\NLW_blk00000003/blk00000327/blk00000339_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000338 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001252 ), + .Q(\blk00000003/sig00000938 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000337 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001251 ), + .Q(\blk00000003/sig00000939 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000336 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001250 ), + .Q(\blk00000003/sig0000093a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000335 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig0000124f ), + .Q(\blk00000003/sig0000093b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000334 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig0000124e ), + .Q(\blk00000003/sig0000093c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000333 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig0000124d ), + .Q(\blk00000003/sig0000093d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000332 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig0000124c ), + .Q(\blk00000003/sig0000093e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000331 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig0000124b ), + .Q(\blk00000003/sig0000093f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000330 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig0000124a ), + .Q(\blk00000003/sig00000940 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk0000032f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001249 ), + .Q(\blk00000003/sig00000941 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk0000032e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001248 ), + .Q(\blk00000003/sig00000942 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk0000032d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001247 ), + .Q(\blk00000003/sig00000943 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk0000032c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001246 ), + .Q(\blk00000003/sig00000944 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk0000032b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001245 ), + .Q(\blk00000003/sig00000945 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk0000032a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001244 ), + .Q(\blk00000003/sig00000946 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000329 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001243 ), + .Q(\blk00000003/sig00000947 ) + ); + GND \blk00000003/blk00000327/blk00000328 ( + .G(\blk00000003/blk00000327/sig00001242 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000034a/blk0000036c ( + .I0(\blk00000003/sig00000a0a ), + .I1(ce), + .O(\blk00000003/blk0000034a/sig00001289 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk0000036b ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a87 ), + .Q(\blk00000003/blk0000034a/sig00001288 ), + .Q15(\NLW_blk00000003/blk0000034a/blk0000036b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk0000036a ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a88 ), + .Q(\blk00000003/blk0000034a/sig00001287 ), + .Q15(\NLW_blk00000003/blk0000034a/blk0000036a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000369 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a89 ), + .Q(\blk00000003/blk0000034a/sig00001286 ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000369_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000368 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a8a ), + .Q(\blk00000003/blk0000034a/sig00001285 ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000368_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000367 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a8b ), + .Q(\blk00000003/blk0000034a/sig00001284 ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000367_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000366 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a8c ), + .Q(\blk00000003/blk0000034a/sig00001283 ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000366_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000365 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a8d ), + .Q(\blk00000003/blk0000034a/sig00001282 ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000365_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000364 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a8e ), + .Q(\blk00000003/blk0000034a/sig00001281 ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000364_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000363 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a8f ), + .Q(\blk00000003/blk0000034a/sig00001280 ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000363_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000362 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a90 ), + .Q(\blk00000003/blk0000034a/sig0000127f ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000362_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000361 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a91 ), + .Q(\blk00000003/blk0000034a/sig0000127e ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000361_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000360 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a92 ), + .Q(\blk00000003/blk0000034a/sig0000127d ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000360_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk0000035f ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a93 ), + .Q(\blk00000003/blk0000034a/sig0000127c ), + .Q15(\NLW_blk00000003/blk0000034a/blk0000035f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk0000035e ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a94 ), + .Q(\blk00000003/blk0000034a/sig0000127b ), + .Q15(\NLW_blk00000003/blk0000034a/blk0000035e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk0000035d ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a95 ), + .Q(\blk00000003/blk0000034a/sig0000127a ), + .Q15(\NLW_blk00000003/blk0000034a/blk0000035d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk0000035c ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a96 ), + .Q(\blk00000003/blk0000034a/sig00001279 ), + .Q15(\NLW_blk00000003/blk0000034a/blk0000035c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk0000035b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001288 ), + .Q(\blk00000003/sig00000928 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk0000035a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001287 ), + .Q(\blk00000003/sig00000929 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000359 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001286 ), + .Q(\blk00000003/sig0000092a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000358 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001285 ), + .Q(\blk00000003/sig0000092b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000357 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001284 ), + .Q(\blk00000003/sig0000092c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000356 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001283 ), + .Q(\blk00000003/sig0000092d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000355 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001282 ), + .Q(\blk00000003/sig0000092e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000354 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001281 ), + .Q(\blk00000003/sig0000092f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000353 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001280 ), + .Q(\blk00000003/sig00000930 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000352 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig0000127f ), + .Q(\blk00000003/sig00000931 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000351 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig0000127e ), + .Q(\blk00000003/sig00000932 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000350 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig0000127d ), + .Q(\blk00000003/sig00000933 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk0000034f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig0000127c ), + .Q(\blk00000003/sig00000934 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk0000034e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig0000127b ), + .Q(\blk00000003/sig00000935 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk0000034d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig0000127a ), + .Q(\blk00000003/sig00000936 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk0000034c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001279 ), + .Q(\blk00000003/sig00000937 ) + ); + GND \blk00000003/blk0000034a/blk0000034b ( + .G(\blk00000003/blk0000034a/sig00001278 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000036d/blk0000038f ( + .I0(\blk00000003/sig00000a10 ), + .I1(ce), + .O(\blk00000003/blk0000036d/sig000012bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk0000038e ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig0000041e ), + .Q(\blk00000003/blk0000036d/sig000012be ), + .Q15(\NLW_blk00000003/blk0000036d/blk0000038e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk0000038d ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig0000041f ), + .Q(\blk00000003/blk0000036d/sig000012bd ), + .Q15(\NLW_blk00000003/blk0000036d/blk0000038d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk0000038c ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000420 ), + .Q(\blk00000003/blk0000036d/sig000012bc ), + .Q15(\NLW_blk00000003/blk0000036d/blk0000038c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk0000038b ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000421 ), + .Q(\blk00000003/blk0000036d/sig000012bb ), + .Q15(\NLW_blk00000003/blk0000036d/blk0000038b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk0000038a ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000422 ), + .Q(\blk00000003/blk0000036d/sig000012ba ), + .Q15(\NLW_blk00000003/blk0000036d/blk0000038a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000389 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000423 ), + .Q(\blk00000003/blk0000036d/sig000012b9 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000389_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000388 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000424 ), + .Q(\blk00000003/blk0000036d/sig000012b8 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000388_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000387 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000425 ), + .Q(\blk00000003/blk0000036d/sig000012b7 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000387_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000386 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000426 ), + .Q(\blk00000003/blk0000036d/sig000012b6 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000386_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000385 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000427 ), + .Q(\blk00000003/blk0000036d/sig000012b5 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000385_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000384 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000428 ), + .Q(\blk00000003/blk0000036d/sig000012b4 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000384_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000383 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000429 ), + .Q(\blk00000003/blk0000036d/sig000012b3 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000383_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000382 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig0000042a ), + .Q(\blk00000003/blk0000036d/sig000012b2 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000382_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000381 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig0000042b ), + .Q(\blk00000003/blk0000036d/sig000012b1 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000381_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000380 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig0000042c ), + .Q(\blk00000003/blk0000036d/sig000012b0 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000380_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk0000037f ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig0000042d ), + .Q(\blk00000003/blk0000036d/sig000012af ), + .Q15(\NLW_blk00000003/blk0000036d/blk0000037f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk0000037e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012be ), + .Q(\blk00000003/sig000007d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk0000037d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012bd ), + .Q(\blk00000003/sig000007d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk0000037c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012bc ), + .Q(\blk00000003/sig000007da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk0000037b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012bb ), + .Q(\blk00000003/sig000007db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk0000037a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012ba ), + .Q(\blk00000003/sig000007dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000379 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b9 ), + .Q(\blk00000003/sig000007dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000378 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b8 ), + .Q(\blk00000003/sig000007de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000377 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b7 ), + .Q(\blk00000003/sig000007df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000376 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b6 ), + .Q(\blk00000003/sig000007e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000375 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b5 ), + .Q(\blk00000003/sig000007e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000374 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b4 ), + .Q(\blk00000003/sig000007e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000373 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b3 ), + .Q(\blk00000003/sig000007e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000372 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b2 ), + .Q(\blk00000003/sig000007e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000371 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b1 ), + .Q(\blk00000003/sig000007e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000370 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b0 ), + .Q(\blk00000003/sig000007e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk0000036f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012af ), + .Q(\blk00000003/sig000007e7 ) + ); + GND \blk00000003/blk0000036d/blk0000036e ( + .G(\blk00000003/blk0000036d/sig000012ae ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000390/blk000003b2 ( + .I0(\blk00000003/sig00000a0f ), + .I1(ce), + .O(\blk00000003/blk00000390/sig000012f5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003b1 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a97 ), + .Q(\blk00000003/blk00000390/sig000012f4 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003b1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003b0 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a98 ), + .Q(\blk00000003/blk00000390/sig000012f3 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003af ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a99 ), + .Q(\blk00000003/blk00000390/sig000012f2 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003ae ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a9a ), + .Q(\blk00000003/blk00000390/sig000012f1 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003ad ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a9b ), + .Q(\blk00000003/blk00000390/sig000012f0 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003ac ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a9c ), + .Q(\blk00000003/blk00000390/sig000012ef ), + .Q15(\NLW_blk00000003/blk00000390/blk000003ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003ab ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a9d ), + .Q(\blk00000003/blk00000390/sig000012ee ), + .Q15(\NLW_blk00000003/blk00000390/blk000003ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003aa ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a9e ), + .Q(\blk00000003/blk00000390/sig000012ed ), + .Q15(\NLW_blk00000003/blk00000390/blk000003aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003a9 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a9f ), + .Q(\blk00000003/blk00000390/sig000012ec ), + .Q15(\NLW_blk00000003/blk00000390/blk000003a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003a8 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000aa0 ), + .Q(\blk00000003/blk00000390/sig000012eb ), + .Q15(\NLW_blk00000003/blk00000390/blk000003a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003a7 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000aa1 ), + .Q(\blk00000003/blk00000390/sig000012ea ), + .Q15(\NLW_blk00000003/blk00000390/blk000003a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003a6 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000aa2 ), + .Q(\blk00000003/blk00000390/sig000012e9 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003a5 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000aa3 ), + .Q(\blk00000003/blk00000390/sig000012e8 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003a4 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000aa4 ), + .Q(\blk00000003/blk00000390/sig000012e7 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003a3 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000aa5 ), + .Q(\blk00000003/blk00000390/sig000012e6 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003a2 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000aa6 ), + .Q(\blk00000003/blk00000390/sig000012e5 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003a2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk000003a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012f4 ), + .Q(\blk00000003/sig000007c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk000003a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012f3 ), + .Q(\blk00000003/sig000007c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk0000039f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012f2 ), + .Q(\blk00000003/sig000007ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk0000039e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012f1 ), + .Q(\blk00000003/sig000007cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk0000039d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012f0 ), + .Q(\blk00000003/sig000007cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk0000039c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012ef ), + .Q(\blk00000003/sig000007cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk0000039b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012ee ), + .Q(\blk00000003/sig000007ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk0000039a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012ed ), + .Q(\blk00000003/sig000007cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk00000399 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012ec ), + .Q(\blk00000003/sig000007d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk00000398 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012eb ), + .Q(\blk00000003/sig000007d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk00000397 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012ea ), + .Q(\blk00000003/sig000007d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk00000396 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012e9 ), + .Q(\blk00000003/sig000007d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk00000395 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012e8 ), + .Q(\blk00000003/sig000007d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk00000394 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012e7 ), + .Q(\blk00000003/sig000007d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk00000393 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012e6 ), + .Q(\blk00000003/sig000007d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk00000392 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012e5 ), + .Q(\blk00000003/sig000007d7 ) + ); + GND \blk00000003/blk00000390/blk00000391 ( + .G(\blk00000003/blk00000390/sig000012e4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003b3/blk000003d5 ( + .I0(\blk00000003/sig00000a10 ), + .I1(ce), + .O(\blk00000003/blk000003b3/sig0000132b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003d4 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000046e ), + .Q(\blk00000003/blk000003b3/sig0000132a ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003d3 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000046f ), + .Q(\blk00000003/blk000003b3/sig00001329 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003d2 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000470 ), + .Q(\blk00000003/blk000003b3/sig00001328 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003d1 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000471 ), + .Q(\blk00000003/blk000003b3/sig00001327 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003d0 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000472 ), + .Q(\blk00000003/blk000003b3/sig00001326 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003cf ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000473 ), + .Q(\blk00000003/blk000003b3/sig00001325 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003cf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003ce ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000474 ), + .Q(\blk00000003/blk000003b3/sig00001324 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003ce_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003cd ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000475 ), + .Q(\blk00000003/blk000003b3/sig00001323 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003cd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003cc ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000476 ), + .Q(\blk00000003/blk000003b3/sig00001322 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003cc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003cb ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000477 ), + .Q(\blk00000003/blk000003b3/sig00001321 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003cb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003ca ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000478 ), + .Q(\blk00000003/blk000003b3/sig00001320 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003ca_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003c9 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000479 ), + .Q(\blk00000003/blk000003b3/sig0000131f ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003c9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003c8 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000047a ), + .Q(\blk00000003/blk000003b3/sig0000131e ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003c8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003c7 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000047b ), + .Q(\blk00000003/blk000003b3/sig0000131d ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003c7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003c6 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000047c ), + .Q(\blk00000003/blk000003b3/sig0000131c ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003c6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003c5 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000047d ), + .Q(\blk00000003/blk000003b3/sig0000131b ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003c5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig0000132a ), + .Q(\blk00000003/sig000008e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001329 ), + .Q(\blk00000003/sig000008e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001328 ), + .Q(\blk00000003/sig000008ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001327 ), + .Q(\blk00000003/sig000008eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001326 ), + .Q(\blk00000003/sig000008ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001325 ), + .Q(\blk00000003/sig000008ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001324 ), + .Q(\blk00000003/sig000008ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001323 ), + .Q(\blk00000003/sig000008ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001322 ), + .Q(\blk00000003/sig000008f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001321 ), + .Q(\blk00000003/sig000008f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001320 ), + .Q(\blk00000003/sig000008f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig0000131f ), + .Q(\blk00000003/sig000008f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig0000131e ), + .Q(\blk00000003/sig000008f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig0000131d ), + .Q(\blk00000003/sig000008f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig0000131c ), + .Q(\blk00000003/sig000008f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig0000131b ), + .Q(\blk00000003/sig000008f7 ) + ); + GND \blk00000003/blk000003b3/blk000003b4 ( + .G(\blk00000003/blk000003b3/sig0000131a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003d6/blk000003f8 ( + .I0(\blk00000003/sig00000a0f ), + .I1(ce), + .O(\blk00000003/blk000003d6/sig00001361 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003f7 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aa7 ), + .Q(\blk00000003/blk000003d6/sig00001360 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003f7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003f6 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aa8 ), + .Q(\blk00000003/blk000003d6/sig0000135f ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003f6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003f5 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aa9 ), + .Q(\blk00000003/blk000003d6/sig0000135e ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003f5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003f4 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aaa ), + .Q(\blk00000003/blk000003d6/sig0000135d ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003f4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003f3 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aab ), + .Q(\blk00000003/blk000003d6/sig0000135c ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003f3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003f2 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aac ), + .Q(\blk00000003/blk000003d6/sig0000135b ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003f2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003f1 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aad ), + .Q(\blk00000003/blk000003d6/sig0000135a ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003f1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003f0 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aae ), + .Q(\blk00000003/blk000003d6/sig00001359 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003f0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003ef ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aaf ), + .Q(\blk00000003/blk000003d6/sig00001358 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003ef_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003ee ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000ab0 ), + .Q(\blk00000003/blk000003d6/sig00001357 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003ee_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003ed ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000ab1 ), + .Q(\blk00000003/blk000003d6/sig00001356 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003ed_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003ec ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000ab2 ), + .Q(\blk00000003/blk000003d6/sig00001355 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003ec_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003eb ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000ab3 ), + .Q(\blk00000003/blk000003d6/sig00001354 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003eb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003ea ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000ab4 ), + .Q(\blk00000003/blk000003d6/sig00001353 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003ea_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003e9 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000ab5 ), + .Q(\blk00000003/blk000003d6/sig00001352 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003e9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003e8 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000ab6 ), + .Q(\blk00000003/blk000003d6/sig00001351 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003e8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001360 ), + .Q(\blk00000003/sig000008d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig0000135f ), + .Q(\blk00000003/sig000008d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig0000135e ), + .Q(\blk00000003/sig000008da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig0000135d ), + .Q(\blk00000003/sig000008db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig0000135c ), + .Q(\blk00000003/sig000008dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig0000135b ), + .Q(\blk00000003/sig000008dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig0000135a ), + .Q(\blk00000003/sig000008de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001359 ), + .Q(\blk00000003/sig000008df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003df ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001358 ), + .Q(\blk00000003/sig000008e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003de ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001357 ), + .Q(\blk00000003/sig000008e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001356 ), + .Q(\blk00000003/sig000008e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001355 ), + .Q(\blk00000003/sig000008e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003db ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001354 ), + .Q(\blk00000003/sig000008e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003da ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001353 ), + .Q(\blk00000003/sig000008e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001352 ), + .Q(\blk00000003/sig000008e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001351 ), + .Q(\blk00000003/sig000008e7 ) + ); + GND \blk00000003/blk000003d6/blk000003d7 ( + .G(\blk00000003/blk000003d6/sig00001350 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003f9/blk0000041b ( + .I0(\blk00000003/sig00000a16 ), + .I1(ce), + .O(\blk00000003/blk000003f9/sig00001397 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk0000041a ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ab7 ), + .Q(\blk00000003/blk000003f9/sig00001396 ), + .Q15(\NLW_blk00000003/blk000003f9/blk0000041a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000419 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ab8 ), + .Q(\blk00000003/blk000003f9/sig00001395 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000419_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000418 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ab9 ), + .Q(\blk00000003/blk000003f9/sig00001394 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000418_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000417 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000aba ), + .Q(\blk00000003/blk000003f9/sig00001393 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000417_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000416 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000abb ), + .Q(\blk00000003/blk000003f9/sig00001392 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000416_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000415 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000abc ), + .Q(\blk00000003/blk000003f9/sig00001391 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000415_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000414 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000abd ), + .Q(\blk00000003/blk000003f9/sig00001390 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000414_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000413 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000abe ), + .Q(\blk00000003/blk000003f9/sig0000138f ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000413_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000412 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000abf ), + .Q(\blk00000003/blk000003f9/sig0000138e ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000412_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000411 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ac0 ), + .Q(\blk00000003/blk000003f9/sig0000138d ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000411_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000410 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ac1 ), + .Q(\blk00000003/blk000003f9/sig0000138c ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000410_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk0000040f ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ac2 ), + .Q(\blk00000003/blk000003f9/sig0000138b ), + .Q15(\NLW_blk00000003/blk000003f9/blk0000040f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk0000040e ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ac3 ), + .Q(\blk00000003/blk000003f9/sig0000138a ), + .Q15(\NLW_blk00000003/blk000003f9/blk0000040e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk0000040d ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ac4 ), + .Q(\blk00000003/blk000003f9/sig00001389 ), + .Q15(\NLW_blk00000003/blk000003f9/blk0000040d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk0000040c ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ac5 ), + .Q(\blk00000003/blk000003f9/sig00001388 ), + .Q15(\NLW_blk00000003/blk000003f9/blk0000040c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk0000040b ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ac6 ), + .Q(\blk00000003/blk000003f9/sig00001387 ), + .Q15(\NLW_blk00000003/blk000003f9/blk0000040b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk0000040a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001396 ), + .Q(\blk00000003/sig0000041e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000409 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001395 ), + .Q(\blk00000003/sig0000041f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000408 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001394 ), + .Q(\blk00000003/sig00000420 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000407 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001393 ), + .Q(\blk00000003/sig00000421 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000406 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001392 ), + .Q(\blk00000003/sig00000422 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000405 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001391 ), + .Q(\blk00000003/sig00000423 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000404 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001390 ), + .Q(\blk00000003/sig00000424 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000403 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig0000138f ), + .Q(\blk00000003/sig00000425 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000402 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig0000138e ), + .Q(\blk00000003/sig00000426 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000401 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig0000138d ), + .Q(\blk00000003/sig00000427 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000400 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig0000138c ), + .Q(\blk00000003/sig00000428 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig0000138b ), + .Q(\blk00000003/sig00000429 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig0000138a ), + .Q(\blk00000003/sig0000042a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001389 ), + .Q(\blk00000003/sig0000042b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001388 ), + .Q(\blk00000003/sig0000042c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001387 ), + .Q(\blk00000003/sig0000042d ) + ); + GND \blk00000003/blk000003f9/blk000003fa ( + .G(\blk00000003/blk000003f9/sig00001386 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000041c/blk0000043e ( + .I0(\blk00000003/sig00000a15 ), + .I1(ce), + .O(\blk00000003/blk0000041c/sig000013cd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk0000043d ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ac7 ), + .Q(\blk00000003/blk0000041c/sig000013cc ), + .Q15(\NLW_blk00000003/blk0000041c/blk0000043d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk0000043c ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ac8 ), + .Q(\blk00000003/blk0000041c/sig000013cb ), + .Q15(\NLW_blk00000003/blk0000041c/blk0000043c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk0000043b ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ac9 ), + .Q(\blk00000003/blk0000041c/sig000013ca ), + .Q15(\NLW_blk00000003/blk0000041c/blk0000043b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk0000043a ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000aca ), + .Q(\blk00000003/blk0000041c/sig000013c9 ), + .Q15(\NLW_blk00000003/blk0000041c/blk0000043a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000439 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000acb ), + .Q(\blk00000003/blk0000041c/sig000013c8 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000439_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000438 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000acc ), + .Q(\blk00000003/blk0000041c/sig000013c7 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000438_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000437 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000acd ), + .Q(\blk00000003/blk0000041c/sig000013c6 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000437_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000436 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ace ), + .Q(\blk00000003/blk0000041c/sig000013c5 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000436_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000435 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000acf ), + .Q(\blk00000003/blk0000041c/sig000013c4 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000435_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000434 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ad0 ), + .Q(\blk00000003/blk0000041c/sig000013c3 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000434_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000433 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ad1 ), + .Q(\blk00000003/blk0000041c/sig000013c2 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000433_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000432 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ad2 ), + .Q(\blk00000003/blk0000041c/sig000013c1 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000432_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000431 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ad3 ), + .Q(\blk00000003/blk0000041c/sig000013c0 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000431_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000430 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ad4 ), + .Q(\blk00000003/blk0000041c/sig000013bf ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000430_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk0000042f ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ad5 ), + .Q(\blk00000003/blk0000041c/sig000013be ), + .Q15(\NLW_blk00000003/blk0000041c/blk0000042f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk0000042e ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ad6 ), + .Q(\blk00000003/blk0000041c/sig000013bd ), + .Q15(\NLW_blk00000003/blk0000041c/blk0000042e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk0000042d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013cc ), + .Q(\blk00000003/sig0000040e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk0000042c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013cb ), + .Q(\blk00000003/sig0000040f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk0000042b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013ca ), + .Q(\blk00000003/sig00000410 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk0000042a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c9 ), + .Q(\blk00000003/sig00000411 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000429 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c8 ), + .Q(\blk00000003/sig00000412 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000428 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c7 ), + .Q(\blk00000003/sig00000413 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000427 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c6 ), + .Q(\blk00000003/sig00000414 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000426 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c5 ), + .Q(\blk00000003/sig00000415 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000425 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c4 ), + .Q(\blk00000003/sig00000416 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000424 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c3 ), + .Q(\blk00000003/sig00000417 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000423 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c2 ), + .Q(\blk00000003/sig00000418 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000422 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c1 ), + .Q(\blk00000003/sig00000419 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000421 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c0 ), + .Q(\blk00000003/sig0000041a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000420 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013bf ), + .Q(\blk00000003/sig0000041b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk0000041f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013be ), + .Q(\blk00000003/sig0000041c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk0000041e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013bd ), + .Q(\blk00000003/sig0000041d ) + ); + GND \blk00000003/blk0000041c/blk0000041d ( + .G(\blk00000003/blk0000041c/sig000013bc ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000043f/blk00000461 ( + .I0(\blk00000003/sig00000a16 ), + .I1(ce), + .O(\blk00000003/blk0000043f/sig00001403 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000460 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ad7 ), + .Q(\blk00000003/blk0000043f/sig00001402 ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000460_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk0000045f ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ad8 ), + .Q(\blk00000003/blk0000043f/sig00001401 ), + .Q15(\NLW_blk00000003/blk0000043f/blk0000045f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk0000045e ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ad9 ), + .Q(\blk00000003/blk0000043f/sig00001400 ), + .Q15(\NLW_blk00000003/blk0000043f/blk0000045e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk0000045d ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ada ), + .Q(\blk00000003/blk0000043f/sig000013ff ), + .Q15(\NLW_blk00000003/blk0000043f/blk0000045d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk0000045c ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000adb ), + .Q(\blk00000003/blk0000043f/sig000013fe ), + .Q15(\NLW_blk00000003/blk0000043f/blk0000045c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk0000045b ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000adc ), + .Q(\blk00000003/blk0000043f/sig000013fd ), + .Q15(\NLW_blk00000003/blk0000043f/blk0000045b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk0000045a ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000add ), + .Q(\blk00000003/blk0000043f/sig000013fc ), + .Q15(\NLW_blk00000003/blk0000043f/blk0000045a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000459 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ade ), + .Q(\blk00000003/blk0000043f/sig000013fb ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000459_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000458 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000adf ), + .Q(\blk00000003/blk0000043f/sig000013fa ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000458_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000457 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ae0 ), + .Q(\blk00000003/blk0000043f/sig000013f9 ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000457_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000456 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ae1 ), + .Q(\blk00000003/blk0000043f/sig000013f8 ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000456_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000455 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ae2 ), + .Q(\blk00000003/blk0000043f/sig000013f7 ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000455_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000454 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ae3 ), + .Q(\blk00000003/blk0000043f/sig000013f6 ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000454_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000453 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ae4 ), + .Q(\blk00000003/blk0000043f/sig000013f5 ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000453_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000452 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ae5 ), + .Q(\blk00000003/blk0000043f/sig000013f4 ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000452_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000451 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ae6 ), + .Q(\blk00000003/blk0000043f/sig000013f3 ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000451_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000450 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig00001402 ), + .Q(\blk00000003/sig0000046e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk0000044f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig00001401 ), + .Q(\blk00000003/sig0000046f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk0000044e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig00001400 ), + .Q(\blk00000003/sig00000470 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk0000044d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013ff ), + .Q(\blk00000003/sig00000471 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk0000044c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013fe ), + .Q(\blk00000003/sig00000472 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk0000044b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013fd ), + .Q(\blk00000003/sig00000473 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk0000044a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013fc ), + .Q(\blk00000003/sig00000474 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000449 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013fb ), + .Q(\blk00000003/sig00000475 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000448 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013fa ), + .Q(\blk00000003/sig00000476 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000447 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013f9 ), + .Q(\blk00000003/sig00000477 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000446 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013f8 ), + .Q(\blk00000003/sig00000478 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000445 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013f7 ), + .Q(\blk00000003/sig00000479 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000444 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013f6 ), + .Q(\blk00000003/sig0000047a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000443 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013f5 ), + .Q(\blk00000003/sig0000047b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000442 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013f4 ), + .Q(\blk00000003/sig0000047c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000441 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013f3 ), + .Q(\blk00000003/sig0000047d ) + ); + GND \blk00000003/blk0000043f/blk00000440 ( + .G(\blk00000003/blk0000043f/sig000013f2 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000462/blk00000484 ( + .I0(\blk00000003/sig00000a15 ), + .I1(ce), + .O(\blk00000003/blk00000462/sig00001439 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000483 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000ae7 ), + .Q(\blk00000003/blk00000462/sig00001438 ), + .Q15(\NLW_blk00000003/blk00000462/blk00000483_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000482 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000ae8 ), + .Q(\blk00000003/blk00000462/sig00001437 ), + .Q15(\NLW_blk00000003/blk00000462/blk00000482_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000481 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000ae9 ), + .Q(\blk00000003/blk00000462/sig00001436 ), + .Q15(\NLW_blk00000003/blk00000462/blk00000481_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000480 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000aea ), + .Q(\blk00000003/blk00000462/sig00001435 ), + .Q15(\NLW_blk00000003/blk00000462/blk00000480_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk0000047f ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000aeb ), + .Q(\blk00000003/blk00000462/sig00001434 ), + .Q15(\NLW_blk00000003/blk00000462/blk0000047f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk0000047e ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000aec ), + .Q(\blk00000003/blk00000462/sig00001433 ), + .Q15(\NLW_blk00000003/blk00000462/blk0000047e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk0000047d ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000aed ), + .Q(\blk00000003/blk00000462/sig00001432 ), + .Q15(\NLW_blk00000003/blk00000462/blk0000047d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk0000047c ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000aee ), + .Q(\blk00000003/blk00000462/sig00001431 ), + .Q15(\NLW_blk00000003/blk00000462/blk0000047c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk0000047b ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000aef ), + .Q(\blk00000003/blk00000462/sig00001430 ), + .Q15(\NLW_blk00000003/blk00000462/blk0000047b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk0000047a ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000af0 ), + .Q(\blk00000003/blk00000462/sig0000142f ), + .Q15(\NLW_blk00000003/blk00000462/blk0000047a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000479 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000af1 ), + .Q(\blk00000003/blk00000462/sig0000142e ), + .Q15(\NLW_blk00000003/blk00000462/blk00000479_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000478 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000af2 ), + .Q(\blk00000003/blk00000462/sig0000142d ), + .Q15(\NLW_blk00000003/blk00000462/blk00000478_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000477 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000af3 ), + .Q(\blk00000003/blk00000462/sig0000142c ), + .Q15(\NLW_blk00000003/blk00000462/blk00000477_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000476 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000af4 ), + .Q(\blk00000003/blk00000462/sig0000142b ), + .Q15(\NLW_blk00000003/blk00000462/blk00000476_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000475 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000af5 ), + .Q(\blk00000003/blk00000462/sig0000142a ), + .Q15(\NLW_blk00000003/blk00000462/blk00000475_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000474 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000af6 ), + .Q(\blk00000003/blk00000462/sig00001429 ), + .Q15(\NLW_blk00000003/blk00000462/blk00000474_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000473 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001438 ), + .Q(\blk00000003/sig0000045e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000472 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001437 ), + .Q(\blk00000003/sig0000045f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000471 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001436 ), + .Q(\blk00000003/sig00000460 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000470 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001435 ), + .Q(\blk00000003/sig00000461 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk0000046f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001434 ), + .Q(\blk00000003/sig00000462 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk0000046e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001433 ), + .Q(\blk00000003/sig00000463 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk0000046d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001432 ), + .Q(\blk00000003/sig00000464 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk0000046c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001431 ), + .Q(\blk00000003/sig00000465 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk0000046b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001430 ), + .Q(\blk00000003/sig00000466 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk0000046a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig0000142f ), + .Q(\blk00000003/sig00000467 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000469 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig0000142e ), + .Q(\blk00000003/sig00000468 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000468 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig0000142d ), + .Q(\blk00000003/sig00000469 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000467 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig0000142c ), + .Q(\blk00000003/sig0000046a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000466 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig0000142b ), + .Q(\blk00000003/sig0000046b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000465 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig0000142a ), + .Q(\blk00000003/sig0000046c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000464 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001429 ), + .Q(\blk00000003/sig0000046d ) + ); + GND \blk00000003/blk00000462/blk00000463 ( + .G(\blk00000003/blk00000462/sig00001428 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000485/blk000004bd ( + .I0(\blk00000003/sig0000030c ), + .I1(ce), + .O(\blk00000003/blk00000485/sig0000149c ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004bc ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000af7 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001489 ), + .DPO(\blk00000003/blk00000485/sig0000149b ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004bb ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000af8 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001488 ), + .DPO(\blk00000003/blk00000485/sig0000149a ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004ba ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000af9 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001487 ), + .DPO(\blk00000003/blk00000485/sig00001499 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004b9 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000afa ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001486 ), + .DPO(\blk00000003/blk00000485/sig00001498 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004b8 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000afb ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001485 ), + .DPO(\blk00000003/blk00000485/sig00001497 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004b7 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000afc ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001484 ), + .DPO(\blk00000003/blk00000485/sig00001496 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004b6 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000afe ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001482 ), + .DPO(\blk00000003/blk00000485/sig00001494 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004b5 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000aff ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001481 ), + .DPO(\blk00000003/blk00000485/sig00001493 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004b4 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000afd ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001483 ), + .DPO(\blk00000003/blk00000485/sig00001495 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004b3 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b00 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001480 ), + .DPO(\blk00000003/blk00000485/sig00001492 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000485/blk000004b2 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b01 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig0000147f ), + .DPO(\blk00000003/blk00000485/sig00001491 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000485/blk000004b1 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b02 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig0000147e ), + .DPO(\blk00000003/blk00000485/sig00001490 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000485/blk000004b0 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b03 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig0000147d ), + .DPO(\blk00000003/blk00000485/sig0000148f ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000485/blk000004af ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b04 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig0000147c ), + .DPO(\blk00000003/blk00000485/sig0000148e ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000485/blk000004ae ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b05 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig0000147b ), + .DPO(\blk00000003/blk00000485/sig0000148d ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000485/blk000004ad ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b07 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001479 ), + .DPO(\blk00000003/blk00000485/sig0000148b ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000485/blk000004ac ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b08 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001478 ), + .DPO(\blk00000003/blk00000485/sig0000148a ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000485/blk000004ab ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b06 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig0000147a ), + .DPO(\blk00000003/blk00000485/sig0000148c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000149b ), + .Q(\blk00000003/sig000003bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000149a ), + .Q(\blk00000003/sig000003bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001499 ), + .Q(\blk00000003/sig000003be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001498 ), + .Q(\blk00000003/sig000003bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001497 ), + .Q(\blk00000003/sig000003c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001496 ), + .Q(\blk00000003/sig000003c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001495 ), + .Q(\blk00000003/sig000003c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001494 ), + .Q(\blk00000003/sig000003c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001493 ), + .Q(\blk00000003/sig000003c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001492 ), + .Q(\blk00000003/sig000003c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001491 ), + .Q(\blk00000003/sig000003c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000049f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001490 ), + .Q(\blk00000003/sig000003c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000049e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000148f ), + .Q(\blk00000003/sig000003c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000049d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000148e ), + .Q(\blk00000003/sig000003c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000049c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000148d ), + .Q(\blk00000003/sig000003ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000049b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000148c ), + .Q(\blk00000003/sig000003cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000049a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000148b ), + .Q(\blk00000003/sig000003cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000499 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000148a ), + .Q(\blk00000003/sig000003cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000498 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001489 ), + .Q(\blk00000003/sig00000b09 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000497 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001488 ), + .Q(\blk00000003/sig00000b0a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000496 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001487 ), + .Q(\blk00000003/sig00000b0b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000495 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001486 ), + .Q(\blk00000003/sig00000b0c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000494 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001485 ), + .Q(\blk00000003/sig00000b0d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000493 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001484 ), + .Q(\blk00000003/sig00000b0e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000492 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001483 ), + .Q(\blk00000003/sig00000b0f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000491 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001482 ), + .Q(\blk00000003/sig00000b10 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000490 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001481 ), + .Q(\blk00000003/sig00000b11 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000048f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001480 ), + .Q(\blk00000003/sig00000b12 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000048e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000147f ), + .Q(\blk00000003/sig00000b13 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000048d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000147e ), + .Q(\blk00000003/sig00000b14 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000048c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000147d ), + .Q(\blk00000003/sig00000b15 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000048b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000147c ), + .Q(\blk00000003/sig00000b16 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000048a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000147b ), + .Q(\blk00000003/sig00000b17 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000489 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000147a ), + .Q(\blk00000003/sig00000b18 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000488 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001479 ), + .Q(\blk00000003/sig00000b19 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000487 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001478 ), + .Q(\blk00000003/sig00000b1a ) + ); + GND \blk00000003/blk00000485/blk00000486 ( + .G(\blk00000003/blk00000485/sig00001477 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000004be/blk000004f6 ( + .I0(\blk00000003/sig000009f2 ), + .I1(ce), + .O(\blk00000003/blk000004be/sig000014ff ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004f5 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b09 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014ec ), + .DPO(\blk00000003/blk000004be/sig000014fe ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004f4 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b0a ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014eb ), + .DPO(\blk00000003/blk000004be/sig000014fd ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004f3 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b0b ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014ea ), + .DPO(\blk00000003/blk000004be/sig000014fc ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004f2 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b0c ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e9 ), + .DPO(\blk00000003/blk000004be/sig000014fb ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004f1 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b0d ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e8 ), + .DPO(\blk00000003/blk000004be/sig000014fa ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004f0 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b0e ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e7 ), + .DPO(\blk00000003/blk000004be/sig000014f9 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004ef ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b10 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e5 ), + .DPO(\blk00000003/blk000004be/sig000014f7 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000004be/blk000004ee ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b11 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e4 ), + .DPO(\blk00000003/blk000004be/sig000014f6 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004ed ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b0f ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e6 ), + .DPO(\blk00000003/blk000004be/sig000014f8 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000004be/blk000004ec ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b12 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e3 ), + .DPO(\blk00000003/blk000004be/sig000014f5 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004be/blk000004eb ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b13 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e2 ), + .DPO(\blk00000003/blk000004be/sig000014f4 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000004be/blk000004ea ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b14 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e1 ), + .DPO(\blk00000003/blk000004be/sig000014f3 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004be/blk000004e9 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b15 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e0 ), + .DPO(\blk00000003/blk000004be/sig000014f2 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000004be/blk000004e8 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b16 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014df ), + .DPO(\blk00000003/blk000004be/sig000014f1 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004e7 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b17 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014de ), + .DPO(\blk00000003/blk000004be/sig000014f0 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000004be/blk000004e6 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b19 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014dc ), + .DPO(\blk00000003/blk000004be/sig000014ee ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000004be/blk000004e5 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b1a ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014db ), + .DPO(\blk00000003/blk000004be/sig000014ed ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000004be/blk000004e4 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b18 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014dd ), + .DPO(\blk00000003/blk000004be/sig000014ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014fe ), + .Q(\blk00000003/sig00000580 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014fd ), + .Q(\blk00000003/sig00000581 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014fc ), + .Q(\blk00000003/sig00000582 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014fb ), + .Q(\blk00000003/sig00000583 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004df ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014fa ), + .Q(\blk00000003/sig00000584 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004de ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f9 ), + .Q(\blk00000003/sig00000585 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f8 ), + .Q(\blk00000003/sig00000586 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f7 ), + .Q(\blk00000003/sig00000587 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004db ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f6 ), + .Q(\blk00000003/sig00000588 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004da ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f5 ), + .Q(\blk00000003/sig00000589 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f4 ), + .Q(\blk00000003/sig0000058a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f3 ), + .Q(\blk00000003/sig0000058b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f2 ), + .Q(\blk00000003/sig0000058c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f1 ), + .Q(\blk00000003/sig0000058d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f0 ), + .Q(\blk00000003/sig0000058e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014ef ), + .Q(\blk00000003/sig0000058f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014ee ), + .Q(\blk00000003/sig00000590 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014ed ), + .Q(\blk00000003/sig00000591 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014ec ), + .Q(\blk00000003/sig00000b1b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014eb ), + .Q(\blk00000003/sig00000b1c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014ea ), + .Q(\blk00000003/sig00000b1d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e9 ), + .Q(\blk00000003/sig00000b1e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e8 ), + .Q(\blk00000003/sig00000b1f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e7 ), + .Q(\blk00000003/sig00000b20 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e6 ), + .Q(\blk00000003/sig00000b21 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e5 ), + .Q(\blk00000003/sig00000b22 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e4 ), + .Q(\blk00000003/sig00000b23 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e3 ), + .Q(\blk00000003/sig00000b24 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e2 ), + .Q(\blk00000003/sig00000b25 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e1 ), + .Q(\blk00000003/sig00000b26 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e0 ), + .Q(\blk00000003/sig00000b27 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014df ), + .Q(\blk00000003/sig00000b28 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014de ), + .Q(\blk00000003/sig00000b29 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014dd ), + .Q(\blk00000003/sig00000b2a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014dc ), + .Q(\blk00000003/sig00000b2b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014db ), + .Q(\blk00000003/sig00000b2c ) + ); + GND \blk00000003/blk000004be/blk000004bf ( + .G(\blk00000003/blk000004be/sig000014da ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000004f7/blk0000052f ( + .I0(\blk00000003/sig000009f3 ), + .I1(ce), + .O(\blk00000003/blk000004f7/sig00001562 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk0000052e ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b1b ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig0000154f ), + .DPO(\blk00000003/blk000004f7/sig00001561 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk0000052d ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b1c ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig0000154e ), + .DPO(\blk00000003/blk000004f7/sig00001560 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk0000052c ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b1d ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig0000154d ), + .DPO(\blk00000003/blk000004f7/sig0000155f ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk0000052b ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b1e ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig0000154c ), + .DPO(\blk00000003/blk000004f7/sig0000155e ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk0000052a ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b1f ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig0000154b ), + .DPO(\blk00000003/blk000004f7/sig0000155d ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk00000529 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b20 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig0000154a ), + .DPO(\blk00000003/blk000004f7/sig0000155c ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004f7/blk00000528 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b22 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001548 ), + .DPO(\blk00000003/blk000004f7/sig0000155a ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk00000527 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b23 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001547 ), + .DPO(\blk00000003/blk000004f7/sig00001559 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000004f7/blk00000526 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b21 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001549 ), + .DPO(\blk00000003/blk000004f7/sig0000155b ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000004f7/blk00000525 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b24 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001546 ), + .DPO(\blk00000003/blk000004f7/sig00001558 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000004f7/blk00000524 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b25 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001545 ), + .DPO(\blk00000003/blk000004f7/sig00001557 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004f7/blk00000523 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b26 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001544 ), + .DPO(\blk00000003/blk000004f7/sig00001556 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000004f7/blk00000522 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b27 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001543 ), + .DPO(\blk00000003/blk000004f7/sig00001555 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk00000521 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b28 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001542 ), + .DPO(\blk00000003/blk000004f7/sig00001554 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000004f7/blk00000520 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b29 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001541 ), + .DPO(\blk00000003/blk000004f7/sig00001553 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000004f7/blk0000051f ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b2b ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig0000153f ), + .DPO(\blk00000003/blk000004f7/sig00001551 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk0000051e ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b2c ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig0000153e ), + .DPO(\blk00000003/blk000004f7/sig00001550 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000004f7/blk0000051d ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b2a ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001540 ), + .DPO(\blk00000003/blk000004f7/sig00001552 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000051c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001561 ), + .Q(\blk00000003/sig000005d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000051b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001560 ), + .Q(\blk00000003/sig000005d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000051a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000155f ), + .Q(\blk00000003/sig000005d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000519 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000155e ), + .Q(\blk00000003/sig000005d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000518 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000155d ), + .Q(\blk00000003/sig000005d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000517 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000155c ), + .Q(\blk00000003/sig000005d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000516 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000155b ), + .Q(\blk00000003/sig000005d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000515 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000155a ), + .Q(\blk00000003/sig000005d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000514 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001559 ), + .Q(\blk00000003/sig000005da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000513 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001558 ), + .Q(\blk00000003/sig000005db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000512 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001557 ), + .Q(\blk00000003/sig000005dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000511 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001556 ), + .Q(\blk00000003/sig000005dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000510 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001555 ), + .Q(\blk00000003/sig000005de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000050f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001554 ), + .Q(\blk00000003/sig000005df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000050e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001553 ), + .Q(\blk00000003/sig000005e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000050d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001552 ), + .Q(\blk00000003/sig000005e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000050c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001551 ), + .Q(\blk00000003/sig000005e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000050b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001550 ), + .Q(\blk00000003/sig000005e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000050a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000154f ), + .Q(\blk00000003/sig00000b2d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000509 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000154e ), + .Q(\blk00000003/sig00000b2e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000508 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000154d ), + .Q(\blk00000003/sig00000b2f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000507 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000154c ), + .Q(\blk00000003/sig00000b30 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000506 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000154b ), + .Q(\blk00000003/sig00000b31 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000505 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000154a ), + .Q(\blk00000003/sig00000b32 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000504 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001549 ), + .Q(\blk00000003/sig00000b33 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000503 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001548 ), + .Q(\blk00000003/sig00000b34 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000502 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001547 ), + .Q(\blk00000003/sig00000b35 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000501 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001546 ), + .Q(\blk00000003/sig00000b36 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000500 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001545 ), + .Q(\blk00000003/sig00000b37 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk000004ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001544 ), + .Q(\blk00000003/sig00000b38 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk000004fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001543 ), + .Q(\blk00000003/sig00000b39 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk000004fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001542 ), + .Q(\blk00000003/sig00000b3a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk000004fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001541 ), + .Q(\blk00000003/sig00000b3b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk000004fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001540 ), + .Q(\blk00000003/sig00000b3c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk000004fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000153f ), + .Q(\blk00000003/sig00000b3d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk000004f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000153e ), + .Q(\blk00000003/sig00000b3e ) + ); + GND \blk00000003/blk000004f7/blk000004f8 ( + .G(\blk00000003/blk000004f7/sig0000153d ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000530/blk00000568 ( + .I0(\blk00000003/sig000009f4 ), + .I1(ce), + .O(\blk00000003/blk00000530/sig000015c5 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000530/blk00000567 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b2d ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015b2 ), + .DPO(\blk00000003/blk00000530/sig000015c4 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000530/blk00000566 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b2e ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015b1 ), + .DPO(\blk00000003/blk00000530/sig000015c3 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000530/blk00000565 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b2f ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015b0 ), + .DPO(\blk00000003/blk00000530/sig000015c2 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000530/blk00000564 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b30 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015af ), + .DPO(\blk00000003/blk00000530/sig000015c1 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000530/blk00000563 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b31 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015ae ), + .DPO(\blk00000003/blk00000530/sig000015c0 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000530/blk00000562 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b32 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015ad ), + .DPO(\blk00000003/blk00000530/sig000015bf ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000530/blk00000561 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b34 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015ab ), + .DPO(\blk00000003/blk00000530/sig000015bd ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000530/blk00000560 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b35 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015aa ), + .DPO(\blk00000003/blk00000530/sig000015bc ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000530/blk0000055f ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b33 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015ac ), + .DPO(\blk00000003/blk00000530/sig000015be ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000530/blk0000055e ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b36 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a9 ), + .DPO(\blk00000003/blk00000530/sig000015bb ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000530/blk0000055d ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b37 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a8 ), + .DPO(\blk00000003/blk00000530/sig000015ba ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000530/blk0000055c ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b38 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a7 ), + .DPO(\blk00000003/blk00000530/sig000015b9 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000530/blk0000055b ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b39 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a6 ), + .DPO(\blk00000003/blk00000530/sig000015b8 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000530/blk0000055a ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b3a ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a5 ), + .DPO(\blk00000003/blk00000530/sig000015b7 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000530/blk00000559 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b3b ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a4 ), + .DPO(\blk00000003/blk00000530/sig000015b6 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000530/blk00000558 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b3d ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a2 ), + .DPO(\blk00000003/blk00000530/sig000015b4 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000530/blk00000557 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b3e ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a1 ), + .DPO(\blk00000003/blk00000530/sig000015b3 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000530/blk00000556 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b3c ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a3 ), + .DPO(\blk00000003/blk00000530/sig000015b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000555 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015c4 ), + .Q(\blk00000003/sig00000624 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000554 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015c3 ), + .Q(\blk00000003/sig00000625 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000553 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015c2 ), + .Q(\blk00000003/sig00000626 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000552 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015c1 ), + .Q(\blk00000003/sig00000627 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000551 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015c0 ), + .Q(\blk00000003/sig00000628 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000550 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015bf ), + .Q(\blk00000003/sig00000629 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000054f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015be ), + .Q(\blk00000003/sig0000062a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000054e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015bd ), + .Q(\blk00000003/sig0000062b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000054d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015bc ), + .Q(\blk00000003/sig0000062c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000054c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015bb ), + .Q(\blk00000003/sig0000062d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000054b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015ba ), + .Q(\blk00000003/sig0000062e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000054a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b9 ), + .Q(\blk00000003/sig0000062f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000549 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b8 ), + .Q(\blk00000003/sig00000630 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000548 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b7 ), + .Q(\blk00000003/sig00000631 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000547 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b6 ), + .Q(\blk00000003/sig00000632 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000546 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b5 ), + .Q(\blk00000003/sig00000633 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000545 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b4 ), + .Q(\blk00000003/sig00000634 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000544 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b3 ), + .Q(\blk00000003/sig00000635 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000543 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b2 ), + .Q(\blk00000003/sig00000b3f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000542 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b1 ), + .Q(\blk00000003/sig00000b40 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000541 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b0 ), + .Q(\blk00000003/sig00000b41 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000540 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015af ), + .Q(\blk00000003/sig00000b42 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000053f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015ae ), + .Q(\blk00000003/sig00000b43 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000053e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015ad ), + .Q(\blk00000003/sig00000b44 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000053d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015ac ), + .Q(\blk00000003/sig00000b45 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000053c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015ab ), + .Q(\blk00000003/sig00000b46 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000053b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015aa ), + .Q(\blk00000003/sig00000b47 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000053a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a9 ), + .Q(\blk00000003/sig00000b48 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000539 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a8 ), + .Q(\blk00000003/sig00000b49 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000538 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a7 ), + .Q(\blk00000003/sig00000b4a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000537 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a6 ), + .Q(\blk00000003/sig00000b4b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000536 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a5 ), + .Q(\blk00000003/sig00000b4c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000535 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a4 ), + .Q(\blk00000003/sig00000b4d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000534 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a3 ), + .Q(\blk00000003/sig00000b4e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000533 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a2 ), + .Q(\blk00000003/sig00000b4f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000532 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a1 ), + .Q(\blk00000003/sig00000b50 ) + ); + GND \blk00000003/blk00000530/blk00000531 ( + .G(\blk00000003/blk00000530/sig000015a0 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000569/blk000005a1 ( + .I0(\blk00000003/sig000009f5 ), + .I1(ce), + .O(\blk00000003/blk00000569/sig00001628 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000569/blk000005a0 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b3f ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001615 ), + .DPO(\blk00000003/blk00000569/sig00001627 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000569/blk0000059f ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b40 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001614 ), + .DPO(\blk00000003/blk00000569/sig00001626 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000569/blk0000059e ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b41 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001613 ), + .DPO(\blk00000003/blk00000569/sig00001625 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000569/blk0000059d ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b42 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001612 ), + .DPO(\blk00000003/blk00000569/sig00001624 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000569/blk0000059c ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b43 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001611 ), + .DPO(\blk00000003/blk00000569/sig00001623 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000569/blk0000059b ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b44 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001610 ), + .DPO(\blk00000003/blk00000569/sig00001622 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000569/blk0000059a ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b46 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig0000160e ), + .DPO(\blk00000003/blk00000569/sig00001620 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000569/blk00000599 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b47 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig0000160d ), + .DPO(\blk00000003/blk00000569/sig0000161f ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000569/blk00000598 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b45 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig0000160f ), + .DPO(\blk00000003/blk00000569/sig00001621 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000569/blk00000597 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b48 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig0000160c ), + .DPO(\blk00000003/blk00000569/sig0000161e ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000569/blk00000596 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b49 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig0000160b ), + .DPO(\blk00000003/blk00000569/sig0000161d ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000569/blk00000595 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b4a ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig0000160a ), + .DPO(\blk00000003/blk00000569/sig0000161c ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000569/blk00000594 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b4b ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001609 ), + .DPO(\blk00000003/blk00000569/sig0000161b ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000569/blk00000593 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b4c ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001608 ), + .DPO(\blk00000003/blk00000569/sig0000161a ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000569/blk00000592 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b4d ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001607 ), + .DPO(\blk00000003/blk00000569/sig00001619 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000569/blk00000591 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b4f ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001605 ), + .DPO(\blk00000003/blk00000569/sig00001617 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000569/blk00000590 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b50 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001604 ), + .DPO(\blk00000003/blk00000569/sig00001616 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000569/blk0000058f ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b4e ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001606 ), + .DPO(\blk00000003/blk00000569/sig00001618 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000058e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001627 ), + .Q(\blk00000003/sig00000646 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000058d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001626 ), + .Q(\blk00000003/sig00000647 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000058c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001625 ), + .Q(\blk00000003/sig00000648 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000058b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001624 ), + .Q(\blk00000003/sig00000649 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000058a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001623 ), + .Q(\blk00000003/sig0000064a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000589 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001622 ), + .Q(\blk00000003/sig0000064b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000588 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001621 ), + .Q(\blk00000003/sig0000064c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000587 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001620 ), + .Q(\blk00000003/sig0000064d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000586 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000161f ), + .Q(\blk00000003/sig0000064e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000585 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000161e ), + .Q(\blk00000003/sig0000064f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000584 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000161d ), + .Q(\blk00000003/sig00000650 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000583 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000161c ), + .Q(\blk00000003/sig00000651 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000582 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000161b ), + .Q(\blk00000003/sig00000652 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000581 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000161a ), + .Q(\blk00000003/sig00000653 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000580 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001619 ), + .Q(\blk00000003/sig00000654 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000057f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001618 ), + .Q(\blk00000003/sig00000655 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000057e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001617 ), + .Q(\blk00000003/sig00000656 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000057d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001616 ), + .Q(\blk00000003/sig00000657 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000057c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001615 ), + .Q(\blk00000003/sig00000b51 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000057b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001614 ), + .Q(\blk00000003/sig00000b52 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000057a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001613 ), + .Q(\blk00000003/sig00000b53 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000579 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001612 ), + .Q(\blk00000003/sig00000b54 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000578 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001611 ), + .Q(\blk00000003/sig00000b55 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000577 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001610 ), + .Q(\blk00000003/sig00000b56 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000576 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000160f ), + .Q(\blk00000003/sig00000b57 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000575 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000160e ), + .Q(\blk00000003/sig00000b58 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000574 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000160d ), + .Q(\blk00000003/sig00000b59 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000573 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000160c ), + .Q(\blk00000003/sig00000b5a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000572 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000160b ), + .Q(\blk00000003/sig00000b5b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000571 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000160a ), + .Q(\blk00000003/sig00000b5c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000570 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001609 ), + .Q(\blk00000003/sig00000b5d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000056f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001608 ), + .Q(\blk00000003/sig00000b5e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000056e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001607 ), + .Q(\blk00000003/sig00000b5f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000056d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001606 ), + .Q(\blk00000003/sig00000b60 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000056c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001605 ), + .Q(\blk00000003/sig00000b61 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000056b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001604 ), + .Q(\blk00000003/sig00000b62 ) + ); + GND \blk00000003/blk00000569/blk0000056a ( + .G(\blk00000003/blk00000569/sig00001603 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005a2/blk000005c8 ( + .I0(\blk00000003/sig000009f6 ), + .I1(ce), + .O(\blk00000003/blk000005a2/sig00001667 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000005a2/blk000005c7 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b51 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005c7_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001666 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000005a2/blk000005c6 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b52 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005c6_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001665 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000005a2/blk000005c5 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b53 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005c5_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001664 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000005a2/blk000005c4 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b54 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005c4_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001663 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a2/blk000005c3 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b55 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005c3_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001662 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000005a2/blk000005c2 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b56 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005c2_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001661 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000005a2/blk000005c1 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b58 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005c1_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig0000165f ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a2/blk000005c0 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b59 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005c0_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig0000165e ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000005a2/blk000005bf ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b57 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005bf_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001660 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a2/blk000005be ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b5a ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005be_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig0000165d ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a2/blk000005bd ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b5b ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005bd_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig0000165c ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000005a2/blk000005bc ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b5c ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005bc_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig0000165b ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a2/blk000005bb ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b5d ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005bb_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig0000165a ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000005a2/blk000005ba ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b5e ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005ba_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001659 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000005a2/blk000005b9 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b5f ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005b9_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001658 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a2/blk000005b8 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b61 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005b8_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001656 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000005a2/blk000005b7 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b62 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005b7_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001655 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a2/blk000005b6 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b60 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005b6_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001657 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001666 ), + .Q(\blk00000003/sig000004ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001665 ), + .Q(\blk00000003/sig000004ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001664 ), + .Q(\blk00000003/sig000004f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001663 ), + .Q(\blk00000003/sig000004f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001662 ), + .Q(\blk00000003/sig000004f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001661 ), + .Q(\blk00000003/sig000004f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005af ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001660 ), + .Q(\blk00000003/sig000004f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig0000165f ), + .Q(\blk00000003/sig000004f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig0000165e ), + .Q(\blk00000003/sig000004f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig0000165d ), + .Q(\blk00000003/sig000004f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig0000165c ), + .Q(\blk00000003/sig000004f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig0000165b ), + .Q(\blk00000003/sig000004f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig0000165a ), + .Q(\blk00000003/sig000004fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001659 ), + .Q(\blk00000003/sig000004fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001658 ), + .Q(\blk00000003/sig000004fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001657 ), + .Q(\blk00000003/sig000004fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001656 ), + .Q(\blk00000003/sig000004fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001655 ), + .Q(\blk00000003/sig000004ff ) + ); + GND \blk00000003/blk000005a2/blk000005a3 ( + .G(\blk00000003/blk000005a2/sig00001654 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005c9/blk000005db ( + .I0(\blk00000003/sig000009fa ), + .I1(ce), + .O(\blk00000003/blk000005c9/sig00001685 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c9/blk000005da ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005c9/sig0000167c ), + .A2(\blk00000003/blk000005c9/sig0000167c ), + .A3(\blk00000003/blk000005c9/sig0000167c ), + .CE(\blk00000003/blk000005c9/sig00001685 ), + .CLK(clk), + .D(\blk00000003/sig0000063e ), + .Q(\blk00000003/blk000005c9/sig00001684 ), + .Q15(\NLW_blk00000003/blk000005c9/blk000005da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c9/blk000005d9 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005c9/sig0000167c ), + .A2(\blk00000003/blk000005c9/sig0000167c ), + .A3(\blk00000003/blk000005c9/sig0000167c ), + .CE(\blk00000003/blk000005c9/sig00001685 ), + .CLK(clk), + .D(\blk00000003/sig0000063f ), + .Q(\blk00000003/blk000005c9/sig00001683 ), + .Q15(\NLW_blk00000003/blk000005c9/blk000005d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c9/blk000005d8 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005c9/sig0000167c ), + .A2(\blk00000003/blk000005c9/sig0000167c ), + .A3(\blk00000003/blk000005c9/sig0000167c ), + .CE(\blk00000003/blk000005c9/sig00001685 ), + .CLK(clk), + .D(\blk00000003/sig00000640 ), + .Q(\blk00000003/blk000005c9/sig00001682 ), + .Q15(\NLW_blk00000003/blk000005c9/blk000005d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c9/blk000005d7 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005c9/sig0000167c ), + .A2(\blk00000003/blk000005c9/sig0000167c ), + .A3(\blk00000003/blk000005c9/sig0000167c ), + .CE(\blk00000003/blk000005c9/sig00001685 ), + .CLK(clk), + .D(\blk00000003/sig00000641 ), + .Q(\blk00000003/blk000005c9/sig00001681 ), + .Q15(\NLW_blk00000003/blk000005c9/blk000005d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c9/blk000005d6 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005c9/sig0000167c ), + .A2(\blk00000003/blk000005c9/sig0000167c ), + .A3(\blk00000003/blk000005c9/sig0000167c ), + .CE(\blk00000003/blk000005c9/sig00001685 ), + .CLK(clk), + .D(\blk00000003/sig00000642 ), + .Q(\blk00000003/blk000005c9/sig00001680 ), + .Q15(\NLW_blk00000003/blk000005c9/blk000005d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c9/blk000005d5 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005c9/sig0000167c ), + .A2(\blk00000003/blk000005c9/sig0000167c ), + .A3(\blk00000003/blk000005c9/sig0000167c ), + .CE(\blk00000003/blk000005c9/sig00001685 ), + .CLK(clk), + .D(\blk00000003/sig00000643 ), + .Q(\blk00000003/blk000005c9/sig0000167f ), + .Q15(\NLW_blk00000003/blk000005c9/blk000005d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c9/blk000005d4 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005c9/sig0000167c ), + .A2(\blk00000003/blk000005c9/sig0000167c ), + .A3(\blk00000003/blk000005c9/sig0000167c ), + .CE(\blk00000003/blk000005c9/sig00001685 ), + .CLK(clk), + .D(\blk00000003/sig00000644 ), + .Q(\blk00000003/blk000005c9/sig0000167e ), + .Q15(\NLW_blk00000003/blk000005c9/blk000005d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c9/blk000005d3 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005c9/sig0000167c ), + .A2(\blk00000003/blk000005c9/sig0000167c ), + .A3(\blk00000003/blk000005c9/sig0000167c ), + .CE(\blk00000003/blk000005c9/sig00001685 ), + .CLK(clk), + .D(\blk00000003/sig00000645 ), + .Q(\blk00000003/blk000005c9/sig0000167d ), + .Q15(\NLW_blk00000003/blk000005c9/blk000005d3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9/blk000005d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005c9/sig00001684 ), + .Q(\blk00000003/sig000004e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9/blk000005d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005c9/sig00001683 ), + .Q(\blk00000003/sig000004e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9/blk000005d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005c9/sig00001682 ), + .Q(\blk00000003/sig000004e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9/blk000005cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005c9/sig00001681 ), + .Q(\blk00000003/sig000004e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9/blk000005ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005c9/sig00001680 ), + .Q(\blk00000003/sig000004ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9/blk000005cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005c9/sig0000167f ), + .Q(\blk00000003/sig000004eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9/blk000005cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005c9/sig0000167e ), + .Q(\blk00000003/sig000004ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9/blk000005cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005c9/sig0000167d ), + .Q(\blk00000003/sig000004ed ) + ); + GND \blk00000003/blk000005c9/blk000005ca ( + .G(\blk00000003/blk000005c9/sig0000167c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005dc/blk000005ee ( + .I0(\blk00000003/sig000009f8 ), + .I1(ce), + .O(\blk00000003/blk000005dc/sig000016a3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc/blk000005ed ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000005dc/sig0000169a ), + .A2(\blk00000003/blk000005dc/sig0000169a ), + .A3(\blk00000003/blk000005dc/sig0000169a ), + .CE(\blk00000003/blk000005dc/sig000016a3 ), + .CLK(clk), + .D(\blk00000003/sig00000b63 ), + .Q(\blk00000003/blk000005dc/sig000016a2 ), + .Q15(\NLW_blk00000003/blk000005dc/blk000005ed_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc/blk000005ec ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000005dc/sig0000169a ), + .A2(\blk00000003/blk000005dc/sig0000169a ), + .A3(\blk00000003/blk000005dc/sig0000169a ), + .CE(\blk00000003/blk000005dc/sig000016a3 ), + .CLK(clk), + .D(\blk00000003/sig00000b64 ), + .Q(\blk00000003/blk000005dc/sig000016a1 ), + .Q15(\NLW_blk00000003/blk000005dc/blk000005ec_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc/blk000005eb ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000005dc/sig0000169a ), + .A2(\blk00000003/blk000005dc/sig0000169a ), + .A3(\blk00000003/blk000005dc/sig0000169a ), + .CE(\blk00000003/blk000005dc/sig000016a3 ), + .CLK(clk), + .D(\blk00000003/sig00000b65 ), + .Q(\blk00000003/blk000005dc/sig000016a0 ), + .Q15(\NLW_blk00000003/blk000005dc/blk000005eb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc/blk000005ea ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000005dc/sig0000169a ), + .A2(\blk00000003/blk000005dc/sig0000169a ), + .A3(\blk00000003/blk000005dc/sig0000169a ), + .CE(\blk00000003/blk000005dc/sig000016a3 ), + .CLK(clk), + .D(\blk00000003/sig00000b66 ), + .Q(\blk00000003/blk000005dc/sig0000169f ), + .Q15(\NLW_blk00000003/blk000005dc/blk000005ea_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc/blk000005e9 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000005dc/sig0000169a ), + .A2(\blk00000003/blk000005dc/sig0000169a ), + .A3(\blk00000003/blk000005dc/sig0000169a ), + .CE(\blk00000003/blk000005dc/sig000016a3 ), + .CLK(clk), + .D(\blk00000003/sig00000b67 ), + .Q(\blk00000003/blk000005dc/sig0000169e ), + .Q15(\NLW_blk00000003/blk000005dc/blk000005e9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc/blk000005e8 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000005dc/sig0000169a ), + .A2(\blk00000003/blk000005dc/sig0000169a ), + .A3(\blk00000003/blk000005dc/sig0000169a ), + .CE(\blk00000003/blk000005dc/sig000016a3 ), + .CLK(clk), + .D(\blk00000003/sig00000b68 ), + .Q(\blk00000003/blk000005dc/sig0000169d ), + .Q15(\NLW_blk00000003/blk000005dc/blk000005e8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc/blk000005e7 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000005dc/sig0000169a ), + .A2(\blk00000003/blk000005dc/sig0000169a ), + .A3(\blk00000003/blk000005dc/sig0000169a ), + .CE(\blk00000003/blk000005dc/sig000016a3 ), + .CLK(clk), + .D(\blk00000003/sig00000b69 ), + .Q(\blk00000003/blk000005dc/sig0000169c ), + .Q15(\NLW_blk00000003/blk000005dc/blk000005e7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc/blk000005e6 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000005dc/sig0000169a ), + .A2(\blk00000003/blk000005dc/sig0000169a ), + .A3(\blk00000003/blk000005dc/sig0000169a ), + .CE(\blk00000003/blk000005dc/sig000016a3 ), + .CLK(clk), + .D(\blk00000003/sig00000b6a ), + .Q(\blk00000003/blk000005dc/sig0000169b ), + .Q15(\NLW_blk00000003/blk000005dc/blk000005e6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dc/blk000005e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005dc/sig000016a2 ), + .Q(\blk00000003/sig000004ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dc/blk000005e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005dc/sig000016a1 ), + .Q(\blk00000003/sig000004af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dc/blk000005e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005dc/sig000016a0 ), + .Q(\blk00000003/sig000004b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dc/blk000005e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005dc/sig0000169f ), + .Q(\blk00000003/sig000004b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dc/blk000005e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005dc/sig0000169e ), + .Q(\blk00000003/sig000004b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dc/blk000005e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005dc/sig0000169d ), + .Q(\blk00000003/sig000004b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dc/blk000005df ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005dc/sig0000169c ), + .Q(\blk00000003/sig000004b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dc/blk000005de ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005dc/sig0000169b ), + .Q(\blk00000003/sig000004b5 ) + ); + GND \blk00000003/blk000005dc/blk000005dd ( + .G(\blk00000003/blk000005dc/sig0000169a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005ef/blk00000601 ( + .I0(\blk00000003/sig000009fa ), + .I1(ce), + .O(\blk00000003/blk000005ef/sig000016c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ef/blk00000600 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005ef/sig000016b8 ), + .A2(\blk00000003/blk000005ef/sig000016b8 ), + .A3(\blk00000003/blk000005ef/sig000016b8 ), + .CE(\blk00000003/blk000005ef/sig000016c1 ), + .CLK(clk), + .D(\blk00000003/sig00000720 ), + .Q(\blk00000003/blk000005ef/sig000016c0 ), + .Q15(\NLW_blk00000003/blk000005ef/blk00000600_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ef/blk000005ff ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005ef/sig000016b8 ), + .A2(\blk00000003/blk000005ef/sig000016b8 ), + .A3(\blk00000003/blk000005ef/sig000016b8 ), + .CE(\blk00000003/blk000005ef/sig000016c1 ), + .CLK(clk), + .D(\blk00000003/sig00000721 ), + .Q(\blk00000003/blk000005ef/sig000016bf ), + .Q15(\NLW_blk00000003/blk000005ef/blk000005ff_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ef/blk000005fe ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005ef/sig000016b8 ), + .A2(\blk00000003/blk000005ef/sig000016b8 ), + .A3(\blk00000003/blk000005ef/sig000016b8 ), + .CE(\blk00000003/blk000005ef/sig000016c1 ), + .CLK(clk), + .D(\blk00000003/sig00000722 ), + .Q(\blk00000003/blk000005ef/sig000016be ), + .Q15(\NLW_blk00000003/blk000005ef/blk000005fe_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ef/blk000005fd ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005ef/sig000016b8 ), + .A2(\blk00000003/blk000005ef/sig000016b8 ), + .A3(\blk00000003/blk000005ef/sig000016b8 ), + .CE(\blk00000003/blk000005ef/sig000016c1 ), + .CLK(clk), + .D(\blk00000003/sig00000723 ), + .Q(\blk00000003/blk000005ef/sig000016bd ), + .Q15(\NLW_blk00000003/blk000005ef/blk000005fd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ef/blk000005fc ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005ef/sig000016b8 ), + .A2(\blk00000003/blk000005ef/sig000016b8 ), + .A3(\blk00000003/blk000005ef/sig000016b8 ), + .CE(\blk00000003/blk000005ef/sig000016c1 ), + .CLK(clk), + .D(\blk00000003/sig00000724 ), + .Q(\blk00000003/blk000005ef/sig000016bc ), + .Q15(\NLW_blk00000003/blk000005ef/blk000005fc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ef/blk000005fb ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005ef/sig000016b8 ), + .A2(\blk00000003/blk000005ef/sig000016b8 ), + .A3(\blk00000003/blk000005ef/sig000016b8 ), + .CE(\blk00000003/blk000005ef/sig000016c1 ), + .CLK(clk), + .D(\blk00000003/sig00000725 ), + .Q(\blk00000003/blk000005ef/sig000016bb ), + .Q15(\NLW_blk00000003/blk000005ef/blk000005fb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ef/blk000005fa ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005ef/sig000016b8 ), + .A2(\blk00000003/blk000005ef/sig000016b8 ), + .A3(\blk00000003/blk000005ef/sig000016b8 ), + .CE(\blk00000003/blk000005ef/sig000016c1 ), + .CLK(clk), + .D(\blk00000003/sig00000726 ), + .Q(\blk00000003/blk000005ef/sig000016ba ), + .Q15(\NLW_blk00000003/blk000005ef/blk000005fa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ef/blk000005f9 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005ef/sig000016b8 ), + .A2(\blk00000003/blk000005ef/sig000016b8 ), + .A3(\blk00000003/blk000005ef/sig000016b8 ), + .CE(\blk00000003/blk000005ef/sig000016c1 ), + .CLK(clk), + .D(\blk00000003/sig00000727 ), + .Q(\blk00000003/blk000005ef/sig000016b9 ), + .Q15(\NLW_blk00000003/blk000005ef/blk000005f9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef/blk000005f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005ef/sig000016c0 ), + .Q(\blk00000003/sig00000538 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef/blk000005f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005ef/sig000016bf ), + .Q(\blk00000003/sig00000539 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef/blk000005f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005ef/sig000016be ), + .Q(\blk00000003/sig0000053a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef/blk000005f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005ef/sig000016bd ), + .Q(\blk00000003/sig0000053b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef/blk000005f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005ef/sig000016bc ), + .Q(\blk00000003/sig0000053c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef/blk000005f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005ef/sig000016bb ), + .Q(\blk00000003/sig0000053d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef/blk000005f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005ef/sig000016ba ), + .Q(\blk00000003/sig0000053e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef/blk000005f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005ef/sig000016b9 ), + .Q(\blk00000003/sig0000053f ) + ); + GND \blk00000003/blk000005ef/blk000005f0 ( + .G(\blk00000003/blk000005ef/sig000016b8 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000602/blk00000614 ( + .I0(\blk00000003/sig000009f8 ), + .I1(ce), + .O(\blk00000003/blk00000602/sig000016df ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602/blk00000613 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000602/sig000016d6 ), + .A2(\blk00000003/blk00000602/sig000016d6 ), + .A3(\blk00000003/blk00000602/sig000016d6 ), + .CE(\blk00000003/blk00000602/sig000016df ), + .CLK(clk), + .D(\blk00000003/sig00000b6b ), + .Q(\blk00000003/blk00000602/sig000016de ), + .Q15(\NLW_blk00000003/blk00000602/blk00000613_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602/blk00000612 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000602/sig000016d6 ), + .A2(\blk00000003/blk00000602/sig000016d6 ), + .A3(\blk00000003/blk00000602/sig000016d6 ), + .CE(\blk00000003/blk00000602/sig000016df ), + .CLK(clk), + .D(\blk00000003/sig00000b6c ), + .Q(\blk00000003/blk00000602/sig000016dd ), + .Q15(\NLW_blk00000003/blk00000602/blk00000612_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602/blk00000611 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000602/sig000016d6 ), + .A2(\blk00000003/blk00000602/sig000016d6 ), + .A3(\blk00000003/blk00000602/sig000016d6 ), + .CE(\blk00000003/blk00000602/sig000016df ), + .CLK(clk), + .D(\blk00000003/sig00000b6d ), + .Q(\blk00000003/blk00000602/sig000016dc ), + .Q15(\NLW_blk00000003/blk00000602/blk00000611_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602/blk00000610 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000602/sig000016d6 ), + .A2(\blk00000003/blk00000602/sig000016d6 ), + .A3(\blk00000003/blk00000602/sig000016d6 ), + .CE(\blk00000003/blk00000602/sig000016df ), + .CLK(clk), + .D(\blk00000003/sig00000b6e ), + .Q(\blk00000003/blk00000602/sig000016db ), + .Q15(\NLW_blk00000003/blk00000602/blk00000610_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602/blk0000060f ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000602/sig000016d6 ), + .A2(\blk00000003/blk00000602/sig000016d6 ), + .A3(\blk00000003/blk00000602/sig000016d6 ), + .CE(\blk00000003/blk00000602/sig000016df ), + .CLK(clk), + .D(\blk00000003/sig00000b6f ), + .Q(\blk00000003/blk00000602/sig000016da ), + .Q15(\NLW_blk00000003/blk00000602/blk0000060f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602/blk0000060e ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000602/sig000016d6 ), + .A2(\blk00000003/blk00000602/sig000016d6 ), + .A3(\blk00000003/blk00000602/sig000016d6 ), + .CE(\blk00000003/blk00000602/sig000016df ), + .CLK(clk), + .D(\blk00000003/sig00000b70 ), + .Q(\blk00000003/blk00000602/sig000016d9 ), + .Q15(\NLW_blk00000003/blk00000602/blk0000060e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602/blk0000060d ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000602/sig000016d6 ), + .A2(\blk00000003/blk00000602/sig000016d6 ), + .A3(\blk00000003/blk00000602/sig000016d6 ), + .CE(\blk00000003/blk00000602/sig000016df ), + .CLK(clk), + .D(\blk00000003/sig00000b71 ), + .Q(\blk00000003/blk00000602/sig000016d8 ), + .Q15(\NLW_blk00000003/blk00000602/blk0000060d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602/blk0000060c ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000602/sig000016d6 ), + .A2(\blk00000003/blk00000602/sig000016d6 ), + .A3(\blk00000003/blk00000602/sig000016d6 ), + .CE(\blk00000003/blk00000602/sig000016df ), + .CLK(clk), + .D(\blk00000003/sig00000b72 ), + .Q(\blk00000003/blk00000602/sig000016d7 ), + .Q15(\NLW_blk00000003/blk00000602/blk0000060c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000602/blk0000060b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000602/sig000016de ), + .Q(\blk00000003/sig00000500 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000602/blk0000060a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000602/sig000016dd ), + .Q(\blk00000003/sig00000501 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000602/blk00000609 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000602/sig000016dc ), + .Q(\blk00000003/sig00000502 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000602/blk00000608 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000602/sig000016db ), + .Q(\blk00000003/sig00000503 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000602/blk00000607 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000602/sig000016da ), + .Q(\blk00000003/sig00000504 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000602/blk00000606 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000602/sig000016d9 ), + .Q(\blk00000003/sig00000505 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000602/blk00000605 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000602/sig000016d8 ), + .Q(\blk00000003/sig00000506 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000602/blk00000604 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000602/sig000016d7 ), + .Q(\blk00000003/sig00000507 ) + ); + GND \blk00000003/blk00000602/blk00000603 ( + .G(\blk00000003/blk00000602/sig000016d6 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000615/blk00000627 ( + .I0(\blk00000003/sig000009f9 ), + .I1(ce), + .O(\blk00000003/blk00000615/sig000016fd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000615/blk00000626 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk00000615/sig000016f4 ), + .A2(\blk00000003/blk00000615/sig000016f4 ), + .A3(\blk00000003/blk00000615/sig000016f4 ), + .CE(\blk00000003/blk00000615/sig000016fd ), + .CLK(clk), + .D(\blk00000003/sig000005ec ), + .Q(\blk00000003/blk00000615/sig000016fc ), + .Q15(\NLW_blk00000003/blk00000615/blk00000626_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000615/blk00000625 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk00000615/sig000016f4 ), + .A2(\blk00000003/blk00000615/sig000016f4 ), + .A3(\blk00000003/blk00000615/sig000016f4 ), + .CE(\blk00000003/blk00000615/sig000016fd ), + .CLK(clk), + .D(\blk00000003/sig000005ed ), + .Q(\blk00000003/blk00000615/sig000016fb ), + .Q15(\NLW_blk00000003/blk00000615/blk00000625_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000615/blk00000624 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk00000615/sig000016f4 ), + .A2(\blk00000003/blk00000615/sig000016f4 ), + .A3(\blk00000003/blk00000615/sig000016f4 ), + .CE(\blk00000003/blk00000615/sig000016fd ), + .CLK(clk), + .D(\blk00000003/sig000005ee ), + .Q(\blk00000003/blk00000615/sig000016fa ), + .Q15(\NLW_blk00000003/blk00000615/blk00000624_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000615/blk00000623 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk00000615/sig000016f4 ), + .A2(\blk00000003/blk00000615/sig000016f4 ), + .A3(\blk00000003/blk00000615/sig000016f4 ), + .CE(\blk00000003/blk00000615/sig000016fd ), + .CLK(clk), + .D(\blk00000003/sig000005ef ), + .Q(\blk00000003/blk00000615/sig000016f9 ), + .Q15(\NLW_blk00000003/blk00000615/blk00000623_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000615/blk00000622 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk00000615/sig000016f4 ), + .A2(\blk00000003/blk00000615/sig000016f4 ), + .A3(\blk00000003/blk00000615/sig000016f4 ), + .CE(\blk00000003/blk00000615/sig000016fd ), + .CLK(clk), + .D(\blk00000003/sig000005f0 ), + .Q(\blk00000003/blk00000615/sig000016f8 ), + .Q15(\NLW_blk00000003/blk00000615/blk00000622_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000615/blk00000621 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk00000615/sig000016f4 ), + .A2(\blk00000003/blk00000615/sig000016f4 ), + .A3(\blk00000003/blk00000615/sig000016f4 ), + .CE(\blk00000003/blk00000615/sig000016fd ), + .CLK(clk), + .D(\blk00000003/sig000005f1 ), + .Q(\blk00000003/blk00000615/sig000016f7 ), + .Q15(\NLW_blk00000003/blk00000615/blk00000621_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000615/blk00000620 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk00000615/sig000016f4 ), + .A2(\blk00000003/blk00000615/sig000016f4 ), + .A3(\blk00000003/blk00000615/sig000016f4 ), + .CE(\blk00000003/blk00000615/sig000016fd ), + .CLK(clk), + .D(\blk00000003/sig000005f2 ), + .Q(\blk00000003/blk00000615/sig000016f6 ), + .Q15(\NLW_blk00000003/blk00000615/blk00000620_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000615/blk0000061f ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk00000615/sig000016f4 ), + .A2(\blk00000003/blk00000615/sig000016f4 ), + .A3(\blk00000003/blk00000615/sig000016f4 ), + .CE(\blk00000003/blk00000615/sig000016fd ), + .CLK(clk), + .D(\blk00000003/sig000005f3 ), + .Q(\blk00000003/blk00000615/sig000016f5 ), + .Q15(\NLW_blk00000003/blk00000615/blk0000061f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615/blk0000061e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000615/sig000016fc ), + .Q(\blk00000003/sig0000063e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615/blk0000061d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000615/sig000016fb ), + .Q(\blk00000003/sig0000063f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615/blk0000061c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000615/sig000016fa ), + .Q(\blk00000003/sig00000640 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615/blk0000061b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000615/sig000016f9 ), + .Q(\blk00000003/sig00000641 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615/blk0000061a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000615/sig000016f8 ), + .Q(\blk00000003/sig00000642 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615/blk00000619 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000615/sig000016f7 ), + .Q(\blk00000003/sig00000643 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615/blk00000618 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000615/sig000016f6 ), + .Q(\blk00000003/sig00000644 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615/blk00000617 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000615/sig000016f5 ), + .Q(\blk00000003/sig00000645 ) + ); + GND \blk00000003/blk00000615/blk00000616 ( + .G(\blk00000003/blk00000615/sig000016f4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000628/blk0000063a ( + .I0(\blk00000003/sig000009f7 ), + .I1(ce), + .O(\blk00000003/blk00000628/sig0000171b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628/blk00000639 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000628/sig00001712 ), + .A2(\blk00000003/blk00000628/sig00001712 ), + .A3(\blk00000003/blk00000628/sig00001712 ), + .CE(\blk00000003/blk00000628/sig0000171b ), + .CLK(clk), + .D(\blk00000003/sig00000b73 ), + .Q(\blk00000003/blk00000628/sig0000171a ), + .Q15(\NLW_blk00000003/blk00000628/blk00000639_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628/blk00000638 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000628/sig00001712 ), + .A2(\blk00000003/blk00000628/sig00001712 ), + .A3(\blk00000003/blk00000628/sig00001712 ), + .CE(\blk00000003/blk00000628/sig0000171b ), + .CLK(clk), + .D(\blk00000003/sig00000b74 ), + .Q(\blk00000003/blk00000628/sig00001719 ), + .Q15(\NLW_blk00000003/blk00000628/blk00000638_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628/blk00000637 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000628/sig00001712 ), + .A2(\blk00000003/blk00000628/sig00001712 ), + .A3(\blk00000003/blk00000628/sig00001712 ), + .CE(\blk00000003/blk00000628/sig0000171b ), + .CLK(clk), + .D(\blk00000003/sig00000b75 ), + .Q(\blk00000003/blk00000628/sig00001718 ), + .Q15(\NLW_blk00000003/blk00000628/blk00000637_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628/blk00000636 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000628/sig00001712 ), + .A2(\blk00000003/blk00000628/sig00001712 ), + .A3(\blk00000003/blk00000628/sig00001712 ), + .CE(\blk00000003/blk00000628/sig0000171b ), + .CLK(clk), + .D(\blk00000003/sig00000b76 ), + .Q(\blk00000003/blk00000628/sig00001717 ), + .Q15(\NLW_blk00000003/blk00000628/blk00000636_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628/blk00000635 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000628/sig00001712 ), + .A2(\blk00000003/blk00000628/sig00001712 ), + .A3(\blk00000003/blk00000628/sig00001712 ), + .CE(\blk00000003/blk00000628/sig0000171b ), + .CLK(clk), + .D(\blk00000003/sig00000b77 ), + .Q(\blk00000003/blk00000628/sig00001716 ), + .Q15(\NLW_blk00000003/blk00000628/blk00000635_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628/blk00000634 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000628/sig00001712 ), + .A2(\blk00000003/blk00000628/sig00001712 ), + .A3(\blk00000003/blk00000628/sig00001712 ), + .CE(\blk00000003/blk00000628/sig0000171b ), + .CLK(clk), + .D(\blk00000003/sig00000b78 ), + .Q(\blk00000003/blk00000628/sig00001715 ), + .Q15(\NLW_blk00000003/blk00000628/blk00000634_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628/blk00000633 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000628/sig00001712 ), + .A2(\blk00000003/blk00000628/sig00001712 ), + .A3(\blk00000003/blk00000628/sig00001712 ), + .CE(\blk00000003/blk00000628/sig0000171b ), + .CLK(clk), + .D(\blk00000003/sig00000b79 ), + .Q(\blk00000003/blk00000628/sig00001714 ), + .Q15(\NLW_blk00000003/blk00000628/blk00000633_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628/blk00000632 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000628/sig00001712 ), + .A2(\blk00000003/blk00000628/sig00001712 ), + .A3(\blk00000003/blk00000628/sig00001712 ), + .CE(\blk00000003/blk00000628/sig0000171b ), + .CLK(clk), + .D(\blk00000003/sig00000b7a ), + .Q(\blk00000003/blk00000628/sig00001713 ), + .Q15(\NLW_blk00000003/blk00000628/blk00000632_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000628/blk00000631 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000628/sig0000171a ), + .Q(\blk00000003/sig00000636 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000628/blk00000630 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000628/sig00001719 ), + .Q(\blk00000003/sig00000637 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000628/blk0000062f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000628/sig00001718 ), + .Q(\blk00000003/sig00000638 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000628/blk0000062e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000628/sig00001717 ), + .Q(\blk00000003/sig00000639 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000628/blk0000062d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000628/sig00001716 ), + .Q(\blk00000003/sig0000063a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000628/blk0000062c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000628/sig00001715 ), + .Q(\blk00000003/sig0000063b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000628/blk0000062b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000628/sig00001714 ), + .Q(\blk00000003/sig0000063c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000628/blk0000062a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000628/sig00001713 ), + .Q(\blk00000003/sig0000063d ) + ); + GND \blk00000003/blk00000628/blk00000629 ( + .G(\blk00000003/blk00000628/sig00001712 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000063b/blk0000064d ( + .I0(\blk00000003/sig000009f9 ), + .I1(ce), + .O(\blk00000003/blk0000063b/sig00001739 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063b/blk0000064c ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000063b/sig00001730 ), + .A2(\blk00000003/blk0000063b/sig00001730 ), + .A3(\blk00000003/blk0000063b/sig00001730 ), + .CE(\blk00000003/blk0000063b/sig00001739 ), + .CLK(clk), + .D(\blk00000003/sig000006e0 ), + .Q(\blk00000003/blk0000063b/sig00001738 ), + .Q15(\NLW_blk00000003/blk0000063b/blk0000064c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063b/blk0000064b ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000063b/sig00001730 ), + .A2(\blk00000003/blk0000063b/sig00001730 ), + .A3(\blk00000003/blk0000063b/sig00001730 ), + .CE(\blk00000003/blk0000063b/sig00001739 ), + .CLK(clk), + .D(\blk00000003/sig000006e1 ), + .Q(\blk00000003/blk0000063b/sig00001737 ), + .Q15(\NLW_blk00000003/blk0000063b/blk0000064b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063b/blk0000064a ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000063b/sig00001730 ), + .A2(\blk00000003/blk0000063b/sig00001730 ), + .A3(\blk00000003/blk0000063b/sig00001730 ), + .CE(\blk00000003/blk0000063b/sig00001739 ), + .CLK(clk), + .D(\blk00000003/sig000006e2 ), + .Q(\blk00000003/blk0000063b/sig00001736 ), + .Q15(\NLW_blk00000003/blk0000063b/blk0000064a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063b/blk00000649 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000063b/sig00001730 ), + .A2(\blk00000003/blk0000063b/sig00001730 ), + .A3(\blk00000003/blk0000063b/sig00001730 ), + .CE(\blk00000003/blk0000063b/sig00001739 ), + .CLK(clk), + .D(\blk00000003/sig000006e3 ), + .Q(\blk00000003/blk0000063b/sig00001735 ), + .Q15(\NLW_blk00000003/blk0000063b/blk00000649_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063b/blk00000648 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000063b/sig00001730 ), + .A2(\blk00000003/blk0000063b/sig00001730 ), + .A3(\blk00000003/blk0000063b/sig00001730 ), + .CE(\blk00000003/blk0000063b/sig00001739 ), + .CLK(clk), + .D(\blk00000003/sig000006e4 ), + .Q(\blk00000003/blk0000063b/sig00001734 ), + .Q15(\NLW_blk00000003/blk0000063b/blk00000648_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063b/blk00000647 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000063b/sig00001730 ), + .A2(\blk00000003/blk0000063b/sig00001730 ), + .A3(\blk00000003/blk0000063b/sig00001730 ), + .CE(\blk00000003/blk0000063b/sig00001739 ), + .CLK(clk), + .D(\blk00000003/sig000006e5 ), + .Q(\blk00000003/blk0000063b/sig00001733 ), + .Q15(\NLW_blk00000003/blk0000063b/blk00000647_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063b/blk00000646 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000063b/sig00001730 ), + .A2(\blk00000003/blk0000063b/sig00001730 ), + .A3(\blk00000003/blk0000063b/sig00001730 ), + .CE(\blk00000003/blk0000063b/sig00001739 ), + .CLK(clk), + .D(\blk00000003/sig000006e6 ), + .Q(\blk00000003/blk0000063b/sig00001732 ), + .Q15(\NLW_blk00000003/blk0000063b/blk00000646_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063b/blk00000645 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000063b/sig00001730 ), + .A2(\blk00000003/blk0000063b/sig00001730 ), + .A3(\blk00000003/blk0000063b/sig00001730 ), + .CE(\blk00000003/blk0000063b/sig00001739 ), + .CLK(clk), + .D(\blk00000003/sig000006e7 ), + .Q(\blk00000003/blk0000063b/sig00001731 ), + .Q15(\NLW_blk00000003/blk0000063b/blk00000645_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b/blk00000644 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000063b/sig00001738 ), + .Q(\blk00000003/sig00000720 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b/blk00000643 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000063b/sig00001737 ), + .Q(\blk00000003/sig00000721 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b/blk00000642 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000063b/sig00001736 ), + .Q(\blk00000003/sig00000722 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b/blk00000641 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000063b/sig00001735 ), + .Q(\blk00000003/sig00000723 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b/blk00000640 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000063b/sig00001734 ), + .Q(\blk00000003/sig00000724 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b/blk0000063f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000063b/sig00001733 ), + .Q(\blk00000003/sig00000725 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b/blk0000063e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000063b/sig00001732 ), + .Q(\blk00000003/sig00000726 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b/blk0000063d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000063b/sig00001731 ), + .Q(\blk00000003/sig00000727 ) + ); + GND \blk00000003/blk0000063b/blk0000063c ( + .G(\blk00000003/blk0000063b/sig00001730 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000064e/blk00000660 ( + .I0(\blk00000003/sig000009f7 ), + .I1(ce), + .O(\blk00000003/blk0000064e/sig00001757 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e/blk0000065f ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk0000064e/sig0000174e ), + .A2(\blk00000003/blk0000064e/sig0000174e ), + .A3(\blk00000003/blk0000064e/sig0000174e ), + .CE(\blk00000003/blk0000064e/sig00001757 ), + .CLK(clk), + .D(\blk00000003/sig00000b7b ), + .Q(\blk00000003/blk0000064e/sig00001756 ), + .Q15(\NLW_blk00000003/blk0000064e/blk0000065f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e/blk0000065e ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk0000064e/sig0000174e ), + .A2(\blk00000003/blk0000064e/sig0000174e ), + .A3(\blk00000003/blk0000064e/sig0000174e ), + .CE(\blk00000003/blk0000064e/sig00001757 ), + .CLK(clk), + .D(\blk00000003/sig00000b7c ), + .Q(\blk00000003/blk0000064e/sig00001755 ), + .Q15(\NLW_blk00000003/blk0000064e/blk0000065e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e/blk0000065d ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk0000064e/sig0000174e ), + .A2(\blk00000003/blk0000064e/sig0000174e ), + .A3(\blk00000003/blk0000064e/sig0000174e ), + .CE(\blk00000003/blk0000064e/sig00001757 ), + .CLK(clk), + .D(\blk00000003/sig00000b7d ), + .Q(\blk00000003/blk0000064e/sig00001754 ), + .Q15(\NLW_blk00000003/blk0000064e/blk0000065d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e/blk0000065c ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk0000064e/sig0000174e ), + .A2(\blk00000003/blk0000064e/sig0000174e ), + .A3(\blk00000003/blk0000064e/sig0000174e ), + .CE(\blk00000003/blk0000064e/sig00001757 ), + .CLK(clk), + .D(\blk00000003/sig00000b7e ), + .Q(\blk00000003/blk0000064e/sig00001753 ), + .Q15(\NLW_blk00000003/blk0000064e/blk0000065c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e/blk0000065b ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk0000064e/sig0000174e ), + .A2(\blk00000003/blk0000064e/sig0000174e ), + .A3(\blk00000003/blk0000064e/sig0000174e ), + .CE(\blk00000003/blk0000064e/sig00001757 ), + .CLK(clk), + .D(\blk00000003/sig00000b7f ), + .Q(\blk00000003/blk0000064e/sig00001752 ), + .Q15(\NLW_blk00000003/blk0000064e/blk0000065b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e/blk0000065a ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk0000064e/sig0000174e ), + .A2(\blk00000003/blk0000064e/sig0000174e ), + .A3(\blk00000003/blk0000064e/sig0000174e ), + .CE(\blk00000003/blk0000064e/sig00001757 ), + .CLK(clk), + .D(\blk00000003/sig00000b80 ), + .Q(\blk00000003/blk0000064e/sig00001751 ), + .Q15(\NLW_blk00000003/blk0000064e/blk0000065a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e/blk00000659 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk0000064e/sig0000174e ), + .A2(\blk00000003/blk0000064e/sig0000174e ), + .A3(\blk00000003/blk0000064e/sig0000174e ), + .CE(\blk00000003/blk0000064e/sig00001757 ), + .CLK(clk), + .D(\blk00000003/sig00000b81 ), + .Q(\blk00000003/blk0000064e/sig00001750 ), + .Q15(\NLW_blk00000003/blk0000064e/blk00000659_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e/blk00000658 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk0000064e/sig0000174e ), + .A2(\blk00000003/blk0000064e/sig0000174e ), + .A3(\blk00000003/blk0000064e/sig0000174e ), + .CE(\blk00000003/blk0000064e/sig00001757 ), + .CLK(clk), + .D(\blk00000003/sig00000b82 ), + .Q(\blk00000003/blk0000064e/sig0000174f ), + .Q15(\NLW_blk00000003/blk0000064e/blk00000658_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064e/blk00000657 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000064e/sig00001756 ), + .Q(\blk00000003/sig00000718 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064e/blk00000656 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000064e/sig00001755 ), + .Q(\blk00000003/sig00000719 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064e/blk00000655 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000064e/sig00001754 ), + .Q(\blk00000003/sig0000071a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064e/blk00000654 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000064e/sig00001753 ), + .Q(\blk00000003/sig0000071b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064e/blk00000653 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000064e/sig00001752 ), + .Q(\blk00000003/sig0000071c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064e/blk00000652 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000064e/sig00001751 ), + .Q(\blk00000003/sig0000071d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064e/blk00000651 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000064e/sig00001750 ), + .Q(\blk00000003/sig0000071e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064e/blk00000650 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000064e/sig0000174f ), + .Q(\blk00000003/sig0000071f ) + ); + GND \blk00000003/blk0000064e/blk0000064f ( + .G(\blk00000003/blk0000064e/sig0000174e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000661/blk00000673 ( + .I0(\blk00000003/sig00000a06 ), + .I1(ce), + .O(\blk00000003/blk00000661/sig00001775 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000661/blk00000672 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000661/sig0000176c ), + .A2(\blk00000003/blk00000661/sig0000176c ), + .A3(\blk00000003/blk00000661/sig0000176c ), + .CE(\blk00000003/blk00000661/sig00001775 ), + .CLK(clk), + .D(\blk00000003/sig0000059a ), + .Q(\blk00000003/blk00000661/sig00001774 ), + .Q15(\NLW_blk00000003/blk00000661/blk00000672_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000661/blk00000671 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000661/sig0000176c ), + .A2(\blk00000003/blk00000661/sig0000176c ), + .A3(\blk00000003/blk00000661/sig0000176c ), + .CE(\blk00000003/blk00000661/sig00001775 ), + .CLK(clk), + .D(\blk00000003/sig0000059b ), + .Q(\blk00000003/blk00000661/sig00001773 ), + .Q15(\NLW_blk00000003/blk00000661/blk00000671_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000661/blk00000670 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000661/sig0000176c ), + .A2(\blk00000003/blk00000661/sig0000176c ), + .A3(\blk00000003/blk00000661/sig0000176c ), + .CE(\blk00000003/blk00000661/sig00001775 ), + .CLK(clk), + .D(\blk00000003/sig0000059c ), + .Q(\blk00000003/blk00000661/sig00001772 ), + .Q15(\NLW_blk00000003/blk00000661/blk00000670_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000661/blk0000066f ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000661/sig0000176c ), + .A2(\blk00000003/blk00000661/sig0000176c ), + .A3(\blk00000003/blk00000661/sig0000176c ), + .CE(\blk00000003/blk00000661/sig00001775 ), + .CLK(clk), + .D(\blk00000003/sig0000059d ), + .Q(\blk00000003/blk00000661/sig00001771 ), + .Q15(\NLW_blk00000003/blk00000661/blk0000066f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000661/blk0000066e ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000661/sig0000176c ), + .A2(\blk00000003/blk00000661/sig0000176c ), + .A3(\blk00000003/blk00000661/sig0000176c ), + .CE(\blk00000003/blk00000661/sig00001775 ), + .CLK(clk), + .D(\blk00000003/sig0000059e ), + .Q(\blk00000003/blk00000661/sig00001770 ), + .Q15(\NLW_blk00000003/blk00000661/blk0000066e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000661/blk0000066d ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000661/sig0000176c ), + .A2(\blk00000003/blk00000661/sig0000176c ), + .A3(\blk00000003/blk00000661/sig0000176c ), + .CE(\blk00000003/blk00000661/sig00001775 ), + .CLK(clk), + .D(\blk00000003/sig0000059f ), + .Q(\blk00000003/blk00000661/sig0000176f ), + .Q15(\NLW_blk00000003/blk00000661/blk0000066d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000661/blk0000066c ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000661/sig0000176c ), + .A2(\blk00000003/blk00000661/sig0000176c ), + .A3(\blk00000003/blk00000661/sig0000176c ), + .CE(\blk00000003/blk00000661/sig00001775 ), + .CLK(clk), + .D(\blk00000003/sig000005a0 ), + .Q(\blk00000003/blk00000661/sig0000176e ), + .Q15(\NLW_blk00000003/blk00000661/blk0000066c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000661/blk0000066b ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000661/sig0000176c ), + .A2(\blk00000003/blk00000661/sig0000176c ), + .A3(\blk00000003/blk00000661/sig0000176c ), + .CE(\blk00000003/blk00000661/sig00001775 ), + .CLK(clk), + .D(\blk00000003/sig000005a1 ), + .Q(\blk00000003/blk00000661/sig0000176d ), + .Q15(\NLW_blk00000003/blk00000661/blk0000066b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661/blk0000066a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000661/sig00001774 ), + .Q(\blk00000003/sig000005ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661/blk00000669 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000661/sig00001773 ), + .Q(\blk00000003/sig000005ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661/blk00000668 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000661/sig00001772 ), + .Q(\blk00000003/sig000005ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661/blk00000667 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000661/sig00001771 ), + .Q(\blk00000003/sig000005ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661/blk00000666 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000661/sig00001770 ), + .Q(\blk00000003/sig000005f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661/blk00000665 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000661/sig0000176f ), + .Q(\blk00000003/sig000005f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661/blk00000664 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000661/sig0000176e ), + .Q(\blk00000003/sig000005f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661/blk00000663 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000661/sig0000176d ), + .Q(\blk00000003/sig000005f3 ) + ); + GND \blk00000003/blk00000661/blk00000662 ( + .G(\blk00000003/blk00000661/sig0000176c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000674/blk00000686 ( + .I0(\blk00000003/sig00000a03 ), + .I1(ce), + .O(\blk00000003/blk00000674/sig00001793 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674/blk00000685 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000674/sig0000178a ), + .A2(\blk00000003/blk00000674/sig0000178a ), + .A3(\blk00000003/blk00000674/sig0000178a ), + .CE(\blk00000003/blk00000674/sig00001793 ), + .CLK(clk), + .D(\blk00000003/sig00000b83 ), + .Q(\blk00000003/blk00000674/sig00001792 ), + .Q15(\NLW_blk00000003/blk00000674/blk00000685_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674/blk00000684 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000674/sig0000178a ), + .A2(\blk00000003/blk00000674/sig0000178a ), + .A3(\blk00000003/blk00000674/sig0000178a ), + .CE(\blk00000003/blk00000674/sig00001793 ), + .CLK(clk), + .D(\blk00000003/sig00000b84 ), + .Q(\blk00000003/blk00000674/sig00001791 ), + .Q15(\NLW_blk00000003/blk00000674/blk00000684_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674/blk00000683 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000674/sig0000178a ), + .A2(\blk00000003/blk00000674/sig0000178a ), + .A3(\blk00000003/blk00000674/sig0000178a ), + .CE(\blk00000003/blk00000674/sig00001793 ), + .CLK(clk), + .D(\blk00000003/sig00000b85 ), + .Q(\blk00000003/blk00000674/sig00001790 ), + .Q15(\NLW_blk00000003/blk00000674/blk00000683_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674/blk00000682 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000674/sig0000178a ), + .A2(\blk00000003/blk00000674/sig0000178a ), + .A3(\blk00000003/blk00000674/sig0000178a ), + .CE(\blk00000003/blk00000674/sig00001793 ), + .CLK(clk), + .D(\blk00000003/sig00000b86 ), + .Q(\blk00000003/blk00000674/sig0000178f ), + .Q15(\NLW_blk00000003/blk00000674/blk00000682_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674/blk00000681 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000674/sig0000178a ), + .A2(\blk00000003/blk00000674/sig0000178a ), + .A3(\blk00000003/blk00000674/sig0000178a ), + .CE(\blk00000003/blk00000674/sig00001793 ), + .CLK(clk), + .D(\blk00000003/sig00000b87 ), + .Q(\blk00000003/blk00000674/sig0000178e ), + .Q15(\NLW_blk00000003/blk00000674/blk00000681_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674/blk00000680 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000674/sig0000178a ), + .A2(\blk00000003/blk00000674/sig0000178a ), + .A3(\blk00000003/blk00000674/sig0000178a ), + .CE(\blk00000003/blk00000674/sig00001793 ), + .CLK(clk), + .D(\blk00000003/sig00000b88 ), + .Q(\blk00000003/blk00000674/sig0000178d ), + .Q15(\NLW_blk00000003/blk00000674/blk00000680_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674/blk0000067f ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000674/sig0000178a ), + .A2(\blk00000003/blk00000674/sig0000178a ), + .A3(\blk00000003/blk00000674/sig0000178a ), + .CE(\blk00000003/blk00000674/sig00001793 ), + .CLK(clk), + .D(\blk00000003/sig00000b89 ), + .Q(\blk00000003/blk00000674/sig0000178c ), + .Q15(\NLW_blk00000003/blk00000674/blk0000067f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674/blk0000067e ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000674/sig0000178a ), + .A2(\blk00000003/blk00000674/sig0000178a ), + .A3(\blk00000003/blk00000674/sig0000178a ), + .CE(\blk00000003/blk00000674/sig00001793 ), + .CLK(clk), + .D(\blk00000003/sig00000b8a ), + .Q(\blk00000003/blk00000674/sig0000178b ), + .Q15(\NLW_blk00000003/blk00000674/blk0000067e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674/blk0000067d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000674/sig00001792 ), + .Q(\blk00000003/sig000005e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674/blk0000067c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000674/sig00001791 ), + .Q(\blk00000003/sig000005e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674/blk0000067b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000674/sig00001790 ), + .Q(\blk00000003/sig000005e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674/blk0000067a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000674/sig0000178f ), + .Q(\blk00000003/sig000005e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674/blk00000679 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000674/sig0000178e ), + .Q(\blk00000003/sig000005e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674/blk00000678 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000674/sig0000178d ), + .Q(\blk00000003/sig000005e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674/blk00000677 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000674/sig0000178c ), + .Q(\blk00000003/sig000005ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674/blk00000676 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000674/sig0000178b ), + .Q(\blk00000003/sig000005eb ) + ); + GND \blk00000003/blk00000674/blk00000675 ( + .G(\blk00000003/blk00000674/sig0000178a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000687/blk00000699 ( + .I0(\blk00000003/sig00000a06 ), + .I1(ce), + .O(\blk00000003/blk00000687/sig000017b1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687/blk00000698 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000687/sig000017a8 ), + .A2(\blk00000003/blk00000687/sig000017a8 ), + .A3(\blk00000003/blk00000687/sig000017a8 ), + .CE(\blk00000003/blk00000687/sig000017b1 ), + .CLK(clk), + .D(\blk00000003/sig000006a0 ), + .Q(\blk00000003/blk00000687/sig000017b0 ), + .Q15(\NLW_blk00000003/blk00000687/blk00000698_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687/blk00000697 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000687/sig000017a8 ), + .A2(\blk00000003/blk00000687/sig000017a8 ), + .A3(\blk00000003/blk00000687/sig000017a8 ), + .CE(\blk00000003/blk00000687/sig000017b1 ), + .CLK(clk), + .D(\blk00000003/sig000006a1 ), + .Q(\blk00000003/blk00000687/sig000017af ), + .Q15(\NLW_blk00000003/blk00000687/blk00000697_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687/blk00000696 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000687/sig000017a8 ), + .A2(\blk00000003/blk00000687/sig000017a8 ), + .A3(\blk00000003/blk00000687/sig000017a8 ), + .CE(\blk00000003/blk00000687/sig000017b1 ), + .CLK(clk), + .D(\blk00000003/sig000006a2 ), + .Q(\blk00000003/blk00000687/sig000017ae ), + .Q15(\NLW_blk00000003/blk00000687/blk00000696_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687/blk00000695 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000687/sig000017a8 ), + .A2(\blk00000003/blk00000687/sig000017a8 ), + .A3(\blk00000003/blk00000687/sig000017a8 ), + .CE(\blk00000003/blk00000687/sig000017b1 ), + .CLK(clk), + .D(\blk00000003/sig000006a3 ), + .Q(\blk00000003/blk00000687/sig000017ad ), + .Q15(\NLW_blk00000003/blk00000687/blk00000695_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687/blk00000694 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000687/sig000017a8 ), + .A2(\blk00000003/blk00000687/sig000017a8 ), + .A3(\blk00000003/blk00000687/sig000017a8 ), + .CE(\blk00000003/blk00000687/sig000017b1 ), + .CLK(clk), + .D(\blk00000003/sig000006a4 ), + .Q(\blk00000003/blk00000687/sig000017ac ), + .Q15(\NLW_blk00000003/blk00000687/blk00000694_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687/blk00000693 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000687/sig000017a8 ), + .A2(\blk00000003/blk00000687/sig000017a8 ), + .A3(\blk00000003/blk00000687/sig000017a8 ), + .CE(\blk00000003/blk00000687/sig000017b1 ), + .CLK(clk), + .D(\blk00000003/sig000006a5 ), + .Q(\blk00000003/blk00000687/sig000017ab ), + .Q15(\NLW_blk00000003/blk00000687/blk00000693_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687/blk00000692 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000687/sig000017a8 ), + .A2(\blk00000003/blk00000687/sig000017a8 ), + .A3(\blk00000003/blk00000687/sig000017a8 ), + .CE(\blk00000003/blk00000687/sig000017b1 ), + .CLK(clk), + .D(\blk00000003/sig000006a6 ), + .Q(\blk00000003/blk00000687/sig000017aa ), + .Q15(\NLW_blk00000003/blk00000687/blk00000692_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687/blk00000691 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000687/sig000017a8 ), + .A2(\blk00000003/blk00000687/sig000017a8 ), + .A3(\blk00000003/blk00000687/sig000017a8 ), + .CE(\blk00000003/blk00000687/sig000017b1 ), + .CLK(clk), + .D(\blk00000003/sig000006a7 ), + .Q(\blk00000003/blk00000687/sig000017a9 ), + .Q15(\NLW_blk00000003/blk00000687/blk00000691_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687/blk00000690 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000687/sig000017b0 ), + .Q(\blk00000003/sig000006e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687/blk0000068f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000687/sig000017af ), + .Q(\blk00000003/sig000006e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687/blk0000068e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000687/sig000017ae ), + .Q(\blk00000003/sig000006e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687/blk0000068d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000687/sig000017ad ), + .Q(\blk00000003/sig000006e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687/blk0000068c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000687/sig000017ac ), + .Q(\blk00000003/sig000006e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687/blk0000068b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000687/sig000017ab ), + .Q(\blk00000003/sig000006e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687/blk0000068a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000687/sig000017aa ), + .Q(\blk00000003/sig000006e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687/blk00000689 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000687/sig000017a9 ), + .Q(\blk00000003/sig000006e7 ) + ); + GND \blk00000003/blk00000687/blk00000688 ( + .G(\blk00000003/blk00000687/sig000017a8 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000069a/blk000006ac ( + .I0(\blk00000003/sig00000a03 ), + .I1(ce), + .O(\blk00000003/blk0000069a/sig000017cf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a/blk000006ab ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk0000069a/sig000017c6 ), + .A2(\blk00000003/blk0000069a/sig000017c6 ), + .A3(\blk00000003/blk0000069a/sig000017c6 ), + .CE(\blk00000003/blk0000069a/sig000017cf ), + .CLK(clk), + .D(\blk00000003/sig00000b8b ), + .Q(\blk00000003/blk0000069a/sig000017ce ), + .Q15(\NLW_blk00000003/blk0000069a/blk000006ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a/blk000006aa ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk0000069a/sig000017c6 ), + .A2(\blk00000003/blk0000069a/sig000017c6 ), + .A3(\blk00000003/blk0000069a/sig000017c6 ), + .CE(\blk00000003/blk0000069a/sig000017cf ), + .CLK(clk), + .D(\blk00000003/sig00000b8c ), + .Q(\blk00000003/blk0000069a/sig000017cd ), + .Q15(\NLW_blk00000003/blk0000069a/blk000006aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a/blk000006a9 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk0000069a/sig000017c6 ), + .A2(\blk00000003/blk0000069a/sig000017c6 ), + .A3(\blk00000003/blk0000069a/sig000017c6 ), + .CE(\blk00000003/blk0000069a/sig000017cf ), + .CLK(clk), + .D(\blk00000003/sig00000b8d ), + .Q(\blk00000003/blk0000069a/sig000017cc ), + .Q15(\NLW_blk00000003/blk0000069a/blk000006a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a/blk000006a8 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk0000069a/sig000017c6 ), + .A2(\blk00000003/blk0000069a/sig000017c6 ), + .A3(\blk00000003/blk0000069a/sig000017c6 ), + .CE(\blk00000003/blk0000069a/sig000017cf ), + .CLK(clk), + .D(\blk00000003/sig00000b8e ), + .Q(\blk00000003/blk0000069a/sig000017cb ), + .Q15(\NLW_blk00000003/blk0000069a/blk000006a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a/blk000006a7 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk0000069a/sig000017c6 ), + .A2(\blk00000003/blk0000069a/sig000017c6 ), + .A3(\blk00000003/blk0000069a/sig000017c6 ), + .CE(\blk00000003/blk0000069a/sig000017cf ), + .CLK(clk), + .D(\blk00000003/sig00000b8f ), + .Q(\blk00000003/blk0000069a/sig000017ca ), + .Q15(\NLW_blk00000003/blk0000069a/blk000006a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a/blk000006a6 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk0000069a/sig000017c6 ), + .A2(\blk00000003/blk0000069a/sig000017c6 ), + .A3(\blk00000003/blk0000069a/sig000017c6 ), + .CE(\blk00000003/blk0000069a/sig000017cf ), + .CLK(clk), + .D(\blk00000003/sig00000b90 ), + .Q(\blk00000003/blk0000069a/sig000017c9 ), + .Q15(\NLW_blk00000003/blk0000069a/blk000006a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a/blk000006a5 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk0000069a/sig000017c6 ), + .A2(\blk00000003/blk0000069a/sig000017c6 ), + .A3(\blk00000003/blk0000069a/sig000017c6 ), + .CE(\blk00000003/blk0000069a/sig000017cf ), + .CLK(clk), + .D(\blk00000003/sig00000b91 ), + .Q(\blk00000003/blk0000069a/sig000017c8 ), + .Q15(\NLW_blk00000003/blk0000069a/blk000006a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a/blk000006a4 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk0000069a/sig000017c6 ), + .A2(\blk00000003/blk0000069a/sig000017c6 ), + .A3(\blk00000003/blk0000069a/sig000017c6 ), + .CE(\blk00000003/blk0000069a/sig000017cf ), + .CLK(clk), + .D(\blk00000003/sig00000b92 ), + .Q(\blk00000003/blk0000069a/sig000017c7 ), + .Q15(\NLW_blk00000003/blk0000069a/blk000006a4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a/blk000006a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000069a/sig000017ce ), + .Q(\blk00000003/sig000006d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a/blk000006a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000069a/sig000017cd ), + .Q(\blk00000003/sig000006d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a/blk000006a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000069a/sig000017cc ), + .Q(\blk00000003/sig000006da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a/blk000006a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000069a/sig000017cb ), + .Q(\blk00000003/sig000006db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a/blk0000069f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000069a/sig000017ca ), + .Q(\blk00000003/sig000006dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a/blk0000069e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000069a/sig000017c9 ), + .Q(\blk00000003/sig000006dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a/blk0000069d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000069a/sig000017c8 ), + .Q(\blk00000003/sig000006de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a/blk0000069c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000069a/sig000017c7 ), + .Q(\blk00000003/sig000006df ) + ); + GND \blk00000003/blk0000069a/blk0000069b ( + .G(\blk00000003/blk0000069a/sig000017c6 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000006ad/blk000006bf ( + .I0(\blk00000003/sig00000a09 ), + .I1(ce), + .O(\blk00000003/blk000006ad/sig000017ed ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad/blk000006be ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006ad/sig000017e4 ), + .A2(\blk00000003/blk000006ad/sig000017e4 ), + .A3(\blk00000003/blk000006ad/sig000017e4 ), + .CE(\blk00000003/blk000006ad/sig000017ed ), + .CLK(clk), + .D(\blk00000003/sig00000548 ), + .Q(\blk00000003/blk000006ad/sig000017ec ), + .Q15(\NLW_blk00000003/blk000006ad/blk000006be_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad/blk000006bd ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006ad/sig000017e4 ), + .A2(\blk00000003/blk000006ad/sig000017e4 ), + .A3(\blk00000003/blk000006ad/sig000017e4 ), + .CE(\blk00000003/blk000006ad/sig000017ed ), + .CLK(clk), + .D(\blk00000003/sig00000549 ), + .Q(\blk00000003/blk000006ad/sig000017eb ), + .Q15(\NLW_blk00000003/blk000006ad/blk000006bd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad/blk000006bc ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006ad/sig000017e4 ), + .A2(\blk00000003/blk000006ad/sig000017e4 ), + .A3(\blk00000003/blk000006ad/sig000017e4 ), + .CE(\blk00000003/blk000006ad/sig000017ed ), + .CLK(clk), + .D(\blk00000003/sig0000054a ), + .Q(\blk00000003/blk000006ad/sig000017ea ), + .Q15(\NLW_blk00000003/blk000006ad/blk000006bc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad/blk000006bb ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006ad/sig000017e4 ), + .A2(\blk00000003/blk000006ad/sig000017e4 ), + .A3(\blk00000003/blk000006ad/sig000017e4 ), + .CE(\blk00000003/blk000006ad/sig000017ed ), + .CLK(clk), + .D(\blk00000003/sig0000054b ), + .Q(\blk00000003/blk000006ad/sig000017e9 ), + .Q15(\NLW_blk00000003/blk000006ad/blk000006bb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad/blk000006ba ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006ad/sig000017e4 ), + .A2(\blk00000003/blk000006ad/sig000017e4 ), + .A3(\blk00000003/blk000006ad/sig000017e4 ), + .CE(\blk00000003/blk000006ad/sig000017ed ), + .CLK(clk), + .D(\blk00000003/sig0000054c ), + .Q(\blk00000003/blk000006ad/sig000017e8 ), + .Q15(\NLW_blk00000003/blk000006ad/blk000006ba_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad/blk000006b9 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006ad/sig000017e4 ), + .A2(\blk00000003/blk000006ad/sig000017e4 ), + .A3(\blk00000003/blk000006ad/sig000017e4 ), + .CE(\blk00000003/blk000006ad/sig000017ed ), + .CLK(clk), + .D(\blk00000003/sig0000054d ), + .Q(\blk00000003/blk000006ad/sig000017e7 ), + .Q15(\NLW_blk00000003/blk000006ad/blk000006b9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad/blk000006b8 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006ad/sig000017e4 ), + .A2(\blk00000003/blk000006ad/sig000017e4 ), + .A3(\blk00000003/blk000006ad/sig000017e4 ), + .CE(\blk00000003/blk000006ad/sig000017ed ), + .CLK(clk), + .D(\blk00000003/sig0000054e ), + .Q(\blk00000003/blk000006ad/sig000017e6 ), + .Q15(\NLW_blk00000003/blk000006ad/blk000006b8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad/blk000006b7 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006ad/sig000017e4 ), + .A2(\blk00000003/blk000006ad/sig000017e4 ), + .A3(\blk00000003/blk000006ad/sig000017e4 ), + .CE(\blk00000003/blk000006ad/sig000017ed ), + .CLK(clk), + .D(\blk00000003/sig0000054f ), + .Q(\blk00000003/blk000006ad/sig000017e5 ), + .Q15(\NLW_blk00000003/blk000006ad/blk000006b7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad/blk000006b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006ad/sig000017ec ), + .Q(\blk00000003/sig0000059a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad/blk000006b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006ad/sig000017eb ), + .Q(\blk00000003/sig0000059b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad/blk000006b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006ad/sig000017ea ), + .Q(\blk00000003/sig0000059c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad/blk000006b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006ad/sig000017e9 ), + .Q(\blk00000003/sig0000059d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad/blk000006b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006ad/sig000017e8 ), + .Q(\blk00000003/sig0000059e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad/blk000006b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006ad/sig000017e7 ), + .Q(\blk00000003/sig0000059f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad/blk000006b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006ad/sig000017e6 ), + .Q(\blk00000003/sig000005a0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad/blk000006af ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006ad/sig000017e5 ), + .Q(\blk00000003/sig000005a1 ) + ); + GND \blk00000003/blk000006ad/blk000006ae ( + .G(\blk00000003/blk000006ad/sig000017e4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000006c0/blk000006d2 ( + .I0(\blk00000003/sig00000a0a ), + .I1(ce), + .O(\blk00000003/blk000006c0/sig0000180b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0/blk000006d1 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006c0/sig00001802 ), + .A2(\blk00000003/blk000006c0/sig00001802 ), + .A3(\blk00000003/blk000006c0/sig00001802 ), + .CE(\blk00000003/blk000006c0/sig0000180b ), + .CLK(clk), + .D(\blk00000003/sig00000b93 ), + .Q(\blk00000003/blk000006c0/sig0000180a ), + .Q15(\NLW_blk00000003/blk000006c0/blk000006d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0/blk000006d0 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006c0/sig00001802 ), + .A2(\blk00000003/blk000006c0/sig00001802 ), + .A3(\blk00000003/blk000006c0/sig00001802 ), + .CE(\blk00000003/blk000006c0/sig0000180b ), + .CLK(clk), + .D(\blk00000003/sig00000b94 ), + .Q(\blk00000003/blk000006c0/sig00001809 ), + .Q15(\NLW_blk00000003/blk000006c0/blk000006d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0/blk000006cf ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006c0/sig00001802 ), + .A2(\blk00000003/blk000006c0/sig00001802 ), + .A3(\blk00000003/blk000006c0/sig00001802 ), + .CE(\blk00000003/blk000006c0/sig0000180b ), + .CLK(clk), + .D(\blk00000003/sig00000b95 ), + .Q(\blk00000003/blk000006c0/sig00001808 ), + .Q15(\NLW_blk00000003/blk000006c0/blk000006cf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0/blk000006ce ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006c0/sig00001802 ), + .A2(\blk00000003/blk000006c0/sig00001802 ), + .A3(\blk00000003/blk000006c0/sig00001802 ), + .CE(\blk00000003/blk000006c0/sig0000180b ), + .CLK(clk), + .D(\blk00000003/sig00000b96 ), + .Q(\blk00000003/blk000006c0/sig00001807 ), + .Q15(\NLW_blk00000003/blk000006c0/blk000006ce_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0/blk000006cd ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006c0/sig00001802 ), + .A2(\blk00000003/blk000006c0/sig00001802 ), + .A3(\blk00000003/blk000006c0/sig00001802 ), + .CE(\blk00000003/blk000006c0/sig0000180b ), + .CLK(clk), + .D(\blk00000003/sig00000b97 ), + .Q(\blk00000003/blk000006c0/sig00001806 ), + .Q15(\NLW_blk00000003/blk000006c0/blk000006cd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0/blk000006cc ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006c0/sig00001802 ), + .A2(\blk00000003/blk000006c0/sig00001802 ), + .A3(\blk00000003/blk000006c0/sig00001802 ), + .CE(\blk00000003/blk000006c0/sig0000180b ), + .CLK(clk), + .D(\blk00000003/sig00000b98 ), + .Q(\blk00000003/blk000006c0/sig00001805 ), + .Q15(\NLW_blk00000003/blk000006c0/blk000006cc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0/blk000006cb ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006c0/sig00001802 ), + .A2(\blk00000003/blk000006c0/sig00001802 ), + .A3(\blk00000003/blk000006c0/sig00001802 ), + .CE(\blk00000003/blk000006c0/sig0000180b ), + .CLK(clk), + .D(\blk00000003/sig00000b99 ), + .Q(\blk00000003/blk000006c0/sig00001804 ), + .Q15(\NLW_blk00000003/blk000006c0/blk000006cb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0/blk000006ca ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006c0/sig00001802 ), + .A2(\blk00000003/blk000006c0/sig00001802 ), + .A3(\blk00000003/blk000006c0/sig00001802 ), + .CE(\blk00000003/blk000006c0/sig0000180b ), + .CLK(clk), + .D(\blk00000003/sig00000b9a ), + .Q(\blk00000003/blk000006c0/sig00001803 ), + .Q15(\NLW_blk00000003/blk000006c0/blk000006ca_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0/blk000006c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006c0/sig0000180a ), + .Q(\blk00000003/sig00000592 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0/blk000006c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006c0/sig00001809 ), + .Q(\blk00000003/sig00000593 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0/blk000006c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006c0/sig00001808 ), + .Q(\blk00000003/sig00000594 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0/blk000006c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006c0/sig00001807 ), + .Q(\blk00000003/sig00000595 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0/blk000006c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006c0/sig00001806 ), + .Q(\blk00000003/sig00000596 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0/blk000006c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006c0/sig00001805 ), + .Q(\blk00000003/sig00000597 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0/blk000006c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006c0/sig00001804 ), + .Q(\blk00000003/sig00000598 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0/blk000006c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006c0/sig00001803 ), + .Q(\blk00000003/sig00000599 ) + ); + GND \blk00000003/blk000006c0/blk000006c1 ( + .G(\blk00000003/blk000006c0/sig00001802 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000006d3/blk000006e5 ( + .I0(\blk00000003/sig00000a09 ), + .I1(ce), + .O(\blk00000003/blk000006d3/sig00001829 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3/blk000006e4 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006d3/sig00001820 ), + .A2(\blk00000003/blk000006d3/sig00001820 ), + .A3(\blk00000003/blk000006d3/sig00001820 ), + .CE(\blk00000003/blk000006d3/sig00001829 ), + .CLK(clk), + .D(\blk00000003/sig00000660 ), + .Q(\blk00000003/blk000006d3/sig00001828 ), + .Q15(\NLW_blk00000003/blk000006d3/blk000006e4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3/blk000006e3 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006d3/sig00001820 ), + .A2(\blk00000003/blk000006d3/sig00001820 ), + .A3(\blk00000003/blk000006d3/sig00001820 ), + .CE(\blk00000003/blk000006d3/sig00001829 ), + .CLK(clk), + .D(\blk00000003/sig00000661 ), + .Q(\blk00000003/blk000006d3/sig00001827 ), + .Q15(\NLW_blk00000003/blk000006d3/blk000006e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3/blk000006e2 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006d3/sig00001820 ), + .A2(\blk00000003/blk000006d3/sig00001820 ), + .A3(\blk00000003/blk000006d3/sig00001820 ), + .CE(\blk00000003/blk000006d3/sig00001829 ), + .CLK(clk), + .D(\blk00000003/sig00000662 ), + .Q(\blk00000003/blk000006d3/sig00001826 ), + .Q15(\NLW_blk00000003/blk000006d3/blk000006e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3/blk000006e1 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006d3/sig00001820 ), + .A2(\blk00000003/blk000006d3/sig00001820 ), + .A3(\blk00000003/blk000006d3/sig00001820 ), + .CE(\blk00000003/blk000006d3/sig00001829 ), + .CLK(clk), + .D(\blk00000003/sig00000663 ), + .Q(\blk00000003/blk000006d3/sig00001825 ), + .Q15(\NLW_blk00000003/blk000006d3/blk000006e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3/blk000006e0 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006d3/sig00001820 ), + .A2(\blk00000003/blk000006d3/sig00001820 ), + .A3(\blk00000003/blk000006d3/sig00001820 ), + .CE(\blk00000003/blk000006d3/sig00001829 ), + .CLK(clk), + .D(\blk00000003/sig00000664 ), + .Q(\blk00000003/blk000006d3/sig00001824 ), + .Q15(\NLW_blk00000003/blk000006d3/blk000006e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3/blk000006df ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006d3/sig00001820 ), + .A2(\blk00000003/blk000006d3/sig00001820 ), + .A3(\blk00000003/blk000006d3/sig00001820 ), + .CE(\blk00000003/blk000006d3/sig00001829 ), + .CLK(clk), + .D(\blk00000003/sig00000665 ), + .Q(\blk00000003/blk000006d3/sig00001823 ), + .Q15(\NLW_blk00000003/blk000006d3/blk000006df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3/blk000006de ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006d3/sig00001820 ), + .A2(\blk00000003/blk000006d3/sig00001820 ), + .A3(\blk00000003/blk000006d3/sig00001820 ), + .CE(\blk00000003/blk000006d3/sig00001829 ), + .CLK(clk), + .D(\blk00000003/sig00000666 ), + .Q(\blk00000003/blk000006d3/sig00001822 ), + .Q15(\NLW_blk00000003/blk000006d3/blk000006de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3/blk000006dd ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006d3/sig00001820 ), + .A2(\blk00000003/blk000006d3/sig00001820 ), + .A3(\blk00000003/blk000006d3/sig00001820 ), + .CE(\blk00000003/blk000006d3/sig00001829 ), + .CLK(clk), + .D(\blk00000003/sig00000667 ), + .Q(\blk00000003/blk000006d3/sig00001821 ), + .Q15(\NLW_blk00000003/blk000006d3/blk000006dd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3/blk000006dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006d3/sig00001828 ), + .Q(\blk00000003/sig000006a0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3/blk000006db ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006d3/sig00001827 ), + .Q(\blk00000003/sig000006a1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3/blk000006da ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006d3/sig00001826 ), + .Q(\blk00000003/sig000006a2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3/blk000006d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006d3/sig00001825 ), + .Q(\blk00000003/sig000006a3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3/blk000006d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006d3/sig00001824 ), + .Q(\blk00000003/sig000006a4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3/blk000006d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006d3/sig00001823 ), + .Q(\blk00000003/sig000006a5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3/blk000006d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006d3/sig00001822 ), + .Q(\blk00000003/sig000006a6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3/blk000006d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006d3/sig00001821 ), + .Q(\blk00000003/sig000006a7 ) + ); + GND \blk00000003/blk000006d3/blk000006d4 ( + .G(\blk00000003/blk000006d3/sig00001820 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000006e6/blk000006f8 ( + .I0(\blk00000003/sig00000a0a ), + .I1(ce), + .O(\blk00000003/blk000006e6/sig00001847 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6/blk000006f7 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006e6/sig0000183e ), + .A2(\blk00000003/blk000006e6/sig0000183e ), + .A3(\blk00000003/blk000006e6/sig0000183e ), + .CE(\blk00000003/blk000006e6/sig00001847 ), + .CLK(clk), + .D(\blk00000003/sig00000b9b ), + .Q(\blk00000003/blk000006e6/sig00001846 ), + .Q15(\NLW_blk00000003/blk000006e6/blk000006f7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6/blk000006f6 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006e6/sig0000183e ), + .A2(\blk00000003/blk000006e6/sig0000183e ), + .A3(\blk00000003/blk000006e6/sig0000183e ), + .CE(\blk00000003/blk000006e6/sig00001847 ), + .CLK(clk), + .D(\blk00000003/sig00000b9c ), + .Q(\blk00000003/blk000006e6/sig00001845 ), + .Q15(\NLW_blk00000003/blk000006e6/blk000006f6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6/blk000006f5 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006e6/sig0000183e ), + .A2(\blk00000003/blk000006e6/sig0000183e ), + .A3(\blk00000003/blk000006e6/sig0000183e ), + .CE(\blk00000003/blk000006e6/sig00001847 ), + .CLK(clk), + .D(\blk00000003/sig00000b9d ), + .Q(\blk00000003/blk000006e6/sig00001844 ), + .Q15(\NLW_blk00000003/blk000006e6/blk000006f5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6/blk000006f4 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006e6/sig0000183e ), + .A2(\blk00000003/blk000006e6/sig0000183e ), + .A3(\blk00000003/blk000006e6/sig0000183e ), + .CE(\blk00000003/blk000006e6/sig00001847 ), + .CLK(clk), + .D(\blk00000003/sig00000b9e ), + .Q(\blk00000003/blk000006e6/sig00001843 ), + .Q15(\NLW_blk00000003/blk000006e6/blk000006f4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6/blk000006f3 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006e6/sig0000183e ), + .A2(\blk00000003/blk000006e6/sig0000183e ), + .A3(\blk00000003/blk000006e6/sig0000183e ), + .CE(\blk00000003/blk000006e6/sig00001847 ), + .CLK(clk), + .D(\blk00000003/sig00000b9f ), + .Q(\blk00000003/blk000006e6/sig00001842 ), + .Q15(\NLW_blk00000003/blk000006e6/blk000006f3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6/blk000006f2 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006e6/sig0000183e ), + .A2(\blk00000003/blk000006e6/sig0000183e ), + .A3(\blk00000003/blk000006e6/sig0000183e ), + .CE(\blk00000003/blk000006e6/sig00001847 ), + .CLK(clk), + .D(\blk00000003/sig00000ba0 ), + .Q(\blk00000003/blk000006e6/sig00001841 ), + .Q15(\NLW_blk00000003/blk000006e6/blk000006f2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6/blk000006f1 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006e6/sig0000183e ), + .A2(\blk00000003/blk000006e6/sig0000183e ), + .A3(\blk00000003/blk000006e6/sig0000183e ), + .CE(\blk00000003/blk000006e6/sig00001847 ), + .CLK(clk), + .D(\blk00000003/sig00000ba1 ), + .Q(\blk00000003/blk000006e6/sig00001840 ), + .Q15(\NLW_blk00000003/blk000006e6/blk000006f1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6/blk000006f0 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006e6/sig0000183e ), + .A2(\blk00000003/blk000006e6/sig0000183e ), + .A3(\blk00000003/blk000006e6/sig0000183e ), + .CE(\blk00000003/blk000006e6/sig00001847 ), + .CLK(clk), + .D(\blk00000003/sig00000ba2 ), + .Q(\blk00000003/blk000006e6/sig0000183f ), + .Q15(\NLW_blk00000003/blk000006e6/blk000006f0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6/blk000006ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006e6/sig00001846 ), + .Q(\blk00000003/sig00000698 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6/blk000006ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006e6/sig00001845 ), + .Q(\blk00000003/sig00000699 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6/blk000006ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006e6/sig00001844 ), + .Q(\blk00000003/sig0000069a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6/blk000006ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006e6/sig00001843 ), + .Q(\blk00000003/sig0000069b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6/blk000006eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006e6/sig00001842 ), + .Q(\blk00000003/sig0000069c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6/blk000006ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006e6/sig00001841 ), + .Q(\blk00000003/sig0000069d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6/blk000006e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006e6/sig00001840 ), + .Q(\blk00000003/sig0000069e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6/blk000006e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006e6/sig0000183f ), + .Q(\blk00000003/sig0000069f ) + ); + GND \blk00000003/blk000006e6/blk000006e7 ( + .G(\blk00000003/blk000006e6/sig0000183e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000006f9/blk0000070b ( + .I0(\blk00000003/sig00000a10 ), + .I1(ce), + .O(\blk00000003/blk000006f9/sig00001865 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9/blk0000070a ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000006f9/sig0000185c ), + .A2(\blk00000003/blk000006f9/sig0000185c ), + .A3(\blk00000003/blk000006f9/sig0000185c ), + .CE(\blk00000003/blk000006f9/sig00001865 ), + .CLK(clk), + .D(\blk00000003/sig00000384 ), + .Q(\blk00000003/blk000006f9/sig00001864 ), + .Q15(\NLW_blk00000003/blk000006f9/blk0000070a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9/blk00000709 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000006f9/sig0000185c ), + .A2(\blk00000003/blk000006f9/sig0000185c ), + .A3(\blk00000003/blk000006f9/sig0000185c ), + .CE(\blk00000003/blk000006f9/sig00001865 ), + .CLK(clk), + .D(\blk00000003/sig00000385 ), + .Q(\blk00000003/blk000006f9/sig00001863 ), + .Q15(\NLW_blk00000003/blk000006f9/blk00000709_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9/blk00000708 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000006f9/sig0000185c ), + .A2(\blk00000003/blk000006f9/sig0000185c ), + .A3(\blk00000003/blk000006f9/sig0000185c ), + .CE(\blk00000003/blk000006f9/sig00001865 ), + .CLK(clk), + .D(\blk00000003/sig00000386 ), + .Q(\blk00000003/blk000006f9/sig00001862 ), + .Q15(\NLW_blk00000003/blk000006f9/blk00000708_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9/blk00000707 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000006f9/sig0000185c ), + .A2(\blk00000003/blk000006f9/sig0000185c ), + .A3(\blk00000003/blk000006f9/sig0000185c ), + .CE(\blk00000003/blk000006f9/sig00001865 ), + .CLK(clk), + .D(\blk00000003/sig00000387 ), + .Q(\blk00000003/blk000006f9/sig00001861 ), + .Q15(\NLW_blk00000003/blk000006f9/blk00000707_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9/blk00000706 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000006f9/sig0000185c ), + .A2(\blk00000003/blk000006f9/sig0000185c ), + .A3(\blk00000003/blk000006f9/sig0000185c ), + .CE(\blk00000003/blk000006f9/sig00001865 ), + .CLK(clk), + .D(\blk00000003/sig00000388 ), + .Q(\blk00000003/blk000006f9/sig00001860 ), + .Q15(\NLW_blk00000003/blk000006f9/blk00000706_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9/blk00000705 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000006f9/sig0000185c ), + .A2(\blk00000003/blk000006f9/sig0000185c ), + .A3(\blk00000003/blk000006f9/sig0000185c ), + .CE(\blk00000003/blk000006f9/sig00001865 ), + .CLK(clk), + .D(\blk00000003/sig00000389 ), + .Q(\blk00000003/blk000006f9/sig0000185f ), + .Q15(\NLW_blk00000003/blk000006f9/blk00000705_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9/blk00000704 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000006f9/sig0000185c ), + .A2(\blk00000003/blk000006f9/sig0000185c ), + .A3(\blk00000003/blk000006f9/sig0000185c ), + .CE(\blk00000003/blk000006f9/sig00001865 ), + .CLK(clk), + .D(\blk00000003/sig0000038a ), + .Q(\blk00000003/blk000006f9/sig0000185e ), + .Q15(\NLW_blk00000003/blk000006f9/blk00000704_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9/blk00000703 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000006f9/sig0000185c ), + .A2(\blk00000003/blk000006f9/sig0000185c ), + .A3(\blk00000003/blk000006f9/sig0000185c ), + .CE(\blk00000003/blk000006f9/sig00001865 ), + .CLK(clk), + .D(\blk00000003/sig0000038b ), + .Q(\blk00000003/blk000006f9/sig0000185d ), + .Q15(\NLW_blk00000003/blk000006f9/blk00000703_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9/blk00000702 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006f9/sig00001864 ), + .Q(\blk00000003/sig00000548 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9/blk00000701 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006f9/sig00001863 ), + .Q(\blk00000003/sig00000549 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9/blk00000700 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006f9/sig00001862 ), + .Q(\blk00000003/sig0000054a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9/blk000006ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006f9/sig00001861 ), + .Q(\blk00000003/sig0000054b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9/blk000006fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006f9/sig00001860 ), + .Q(\blk00000003/sig0000054c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9/blk000006fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006f9/sig0000185f ), + .Q(\blk00000003/sig0000054d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9/blk000006fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006f9/sig0000185e ), + .Q(\blk00000003/sig0000054e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9/blk000006fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006f9/sig0000185d ), + .Q(\blk00000003/sig0000054f ) + ); + GND \blk00000003/blk000006f9/blk000006fa ( + .G(\blk00000003/blk000006f9/sig0000185c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000070c/blk0000071e ( + .I0(\blk00000003/sig00000a0f ), + .I1(ce), + .O(\blk00000003/blk0000070c/sig00001883 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c/blk0000071d ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk0000070c/sig0000187a ), + .A2(\blk00000003/blk0000070c/sig0000187a ), + .A3(\blk00000003/blk0000070c/sig0000187a ), + .CE(\blk00000003/blk0000070c/sig00001883 ), + .CLK(clk), + .D(\blk00000003/sig00000ba3 ), + .Q(\blk00000003/blk0000070c/sig00001882 ), + .Q15(\NLW_blk00000003/blk0000070c/blk0000071d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c/blk0000071c ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk0000070c/sig0000187a ), + .A2(\blk00000003/blk0000070c/sig0000187a ), + .A3(\blk00000003/blk0000070c/sig0000187a ), + .CE(\blk00000003/blk0000070c/sig00001883 ), + .CLK(clk), + .D(\blk00000003/sig00000ba4 ), + .Q(\blk00000003/blk0000070c/sig00001881 ), + .Q15(\NLW_blk00000003/blk0000070c/blk0000071c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c/blk0000071b ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk0000070c/sig0000187a ), + .A2(\blk00000003/blk0000070c/sig0000187a ), + .A3(\blk00000003/blk0000070c/sig0000187a ), + .CE(\blk00000003/blk0000070c/sig00001883 ), + .CLK(clk), + .D(\blk00000003/sig00000ba5 ), + .Q(\blk00000003/blk0000070c/sig00001880 ), + .Q15(\NLW_blk00000003/blk0000070c/blk0000071b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c/blk0000071a ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk0000070c/sig0000187a ), + .A2(\blk00000003/blk0000070c/sig0000187a ), + .A3(\blk00000003/blk0000070c/sig0000187a ), + .CE(\blk00000003/blk0000070c/sig00001883 ), + .CLK(clk), + .D(\blk00000003/sig00000ba6 ), + .Q(\blk00000003/blk0000070c/sig0000187f ), + .Q15(\NLW_blk00000003/blk0000070c/blk0000071a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c/blk00000719 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk0000070c/sig0000187a ), + .A2(\blk00000003/blk0000070c/sig0000187a ), + .A3(\blk00000003/blk0000070c/sig0000187a ), + .CE(\blk00000003/blk0000070c/sig00001883 ), + .CLK(clk), + .D(\blk00000003/sig00000ba7 ), + .Q(\blk00000003/blk0000070c/sig0000187e ), + .Q15(\NLW_blk00000003/blk0000070c/blk00000719_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c/blk00000718 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk0000070c/sig0000187a ), + .A2(\blk00000003/blk0000070c/sig0000187a ), + .A3(\blk00000003/blk0000070c/sig0000187a ), + .CE(\blk00000003/blk0000070c/sig00001883 ), + .CLK(clk), + .D(\blk00000003/sig00000ba8 ), + .Q(\blk00000003/blk0000070c/sig0000187d ), + .Q15(\NLW_blk00000003/blk0000070c/blk00000718_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c/blk00000717 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk0000070c/sig0000187a ), + .A2(\blk00000003/blk0000070c/sig0000187a ), + .A3(\blk00000003/blk0000070c/sig0000187a ), + .CE(\blk00000003/blk0000070c/sig00001883 ), + .CLK(clk), + .D(\blk00000003/sig00000ba9 ), + .Q(\blk00000003/blk0000070c/sig0000187c ), + .Q15(\NLW_blk00000003/blk0000070c/blk00000717_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c/blk00000716 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk0000070c/sig0000187a ), + .A2(\blk00000003/blk0000070c/sig0000187a ), + .A3(\blk00000003/blk0000070c/sig0000187a ), + .CE(\blk00000003/blk0000070c/sig00001883 ), + .CLK(clk), + .D(\blk00000003/sig00000baa ), + .Q(\blk00000003/blk0000070c/sig0000187b ), + .Q15(\NLW_blk00000003/blk0000070c/blk00000716_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c/blk00000715 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000070c/sig00001882 ), + .Q(\blk00000003/sig00000540 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c/blk00000714 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000070c/sig00001881 ), + .Q(\blk00000003/sig00000541 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c/blk00000713 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000070c/sig00001880 ), + .Q(\blk00000003/sig00000542 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c/blk00000712 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000070c/sig0000187f ), + .Q(\blk00000003/sig00000543 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c/blk00000711 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000070c/sig0000187e ), + .Q(\blk00000003/sig00000544 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c/blk00000710 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000070c/sig0000187d ), + .Q(\blk00000003/sig00000545 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c/blk0000070f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000070c/sig0000187c ), + .Q(\blk00000003/sig00000546 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c/blk0000070e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000070c/sig0000187b ), + .Q(\blk00000003/sig00000547 ) + ); + GND \blk00000003/blk0000070c/blk0000070d ( + .G(\blk00000003/blk0000070c/sig0000187a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000071f/blk00000731 ( + .I0(\blk00000003/sig00000a10 ), + .I1(ce), + .O(\blk00000003/blk0000071f/sig000018a1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f/blk00000730 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000071f/sig00001898 ), + .A2(\blk00000003/blk0000071f/sig00001898 ), + .A3(\blk00000003/blk0000071f/sig00001898 ), + .CE(\blk00000003/blk0000071f/sig000018a1 ), + .CLK(clk), + .D(\blk00000003/sig000003d6 ), + .Q(\blk00000003/blk0000071f/sig000018a0 ), + .Q15(\NLW_blk00000003/blk0000071f/blk00000730_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f/blk0000072f ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000071f/sig00001898 ), + .A2(\blk00000003/blk0000071f/sig00001898 ), + .A3(\blk00000003/blk0000071f/sig00001898 ), + .CE(\blk00000003/blk0000071f/sig000018a1 ), + .CLK(clk), + .D(\blk00000003/sig000003d7 ), + .Q(\blk00000003/blk0000071f/sig0000189f ), + .Q15(\NLW_blk00000003/blk0000071f/blk0000072f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f/blk0000072e ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000071f/sig00001898 ), + .A2(\blk00000003/blk0000071f/sig00001898 ), + .A3(\blk00000003/blk0000071f/sig00001898 ), + .CE(\blk00000003/blk0000071f/sig000018a1 ), + .CLK(clk), + .D(\blk00000003/sig000003d8 ), + .Q(\blk00000003/blk0000071f/sig0000189e ), + .Q15(\NLW_blk00000003/blk0000071f/blk0000072e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f/blk0000072d ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000071f/sig00001898 ), + .A2(\blk00000003/blk0000071f/sig00001898 ), + .A3(\blk00000003/blk0000071f/sig00001898 ), + .CE(\blk00000003/blk0000071f/sig000018a1 ), + .CLK(clk), + .D(\blk00000003/sig000003d9 ), + .Q(\blk00000003/blk0000071f/sig0000189d ), + .Q15(\NLW_blk00000003/blk0000071f/blk0000072d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f/blk0000072c ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000071f/sig00001898 ), + .A2(\blk00000003/blk0000071f/sig00001898 ), + .A3(\blk00000003/blk0000071f/sig00001898 ), + .CE(\blk00000003/blk0000071f/sig000018a1 ), + .CLK(clk), + .D(\blk00000003/sig000003da ), + .Q(\blk00000003/blk0000071f/sig0000189c ), + .Q15(\NLW_blk00000003/blk0000071f/blk0000072c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f/blk0000072b ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000071f/sig00001898 ), + .A2(\blk00000003/blk0000071f/sig00001898 ), + .A3(\blk00000003/blk0000071f/sig00001898 ), + .CE(\blk00000003/blk0000071f/sig000018a1 ), + .CLK(clk), + .D(\blk00000003/sig000003db ), + .Q(\blk00000003/blk0000071f/sig0000189b ), + .Q15(\NLW_blk00000003/blk0000071f/blk0000072b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f/blk0000072a ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000071f/sig00001898 ), + .A2(\blk00000003/blk0000071f/sig00001898 ), + .A3(\blk00000003/blk0000071f/sig00001898 ), + .CE(\blk00000003/blk0000071f/sig000018a1 ), + .CLK(clk), + .D(\blk00000003/sig000003dc ), + .Q(\blk00000003/blk0000071f/sig0000189a ), + .Q15(\NLW_blk00000003/blk0000071f/blk0000072a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f/blk00000729 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000071f/sig00001898 ), + .A2(\blk00000003/blk0000071f/sig00001898 ), + .A3(\blk00000003/blk0000071f/sig00001898 ), + .CE(\blk00000003/blk0000071f/sig000018a1 ), + .CLK(clk), + .D(\blk00000003/sig000003dd ), + .Q(\blk00000003/blk0000071f/sig00001899 ), + .Q15(\NLW_blk00000003/blk0000071f/blk00000729_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f/blk00000728 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000071f/sig000018a0 ), + .Q(\blk00000003/sig00000660 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f/blk00000727 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000071f/sig0000189f ), + .Q(\blk00000003/sig00000661 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f/blk00000726 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000071f/sig0000189e ), + .Q(\blk00000003/sig00000662 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f/blk00000725 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000071f/sig0000189d ), + .Q(\blk00000003/sig00000663 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f/blk00000724 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000071f/sig0000189c ), + .Q(\blk00000003/sig00000664 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f/blk00000723 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000071f/sig0000189b ), + .Q(\blk00000003/sig00000665 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f/blk00000722 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000071f/sig0000189a ), + .Q(\blk00000003/sig00000666 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f/blk00000721 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000071f/sig00001899 ), + .Q(\blk00000003/sig00000667 ) + ); + GND \blk00000003/blk0000071f/blk00000720 ( + .G(\blk00000003/blk0000071f/sig00001898 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000732/blk00000744 ( + .I0(\blk00000003/sig00000a0f ), + .I1(ce), + .O(\blk00000003/blk00000732/sig000018bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732/blk00000743 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000732/sig000018b6 ), + .A2(\blk00000003/blk00000732/sig000018b6 ), + .A3(\blk00000003/blk00000732/sig000018b6 ), + .CE(\blk00000003/blk00000732/sig000018bf ), + .CLK(clk), + .D(\blk00000003/sig00000bab ), + .Q(\blk00000003/blk00000732/sig000018be ), + .Q15(\NLW_blk00000003/blk00000732/blk00000743_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732/blk00000742 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000732/sig000018b6 ), + .A2(\blk00000003/blk00000732/sig000018b6 ), + .A3(\blk00000003/blk00000732/sig000018b6 ), + .CE(\blk00000003/blk00000732/sig000018bf ), + .CLK(clk), + .D(\blk00000003/sig00000bac ), + .Q(\blk00000003/blk00000732/sig000018bd ), + .Q15(\NLW_blk00000003/blk00000732/blk00000742_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732/blk00000741 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000732/sig000018b6 ), + .A2(\blk00000003/blk00000732/sig000018b6 ), + .A3(\blk00000003/blk00000732/sig000018b6 ), + .CE(\blk00000003/blk00000732/sig000018bf ), + .CLK(clk), + .D(\blk00000003/sig00000bad ), + .Q(\blk00000003/blk00000732/sig000018bc ), + .Q15(\NLW_blk00000003/blk00000732/blk00000741_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732/blk00000740 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000732/sig000018b6 ), + .A2(\blk00000003/blk00000732/sig000018b6 ), + .A3(\blk00000003/blk00000732/sig000018b6 ), + .CE(\blk00000003/blk00000732/sig000018bf ), + .CLK(clk), + .D(\blk00000003/sig00000bae ), + .Q(\blk00000003/blk00000732/sig000018bb ), + .Q15(\NLW_blk00000003/blk00000732/blk00000740_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732/blk0000073f ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000732/sig000018b6 ), + .A2(\blk00000003/blk00000732/sig000018b6 ), + .A3(\blk00000003/blk00000732/sig000018b6 ), + .CE(\blk00000003/blk00000732/sig000018bf ), + .CLK(clk), + .D(\blk00000003/sig00000baf ), + .Q(\blk00000003/blk00000732/sig000018ba ), + .Q15(\NLW_blk00000003/blk00000732/blk0000073f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732/blk0000073e ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000732/sig000018b6 ), + .A2(\blk00000003/blk00000732/sig000018b6 ), + .A3(\blk00000003/blk00000732/sig000018b6 ), + .CE(\blk00000003/blk00000732/sig000018bf ), + .CLK(clk), + .D(\blk00000003/sig00000bb0 ), + .Q(\blk00000003/blk00000732/sig000018b9 ), + .Q15(\NLW_blk00000003/blk00000732/blk0000073e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732/blk0000073d ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000732/sig000018b6 ), + .A2(\blk00000003/blk00000732/sig000018b6 ), + .A3(\blk00000003/blk00000732/sig000018b6 ), + .CE(\blk00000003/blk00000732/sig000018bf ), + .CLK(clk), + .D(\blk00000003/sig00000bb1 ), + .Q(\blk00000003/blk00000732/sig000018b8 ), + .Q15(\NLW_blk00000003/blk00000732/blk0000073d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732/blk0000073c ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000732/sig000018b6 ), + .A2(\blk00000003/blk00000732/sig000018b6 ), + .A3(\blk00000003/blk00000732/sig000018b6 ), + .CE(\blk00000003/blk00000732/sig000018bf ), + .CLK(clk), + .D(\blk00000003/sig00000bb2 ), + .Q(\blk00000003/blk00000732/sig000018b7 ), + .Q15(\NLW_blk00000003/blk00000732/blk0000073c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732/blk0000073b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000732/sig000018be ), + .Q(\blk00000003/sig00000658 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732/blk0000073a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000732/sig000018bd ), + .Q(\blk00000003/sig00000659 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732/blk00000739 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000732/sig000018bc ), + .Q(\blk00000003/sig0000065a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732/blk00000738 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000732/sig000018bb ), + .Q(\blk00000003/sig0000065b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732/blk00000737 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000732/sig000018ba ), + .Q(\blk00000003/sig0000065c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732/blk00000736 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000732/sig000018b9 ), + .Q(\blk00000003/sig0000065d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732/blk00000735 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000732/sig000018b8 ), + .Q(\blk00000003/sig0000065e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732/blk00000734 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000732/sig000018b7 ), + .Q(\blk00000003/sig0000065f ) + ); + GND \blk00000003/blk00000732/blk00000733 ( + .G(\blk00000003/blk00000732/sig000018b6 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000745/blk00000757 ( + .I0(\blk00000003/sig00000a16 ), + .I1(ce), + .O(\blk00000003/blk00000745/sig000018dd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745/blk00000756 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk00000745/sig000018d4 ), + .A2(\blk00000003/blk00000745/sig000018d4 ), + .A3(\blk00000003/blk00000745/sig000018d4 ), + .CE(\blk00000003/blk00000745/sig000018dd ), + .CLK(clk), + .D(\blk00000003/sig00000bb3 ), + .Q(\blk00000003/blk00000745/sig000018dc ), + .Q15(\NLW_blk00000003/blk00000745/blk00000756_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745/blk00000755 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk00000745/sig000018d4 ), + .A2(\blk00000003/blk00000745/sig000018d4 ), + .A3(\blk00000003/blk00000745/sig000018d4 ), + .CE(\blk00000003/blk00000745/sig000018dd ), + .CLK(clk), + .D(\blk00000003/sig00000bb4 ), + .Q(\blk00000003/blk00000745/sig000018db ), + .Q15(\NLW_blk00000003/blk00000745/blk00000755_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745/blk00000754 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk00000745/sig000018d4 ), + .A2(\blk00000003/blk00000745/sig000018d4 ), + .A3(\blk00000003/blk00000745/sig000018d4 ), + .CE(\blk00000003/blk00000745/sig000018dd ), + .CLK(clk), + .D(\blk00000003/sig00000bb5 ), + .Q(\blk00000003/blk00000745/sig000018da ), + .Q15(\NLW_blk00000003/blk00000745/blk00000754_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745/blk00000753 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk00000745/sig000018d4 ), + .A2(\blk00000003/blk00000745/sig000018d4 ), + .A3(\blk00000003/blk00000745/sig000018d4 ), + .CE(\blk00000003/blk00000745/sig000018dd ), + .CLK(clk), + .D(\blk00000003/sig00000bb6 ), + .Q(\blk00000003/blk00000745/sig000018d9 ), + .Q15(\NLW_blk00000003/blk00000745/blk00000753_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745/blk00000752 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk00000745/sig000018d4 ), + .A2(\blk00000003/blk00000745/sig000018d4 ), + .A3(\blk00000003/blk00000745/sig000018d4 ), + .CE(\blk00000003/blk00000745/sig000018dd ), + .CLK(clk), + .D(\blk00000003/sig00000bb7 ), + .Q(\blk00000003/blk00000745/sig000018d8 ), + .Q15(\NLW_blk00000003/blk00000745/blk00000752_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745/blk00000751 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk00000745/sig000018d4 ), + .A2(\blk00000003/blk00000745/sig000018d4 ), + .A3(\blk00000003/blk00000745/sig000018d4 ), + .CE(\blk00000003/blk00000745/sig000018dd ), + .CLK(clk), + .D(\blk00000003/sig00000bb8 ), + .Q(\blk00000003/blk00000745/sig000018d7 ), + .Q15(\NLW_blk00000003/blk00000745/blk00000751_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745/blk00000750 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk00000745/sig000018d4 ), + .A2(\blk00000003/blk00000745/sig000018d4 ), + .A3(\blk00000003/blk00000745/sig000018d4 ), + .CE(\blk00000003/blk00000745/sig000018dd ), + .CLK(clk), + .D(\blk00000003/sig00000bb9 ), + .Q(\blk00000003/blk00000745/sig000018d6 ), + .Q15(\NLW_blk00000003/blk00000745/blk00000750_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745/blk0000074f ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk00000745/sig000018d4 ), + .A2(\blk00000003/blk00000745/sig000018d4 ), + .A3(\blk00000003/blk00000745/sig000018d4 ), + .CE(\blk00000003/blk00000745/sig000018dd ), + .CLK(clk), + .D(\blk00000003/sig00000bba ), + .Q(\blk00000003/blk00000745/sig000018d5 ), + .Q15(\NLW_blk00000003/blk00000745/blk0000074f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745/blk0000074e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000745/sig000018dc ), + .Q(\blk00000003/sig00000384 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745/blk0000074d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000745/sig000018db ), + .Q(\blk00000003/sig00000385 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745/blk0000074c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000745/sig000018da ), + .Q(\blk00000003/sig00000386 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745/blk0000074b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000745/sig000018d9 ), + .Q(\blk00000003/sig00000387 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745/blk0000074a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000745/sig000018d8 ), + .Q(\blk00000003/sig00000388 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745/blk00000749 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000745/sig000018d7 ), + .Q(\blk00000003/sig00000389 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745/blk00000748 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000745/sig000018d6 ), + .Q(\blk00000003/sig0000038a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745/blk00000747 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000745/sig000018d5 ), + .Q(\blk00000003/sig0000038b ) + ); + GND \blk00000003/blk00000745/blk00000746 ( + .G(\blk00000003/blk00000745/sig000018d4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000758/blk0000076a ( + .I0(\blk00000003/sig00000a15 ), + .I1(ce), + .O(\blk00000003/blk00000758/sig000018fb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758/blk00000769 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000758/sig000018f2 ), + .A2(\blk00000003/blk00000758/sig000018f2 ), + .A3(\blk00000003/blk00000758/sig000018f2 ), + .CE(\blk00000003/blk00000758/sig000018fb ), + .CLK(clk), + .D(\blk00000003/sig00000bbb ), + .Q(\blk00000003/blk00000758/sig000018fa ), + .Q15(\NLW_blk00000003/blk00000758/blk00000769_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758/blk00000768 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000758/sig000018f2 ), + .A2(\blk00000003/blk00000758/sig000018f2 ), + .A3(\blk00000003/blk00000758/sig000018f2 ), + .CE(\blk00000003/blk00000758/sig000018fb ), + .CLK(clk), + .D(\blk00000003/sig00000bbc ), + .Q(\blk00000003/blk00000758/sig000018f9 ), + .Q15(\NLW_blk00000003/blk00000758/blk00000768_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758/blk00000767 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000758/sig000018f2 ), + .A2(\blk00000003/blk00000758/sig000018f2 ), + .A3(\blk00000003/blk00000758/sig000018f2 ), + .CE(\blk00000003/blk00000758/sig000018fb ), + .CLK(clk), + .D(\blk00000003/sig00000bbd ), + .Q(\blk00000003/blk00000758/sig000018f8 ), + .Q15(\NLW_blk00000003/blk00000758/blk00000767_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758/blk00000766 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000758/sig000018f2 ), + .A2(\blk00000003/blk00000758/sig000018f2 ), + .A3(\blk00000003/blk00000758/sig000018f2 ), + .CE(\blk00000003/blk00000758/sig000018fb ), + .CLK(clk), + .D(\blk00000003/sig00000bbe ), + .Q(\blk00000003/blk00000758/sig000018f7 ), + .Q15(\NLW_blk00000003/blk00000758/blk00000766_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758/blk00000765 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000758/sig000018f2 ), + .A2(\blk00000003/blk00000758/sig000018f2 ), + .A3(\blk00000003/blk00000758/sig000018f2 ), + .CE(\blk00000003/blk00000758/sig000018fb ), + .CLK(clk), + .D(\blk00000003/sig00000bbf ), + .Q(\blk00000003/blk00000758/sig000018f6 ), + .Q15(\NLW_blk00000003/blk00000758/blk00000765_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758/blk00000764 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000758/sig000018f2 ), + .A2(\blk00000003/blk00000758/sig000018f2 ), + .A3(\blk00000003/blk00000758/sig000018f2 ), + .CE(\blk00000003/blk00000758/sig000018fb ), + .CLK(clk), + .D(\blk00000003/sig00000bc0 ), + .Q(\blk00000003/blk00000758/sig000018f5 ), + .Q15(\NLW_blk00000003/blk00000758/blk00000764_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758/blk00000763 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000758/sig000018f2 ), + .A2(\blk00000003/blk00000758/sig000018f2 ), + .A3(\blk00000003/blk00000758/sig000018f2 ), + .CE(\blk00000003/blk00000758/sig000018fb ), + .CLK(clk), + .D(\blk00000003/sig00000bc1 ), + .Q(\blk00000003/blk00000758/sig000018f4 ), + .Q15(\NLW_blk00000003/blk00000758/blk00000763_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758/blk00000762 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000758/sig000018f2 ), + .A2(\blk00000003/blk00000758/sig000018f2 ), + .A3(\blk00000003/blk00000758/sig000018f2 ), + .CE(\blk00000003/blk00000758/sig000018fb ), + .CLK(clk), + .D(\blk00000003/sig00000bc2 ), + .Q(\blk00000003/blk00000758/sig000018f3 ), + .Q15(\NLW_blk00000003/blk00000758/blk00000762_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758/blk00000761 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000758/sig000018fa ), + .Q(\blk00000003/sig0000037c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758/blk00000760 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000758/sig000018f9 ), + .Q(\blk00000003/sig0000037d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758/blk0000075f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000758/sig000018f8 ), + .Q(\blk00000003/sig0000037e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758/blk0000075e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000758/sig000018f7 ), + .Q(\blk00000003/sig0000037f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758/blk0000075d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000758/sig000018f6 ), + .Q(\blk00000003/sig00000380 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758/blk0000075c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000758/sig000018f5 ), + .Q(\blk00000003/sig00000381 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758/blk0000075b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000758/sig000018f4 ), + .Q(\blk00000003/sig00000382 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758/blk0000075a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000758/sig000018f3 ), + .Q(\blk00000003/sig00000383 ) + ); + GND \blk00000003/blk00000758/blk00000759 ( + .G(\blk00000003/blk00000758/sig000018f2 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000076b/blk0000077d ( + .I0(\blk00000003/sig00000a16 ), + .I1(ce), + .O(\blk00000003/blk0000076b/sig00001919 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b/blk0000077c ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000076b/sig00001910 ), + .A2(\blk00000003/blk0000076b/sig00001910 ), + .A3(\blk00000003/blk0000076b/sig00001910 ), + .CE(\blk00000003/blk0000076b/sig00001919 ), + .CLK(clk), + .D(\blk00000003/sig00000bc3 ), + .Q(\blk00000003/blk0000076b/sig00001918 ), + .Q15(\NLW_blk00000003/blk0000076b/blk0000077c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b/blk0000077b ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000076b/sig00001910 ), + .A2(\blk00000003/blk0000076b/sig00001910 ), + .A3(\blk00000003/blk0000076b/sig00001910 ), + .CE(\blk00000003/blk0000076b/sig00001919 ), + .CLK(clk), + .D(\blk00000003/sig00000bc4 ), + .Q(\blk00000003/blk0000076b/sig00001917 ), + .Q15(\NLW_blk00000003/blk0000076b/blk0000077b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b/blk0000077a ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000076b/sig00001910 ), + .A2(\blk00000003/blk0000076b/sig00001910 ), + .A3(\blk00000003/blk0000076b/sig00001910 ), + .CE(\blk00000003/blk0000076b/sig00001919 ), + .CLK(clk), + .D(\blk00000003/sig00000bc5 ), + .Q(\blk00000003/blk0000076b/sig00001916 ), + .Q15(\NLW_blk00000003/blk0000076b/blk0000077a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b/blk00000779 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000076b/sig00001910 ), + .A2(\blk00000003/blk0000076b/sig00001910 ), + .A3(\blk00000003/blk0000076b/sig00001910 ), + .CE(\blk00000003/blk0000076b/sig00001919 ), + .CLK(clk), + .D(\blk00000003/sig00000bc6 ), + .Q(\blk00000003/blk0000076b/sig00001915 ), + .Q15(\NLW_blk00000003/blk0000076b/blk00000779_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b/blk00000778 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000076b/sig00001910 ), + .A2(\blk00000003/blk0000076b/sig00001910 ), + .A3(\blk00000003/blk0000076b/sig00001910 ), + .CE(\blk00000003/blk0000076b/sig00001919 ), + .CLK(clk), + .D(\blk00000003/sig00000bc7 ), + .Q(\blk00000003/blk0000076b/sig00001914 ), + .Q15(\NLW_blk00000003/blk0000076b/blk00000778_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b/blk00000777 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000076b/sig00001910 ), + .A2(\blk00000003/blk0000076b/sig00001910 ), + .A3(\blk00000003/blk0000076b/sig00001910 ), + .CE(\blk00000003/blk0000076b/sig00001919 ), + .CLK(clk), + .D(\blk00000003/sig00000bc8 ), + .Q(\blk00000003/blk0000076b/sig00001913 ), + .Q15(\NLW_blk00000003/blk0000076b/blk00000777_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b/blk00000776 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000076b/sig00001910 ), + .A2(\blk00000003/blk0000076b/sig00001910 ), + .A3(\blk00000003/blk0000076b/sig00001910 ), + .CE(\blk00000003/blk0000076b/sig00001919 ), + .CLK(clk), + .D(\blk00000003/sig00000bc9 ), + .Q(\blk00000003/blk0000076b/sig00001912 ), + .Q15(\NLW_blk00000003/blk0000076b/blk00000776_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b/blk00000775 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000076b/sig00001910 ), + .A2(\blk00000003/blk0000076b/sig00001910 ), + .A3(\blk00000003/blk0000076b/sig00001910 ), + .CE(\blk00000003/blk0000076b/sig00001919 ), + .CLK(clk), + .D(\blk00000003/sig00000bca ), + .Q(\blk00000003/blk0000076b/sig00001911 ), + .Q15(\NLW_blk00000003/blk0000076b/blk00000775_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b/blk00000774 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000076b/sig00001918 ), + .Q(\blk00000003/sig000003d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b/blk00000773 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000076b/sig00001917 ), + .Q(\blk00000003/sig000003d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b/blk00000772 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000076b/sig00001916 ), + .Q(\blk00000003/sig000003d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b/blk00000771 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000076b/sig00001915 ), + .Q(\blk00000003/sig000003d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b/blk00000770 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000076b/sig00001914 ), + .Q(\blk00000003/sig000003da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b/blk0000076f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000076b/sig00001913 ), + .Q(\blk00000003/sig000003db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b/blk0000076e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000076b/sig00001912 ), + .Q(\blk00000003/sig000003dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b/blk0000076d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000076b/sig00001911 ), + .Q(\blk00000003/sig000003dd ) + ); + GND \blk00000003/blk0000076b/blk0000076c ( + .G(\blk00000003/blk0000076b/sig00001910 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000077e/blk00000790 ( + .I0(\blk00000003/sig00000a15 ), + .I1(ce), + .O(\blk00000003/blk0000077e/sig00001937 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e/blk0000078f ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000077e/sig0000192e ), + .A2(\blk00000003/blk0000077e/sig0000192e ), + .A3(\blk00000003/blk0000077e/sig0000192e ), + .CE(\blk00000003/blk0000077e/sig00001937 ), + .CLK(clk), + .D(\blk00000003/sig00000bcb ), + .Q(\blk00000003/blk0000077e/sig00001936 ), + .Q15(\NLW_blk00000003/blk0000077e/blk0000078f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e/blk0000078e ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000077e/sig0000192e ), + .A2(\blk00000003/blk0000077e/sig0000192e ), + .A3(\blk00000003/blk0000077e/sig0000192e ), + .CE(\blk00000003/blk0000077e/sig00001937 ), + .CLK(clk), + .D(\blk00000003/sig00000bcc ), + .Q(\blk00000003/blk0000077e/sig00001935 ), + .Q15(\NLW_blk00000003/blk0000077e/blk0000078e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e/blk0000078d ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000077e/sig0000192e ), + .A2(\blk00000003/blk0000077e/sig0000192e ), + .A3(\blk00000003/blk0000077e/sig0000192e ), + .CE(\blk00000003/blk0000077e/sig00001937 ), + .CLK(clk), + .D(\blk00000003/sig00000bcd ), + .Q(\blk00000003/blk0000077e/sig00001934 ), + .Q15(\NLW_blk00000003/blk0000077e/blk0000078d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e/blk0000078c ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000077e/sig0000192e ), + .A2(\blk00000003/blk0000077e/sig0000192e ), + .A3(\blk00000003/blk0000077e/sig0000192e ), + .CE(\blk00000003/blk0000077e/sig00001937 ), + .CLK(clk), + .D(\blk00000003/sig00000bce ), + .Q(\blk00000003/blk0000077e/sig00001933 ), + .Q15(\NLW_blk00000003/blk0000077e/blk0000078c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e/blk0000078b ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000077e/sig0000192e ), + .A2(\blk00000003/blk0000077e/sig0000192e ), + .A3(\blk00000003/blk0000077e/sig0000192e ), + .CE(\blk00000003/blk0000077e/sig00001937 ), + .CLK(clk), + .D(\blk00000003/sig00000bcf ), + .Q(\blk00000003/blk0000077e/sig00001932 ), + .Q15(\NLW_blk00000003/blk0000077e/blk0000078b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e/blk0000078a ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000077e/sig0000192e ), + .A2(\blk00000003/blk0000077e/sig0000192e ), + .A3(\blk00000003/blk0000077e/sig0000192e ), + .CE(\blk00000003/blk0000077e/sig00001937 ), + .CLK(clk), + .D(\blk00000003/sig00000bd0 ), + .Q(\blk00000003/blk0000077e/sig00001931 ), + .Q15(\NLW_blk00000003/blk0000077e/blk0000078a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e/blk00000789 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000077e/sig0000192e ), + .A2(\blk00000003/blk0000077e/sig0000192e ), + .A3(\blk00000003/blk0000077e/sig0000192e ), + .CE(\blk00000003/blk0000077e/sig00001937 ), + .CLK(clk), + .D(\blk00000003/sig00000bd1 ), + .Q(\blk00000003/blk0000077e/sig00001930 ), + .Q15(\NLW_blk00000003/blk0000077e/blk00000789_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e/blk00000788 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000077e/sig0000192e ), + .A2(\blk00000003/blk0000077e/sig0000192e ), + .A3(\blk00000003/blk0000077e/sig0000192e ), + .CE(\blk00000003/blk0000077e/sig00001937 ), + .CLK(clk), + .D(\blk00000003/sig00000bd2 ), + .Q(\blk00000003/blk0000077e/sig0000192f ), + .Q15(\NLW_blk00000003/blk0000077e/blk00000788_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e/blk00000787 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000077e/sig00001936 ), + .Q(\blk00000003/sig000003ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e/blk00000786 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000077e/sig00001935 ), + .Q(\blk00000003/sig000003cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e/blk00000785 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000077e/sig00001934 ), + .Q(\blk00000003/sig000003d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e/blk00000784 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000077e/sig00001933 ), + .Q(\blk00000003/sig000003d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e/blk00000783 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000077e/sig00001932 ), + .Q(\blk00000003/sig000003d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e/blk00000782 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000077e/sig00001931 ), + .Q(\blk00000003/sig000003d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e/blk00000781 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000077e/sig00001930 ), + .Q(\blk00000003/sig000003d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e/blk00000780 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000077e/sig0000192f ), + .Q(\blk00000003/sig000003d5 ) + ); + GND \blk00000003/blk0000077e/blk0000077f ( + .G(\blk00000003/blk0000077e/sig0000192e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000007c1/blk000007e7 ( + .I0(\blk00000003/sig0000030a ), + .I1(ce), + .O(\blk00000003/blk000007c1/sig00001974 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007c1/blk000007e6 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000af7 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007e6_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001973 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007e5 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000af8 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007e5_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001972 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007e4 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000af9 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007e4_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001971 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007e3 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000afa ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007e3_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001970 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007e2 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000afb ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007e2_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig0000196f ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007e1 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000afc ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007e1_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig0000196e ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007e0 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000afe ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007e0_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig0000196c ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007df ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000aff ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007df_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig0000196b ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007de ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000afd ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007de_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig0000196d ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007dd ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b00 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007dd_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig0000196a ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007dc ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b01 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007dc_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001969 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007db ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b02 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007db_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001968 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007da ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b03 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007da_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001967 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007d9 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b04 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007d9_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001966 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007d8 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b05 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007d8_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001965 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007d7 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b07 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007d7_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001963 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007d6 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b08 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007d6_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001962 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007d5 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b06 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007d5_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001964 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001973 ), + .Q(\blk00000003/sig000001b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001972 ), + .Q(\blk00000003/sig000001b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001971 ), + .Q(\blk00000003/sig000001b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001970 ), + .Q(\blk00000003/sig000001b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig0000196f ), + .Q(\blk00000003/sig000001b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig0000196e ), + .Q(\blk00000003/sig000001b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig0000196d ), + .Q(\blk00000003/sig000001b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig0000196c ), + .Q(\blk00000003/sig000001b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig0000196b ), + .Q(\blk00000003/sig000001b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig0000196a ), + .Q(\blk00000003/sig000001b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001969 ), + .Q(\blk00000003/sig000001ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001968 ), + .Q(\blk00000003/sig000001bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001967 ), + .Q(\blk00000003/sig000001bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001966 ), + .Q(\blk00000003/sig000001bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001965 ), + .Q(\blk00000003/sig000001be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001964 ), + .Q(\blk00000003/sig000001bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001963 ), + .Q(\blk00000003/sig000001c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001962 ), + .Q(\blk00000003/sig000001c1 ) + ); + GND \blk00000003/blk000007c1/blk000007c2 ( + .G(\blk00000003/blk000007c1/sig00001961 ) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1.veo b/fpga/usrp3/top/b200/coregen_dsp/hbdec1.veo new file mode 100644 index 000000000..eb615e1ee --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1.veo @@ -0,0 +1,79 @@ +/******************************************************************************* +* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. * +* * +* This file contains confidential and proprietary information * +* of Xilinx, Inc. and is protected under U.S. and * +* international copyright and other intellectual property * +* laws. * +* * +* DISCLAIMER * +* This disclaimer is not a license and does not grant any * +* rights to the materials distributed herewith. Except as * +* otherwise provided in a valid license issued to you by * +* Xilinx, and to the maximum extent permitted by applicable * +* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND * +* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES * +* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING * +* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- * +* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and * +* (2) Xilinx shall not be liable (whether in contract or tort, * +* including negligence, or under any other theory of * +* liability) for any loss or damage of any kind or nature * +* related to, arising under or in connection with these * +* materials, including for any direct, or any indirect, * +* special, incidental, or consequential loss or damage * +* (including loss of data, profits, goodwill, or any type of * +* loss or damage suffered as a result of any action brought * +* by a third party) even if such damage or loss was * +* reasonably foreseeable or Xilinx had been advised of the * +* possibility of the same. * +* * +* CRITICAL APPLICATIONS * +* Xilinx products are not designed or intended to be fail- * +* safe, or for use in any application requiring fail-safe * +* performance, such as life-support or safety devices or * +* systems, Class III medical devices, nuclear facilities, * +* applications related to the deployment of airbags, or any * +* other applications that could lead to death, personal * +* injury, or severe property or environmental damage * +* (individually and collectively, "Critical * +* Applications"). Customer assumes the sole risk and * +* liability of any use of Xilinx products in Critical * +* Applications, subject only to applicable laws and * +* regulations governing limitations on product liability. * +* * +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS * +* PART OF THIS FILE AT ALL TIMES. * +*******************************************************************************/ + +// Generated from component ID: xilinx.com:ip:fir_compiler:5.0 + + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +hbdec1 YourInstanceName ( + .sclr(sclr), // input sclr + .clk(clk), // input clk + .ce(ce), // input ce + .nd(nd), // input nd + .coef_ld(coef_ld), // input coef_ld + .coef_we(coef_we), // input coef_we + .coef_din(coef_din), // input [17 : 0] coef_din + .rfd(rfd), // output rfd + .rdy(rdy), // output rdy + .data_valid(data_valid), // output data_valid + .din_1(din_1), // input [23 : 0] din_1 + .din_2(din_2), // input [23 : 0] din_2 + .dout_1(dout_1), // output [46 : 0] dout_1 + .dout_2(dout_2)); // output [46 : 0] dout_2 + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file hbdec1.v when simulating +// the core, hbdec1. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1.xco b/fpga/usrp3/top/b200/coregen_dsp/hbdec1.xco new file mode 100644 index 000000000..5487ee44b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1.xco @@ -0,0 +1,102 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Fri Jan 9 20:43:38 2015 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fir_compiler:5.0 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx150t +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT FIR_Compiler family Xilinx,_Inc. 5.0 +# END Select +# BEGIN Parameters +CSET allow_rounding_approximation=false +CSET bestprecision=false +CSET chan_in_adv=0 +CSET clock_frequency=64 +CSET coefficient_buffer_type=Automatic +CSET coefficient_file=./hb47.coe +CSET coefficient_fractional_bits=0 +CSET coefficient_reload=true +CSET coefficient_sets=1 +CSET coefficient_sign=Signed +CSET coefficient_structure=Half_Band +CSET coefficient_width=18 +CSET coefficientsource=COE_File +CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 +CSET columnconfig=7 +CSET component_name=hbdec1 +CSET data_buffer_type=Automatic +CSET data_fractional_bits=0 +CSET data_sign=Signed +CSET data_width=24 +CSET decimation_rate=2 +CSET displayreloadorder=false +CSET filter_architecture=Systolic_Multiply_Accumulate +CSET filter_selection=1 +CSET filter_type=Decimation +CSET gui_behaviour=Coregen +CSET hardwareoversamplingrate=1 +CSET has_ce=true +CSET has_data_valid=true +CSET has_nd=true +CSET has_sclr=true +CSET input_buffer_type=Automatic +CSET inter_column_pipe_length=4 +CSET interpolation_rate=1 +CSET multi_column_support=Disabled +CSET number_channels=1 +CSET number_paths=2 +CSET optimization_goal=Area +CSET output_buffer_type=Automatic +CSET output_rounding_mode=Full_Precision +CSET output_width=47 +CSET passband_max=0.5 +CSET passband_min=0.0 +CSET preference_for_other_storage=Automatic +CSET quantization=Integer_Coefficients +CSET rate_change_type=Integer +CSET ratespecification=Frequency_Specification +CSET registered_output=true +CSET sample_frequency=64 +CSET sampleperiod=1 +CSET sclr_deterministic=true +CSET stopband_max=1.0 +CSET stopband_min=0.5 +CSET usechan_in_adv=false +CSET zero_pack_factor=1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-12-18T05:23:34Z +# END Extra information +GENERATE +# CRC: 3310ee85 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_0.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_0.mif new file mode 100644 index 000000000..f19636daf --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_0.mif @@ -0,0 +1,5 @@ +111111111111000010 +000000000011000010 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_1.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_1.mif new file mode 100644 index 000000000..07e316dd3 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_1.mif @@ -0,0 +1,5 @@ +111111111001001000 +000000001101010111 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_2.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_2.mif new file mode 100644 index 000000000..da84300d6 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_2.mif @@ -0,0 +1,5 @@ +111111101000011111 +000000100110101110 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_3.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_3.mif new file mode 100644 index 000000000..ea92ca6c2 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_3.mif @@ -0,0 +1,5 @@ +111111000011000100 +000001011101100110 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_4.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_4.mif new file mode 100644 index 000000000..9e9303211 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_4.mif @@ -0,0 +1,5 @@ +111101110000011101 +000011100100101000 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_5.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_5.mif new file mode 100644 index 000000000..e0c3f05fe --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_5.mif @@ -0,0 +1,5 @@ +111001100001011000 +010100010001000001 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto_HALFBAND_CENTRE0.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto_HALFBAND_CENTRE0.mif new file mode 100644 index 000000000..ca072e0fc --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto_HALFBAND_CENTRE0.mif @@ -0,0 +1,3 @@ +011111111111111111 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1_flist.txt b/fpga/usrp3/top/b200/coregen_dsp/hbdec1_flist.txt new file mode 100644 index 000000000..2bd535f92 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1_flist.txt @@ -0,0 +1,22 @@ +# Output products list for +hbdec1.asy +hbdec1.gise +hbdec1.mif +hbdec1.ngc +hbdec1.v +hbdec1.veo +hbdec1.xco +hbdec1.xise +hbdec1COEFF_auto0_0.mif +hbdec1COEFF_auto0_1.mif +hbdec1COEFF_auto0_2.mif +hbdec1COEFF_auto0_3.mif +hbdec1COEFF_auto0_4.mif +hbdec1COEFF_auto0_5.mif +hbdec1COEFF_auto_HALFBAND_CENTRE0.mif +hbdec1_flist.txt +hbdec1_readme.txt +hbdec1_reload_addrfilt_decode_rom.mif +hbdec1_reload_order.txt +hbdec1_xmdf.tcl +hbdec1filt_decode_rom.mif diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1_readme.txt b/fpga/usrp3/top/b200/coregen_dsp/hbdec1_readme.txt new file mode 100644 index 000000000..0398bd92f --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1_readme.txt @@ -0,0 +1,78 @@ +The following files were generated for 'hbdec1' in directory +/disk2/ianb/ettus/fpgadev2/fpgadev/usrp3/top/b200/coregen_dsp/ + +Model Parameter Resolution: + Resolves generated model parameter values on the component instance. + + * hbdec1.mif + * hbdec1_reload_order.txt + +ISE file generator: + Add description here... + + * hbdec1_flist.txt + +Opens the IP Customization GUI: + Allows the user to customize or recustomize the IP instance. + + * hbdec1.mif + * hbdec1_reload_order.txt + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * hbdec1.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * hbdec1.ngc + * hbdec1.v + * hbdec1.veo + * hbdec1COEFF_auto0_0.mif + * hbdec1COEFF_auto0_1.mif + * hbdec1COEFF_auto0_2.mif + * hbdec1COEFF_auto0_3.mif + * hbdec1COEFF_auto0_4.mif + * hbdec1COEFF_auto0_5.mif + * hbdec1COEFF_auto_HALFBAND_CENTRE0.mif + * hbdec1_reload_addrfilt_decode_rom.mif + * hbdec1filt_decode_rom.mif + +Creates an HDL instantiation template: + Creates an HDL instantiation template for the IP. + + * hbdec1.veo + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * hbdec1.asy + * hbdec1.mif + * hbdec1_reload_order.txt + +Generate ISE metadata: + Create a metadata file for use when including this core in ISE designs + + * hbdec1_xmdf.tcl + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * hbdec1.gise + * hbdec1.xise + +Deliver Readme: + Readme file for the IP. + + * hbdec1_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * hbdec1_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1_reload_addrfilt_decode_rom.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec1_reload_addrfilt_decode_rom.mif new file mode 100644 index 000000000..32d689cd7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1_reload_addrfilt_decode_rom.mif @@ -0,0 +1,17 @@ +00 +10 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1_reload_order.txt b/fpga/usrp3/top/b200/coregen_dsp/hbdec1_reload_order.txt new file mode 100644 index 000000000..11f12084f --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1_reload_order.txt @@ -0,0 +1,25 @@ +Reload index 0 = Index 20 +Reload index 1 = Index 22 +Reload index 2 = Index 16 +Reload index 3 = Index 18 +Reload index 4 = Index 12 +Reload index 5 = Index 14 +Reload index 6 = Index 8 +Reload index 7 = Index 10 +Reload index 8 = Index 4 +Reload index 9 = Index 6 +Reload index 10 = Index 0 +Reload index 11 = Index 2 +Reload index 12 = Index 23 +Reload index 13 = Index 0 +Reload index 14 = Index 0 +Reload index 15 = Index 0 +Reload index 16 = Index 0 +Reload index 17 = Index 0 +Reload index 18 = Index 0 +Reload index 19 = Index 0 +Reload index 20 = Index 0 +Reload index 21 = Index 0 +Reload index 22 = Index 0 +Reload index 23 = Index 0 + diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1_xmdf.tcl b/fpga/usrp3/top/b200/coregen_dsp/hbdec1_xmdf.tcl new file mode 100644 index 000000000..7aa8f91c3 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1_xmdf.tcl @@ -0,0 +1,111 @@ +# The package naming convention is _xmdf +package provide hbdec1_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::hbdec1_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::hbdec1_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name hbdec1 +} +# ::hbdec1_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::hbdec1_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_0.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_1.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_2.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_3.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_4.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_5.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto_HALFBAND_CENTRE0.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1_reload_addrfilt_decode_rom.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1_reload_order.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type text +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1filt_decode_rom.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module hbdec1 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1filt_decode_rom.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec1filt_decode_rom.mif new file mode 100644 index 000000000..32d689cd7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1filt_decode_rom.mif @@ -0,0 +1,17 @@ +00 +10 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2.asy b/fpga/usrp3/top/b200/coregen_dsp/hbdec2.asy new file mode 100644 index 000000000..e9bd5ec37 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2.asy @@ -0,0 +1,61 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 hbdec2 +RECTANGLE Normal 32 32 544 2048 +LINE Normal 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName nd +PINATTR Polarity IN +LINE Wide 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName din_1[23:0] +PINATTR Polarity IN +LINE Wide 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName din_2[23:0] +PINATTR Polarity IN +LINE Normal 0 848 32 848 +PIN 0 848 LEFT 36 +PINATTR PinName coef_ld +PINATTR Polarity IN +LINE Normal 0 880 32 880 +PIN 0 880 LEFT 36 +PINATTR PinName coef_we +PINATTR Polarity IN +LINE Wide 0 912 32 912 +PIN 0 912 LEFT 36 +PINATTR PinName coef_din[17:0] +PINATTR Polarity IN +LINE Normal 0 1008 32 1008 +PIN 0 1008 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Normal 0 1040 32 1040 +PIN 0 1040 LEFT 36 +PINATTR PinName ce +PINATTR Polarity IN +LINE Normal 0 1072 32 1072 +PIN 0 1072 LEFT 36 +PINATTR PinName sclr +PINATTR Polarity IN +LINE Wide 576 240 544 240 +PIN 576 240 RIGHT 36 +PINATTR PinName dout_1[46:0] +PINATTR Polarity OUT +LINE Wide 576 272 544 272 +PIN 576 272 RIGHT 36 +PINATTR PinName dout_2[46:0] +PINATTR Polarity OUT +LINE Normal 576 1840 544 1840 +PIN 576 1840 RIGHT 36 +PINATTR PinName rfd +PINATTR Polarity OUT +LINE Normal 576 1872 544 1872 +PIN 576 1872 RIGHT 36 +PINATTR PinName rdy +PINATTR Polarity OUT +LINE Normal 576 1904 544 1904 +PIN 576 1904 RIGHT 36 +PINATTR PinName data_valid +PINATTR Polarity OUT + diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec2.mif new file mode 100644 index 000000000..78d2dd901 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2.mif @@ -0,0 +1,47 @@ +111111111111000010 +000000000000000000 +000000000011000010 +000000000000000000 +111111111001001000 +000000000000000000 +000000001101010111 +000000000000000000 +111111101000011111 +000000000000000000 +000000100110101110 +000000000000000000 +111111000011000100 +000000000000000000 +000001011101100110 +000000000000000000 +111101110000011101 +000000000000000000 +000011100100101000 +000000000000000000 +111001100001011000 +000000000000000000 +010100010001000001 +011111111111111111 +010100010001000001 +000000000000000000 +111001100001011000 +000000000000000000 +000011100100101000 +000000000000000000 +111101110000011101 +000000000000000000 +000001011101100110 +000000000000000000 +111111000011000100 +000000000000000000 +000000100110101110 +000000000000000000 +111111101000011111 +000000000000000000 +000000001101010111 +000000000000000000 +111111111001001000 +000000000000000000 +000000000011000010 +000000000000000000 +111111111111000010 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2.ngc b/fpga/usrp3/top/b200/coregen_dsp/hbdec2.ngc new file mode 100644 index 000000000..ba9528546 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$37:2~753-Xnzd}foo8#5+421).97 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2we84o=:182M5c82we84o<:182M5c82we84o;:182M5c82we8l:i:182M5c82we8l;?:182M5c82we8l;>:182M5c82we8l;=:182M5c82we8l;<:182M5c82we8l;;:182M5c82we8l;::182M5c82we8l;9:182M5c82we8l;8:182M5c82we8l;7:182M5c82we8o><:182M5c82we8o>;:182M5c82we8o>::182M5c82we8o>9:182M5c82we8o>8:182M5c82we8o>7:182M5c82we8o>6:182M5c82we8o>n:182M5c82we8o>m:182M5c82we8o>l:182M5c82we8ol8:182M5c82we8ol7:182M5c82we8ol6:182M5c82we8oln:182M5c82we8olm:182M5c82we8oll:182M5c82we8olk:182M5c82we8olj:182M5c82we8oli:182M5c82we8om?:182M5c82we8k8<:182M5c82we8k8;:182M5c82we8k8::182M5c82we8k89:182M5c82we8k88:182M5c82we8k87:182M5c82we8k86:182M5c82we8k8n:182M5c82we8k8m:182M5c82we8k8l:182M5c82we8k8k:182M5c82we8k8j:182M5c82we8k8i:182M5c82we8k9?:182M5c82we8k9>:182M5c82we8k9=:182M5c82we8k9<:182M5c82we8k9;:182M5c82we8k9::182M5c82we8k99:182M5c82wvqpNOCz5;40_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f3_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f3_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e6_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e5_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e4_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e3_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e1_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000dd_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000dc_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000db_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000da_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d9_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d8_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d1_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d1_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cd_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cd_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c7_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c3_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c3_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b2_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b1_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a8_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a4_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a3_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a1_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a0_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009f_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009d_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009c_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009a_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000099_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000024_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000020_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001a_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000019_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000013_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000d_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000095_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000094_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000093_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000092_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000091_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000090_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000008f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000008e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000008d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000008c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000008b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000008a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000089_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000088_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000087_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000086_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000085_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000084_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000083_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000082_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000081_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000080_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000007f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000007e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000007d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000007c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000007b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000007a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000079_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000078_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000077_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000076_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000075_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000074_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000073_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000072_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000071_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000070_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000006f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000006e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000006d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000006c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000006b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000006a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000069_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000068_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000067_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000066_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000151_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000150_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk0000014f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk0000014e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk0000014d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk0000014c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk0000014b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk0000014a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000149_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000148_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000147_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000146_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000145_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000144_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000143_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000142_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000174_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000173_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000172_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000171_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000170_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000169_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000168_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000167_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000166_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000165_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000197_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000196_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000195_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000194_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000193_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000192_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000191_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000190_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk0000018f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk0000018e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk0000018d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk0000018c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk0000018b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk0000018a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000189_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000188_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001ba_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk00000200_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001ff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001fe_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001fd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001fc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001fb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001fa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000223_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000222_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000221_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000220_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk0000021f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk0000021e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk0000021d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk0000021c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk0000021b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk0000021a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000219_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000218_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000217_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000216_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000215_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000214_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000246_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000245_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000244_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000243_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000242_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000241_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000240_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk0000023f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk0000023e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk0000023d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk0000023c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk0000023b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk0000023a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000239_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000238_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000237_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000269_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000268_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000267_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000266_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000265_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000264_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000263_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000262_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000261_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000260_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk0000025f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk0000025e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk0000025d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk0000025c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk0000025b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk0000025a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk0000028c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk0000028b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk0000028a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000289_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000288_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000287_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000286_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000285_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000284_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000283_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000282_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000281_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000280_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk0000027f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk0000027e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk0000027d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002cd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002cc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002cb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002ca_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002c9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002c8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002c7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002c6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002c5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002c4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002c3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003ab_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003aa_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a9_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a8_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a7_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a6_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a5_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a4_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a3_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a2_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a1_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a0_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk0000039f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk0000039e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk0000039d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk0000039c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk0000039b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk0000039a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ad/blk000003be_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ad/blk000003bd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ad/blk000003bc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ad/blk000003bb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ad/blk000003ba_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ad/blk000003b9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ad/blk000003b8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ad/blk000003b7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003c0/blk000003d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003c0/blk000003d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003c0/blk000003cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003c0/blk000003ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003c0/blk000003cd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003c0/blk000003cc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003c0/blk000003cb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003c0/blk000003ca_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d3/blk000003e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d3/blk000003e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d3/blk000003e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d3/blk000003e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d3/blk000003e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d3/blk000003df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d3/blk000003de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d3/blk000003dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003e6/blk000003f7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003e6/blk000003f6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003e6/blk000003f5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003e6/blk000003f4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003e6/blk000003f3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003e6/blk000003f2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003e6/blk000003f1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003e6/blk000003f0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk0000040a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000409_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000408_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000407_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000406_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000405_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000404_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000403_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000040c/blk0000041d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000040c/blk0000041c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000040c/blk0000041b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000040c/blk0000041a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000040c/blk00000419_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000040c/blk00000418_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000040c/blk00000417_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000040c/blk00000416_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041f/blk00000430_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041f/blk0000042f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041f/blk0000042e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041f/blk0000042d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041f/blk0000042c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041f/blk0000042b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041f/blk0000042a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041f/blk00000429_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000432/blk00000443_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000432/blk00000442_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000432/blk00000441_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000432/blk00000440_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000432/blk0000043f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000432/blk0000043e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000432/blk0000043d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000432/blk0000043c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000445/blk00000456_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000445/blk00000455_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000445/blk00000454_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000445/blk00000453_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000445/blk00000452_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000445/blk00000451_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000445/blk00000450_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000445/blk0000044f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000458/blk00000469_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000458/blk00000468_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000458/blk00000467_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000458/blk00000466_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000458/blk00000465_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000458/blk00000464_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000458/blk00000463_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000458/blk00000462_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000046b/blk0000047c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000046b/blk0000047b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000046b/blk0000047a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000046b/blk00000479_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000046b/blk00000478_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000046b/blk00000477_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000046b/blk00000476_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000046b/blk00000475_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000047e/blk0000048f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000047e/blk0000048e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000047e/blk0000048d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000047e/blk0000048c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000047e/blk0000048b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000047e/blk0000048a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000047e/blk00000489_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000047e/blk00000488_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk00000506_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk00000505_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk00000504_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk00000503_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk00000502_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk00000501_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk00000500_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004ff_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004fe_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004fd_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004fc_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004fb_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004fa_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004f9_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004f8_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004f7_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004f6_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004f5_SPO_UNCONNECTED ; + wire [17 : 0] coef_din_0; + wire [23 : 0] din_1_1; + wire [23 : 0] din_2_2; + wire [46 : 0] NlwRenamedSig_OI_dout_1; + wire [46 : 0] NlwRenamedSig_OI_dout_2; + assign + rfd = NlwRenamedSig_OI_rfd, + dout_1[46] = NlwRenamedSig_OI_dout_1[46], + dout_1[45] = NlwRenamedSig_OI_dout_1[45], + dout_1[44] = NlwRenamedSig_OI_dout_1[44], + dout_1[43] = NlwRenamedSig_OI_dout_1[43], + dout_1[42] = NlwRenamedSig_OI_dout_1[42], + dout_1[41] = NlwRenamedSig_OI_dout_1[41], + dout_1[40] = NlwRenamedSig_OI_dout_1[40], + dout_1[39] = NlwRenamedSig_OI_dout_1[39], + dout_1[38] = NlwRenamedSig_OI_dout_1[38], + dout_1[37] = NlwRenamedSig_OI_dout_1[37], + dout_1[36] = NlwRenamedSig_OI_dout_1[36], + dout_1[35] = NlwRenamedSig_OI_dout_1[35], + dout_1[34] = NlwRenamedSig_OI_dout_1[34], + dout_1[33] = NlwRenamedSig_OI_dout_1[33], + dout_1[32] = NlwRenamedSig_OI_dout_1[32], + dout_1[31] = NlwRenamedSig_OI_dout_1[31], + dout_1[30] = NlwRenamedSig_OI_dout_1[30], + dout_1[29] = NlwRenamedSig_OI_dout_1[29], + dout_1[28] = NlwRenamedSig_OI_dout_1[28], + dout_1[27] = NlwRenamedSig_OI_dout_1[27], + dout_1[26] = NlwRenamedSig_OI_dout_1[26], + dout_1[25] = NlwRenamedSig_OI_dout_1[25], + dout_1[24] = NlwRenamedSig_OI_dout_1[24], + dout_1[23] = NlwRenamedSig_OI_dout_1[23], + dout_1[22] = NlwRenamedSig_OI_dout_1[22], + dout_1[21] = NlwRenamedSig_OI_dout_1[21], + dout_1[20] = NlwRenamedSig_OI_dout_1[20], + dout_1[19] = NlwRenamedSig_OI_dout_1[19], + dout_1[18] = NlwRenamedSig_OI_dout_1[18], + dout_1[17] = NlwRenamedSig_OI_dout_1[17], + dout_1[16] = NlwRenamedSig_OI_dout_1[16], + dout_1[15] = NlwRenamedSig_OI_dout_1[15], + dout_1[14] = NlwRenamedSig_OI_dout_1[14], + dout_1[13] = NlwRenamedSig_OI_dout_1[13], + dout_1[12] = NlwRenamedSig_OI_dout_1[12], + dout_1[11] = NlwRenamedSig_OI_dout_1[11], + dout_1[10] = NlwRenamedSig_OI_dout_1[10], + dout_1[9] = NlwRenamedSig_OI_dout_1[9], + dout_1[8] = NlwRenamedSig_OI_dout_1[8], + dout_1[7] = NlwRenamedSig_OI_dout_1[7], + dout_1[6] = NlwRenamedSig_OI_dout_1[6], + dout_1[5] = NlwRenamedSig_OI_dout_1[5], + dout_1[4] = NlwRenamedSig_OI_dout_1[4], + dout_1[3] = NlwRenamedSig_OI_dout_1[3], + dout_1[2] = NlwRenamedSig_OI_dout_1[2], + dout_1[1] = NlwRenamedSig_OI_dout_1[1], + dout_1[0] = NlwRenamedSig_OI_dout_1[0], + dout_2[46] = NlwRenamedSig_OI_dout_2[46], + dout_2[45] = NlwRenamedSig_OI_dout_2[45], + dout_2[44] = NlwRenamedSig_OI_dout_2[44], + dout_2[43] = NlwRenamedSig_OI_dout_2[43], + dout_2[42] = NlwRenamedSig_OI_dout_2[42], + dout_2[41] = NlwRenamedSig_OI_dout_2[41], + dout_2[40] = NlwRenamedSig_OI_dout_2[40], + dout_2[39] = NlwRenamedSig_OI_dout_2[39], + dout_2[38] = NlwRenamedSig_OI_dout_2[38], + dout_2[37] = NlwRenamedSig_OI_dout_2[37], + dout_2[36] = NlwRenamedSig_OI_dout_2[36], + dout_2[35] = NlwRenamedSig_OI_dout_2[35], + dout_2[34] = NlwRenamedSig_OI_dout_2[34], + dout_2[33] = NlwRenamedSig_OI_dout_2[33], + dout_2[32] = NlwRenamedSig_OI_dout_2[32], + dout_2[31] = NlwRenamedSig_OI_dout_2[31], + dout_2[30] = NlwRenamedSig_OI_dout_2[30], + dout_2[29] = NlwRenamedSig_OI_dout_2[29], + dout_2[28] = NlwRenamedSig_OI_dout_2[28], + dout_2[27] = NlwRenamedSig_OI_dout_2[27], + dout_2[26] = NlwRenamedSig_OI_dout_2[26], + dout_2[25] = NlwRenamedSig_OI_dout_2[25], + dout_2[24] = NlwRenamedSig_OI_dout_2[24], + dout_2[23] = NlwRenamedSig_OI_dout_2[23], + dout_2[22] = NlwRenamedSig_OI_dout_2[22], + dout_2[21] = NlwRenamedSig_OI_dout_2[21], + dout_2[20] = NlwRenamedSig_OI_dout_2[20], + dout_2[19] = NlwRenamedSig_OI_dout_2[19], + dout_2[18] = NlwRenamedSig_OI_dout_2[18], + dout_2[17] = NlwRenamedSig_OI_dout_2[17], + dout_2[16] = NlwRenamedSig_OI_dout_2[16], + dout_2[15] = NlwRenamedSig_OI_dout_2[15], + dout_2[14] = NlwRenamedSig_OI_dout_2[14], + dout_2[13] = NlwRenamedSig_OI_dout_2[13], + dout_2[12] = NlwRenamedSig_OI_dout_2[12], + dout_2[11] = NlwRenamedSig_OI_dout_2[11], + dout_2[10] = NlwRenamedSig_OI_dout_2[10], + dout_2[9] = NlwRenamedSig_OI_dout_2[9], + dout_2[8] = NlwRenamedSig_OI_dout_2[8], + dout_2[7] = NlwRenamedSig_OI_dout_2[7], + dout_2[6] = NlwRenamedSig_OI_dout_2[6], + dout_2[5] = NlwRenamedSig_OI_dout_2[5], + dout_2[4] = NlwRenamedSig_OI_dout_2[4], + dout_2[3] = NlwRenamedSig_OI_dout_2[3], + dout_2[2] = NlwRenamedSig_OI_dout_2[2], + dout_2[1] = NlwRenamedSig_OI_dout_2[1], + dout_2[0] = NlwRenamedSig_OI_dout_2[0], + din_1_1[23] = din_1[23], + din_1_1[22] = din_1[22], + din_1_1[21] = din_1[21], + din_1_1[20] = din_1[20], + din_1_1[19] = din_1[19], + din_1_1[18] = din_1[18], + din_1_1[17] = din_1[17], + din_1_1[16] = din_1[16], + din_1_1[15] = din_1[15], + din_1_1[14] = din_1[14], + din_1_1[13] = din_1[13], + din_1_1[12] = din_1[12], + din_1_1[11] = din_1[11], + din_1_1[10] = din_1[10], + din_1_1[9] = din_1[9], + din_1_1[8] = din_1[8], + din_1_1[7] = din_1[7], + din_1_1[6] = din_1[6], + din_1_1[5] = din_1[5], + din_1_1[4] = din_1[4], + din_1_1[3] = din_1[3], + din_1_1[2] = din_1[2], + din_1_1[1] = din_1[1], + din_1_1[0] = din_1[0], + din_2_2[23] = din_2[23], + din_2_2[22] = din_2[22], + din_2_2[21] = din_2[21], + din_2_2[20] = din_2[20], + din_2_2[19] = din_2[19], + din_2_2[18] = din_2[18], + din_2_2[17] = din_2[17], + din_2_2[16] = din_2[16], + din_2_2[15] = din_2[15], + din_2_2[14] = din_2[14], + din_2_2[13] = din_2[13], + din_2_2[12] = din_2[12], + din_2_2[11] = din_2[11], + din_2_2[10] = din_2[10], + din_2_2[9] = din_2[9], + din_2_2[8] = din_2[8], + din_2_2[7] = din_2[7], + din_2_2[6] = din_2[6], + din_2_2[5] = din_2[5], + din_2_2[4] = din_2[4], + din_2_2[3] = din_2[3], + din_2_2[2] = din_2[2], + din_2_2[1] = din_2[1], + din_2_2[0] = din_2[0], + coef_din_0[17] = coef_din[17], + coef_din_0[16] = coef_din[16], + coef_din_0[15] = coef_din[15], + coef_din_0[14] = coef_din[14], + coef_din_0[13] = coef_din[13], + coef_din_0[12] = coef_din[12], + coef_din_0[11] = coef_din[11], + coef_din_0[10] = coef_din[10], + coef_din_0[9] = coef_din[9], + coef_din_0[8] = coef_din[8], + coef_din_0[7] = coef_din[7], + coef_din_0[6] = coef_din[6], + coef_din_0[5] = coef_din[5], + coef_din_0[4] = coef_din[4], + coef_din_0[3] = coef_din[3], + coef_din_0[2] = coef_din[2], + coef_din_0[1] = coef_din[1], + coef_din_0[0] = coef_din[0]; + VCC blk00000001 ( + .P(NLW_blk00000001_P_UNCONNECTED) + ); + GND blk00000002 ( + .G(NLW_blk00000002_G_UNCONNECTED) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000800 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093c ), + .Q(\blk00000003/sig0000080e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007ff ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000068c ), + .Q(\blk00000003/sig0000093c ), + .Q15(\NLW_blk00000003/blk000007ff_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093b ), + .Q(\blk00000003/sig000002ae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007fd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000068b ), + .Q(\blk00000003/sig0000093b ), + .Q15(\NLW_blk00000003/blk000007fd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093a ), + .Q(\blk00000003/sig00000251 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007fb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008e4 ), + .Q(\blk00000003/sig0000093a ), + .Q15(\NLW_blk00000003/blk000007fb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000939 ), + .Q(\blk00000003/sig00000250 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007f9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008e8 ), + .Q(\blk00000003/sig00000939 ), + .Q15(\NLW_blk00000003/blk000007f9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000938 ), + .Q(\blk00000003/sig0000024f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007f7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008e6 ), + .Q(\blk00000003/sig00000938 ), + .Q15(\NLW_blk00000003/blk000007f7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000937 ), + .Q(\blk00000003/sig0000024d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007f5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008e0 ), + .Q(\blk00000003/sig00000937 ), + .Q15(\NLW_blk00000003/blk000007f5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000936 ), + .Q(\blk00000003/sig0000024c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007f3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008de ), + .Q(\blk00000003/sig00000936 ), + .Q15(\NLW_blk00000003/blk000007f3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000935 ), + .Q(\blk00000003/sig0000024e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007f1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008e2 ), + .Q(\blk00000003/sig00000935 ), + .Q15(\NLW_blk00000003/blk000007f1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000934 ), + .Q(\blk00000003/sig0000024a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007ef ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008d6 ), + .Q(\blk00000003/sig00000934 ), + .Q15(\NLW_blk00000003/blk000007ef_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000933 ), + .Q(\blk00000003/sig00000249 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007ed ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008da ), + .Q(\blk00000003/sig00000933 ), + .Q15(\NLW_blk00000003/blk000007ed_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000932 ), + .Q(\blk00000003/sig0000024b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007eb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008dc ), + .Q(\blk00000003/sig00000932 ), + .Q15(\NLW_blk00000003/blk000007eb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000931 ), + .Q(\blk00000003/sig00000247 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007e9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008d0 ), + .Q(\blk00000003/sig00000931 ), + .Q15(\NLW_blk00000003/blk000007e9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000930 ), + .Q(\blk00000003/sig00000246 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007e7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008d4 ), + .Q(\blk00000003/sig00000930 ), + .Q15(\NLW_blk00000003/blk000007e7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000092f ), + .Q(\blk00000003/sig00000248 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007e5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008d8 ), + .Q(\blk00000003/sig0000092f ), + .Q15(\NLW_blk00000003/blk000007e5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000092e ), + .Q(\blk00000003/sig00000245 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007e3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008d2 ), + .Q(\blk00000003/sig0000092e ), + .Q15(\NLW_blk00000003/blk000007e3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000092d ), + .Q(\blk00000003/sig00000244 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007e1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008ca ), + .Q(\blk00000003/sig0000092d ), + .Q15(\NLW_blk00000003/blk000007e1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000092c ), + .Q(\blk00000003/sig00000243 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007df ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008ce ), + .Q(\blk00000003/sig0000092c ), + .Q15(\NLW_blk00000003/blk000007df_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007de ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000092b ), + .Q(\blk00000003/sig00000242 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007dd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008cc ), + .Q(\blk00000003/sig0000092b ), + .Q15(\NLW_blk00000003/blk000007dd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000092a ), + .Q(\blk00000003/sig00000210 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007db ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008c6 ), + .Q(\blk00000003/sig0000092a ), + .Q15(\NLW_blk00000003/blk000007db_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007da ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000929 ), + .Q(\blk00000003/sig0000020f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007d9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008c4 ), + .Q(\blk00000003/sig00000929 ), + .Q15(\NLW_blk00000003/blk000007d9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000928 ), + .Q(\blk00000003/sig00000211 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007d7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008c8 ), + .Q(\blk00000003/sig00000928 ), + .Q15(\NLW_blk00000003/blk000007d7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000927 ), + .Q(\blk00000003/sig0000020d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007d5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008bc ), + .Q(\blk00000003/sig00000927 ), + .Q15(\NLW_blk00000003/blk000007d5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000926 ), + .Q(\blk00000003/sig0000020c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007d3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008c0 ), + .Q(\blk00000003/sig00000926 ), + .Q15(\NLW_blk00000003/blk000007d3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000925 ), + .Q(\blk00000003/sig0000020e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007d1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008c2 ), + .Q(\blk00000003/sig00000925 ), + .Q15(\NLW_blk00000003/blk000007d1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000924 ), + .Q(\blk00000003/sig0000020a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007cf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008b6 ), + .Q(\blk00000003/sig00000924 ), + .Q15(\NLW_blk00000003/blk000007cf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000923 ), + .Q(\blk00000003/sig000001c9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007cd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008ba ), + .Q(\blk00000003/sig00000923 ), + .Q15(\NLW_blk00000003/blk000007cd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000922 ), + .Q(\blk00000003/sig0000020b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007cb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008be ), + .Q(\blk00000003/sig00000922 ), + .Q15(\NLW_blk00000003/blk000007cb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000921 ), + .Q(\blk00000003/sig000001c8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007c9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008b8 ), + .Q(\blk00000003/sig00000921 ), + .Q15(\NLW_blk00000003/blk000007c9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000920 ), + .Q(\blk00000003/sig000001c7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007c7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008b0 ), + .Q(\blk00000003/sig00000920 ), + .Q15(\NLW_blk00000003/blk000007c7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000091f ), + .Q(\blk00000003/sig000001c6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007c5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008b4 ), + .Q(\blk00000003/sig0000091f ), + .Q15(\NLW_blk00000003/blk000007c5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000091e ), + .Q(\blk00000003/sig000001c5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007c3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008b2 ), + .Q(\blk00000003/sig0000091e ), + .Q15(\NLW_blk00000003/blk000007c3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000091d ), + .Q(\blk00000003/sig000001c3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007c1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008ae ), + .Q(\blk00000003/sig0000091d ), + .Q15(\NLW_blk00000003/blk000007c1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000091c ), + .Q(\blk00000003/sig000001c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007bf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008ac ), + .Q(\blk00000003/sig0000091c ), + .Q15(\NLW_blk00000003/blk000007bf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000091b ), + .Q(\blk00000003/sig000001c4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007bd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008aa ), + .Q(\blk00000003/sig0000091b ), + .Q15(\NLW_blk00000003/blk000007bd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000091a ), + .Q(\blk00000003/sig000001c0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007bb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008a8 ), + .Q(\blk00000003/sig0000091a ), + .Q15(\NLW_blk00000003/blk000007bb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000919 ), + .Q(\blk00000003/sig000001bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007b9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008a6 ), + .Q(\blk00000003/sig00000919 ), + .Q15(\NLW_blk00000003/blk000007b9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000918 ), + .Q(\blk00000003/sig000001c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007b7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008a4 ), + .Q(\blk00000003/sig00000918 ), + .Q15(\NLW_blk00000003/blk000007b7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000917 ), + .Q(\blk00000003/sig000001bd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007b5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008a2 ), + .Q(\blk00000003/sig00000917 ), + .Q15(\NLW_blk00000003/blk000007b5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000916 ), + .Q(\blk00000003/sig000001bc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007b3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008a0 ), + .Q(\blk00000003/sig00000916 ), + .Q15(\NLW_blk00000003/blk000007b3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000915 ), + .Q(\blk00000003/sig000001be ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007b1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000089e ), + .Q(\blk00000003/sig00000915 ), + .Q15(\NLW_blk00000003/blk000007b1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000914 ), + .Q(\blk00000003/sig000001bb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007af ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000898 ), + .Q(\blk00000003/sig00000914 ), + .Q15(\NLW_blk00000003/blk000007af_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000913 ), + .Q(\blk00000003/sig000001ba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007ad ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000089c ), + .Q(\blk00000003/sig00000913 ), + .Q15(\NLW_blk00000003/blk000007ad_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000912 ), + .Q(\blk00000003/sig00000177 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007ab ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000089a ), + .Q(\blk00000003/sig00000912 ), + .Q15(\NLW_blk00000003/blk000007ab_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000911 ), + .Q(\blk00000003/sig00000176 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007a9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000896 ), + .Q(\blk00000003/sig00000911 ), + .Q15(\NLW_blk00000003/blk000007a9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000910 ), + .Q(\blk00000003/sig00000174 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007a7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000892 ), + .Q(\blk00000003/sig00000910 ), + .Q15(\NLW_blk00000003/blk000007a7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000090f ), + .Q(\blk00000003/sig00000173 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007a5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000890 ), + .Q(\blk00000003/sig0000090f ), + .Q15(\NLW_blk00000003/blk000007a5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000090e ), + .Q(\blk00000003/sig00000175 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007a3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000894 ), + .Q(\blk00000003/sig0000090e ), + .Q15(\NLW_blk00000003/blk000007a3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000090d ), + .Q(\blk00000003/sig00000171 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007a1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000088e ), + .Q(\blk00000003/sig0000090d ), + .Q15(\NLW_blk00000003/blk000007a1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000090c ), + .Q(\blk00000003/sig00000170 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000079f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000088c ), + .Q(\blk00000003/sig0000090c ), + .Q15(\NLW_blk00000003/blk0000079f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000090b ), + .Q(\blk00000003/sig00000172 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000079d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000088a ), + .Q(\blk00000003/sig0000090b ), + .Q15(\NLW_blk00000003/blk0000079d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000090a ), + .Q(\blk00000003/sig0000068c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000079b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002b0 ), + .Q(\blk00000003/sig0000090a ), + .Q15(\NLW_blk00000003/blk0000079b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000909 ), + .Q(\blk00000003/sig0000081a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000799 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000290 ), + .Q(\blk00000003/sig00000909 ), + .Q15(\NLW_blk00000003/blk00000799_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000798 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000908 ), + .Q(\blk00000003/sig00000819 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000797 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028f ), + .Q(\blk00000003/sig00000908 ), + .Q15(\NLW_blk00000003/blk00000797_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000796 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000907 ), + .Q(\blk00000003/sig00000818 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000795 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000291 ), + .Q(\blk00000003/sig00000907 ), + .Q15(\NLW_blk00000003/blk00000795_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000794 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000906 ), + .Q(\blk00000003/sig0000081d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000793 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028d ), + .Q(\blk00000003/sig00000906 ), + .Q15(\NLW_blk00000003/blk00000793_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000792 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000905 ), + .Q(\blk00000003/sig0000081c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000791 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028c ), + .Q(\blk00000003/sig00000905 ), + .Q15(\NLW_blk00000003/blk00000791_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000790 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000904 ), + .Q(\blk00000003/sig0000081b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000078f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028e ), + .Q(\blk00000003/sig00000904 ), + .Q15(\NLW_blk00000003/blk0000078f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000078e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000903 ), + .Q(\blk00000003/sig00000820 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000078d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028a ), + .Q(\blk00000003/sig00000903 ), + .Q15(\NLW_blk00000003/blk0000078d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000078c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000902 ), + .Q(\blk00000003/sig0000081f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000078b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000289 ), + .Q(\blk00000003/sig00000902 ), + .Q15(\NLW_blk00000003/blk0000078b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000078a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000901 ), + .Q(\blk00000003/sig0000081e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000789 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028b ), + .Q(\blk00000003/sig00000901 ), + .Q15(\NLW_blk00000003/blk00000789_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000788 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000900 ), + .Q(\blk00000003/sig00000823 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000787 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000287 ), + .Q(\blk00000003/sig00000900 ), + .Q15(\NLW_blk00000003/blk00000787_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000786 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008ff ), + .Q(\blk00000003/sig00000822 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000785 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000286 ), + .Q(\blk00000003/sig000008ff ), + .Q15(\NLW_blk00000003/blk00000785_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000784 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008fe ), + .Q(\blk00000003/sig00000821 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000783 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000288 ), + .Q(\blk00000003/sig000008fe ), + .Q15(\NLW_blk00000003/blk00000783_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000782 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008fd ), + .Q(\blk00000003/sig00000826 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000781 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000284 ), + .Q(\blk00000003/sig000008fd ), + .Q15(\NLW_blk00000003/blk00000781_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000780 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008fc ), + .Q(\blk00000003/sig00000825 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000283 ), + .Q(\blk00000003/sig000008fc ), + .Q15(\NLW_blk00000003/blk0000077f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008fb ), + .Q(\blk00000003/sig00000824 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000285 ), + .Q(\blk00000003/sig000008fb ), + .Q15(\NLW_blk00000003/blk0000077d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008fa ), + .Q(\blk00000003/sig00000828 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000209 ), + .Q(\blk00000003/sig000008fa ), + .Q15(\NLW_blk00000003/blk0000077b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f9 ), + .Q(\blk00000003/sig00000829 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000779 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000208 ), + .Q(\blk00000003/sig000008f9 ), + .Q15(\NLW_blk00000003/blk00000779_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000778 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f8 ), + .Q(\blk00000003/sig00000827 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000777 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000282 ), + .Q(\blk00000003/sig000008f8 ), + .Q15(\NLW_blk00000003/blk00000777_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000776 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f7 ), + .Q(\blk00000003/sig0000082c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000775 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000206 ), + .Q(\blk00000003/sig000008f7 ), + .Q15(\NLW_blk00000003/blk00000775_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000774 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f6 ), + .Q(\blk00000003/sig0000082b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000773 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000205 ), + .Q(\blk00000003/sig000008f6 ), + .Q15(\NLW_blk00000003/blk00000773_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000772 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f5 ), + .Q(\blk00000003/sig0000082a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000771 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000207 ), + .Q(\blk00000003/sig000008f5 ), + .Q15(\NLW_blk00000003/blk00000771_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000770 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f4 ), + .Q(\blk00000003/sig0000082d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000204 ), + .Q(\blk00000003/sig000008f4 ), + .Q15(\NLW_blk00000003/blk0000076f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f3 ), + .Q(\blk00000003/sig0000082f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000203 ), + .Q(\blk00000003/sig000008f3 ), + .Q15(\NLW_blk00000003/blk0000076d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f2 ), + .Q(\blk00000003/sig0000082e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000202 ), + .Q(\blk00000003/sig000008f2 ), + .Q15(\NLW_blk00000003/blk0000076b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f1 ), + .Q(\blk00000003/sig00000830 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000769 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000201 ), + .Q(\blk00000003/sig000008f1 ), + .Q15(\NLW_blk00000003/blk00000769_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000768 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f0 ), + .Q(\blk00000003/sig00000831 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000767 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ff ), + .Q(\blk00000003/sig000008f0 ), + .Q15(\NLW_blk00000003/blk00000767_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000766 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008ef ), + .Q(\blk00000003/sig00000833 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000765 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fe ), + .Q(\blk00000003/sig000008ef ), + .Q15(\NLW_blk00000003/blk00000765_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000764 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008ee ), + .Q(\blk00000003/sig00000832 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000763 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000200 ), + .Q(\blk00000003/sig000008ee ), + .Q15(\NLW_blk00000003/blk00000763_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000762 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008ed ), + .Q(\blk00000003/sig00000834 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000761 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fc ), + .Q(\blk00000003/sig000008ed ), + .Q15(\NLW_blk00000003/blk00000761_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000760 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008ec ), + .Q(\blk00000003/sig00000836 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000075f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fb ), + .Q(\blk00000003/sig000008ec ), + .Q15(\NLW_blk00000003/blk0000075f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008eb ), + .Q(\blk00000003/sig00000835 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000075d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fd ), + .Q(\blk00000003/sig000008eb ), + .Q15(\NLW_blk00000003/blk0000075d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008ea ), + .Q(\blk00000003/sig00000837 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000075b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fa ), + .Q(\blk00000003/sig000008ea ), + .Q15(\NLW_blk00000003/blk0000075b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008e9 ), + .Q(\blk00000003/sig0000080f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000759 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000294 ), + .Q(\blk00000003/sig000008e9 ), + .Q15(\NLW_blk00000003/blk00000759_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008e7 ), + .Q(\blk00000003/sig000008e8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000757 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e7 ), + .Q(\blk00000003/sig000008e7 ), + .Q15(\NLW_blk00000003/blk00000757_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000756 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008e5 ), + .Q(\blk00000003/sig000008e6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000755 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e6 ), + .Q(\blk00000003/sig000008e5 ), + .Q15(\NLW_blk00000003/blk00000755_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000754 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008e3 ), + .Q(\blk00000003/sig000008e4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000753 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e8 ), + .Q(\blk00000003/sig000008e3 ), + .Q15(\NLW_blk00000003/blk00000753_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000752 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008e1 ), + .Q(\blk00000003/sig000008e2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000751 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e5 ), + .Q(\blk00000003/sig000008e1 ), + .Q15(\NLW_blk00000003/blk00000751_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000750 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008df ), + .Q(\blk00000003/sig000008e0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000074f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e4 ), + .Q(\blk00000003/sig000008df ), + .Q15(\NLW_blk00000003/blk0000074f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074e ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008dd ), + .Q(\blk00000003/sig000008de ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000074d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e3 ), + .Q(\blk00000003/sig000008dd ), + .Q15(\NLW_blk00000003/blk0000074d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074c ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008db ), + .Q(\blk00000003/sig000008dc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000074b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e2 ), + .Q(\blk00000003/sig000008db ), + .Q15(\NLW_blk00000003/blk0000074b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074a ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008d9 ), + .Q(\blk00000003/sig000008da ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000749 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e0 ), + .Q(\blk00000003/sig000008d9 ), + .Q15(\NLW_blk00000003/blk00000749_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000748 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008d7 ), + .Q(\blk00000003/sig000008d8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000747 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002df ), + .Q(\blk00000003/sig000008d7 ), + .Q15(\NLW_blk00000003/blk00000747_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000746 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008d5 ), + .Q(\blk00000003/sig000008d6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e1 ), + .Q(\blk00000003/sig000008d5 ), + .Q15(\NLW_blk00000003/blk00000745_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000744 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008d3 ), + .Q(\blk00000003/sig000008d4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000743 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002dd ), + .Q(\blk00000003/sig000008d3 ), + .Q15(\NLW_blk00000003/blk00000743_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000742 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008d1 ), + .Q(\blk00000003/sig000008d2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000741 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002dc ), + .Q(\blk00000003/sig000008d1 ), + .Q15(\NLW_blk00000003/blk00000741_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000740 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008cf ), + .Q(\blk00000003/sig000008d0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000073f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002de ), + .Q(\blk00000003/sig000008cf ), + .Q15(\NLW_blk00000003/blk0000073f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073e ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008cd ), + .Q(\blk00000003/sig000008ce ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000073d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002da ), + .Q(\blk00000003/sig000008cd ), + .Q15(\NLW_blk00000003/blk0000073d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073c ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008cb ), + .Q(\blk00000003/sig000008cc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000073b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d9 ), + .Q(\blk00000003/sig000008cb ), + .Q15(\NLW_blk00000003/blk0000073b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073a ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008c9 ), + .Q(\blk00000003/sig000008ca ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000739 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002db ), + .Q(\blk00000003/sig000008c9 ), + .Q15(\NLW_blk00000003/blk00000739_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000738 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008c7 ), + .Q(\blk00000003/sig000008c8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000737 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d8 ), + .Q(\blk00000003/sig000008c7 ), + .Q15(\NLW_blk00000003/blk00000737_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000736 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008c5 ), + .Q(\blk00000003/sig000008c6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000735 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d7 ), + .Q(\blk00000003/sig000008c5 ), + .Q15(\NLW_blk00000003/blk00000735_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000734 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008c3 ), + .Q(\blk00000003/sig000008c4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000733 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d6 ), + .Q(\blk00000003/sig000008c3 ), + .Q15(\NLW_blk00000003/blk00000733_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008c1 ), + .Q(\blk00000003/sig000008c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000731 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d5 ), + .Q(\blk00000003/sig000008c1 ), + .Q15(\NLW_blk00000003/blk00000731_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000730 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008bf ), + .Q(\blk00000003/sig000008c0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000072f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d3 ), + .Q(\blk00000003/sig000008bf ), + .Q15(\NLW_blk00000003/blk0000072f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072e ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008bd ), + .Q(\blk00000003/sig000008be ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000072d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d2 ), + .Q(\blk00000003/sig000008bd ), + .Q15(\NLW_blk00000003/blk0000072d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072c ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008bb ), + .Q(\blk00000003/sig000008bc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000072b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d4 ), + .Q(\blk00000003/sig000008bb ), + .Q15(\NLW_blk00000003/blk0000072b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072a ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008b9 ), + .Q(\blk00000003/sig000008ba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000729 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d0 ), + .Q(\blk00000003/sig000008b9 ), + .Q15(\NLW_blk00000003/blk00000729_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000728 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008b7 ), + .Q(\blk00000003/sig000008b8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000727 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002cf ), + .Q(\blk00000003/sig000008b7 ), + .Q15(\NLW_blk00000003/blk00000727_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000726 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008b5 ), + .Q(\blk00000003/sig000008b6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000725 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d1 ), + .Q(\blk00000003/sig000008b5 ), + .Q15(\NLW_blk00000003/blk00000725_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000724 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008b3 ), + .Q(\blk00000003/sig000008b4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000723 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002cd ), + .Q(\blk00000003/sig000008b3 ), + .Q15(\NLW_blk00000003/blk00000723_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000722 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008b1 ), + .Q(\blk00000003/sig000008b2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000721 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002cc ), + .Q(\blk00000003/sig000008b1 ), + .Q15(\NLW_blk00000003/blk00000721_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000720 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008af ), + .Q(\blk00000003/sig000008b0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002ce ), + .Q(\blk00000003/sig000008af ), + .Q15(\NLW_blk00000003/blk0000071f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071e ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008ad ), + .Q(\blk00000003/sig000008ae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002ca ), + .Q(\blk00000003/sig000008ad ), + .Q15(\NLW_blk00000003/blk0000071d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071c ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008ab ), + .Q(\blk00000003/sig000008ac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c9 ), + .Q(\blk00000003/sig000008ab ), + .Q15(\NLW_blk00000003/blk0000071b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071a ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008a9 ), + .Q(\blk00000003/sig000008aa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000719 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002cb ), + .Q(\blk00000003/sig000008a9 ), + .Q15(\NLW_blk00000003/blk00000719_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000718 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008a7 ), + .Q(\blk00000003/sig000008a8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000717 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c7 ), + .Q(\blk00000003/sig000008a7 ), + .Q15(\NLW_blk00000003/blk00000717_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000716 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008a5 ), + .Q(\blk00000003/sig000008a6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000715 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c6 ), + .Q(\blk00000003/sig000008a5 ), + .Q15(\NLW_blk00000003/blk00000715_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000714 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008a3 ), + .Q(\blk00000003/sig000008a4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000713 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c8 ), + .Q(\blk00000003/sig000008a3 ), + .Q15(\NLW_blk00000003/blk00000713_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000712 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008a1 ), + .Q(\blk00000003/sig000008a2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000711 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c4 ), + .Q(\blk00000003/sig000008a1 ), + .Q15(\NLW_blk00000003/blk00000711_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000710 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig0000089f ), + .Q(\blk00000003/sig000008a0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c3 ), + .Q(\blk00000003/sig0000089f ), + .Q15(\NLW_blk00000003/blk0000070f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070e ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig0000089d ), + .Q(\blk00000003/sig0000089e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c5 ), + .Q(\blk00000003/sig0000089d ), + .Q15(\NLW_blk00000003/blk0000070d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig0000089b ), + .Q(\blk00000003/sig0000089c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c1 ), + .Q(\blk00000003/sig0000089b ), + .Q15(\NLW_blk00000003/blk0000070b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070a ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig00000899 ), + .Q(\blk00000003/sig0000089a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000709 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c0 ), + .Q(\blk00000003/sig00000899 ), + .Q15(\NLW_blk00000003/blk00000709_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000708 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig00000897 ), + .Q(\blk00000003/sig00000898 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000707 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig00000897 ), + .Q15(\NLW_blk00000003/blk00000707_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000706 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig00000895 ), + .Q(\blk00000003/sig00000896 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000705 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002bf ), + .Q(\blk00000003/sig00000895 ), + .Q15(\NLW_blk00000003/blk00000705_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000704 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig00000893 ), + .Q(\blk00000003/sig00000894 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000703 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002be ), + .Q(\blk00000003/sig00000893 ), + .Q15(\NLW_blk00000003/blk00000703_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000702 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig00000891 ), + .Q(\blk00000003/sig00000892 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000701 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002bd ), + .Q(\blk00000003/sig00000891 ), + .Q15(\NLW_blk00000003/blk00000701_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000700 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig0000088f ), + .Q(\blk00000003/sig00000890 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ff ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002bc ), + .Q(\blk00000003/sig0000088f ), + .Q15(\NLW_blk00000003/blk000006ff_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006fe ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig0000088d ), + .Q(\blk00000003/sig0000088e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006fd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002ba ), + .Q(\blk00000003/sig0000088d ), + .Q15(\NLW_blk00000003/blk000006fd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006fc ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig0000088b ), + .Q(\blk00000003/sig0000088c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006fb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002b9 ), + .Q(\blk00000003/sig0000088b ), + .Q15(\NLW_blk00000003/blk000006fb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006fa ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig00000889 ), + .Q(\blk00000003/sig0000088a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002bb ), + .Q(\blk00000003/sig00000889 ), + .Q15(\NLW_blk00000003/blk000006f9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000888 ), + .Q(\blk00000003/sig00000816 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000067b ), + .Q(\blk00000003/sig00000888 ), + .Q15(\NLW_blk00000003/blk000006f7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000887 ), + .Q(\blk00000003/sig000006dc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f5 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e8 ), + .Q(\blk00000003/sig00000887 ), + .Q15(\NLW_blk00000003/blk000006f5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000886 ), + .Q(\blk00000003/sig00000815 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000067c ), + .Q(\blk00000003/sig00000886 ), + .Q15(\NLW_blk00000003/blk000006f3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000885 ), + .Q(\blk00000003/sig000006da ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f1 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e6 ), + .Q(\blk00000003/sig00000885 ), + .Q15(\NLW_blk00000003/blk000006f1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000884 ), + .Q(\blk00000003/sig000006d9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ef ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e5 ), + .Q(\blk00000003/sig00000884 ), + .Q15(\NLW_blk00000003/blk000006ef_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000883 ), + .Q(\blk00000003/sig000006db ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ed ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e7 ), + .Q(\blk00000003/sig00000883 ), + .Q15(\NLW_blk00000003/blk000006ed_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000882 ), + .Q(\blk00000003/sig000006d8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006eb ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e4 ), + .Q(\blk00000003/sig00000882 ), + .Q15(\NLW_blk00000003/blk000006eb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000881 ), + .Q(\blk00000003/sig000006d7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e9 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e3 ), + .Q(\blk00000003/sig00000881 ), + .Q15(\NLW_blk00000003/blk000006e9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000880 ), + .Q(\blk00000003/sig000006d6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e7 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e2 ), + .Q(\blk00000003/sig00000880 ), + .Q15(\NLW_blk00000003/blk000006e7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000087f ), + .Q(\blk00000003/sig000006d5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e5 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e1 ), + .Q(\blk00000003/sig0000087f ), + .Q15(\NLW_blk00000003/blk000006e5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000087e ), + .Q(\blk00000003/sig000006d3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e3 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002df ), + .Q(\blk00000003/sig0000087e ), + .Q15(\NLW_blk00000003/blk000006e3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000087d ), + .Q(\blk00000003/sig000006d2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e1 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002de ), + .Q(\blk00000003/sig0000087d ), + .Q15(\NLW_blk00000003/blk000006e1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000087c ), + .Q(\blk00000003/sig000006d4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006df ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e0 ), + .Q(\blk00000003/sig0000087c ), + .Q15(\NLW_blk00000003/blk000006df_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006de ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000087b ), + .Q(\blk00000003/sig000006d0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006dd ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002dc ), + .Q(\blk00000003/sig0000087b ), + .Q15(\NLW_blk00000003/blk000006dd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000087a ), + .Q(\blk00000003/sig000006cf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006db ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002db ), + .Q(\blk00000003/sig0000087a ), + .Q15(\NLW_blk00000003/blk000006db_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006da ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000879 ), + .Q(\blk00000003/sig000006d1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d9 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002dd ), + .Q(\blk00000003/sig00000879 ), + .Q15(\NLW_blk00000003/blk000006d9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000878 ), + .Q(\blk00000003/sig000006cd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d7 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d9 ), + .Q(\blk00000003/sig00000878 ), + .Q15(\NLW_blk00000003/blk000006d7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000877 ), + .Q(\blk00000003/sig0000076c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d5 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d8 ), + .Q(\blk00000003/sig00000877 ), + .Q15(\NLW_blk00000003/blk000006d5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000876 ), + .Q(\blk00000003/sig000006ce ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002da ), + .Q(\blk00000003/sig00000876 ), + .Q15(\NLW_blk00000003/blk000006d3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000875 ), + .Q(\blk00000003/sig0000076b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d1 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d7 ), + .Q(\blk00000003/sig00000875 ), + .Q15(\NLW_blk00000003/blk000006d1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000874 ), + .Q(\blk00000003/sig0000076a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006cf ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d6 ), + .Q(\blk00000003/sig00000874 ), + .Q15(\NLW_blk00000003/blk000006cf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000873 ), + .Q(\blk00000003/sig00000769 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006cd ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d5 ), + .Q(\blk00000003/sig00000873 ), + .Q15(\NLW_blk00000003/blk000006cd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000872 ), + .Q(\blk00000003/sig00000768 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006cb ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d4 ), + .Q(\blk00000003/sig00000872 ), + .Q15(\NLW_blk00000003/blk000006cb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000871 ), + .Q(\blk00000003/sig00000766 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c9 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d2 ), + .Q(\blk00000003/sig00000871 ), + .Q15(\NLW_blk00000003/blk000006c9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000870 ), + .Q(\blk00000003/sig00000765 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c7 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d1 ), + .Q(\blk00000003/sig00000870 ), + .Q15(\NLW_blk00000003/blk000006c7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000086f ), + .Q(\blk00000003/sig00000767 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c5 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d3 ), + .Q(\blk00000003/sig0000086f ), + .Q15(\NLW_blk00000003/blk000006c5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000086e ), + .Q(\blk00000003/sig000006fb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c3 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002cf ), + .Q(\blk00000003/sig0000086e ), + .Q15(\NLW_blk00000003/blk000006c3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000086d ), + .Q(\blk00000003/sig000006fa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c1 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002ce ), + .Q(\blk00000003/sig0000086d ), + .Q15(\NLW_blk00000003/blk000006c1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000086c ), + .Q(\blk00000003/sig000006fc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006bf ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d0 ), + .Q(\blk00000003/sig0000086c ), + .Q15(\NLW_blk00000003/blk000006bf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000086b ), + .Q(\blk00000003/sig000006f8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006bd ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002cc ), + .Q(\blk00000003/sig0000086b ), + .Q15(\NLW_blk00000003/blk000006bd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000086a ), + .Q(\blk00000003/sig000006f7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006bb ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002cb ), + .Q(\blk00000003/sig0000086a ), + .Q15(\NLW_blk00000003/blk000006bb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000869 ), + .Q(\blk00000003/sig000006f9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b9 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002cd ), + .Q(\blk00000003/sig00000869 ), + .Q15(\NLW_blk00000003/blk000006b9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000868 ), + .Q(\blk00000003/sig000006f6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b7 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002ca ), + .Q(\blk00000003/sig00000868 ), + .Q15(\NLW_blk00000003/blk000006b7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000867 ), + .Q(\blk00000003/sig000006f5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b5 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c9 ), + .Q(\blk00000003/sig00000867 ), + .Q15(\NLW_blk00000003/blk000006b5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000866 ), + .Q(\blk00000003/sig000006f4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b3 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c8 ), + .Q(\blk00000003/sig00000866 ), + .Q15(\NLW_blk00000003/blk000006b3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000865 ), + .Q(\blk00000003/sig000006f3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b1 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c7 ), + .Q(\blk00000003/sig00000865 ), + .Q15(\NLW_blk00000003/blk000006b1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000864 ), + .Q(\blk00000003/sig000006f1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006af ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c5 ), + .Q(\blk00000003/sig00000864 ), + .Q15(\NLW_blk00000003/blk000006af_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000863 ), + .Q(\blk00000003/sig000006f0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c4 ), + .Q(\blk00000003/sig00000863 ), + .Q15(\NLW_blk00000003/blk000006ad_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000862 ), + .Q(\blk00000003/sig000006f2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ab ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c6 ), + .Q(\blk00000003/sig00000862 ), + .Q15(\NLW_blk00000003/blk000006ab_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000861 ), + .Q(\blk00000003/sig000006ee ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a9 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig00000861 ), + .Q15(\NLW_blk00000003/blk000006a9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000860 ), + .Q(\blk00000003/sig000006ed ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a7 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c1 ), + .Q(\blk00000003/sig00000860 ), + .Q15(\NLW_blk00000003/blk000006a7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000085f ), + .Q(\blk00000003/sig000006ef ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a5 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c3 ), + .Q(\blk00000003/sig0000085f ), + .Q15(\NLW_blk00000003/blk000006a5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000085e ), + .Q(\blk00000003/sig0000077b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a3 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002bf ), + .Q(\blk00000003/sig0000085e ), + .Q15(\NLW_blk00000003/blk000006a3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000085d ), + .Q(\blk00000003/sig0000077a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a1 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002be ), + .Q(\blk00000003/sig0000085d ), + .Q15(\NLW_blk00000003/blk000006a1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000085c ), + .Q(\blk00000003/sig0000077c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069f ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c0 ), + .Q(\blk00000003/sig0000085c ), + .Q15(\NLW_blk00000003/blk0000069f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000085b ), + .Q(\blk00000003/sig00000779 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069d ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002bd ), + .Q(\blk00000003/sig0000085b ), + .Q15(\NLW_blk00000003/blk0000069d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000085a ), + .Q(\blk00000003/sig00000778 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069b ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002bc ), + .Q(\blk00000003/sig0000085a ), + .Q15(\NLW_blk00000003/blk0000069b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000859 ), + .Q(\blk00000003/sig00000777 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000699 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002bb ), + .Q(\blk00000003/sig00000859 ), + .Q15(\NLW_blk00000003/blk00000699_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000698 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000858 ), + .Q(\blk00000003/sig00000776 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000697 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002ba ), + .Q(\blk00000003/sig00000858 ), + .Q15(\NLW_blk00000003/blk00000697_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000696 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000857 ), + .Q(\blk00000003/sig00000397 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000695 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002a5 ), + .Q(\blk00000003/sig00000857 ), + .Q15(\NLW_blk00000003/blk00000695_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000694 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000856 ), + .Q(\blk00000003/sig00000398 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000693 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000037e ), + .Q(\blk00000003/sig00000856 ), + .Q15(\NLW_blk00000003/blk00000693_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000692 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000855 ), + .Q(\blk00000003/sig00000775 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000691 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002b9 ), + .Q(\blk00000003/sig00000855 ), + .Q15(\NLW_blk00000003/blk00000691_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000690 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000854 ), + .Q(\blk00000003/sig0000071e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000068f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[0]), + .Q(\blk00000003/sig00000854 ), + .Q15(\NLW_blk00000003/blk0000068f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000068e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000853 ), + .Q(\blk00000003/sig0000071d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000068d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[1]), + .Q(\blk00000003/sig00000853 ), + .Q15(\NLW_blk00000003/blk0000068d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000068c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000852 ), + .Q(\blk00000003/sig00000814 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000068b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002a1 ), + .Q(\blk00000003/sig00000852 ), + .Q15(\NLW_blk00000003/blk0000068b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000068a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000851 ), + .Q(\blk00000003/sig0000071b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000689 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[3]), + .Q(\blk00000003/sig00000851 ), + .Q15(\NLW_blk00000003/blk00000689_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000688 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000850 ), + .Q(\blk00000003/sig0000071a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[4]), + .Q(\blk00000003/sig00000850 ), + .Q15(\NLW_blk00000003/blk00000687_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000686 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000084f ), + .Q(\blk00000003/sig0000071c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000685 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[2]), + .Q(\blk00000003/sig0000084f ), + .Q15(\NLW_blk00000003/blk00000685_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000684 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000084e ), + .Q(\blk00000003/sig00000719 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000683 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[5]), + .Q(\blk00000003/sig0000084e ), + .Q15(\NLW_blk00000003/blk00000683_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000682 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000084d ), + .Q(\blk00000003/sig00000718 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000681 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[6]), + .Q(\blk00000003/sig0000084d ), + .Q15(\NLW_blk00000003/blk00000681_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000680 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000084c ), + .Q(\blk00000003/sig00000717 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000067f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[7]), + .Q(\blk00000003/sig0000084c ), + .Q15(\NLW_blk00000003/blk0000067f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000067e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000084b ), + .Q(\blk00000003/sig00000716 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000067d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[8]), + .Q(\blk00000003/sig0000084b ), + .Q15(\NLW_blk00000003/blk0000067d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000067c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000084a ), + .Q(\blk00000003/sig00000714 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000067b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[10]), + .Q(\blk00000003/sig0000084a ), + .Q15(\NLW_blk00000003/blk0000067b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000067a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000849 ), + .Q(\blk00000003/sig00000713 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000679 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[11]), + .Q(\blk00000003/sig00000849 ), + .Q15(\NLW_blk00000003/blk00000679_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000678 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000848 ), + .Q(\blk00000003/sig00000715 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000677 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[9]), + .Q(\blk00000003/sig00000848 ), + .Q15(\NLW_blk00000003/blk00000677_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000676 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000847 ), + .Q(\blk00000003/sig00000711 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000675 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[13]), + .Q(\blk00000003/sig00000847 ), + .Q15(\NLW_blk00000003/blk00000675_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000846 ), + .Q(\blk00000003/sig00000710 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000673 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[14]), + .Q(\blk00000003/sig00000846 ), + .Q15(\NLW_blk00000003/blk00000673_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000672 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000845 ), + .Q(\blk00000003/sig00000712 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000671 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[12]), + .Q(\blk00000003/sig00000845 ), + .Q15(\NLW_blk00000003/blk00000671_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000670 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000844 ), + .Q(\blk00000003/sig0000070e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000066f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[16]), + .Q(\blk00000003/sig00000844 ), + .Q15(\NLW_blk00000003/blk0000066f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000066e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000843 ), + .Q(\blk00000003/sig0000070d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000066d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[17]), + .Q(\blk00000003/sig00000843 ), + .Q15(\NLW_blk00000003/blk0000066d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000066c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000842 ), + .Q(\blk00000003/sig0000070f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000066b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[15]), + .Q(\blk00000003/sig00000842 ), + .Q15(\NLW_blk00000003/blk0000066b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000066a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000841 ), + .Q(\blk00000003/sig000002b0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000669 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002b2 ), + .Q(\blk00000003/sig00000841 ), + .Q15(\NLW_blk00000003/blk00000669_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000668 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000840 ), + .Q(\blk00000003/sig0000068b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000667 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002a7 ), + .Q(\blk00000003/sig00000840 ), + .Q15(\NLW_blk00000003/blk00000667_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000666 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000083f ), + .Q(\blk00000003/sig00000786 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000665 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000029f ), + .Q(\blk00000003/sig0000083f ), + .Q15(\NLW_blk00000003/blk00000665_Q15_UNCONNECTED ) + ); + INV \blk00000003/blk00000664 ( + .I(\blk00000003/sig00000313 ), + .O(\blk00000003/sig00000353 ) + ); + INV \blk00000003/blk00000663 ( + .I(\blk00000003/sig0000035c ), + .O(\blk00000003/sig0000034c ) + ); + INV \blk00000003/blk00000662 ( + .I(\blk00000003/sig00000363 ), + .O(\blk00000003/sig00000352 ) + ); + INV \blk00000003/blk00000661 ( + .I(\blk00000003/sig0000029f ), + .O(\blk00000003/sig00000361 ) + ); + INV \blk00000003/blk00000660 ( + .I(\blk00000003/sig00000795 ), + .O(\blk00000003/sig0000080d ) + ); + INV \blk00000003/blk0000065f ( + .I(\blk00000003/sig00000317 ), + .O(\blk00000003/sig00000364 ) + ); + INV \blk00000003/blk0000065e ( + .I(\blk00000003/sig00000313 ), + .O(\blk00000003/sig0000034d ) + ); + INV \blk00000003/blk0000065d ( + .I(\blk00000003/sig000002ec ), + .O(\blk00000003/sig00000318 ) + ); + INV \blk00000003/blk0000065c ( + .I(\blk00000003/sig0000029d ), + .O(\blk00000003/sig00000166 ) + ); + INV \blk00000003/blk0000065b ( + .I(\blk00000003/sig00000159 ), + .O(\blk00000003/sig00000297 ) + ); + INV \blk00000003/blk0000065a ( + .I(\blk00000003/sig00000163 ), + .O(\blk00000003/sig00000164 ) + ); + LUT3 #( + .INIT ( 8'h40 )) + \blk00000003/blk00000659 ( + .I0(\blk00000003/sig00000320 ), + .I1(\blk00000003/sig00000309 ), + .I2(coef_ld), + .O(\blk00000003/sig0000031c ) + ); + LUT5 #( + .INIT ( 32'h4F444444 )) + \blk00000003/blk00000658 ( + .I0(\blk00000003/sig0000031d ), + .I1(\blk00000003/sig00000311 ), + .I2(\blk00000003/sig00000320 ), + .I3(coef_ld), + .I4(\blk00000003/sig00000309 ), + .O(\blk00000003/sig00000314 ) + ); + LUT4 #( + .INIT ( 16'h1000 )) + \blk00000003/blk00000657 ( + .I0(coef_ld), + .I1(\blk00000003/sig0000030b ), + .I2(coef_we), + .I3(\blk00000003/sig00000309 ), + .O(\blk00000003/sig0000031b ) + ); + LUT5 #( + .INIT ( 32'h20AA2020 )) + \blk00000003/blk00000656 ( + .I0(\blk00000003/sig00000309 ), + .I1(\blk00000003/sig0000030b ), + .I2(coef_we), + .I3(\blk00000003/sig00000320 ), + .I4(coef_ld), + .O(\blk00000003/sig0000031a ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk00000655 ( + .I0(\blk00000003/sig0000035c ), + .I1(ce), + .I2(\blk00000003/sig00000311 ), + .I3(\blk00000003/sig000002ea ), + .O(\blk00000003/sig0000083e ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk00000654 ( + .I0(\blk00000003/sig00000363 ), + .I1(ce), + .I2(\blk00000003/sig0000030f ), + .I3(\blk00000003/sig00000354 ), + .O(\blk00000003/sig0000083d ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk00000653 ( + .I0(\blk00000003/sig00000810 ), + .I1(ce), + .I2(\blk00000003/sig000002a5 ), + .I3(\blk00000003/sig000002a7 ), + .O(\blk00000003/sig0000083b ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk00000652 ( + .I0(ce), + .I1(sclr), + .I2(\blk00000003/sig00000813 ), + .O(\blk00000003/sig0000083a ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk00000651 ( + .I0(ce), + .I1(\blk00000003/sig00000320 ), + .I2(\blk00000003/sig00000811 ), + .O(\blk00000003/sig00000839 ) + ); + LUT5 #( + .INIT ( 32'h6AAAAAAA )) + \blk00000003/blk00000650 ( + .I0(\blk00000003/sig00000812 ), + .I1(\blk00000003/sig00000366 ), + .I2(ce), + .I3(nd), + .I4(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig0000083c ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk0000064f ( + .C(clk), + .D(\blk00000003/sig0000083e ), + .Q(\blk00000003/sig0000035c ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk0000064e ( + .C(clk), + .D(\blk00000003/sig0000083d ), + .Q(\blk00000003/sig00000363 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064d ( + .C(clk), + .D(\blk00000003/sig0000083c ), + .R(sclr), + .Q(\blk00000003/sig00000812 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064c ( + .C(clk), + .D(\blk00000003/sig0000083b ), + .R(sclr), + .Q(\blk00000003/sig00000810 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000064b ( + .I0(\blk00000003/sig00000798 ), + .O(\blk00000003/sig00000793 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000064a ( + .I0(\blk00000003/sig00000797 ), + .O(\blk00000003/sig00000790 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000649 ( + .I0(\blk00000003/sig00000796 ), + .O(\blk00000003/sig0000078d ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000648 ( + .I0(\blk00000003/sig00000795 ), + .O(\blk00000003/sig0000078a ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000647 ( + .I0(\blk00000003/sig00000394 ), + .O(\blk00000003/sig00000395 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000646 ( + .I0(\blk00000003/sig00000390 ), + .O(\blk00000003/sig00000391 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000645 ( + .I0(\blk00000003/sig0000037c ), + .O(\blk00000003/sig00000376 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000644 ( + .I0(\blk00000003/sig00000812 ), + .O(\blk00000003/sig0000036c ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000643 ( + .I0(\blk00000003/sig0000033d ), + .O(\blk00000003/sig0000033e ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000642 ( + .I0(\blk00000003/sig00000339 ), + .O(\blk00000003/sig0000033a ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000641 ( + .I0(\blk00000003/sig0000032b ), + .O(\blk00000003/sig00000329 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000640 ( + .I0(\blk00000003/sig00000324 ), + .O(\blk00000003/sig00000322 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk0000063f ( + .I0(\blk00000003/sig00000324 ), + .I1(\blk00000003/sig00000327 ), + .O(\blk00000003/sig000002fd ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000063e ( + .I0(\blk00000003/sig0000029d ), + .O(\blk00000003/sig00000167 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000807 ), + .R(sclr), + .Q(\blk00000003/sig0000080c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000804 ), + .R(sclr), + .Q(\blk00000003/sig0000080b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000801 ), + .R(sclr), + .Q(\blk00000003/sig0000080a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007fe ), + .R(sclr), + .Q(\blk00000003/sig00000809 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000639 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007fb ), + .R(sclr), + .Q(\blk00000003/sig00000808 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000638 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000788 ), + .R(sclr), + .Q(\blk00000003/sig00000799 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000637 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000794 ), + .R(sclr), + .Q(\blk00000003/sig00000798 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000636 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000791 ), + .R(sclr), + .Q(\blk00000003/sig00000797 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000635 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000078e ), + .R(sclr), + .Q(\blk00000003/sig00000796 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000634 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000078b ), + .S(sclr), + .Q(\blk00000003/sig00000795 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000633 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000396 ), + .R(\blk00000003/sig00000399 ), + .Q(\blk00000003/sig00000394 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000632 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000393 ), + .R(\blk00000003/sig00000399 ), + .Q(\blk00000003/sig00000390 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000631 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000389 ), + .S(\blk00000003/sig00000398 ), + .Q(\blk00000003/sig0000038e ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000630 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000038c ), + .S(\blk00000003/sig00000398 ), + .Q(\blk00000003/sig0000038d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000381 ), + .R(\blk00000003/sig00000398 ), + .Q(\blk00000003/sig00000387 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000384 ), + .R(\blk00000003/sig00000398 ), + .Q(\blk00000003/sig00000386 ) + ); + FDR \blk00000003/blk0000062d ( + .C(clk), + .D(\blk00000003/sig0000083a ), + .R(ce), + .Q(\blk00000003/sig00000813 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000062c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000377 ), + .S(sclr), + .Q(\blk00000003/sig0000037c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000037a ), + .R(sclr), + .Q(\blk00000003/sig0000037b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000371 ), + .R(sclr), + .Q(\blk00000003/sig000002b8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000629 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000374 ), + .R(sclr), + .Q(\blk00000003/sig000002b7 ) + ); + FDR \blk00000003/blk00000628 ( + .C(clk), + .D(\blk00000003/sig00000839 ), + .R(ce), + .Q(\blk00000003/sig00000811 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000627 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000033f ), + .R(\blk00000003/sig00000342 ), + .Q(\blk00000003/sig0000033d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000626 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000033c ), + .R(\blk00000003/sig00000342 ), + .Q(\blk00000003/sig00000339 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000625 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000331 ), + .R(coef_ld), + .Q(\blk00000003/sig00000337 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000624 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000334 ), + .R(coef_ld), + .Q(\blk00000003/sig00000336 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000623 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000032d ), + .R(sclr), + .Q(\blk00000003/sig0000032e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000622 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000032a ), + .R(sclr), + .Q(\blk00000003/sig0000032b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000326 ), + .R(coef_ld), + .Q(\blk00000003/sig00000327 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000620 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000323 ), + .R(coef_ld), + .Q(\blk00000003/sig00000324 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk0000061f ( + .I0(\blk00000003/sig00000163 ), + .I1(sclr), + .O(\blk00000003/sig00000838 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk0000061e ( + .C(clk), + .D(\blk00000003/sig00000838 ), + .Q(\blk00000003/sig00000163 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000061d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000015b ), + .R(sclr), + .Q(\blk00000003/sig00000159 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk0000061c ( + .I0(\blk00000003/sig00000808 ), + .I1(\blk00000003/sig00000795 ), + .O(\blk00000003/sig000007fa ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk0000061b ( + .I0(\blk00000003/sig00000809 ), + .I1(\blk00000003/sig00000795 ), + .O(\blk00000003/sig000007fd ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk0000061a ( + .I0(\blk00000003/sig0000080a ), + .I1(\blk00000003/sig00000795 ), + .O(\blk00000003/sig00000800 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000619 ( + .I0(\blk00000003/sig0000080b ), + .I1(\blk00000003/sig00000795 ), + .O(\blk00000003/sig00000803 ) + ); + LUT3 #( + .INIT ( 8'hDE )) + \blk00000003/blk00000618 ( + .I0(\blk00000003/sig0000080c ), + .I1(\blk00000003/sig00000795 ), + .I2(\blk00000003/sig000002ae ), + .O(\blk00000003/sig00000806 ) + ); + LUT3 #( + .INIT ( 8'h04 )) + \blk00000003/blk00000617 ( + .I0(\blk00000003/sig000002ae ), + .I1(\blk00000003/sig0000004a ), + .I2(\blk00000003/sig00000795 ), + .O(\blk00000003/sig000007f8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000616 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000df ), + .I3(NlwRenamedSig_OI_dout_2[45]), + .O(\blk00000003/sig000007f6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000615 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000de ), + .I3(NlwRenamedSig_OI_dout_2[46]), + .O(\blk00000003/sig000007f7 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000614 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e0 ), + .I3(NlwRenamedSig_OI_dout_2[44]), + .O(\blk00000003/sig000007f5 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000613 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e2 ), + .I3(NlwRenamedSig_OI_dout_2[42]), + .O(\blk00000003/sig000007f3 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000612 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e1 ), + .I3(NlwRenamedSig_OI_dout_2[43]), + .O(\blk00000003/sig000007f4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000611 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e3 ), + .I3(NlwRenamedSig_OI_dout_2[41]), + .O(\blk00000003/sig000007f2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000610 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e5 ), + .I3(NlwRenamedSig_OI_dout_2[39]), + .O(\blk00000003/sig000007f0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000060f ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e4 ), + .I3(NlwRenamedSig_OI_dout_2[40]), + .O(\blk00000003/sig000007f1 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000060e ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e6 ), + .I3(NlwRenamedSig_OI_dout_2[38]), + .O(\blk00000003/sig000007ef ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000060d ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e8 ), + .I3(NlwRenamedSig_OI_dout_2[36]), + .O(\blk00000003/sig000007ed ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000060c ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e7 ), + .I3(NlwRenamedSig_OI_dout_2[37]), + .O(\blk00000003/sig000007ee ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000060b ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e9 ), + .I3(NlwRenamedSig_OI_dout_2[35]), + .O(\blk00000003/sig000007ec ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000060a ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000eb ), + .I3(NlwRenamedSig_OI_dout_2[33]), + .O(\blk00000003/sig000007ea ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000609 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000ea ), + .I3(NlwRenamedSig_OI_dout_2[34]), + .O(\blk00000003/sig000007eb ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000608 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000ec ), + .I3(NlwRenamedSig_OI_dout_2[32]), + .O(\blk00000003/sig000007e9 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000607 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000ee ), + .I3(NlwRenamedSig_OI_dout_2[30]), + .O(\blk00000003/sig000007e7 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000606 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000ed ), + .I3(NlwRenamedSig_OI_dout_2[31]), + .O(\blk00000003/sig000007e8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000605 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000ef ), + .I3(NlwRenamedSig_OI_dout_2[29]), + .O(\blk00000003/sig000007e6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000604 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f1 ), + .I3(NlwRenamedSig_OI_dout_2[27]), + .O(\blk00000003/sig000007e4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000603 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f0 ), + .I3(NlwRenamedSig_OI_dout_2[28]), + .O(\blk00000003/sig000007e5 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000602 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f2 ), + .I3(NlwRenamedSig_OI_dout_2[26]), + .O(\blk00000003/sig000007e3 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000601 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f4 ), + .I3(NlwRenamedSig_OI_dout_2[24]), + .O(\blk00000003/sig000007e1 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000600 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f3 ), + .I3(NlwRenamedSig_OI_dout_2[25]), + .O(\blk00000003/sig000007e2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ff ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f5 ), + .I3(NlwRenamedSig_OI_dout_2[23]), + .O(\blk00000003/sig000007e0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005fe ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f7 ), + .I3(NlwRenamedSig_OI_dout_2[21]), + .O(\blk00000003/sig000007de ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005fd ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f6 ), + .I3(NlwRenamedSig_OI_dout_2[22]), + .O(\blk00000003/sig000007df ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005fc ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f8 ), + .I3(NlwRenamedSig_OI_dout_2[20]), + .O(\blk00000003/sig000007dd ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005fb ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000fa ), + .I3(NlwRenamedSig_OI_dout_2[18]), + .O(\blk00000003/sig000007db ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005fa ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f9 ), + .I3(NlwRenamedSig_OI_dout_2[19]), + .O(\blk00000003/sig000007dc ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f9 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000fb ), + .I3(NlwRenamedSig_OI_dout_2[17]), + .O(\blk00000003/sig000007da ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f8 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000837 ), + .I3(NlwRenamedSig_OI_dout_2[15]), + .O(\blk00000003/sig000007d8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f7 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000fc ), + .I3(NlwRenamedSig_OI_dout_2[16]), + .O(\blk00000003/sig000007d9 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f6 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000836 ), + .I3(NlwRenamedSig_OI_dout_2[14]), + .O(\blk00000003/sig000007d7 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f5 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000835 ), + .I3(NlwRenamedSig_OI_dout_2[12]), + .O(\blk00000003/sig000007d5 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f4 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000834 ), + .I3(NlwRenamedSig_OI_dout_2[13]), + .O(\blk00000003/sig000007d6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f3 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000833 ), + .I3(NlwRenamedSig_OI_dout_2[11]), + .O(\blk00000003/sig000007d4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f2 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000832 ), + .I3(NlwRenamedSig_OI_dout_2[9]), + .O(\blk00000003/sig000007d2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f1 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000831 ), + .I3(NlwRenamedSig_OI_dout_2[10]), + .O(\blk00000003/sig000007d3 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f0 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000830 ), + .I3(NlwRenamedSig_OI_dout_2[8]), + .O(\blk00000003/sig000007d1 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ef ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000082f ), + .I3(NlwRenamedSig_OI_dout_2[6]), + .O(\blk00000003/sig000007cf ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ee ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000082e ), + .I3(NlwRenamedSig_OI_dout_2[7]), + .O(\blk00000003/sig000007d0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ed ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000082d ), + .I3(NlwRenamedSig_OI_dout_2[5]), + .O(\blk00000003/sig000007ce ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ec ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000082c ), + .I3(NlwRenamedSig_OI_dout_2[3]), + .O(\blk00000003/sig000007cc ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005eb ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000082b ), + .I3(NlwRenamedSig_OI_dout_2[4]), + .O(\blk00000003/sig000007cd ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ea ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000082a ), + .I3(NlwRenamedSig_OI_dout_2[2]), + .O(\blk00000003/sig000007cb ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e9 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000829 ), + .I3(NlwRenamedSig_OI_dout_2[1]), + .O(\blk00000003/sig000007ca ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e8 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000134 ), + .I3(NlwRenamedSig_OI_dout_1[46]), + .O(\blk00000003/sig000007c8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e7 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000828 ), + .I3(NlwRenamedSig_OI_dout_2[0]), + .O(\blk00000003/sig000007c9 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e6 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000135 ), + .I3(NlwRenamedSig_OI_dout_1[45]), + .O(\blk00000003/sig000007c7 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e5 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000137 ), + .I3(NlwRenamedSig_OI_dout_1[43]), + .O(\blk00000003/sig000007c5 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e4 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000136 ), + .I3(NlwRenamedSig_OI_dout_1[44]), + .O(\blk00000003/sig000007c6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e3 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000138 ), + .I3(NlwRenamedSig_OI_dout_1[42]), + .O(\blk00000003/sig000007c4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e2 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000013a ), + .I3(NlwRenamedSig_OI_dout_1[40]), + .O(\blk00000003/sig000007c2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e1 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000139 ), + .I3(NlwRenamedSig_OI_dout_1[41]), + .O(\blk00000003/sig000007c3 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e0 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000013b ), + .I3(NlwRenamedSig_OI_dout_1[39]), + .O(\blk00000003/sig000007c1 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005df ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000013d ), + .I3(NlwRenamedSig_OI_dout_1[37]), + .O(\blk00000003/sig000007bf ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005de ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000013c ), + .I3(NlwRenamedSig_OI_dout_1[38]), + .O(\blk00000003/sig000007c0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005dd ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000013e ), + .I3(NlwRenamedSig_OI_dout_1[36]), + .O(\blk00000003/sig000007be ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005dc ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000140 ), + .I3(NlwRenamedSig_OI_dout_1[34]), + .O(\blk00000003/sig000007bc ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005db ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000013f ), + .I3(NlwRenamedSig_OI_dout_1[35]), + .O(\blk00000003/sig000007bd ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005da ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000141 ), + .I3(NlwRenamedSig_OI_dout_1[33]), + .O(\blk00000003/sig000007bb ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d9 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000143 ), + .I3(NlwRenamedSig_OI_dout_1[31]), + .O(\blk00000003/sig000007b9 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d8 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000142 ), + .I3(NlwRenamedSig_OI_dout_1[32]), + .O(\blk00000003/sig000007ba ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d7 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000144 ), + .I3(NlwRenamedSig_OI_dout_1[30]), + .O(\blk00000003/sig000007b8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d6 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000146 ), + .I3(NlwRenamedSig_OI_dout_1[28]), + .O(\blk00000003/sig000007b6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d5 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000145 ), + .I3(NlwRenamedSig_OI_dout_1[29]), + .O(\blk00000003/sig000007b7 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d4 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000147 ), + .I3(NlwRenamedSig_OI_dout_1[27]), + .O(\blk00000003/sig000007b5 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d3 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000149 ), + .I3(NlwRenamedSig_OI_dout_1[25]), + .O(\blk00000003/sig000007b3 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d2 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000148 ), + .I3(NlwRenamedSig_OI_dout_1[26]), + .O(\blk00000003/sig000007b4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d1 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000014a ), + .I3(NlwRenamedSig_OI_dout_1[24]), + .O(\blk00000003/sig000007b2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d0 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000014c ), + .I3(NlwRenamedSig_OI_dout_1[22]), + .O(\blk00000003/sig000007b0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005cf ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000014b ), + .I3(NlwRenamedSig_OI_dout_1[23]), + .O(\blk00000003/sig000007b1 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ce ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000014d ), + .I3(NlwRenamedSig_OI_dout_1[21]), + .O(\blk00000003/sig000007af ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005cd ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000014f ), + .I3(NlwRenamedSig_OI_dout_1[19]), + .O(\blk00000003/sig000007ad ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005cc ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000014e ), + .I3(NlwRenamedSig_OI_dout_1[20]), + .O(\blk00000003/sig000007ae ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005cb ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000150 ), + .I3(NlwRenamedSig_OI_dout_1[18]), + .O(\blk00000003/sig000007ac ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ca ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000152 ), + .I3(NlwRenamedSig_OI_dout_1[16]), + .O(\blk00000003/sig000007aa ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c9 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000151 ), + .I3(NlwRenamedSig_OI_dout_1[17]), + .O(\blk00000003/sig000007ab ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c8 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000827 ), + .I3(NlwRenamedSig_OI_dout_1[15]), + .O(\blk00000003/sig000007a9 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c7 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000826 ), + .I3(NlwRenamedSig_OI_dout_1[13]), + .O(\blk00000003/sig000007a7 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c6 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000825 ), + .I3(NlwRenamedSig_OI_dout_1[14]), + .O(\blk00000003/sig000007a8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c5 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000824 ), + .I3(NlwRenamedSig_OI_dout_1[12]), + .O(\blk00000003/sig000007a6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c4 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000823 ), + .I3(NlwRenamedSig_OI_dout_1[10]), + .O(\blk00000003/sig000007a4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c3 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000822 ), + .I3(NlwRenamedSig_OI_dout_1[11]), + .O(\blk00000003/sig000007a5 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c2 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000821 ), + .I3(NlwRenamedSig_OI_dout_1[9]), + .O(\blk00000003/sig000007a3 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c1 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000820 ), + .I3(NlwRenamedSig_OI_dout_1[7]), + .O(\blk00000003/sig000007a1 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c0 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000081f ), + .I3(NlwRenamedSig_OI_dout_1[8]), + .O(\blk00000003/sig000007a2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005bf ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000081e ), + .I3(NlwRenamedSig_OI_dout_1[6]), + .O(\blk00000003/sig000007a0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005be ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000081d ), + .I3(NlwRenamedSig_OI_dout_1[4]), + .O(\blk00000003/sig0000079e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005bd ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000081c ), + .I3(NlwRenamedSig_OI_dout_1[5]), + .O(\blk00000003/sig0000079f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005bc ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000081b ), + .I3(NlwRenamedSig_OI_dout_1[3]), + .O(\blk00000003/sig0000079d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005bb ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000081a ), + .I3(NlwRenamedSig_OI_dout_1[1]), + .O(\blk00000003/sig0000079b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ba ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000819 ), + .I3(NlwRenamedSig_OI_dout_1[2]), + .O(\blk00000003/sig0000079c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b9 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000818 ), + .I3(NlwRenamedSig_OI_dout_1[0]), + .O(\blk00000003/sig0000079a ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000005b8 ( + .I0(\blk00000003/sig00000799 ), + .I1(\blk00000003/sig00000795 ), + .O(\blk00000003/sig00000787 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005b7 ( + .I0(ce), + .I1(\blk00000003/sig000002b0 ), + .O(\blk00000003/sig00000817 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005b6 ( + .I0(ce), + .I1(\blk00000003/sig0000067a ), + .O(\blk00000003/sig00000785 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005b5 ( + .I0(ce), + .I1(\blk00000003/sig00000816 ), + .O(\blk00000003/sig00000744 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005b4 ( + .I0(ce), + .I1(\blk00000003/sig00000815 ), + .O(\blk00000003/sig00000743 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000005b3 ( + .I0(\blk00000003/sig0000038d ), + .I1(\blk00000003/sig00000397 ), + .O(\blk00000003/sig0000038b ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000005b2 ( + .I0(\blk00000003/sig0000038e ), + .I1(\blk00000003/sig00000397 ), + .O(\blk00000003/sig00000388 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk000005b1 ( + .I0(\blk00000003/sig00000397 ), + .I1(\blk00000003/sig00000814 ), + .O(\blk00000003/sig00000385 ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk000005b0 ( + .I0(\blk00000003/sig00000386 ), + .I1(\blk00000003/sig00000397 ), + .I2(\blk00000003/sig00000814 ), + .O(\blk00000003/sig00000383 ) + ); + LUT3 #( + .INIT ( 8'hDA )) + \blk00000003/blk000005af ( + .I0(\blk00000003/sig00000387 ), + .I1(\blk00000003/sig00000814 ), + .I2(\blk00000003/sig00000397 ), + .O(\blk00000003/sig00000380 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000005ae ( + .I0(sclr), + .I1(\blk00000003/sig00000813 ), + .O(\blk00000003/sig0000037d ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000005ad ( + .I0(\blk00000003/sig0000037b ), + .I1(\blk00000003/sig000002a7 ), + .O(\blk00000003/sig00000379 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk000005ac ( + .I0(\blk00000003/sig0000036e ), + .I1(nd), + .I2(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig00000375 ) + ); + LUT4 #( + .INIT ( 16'hFF80 )) + \blk00000003/blk000005ab ( + .I0(nd), + .I1(\blk00000003/sig0000036e ), + .I2(NlwRenamedSig_OI_rfd), + .I3(\blk00000003/sig000002b7 ), + .O(\blk00000003/sig00000373 ) + ); + LUT4 #( + .INIT ( 16'hDFA0 )) + \blk00000003/blk000005aa ( + .I0(nd), + .I1(\blk00000003/sig0000036e ), + .I2(NlwRenamedSig_OI_rfd), + .I3(\blk00000003/sig000002b8 ), + .O(\blk00000003/sig00000370 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005a9 ( + .I0(nd), + .I1(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig00000368 ) + ); + LUT3 #( + .INIT ( 8'h09 )) + \blk00000003/blk000005a8 ( + .I0(\blk00000003/sig00000812 ), + .I1(\blk00000003/sig000002b7 ), + .I2(\blk00000003/sig000002b8 ), + .O(\blk00000003/sig0000036b ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk000005a7 ( + .I0(\blk00000003/sig00000317 ), + .I1(\blk00000003/sig00000310 ), + .O(\blk00000003/sig00000362 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk000005a6 ( + .I0(\blk00000003/sig00000317 ), + .I1(\blk00000003/sig0000030f ), + .O(\blk00000003/sig0000035f ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk000005a5 ( + .I0(\blk00000003/sig00000317 ), + .I1(\blk00000003/sig00000313 ), + .O(\blk00000003/sig0000035d ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk000005a4 ( + .I0(\blk00000003/sig00000317 ), + .I1(\blk00000003/sig00000315 ), + .I2(\blk00000003/sig0000031d ), + .O(\blk00000003/sig00000358 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk000005a3 ( + .I0(\blk00000003/sig00000315 ), + .I1(\blk00000003/sig00000313 ), + .I2(\blk00000003/sig00000317 ), + .O(\blk00000003/sig0000035a ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk000005a2 ( + .I0(\blk00000003/sig00000313 ), + .I1(\blk00000003/sig00000310 ), + .O(\blk00000003/sig00000351 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk000005a1 ( + .I0(\blk00000003/sig00000313 ), + .I1(\blk00000003/sig0000030f ), + .O(\blk00000003/sig0000034f ) + ); + LUT3 #( + .INIT ( 8'hBF )) + \blk00000003/blk000005a0 ( + .I0(\blk00000003/sig00000317 ), + .I1(\blk00000003/sig00000313 ), + .I2(\blk00000003/sig0000030d ), + .O(\blk00000003/sig0000034a ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000059f ( + .I0(\blk00000003/sig00000312 ), + .I1(\blk00000003/sig00000313 ), + .O(\blk00000003/sig00000346 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk0000059e ( + .I0(\blk00000003/sig00000311 ), + .I1(\blk00000003/sig00000313 ), + .I2(\blk00000003/sig0000031d ), + .O(\blk00000003/sig00000348 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk0000059d ( + .I0(\blk00000003/sig00000320 ), + .I1(\blk00000003/sig00000811 ), + .O(\blk00000003/sig00000341 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk0000059c ( + .I0(\blk00000003/sig000002f3 ), + .I1(coef_we), + .I2(\blk00000003/sig000002f9 ), + .O(\blk00000003/sig00000335 ) + ); + LUT4 #( + .INIT ( 16'hEAAA )) + \blk00000003/blk0000059b ( + .I0(\blk00000003/sig00000336 ), + .I1(coef_we), + .I2(\blk00000003/sig000002f9 ), + .I3(\blk00000003/sig000002f3 ), + .O(\blk00000003/sig00000333 ) + ); + LUT4 #( + .INIT ( 16'hDAAA )) + \blk00000003/blk0000059a ( + .I0(\blk00000003/sig00000337 ), + .I1(\blk00000003/sig000002f3 ), + .I2(\blk00000003/sig000002f9 ), + .I3(coef_we), + .O(\blk00000003/sig00000330 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000599 ( + .I0(\blk00000003/sig0000032e ), + .I1(\blk00000003/sig00000294 ), + .O(\blk00000003/sig0000032c ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000598 ( + .I0(\blk00000003/sig00000327 ), + .I1(coef_we), + .O(\blk00000003/sig00000325 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000597 ( + .I0(coef_ld), + .I1(\blk00000003/sig00000320 ), + .O(\blk00000003/sig00000316 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000596 ( + .I0(coef_we), + .I1(\blk00000003/sig000002f9 ), + .O(\blk00000003/sig000002f4 ) + ); + LUT3 #( + .INIT ( 8'h40 )) + \blk00000003/blk00000595 ( + .I0(coef_ld), + .I1(coef_we), + .I2(\blk00000003/sig0000030b ), + .O(\blk00000003/sig0000031e ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000594 ( + .I0(\blk00000003/sig00000336 ), + .I1(\blk00000003/sig00000337 ), + .O(\blk00000003/sig00000301 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000593 ( + .I0(\blk00000003/sig00000324 ), + .I1(\blk00000003/sig00000327 ), + .O(\blk00000003/sig000002fc ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000592 ( + .I0(\blk00000003/sig00000337 ), + .I1(\blk00000003/sig00000336 ), + .O(\blk00000003/sig000002f7 ) + ); + LUT3 #( + .INIT ( 8'hBF )) + \blk00000003/blk00000591 ( + .I0(\blk00000003/sig00000320 ), + .I1(\blk00000003/sig00000309 ), + .I2(coef_ld), + .O(\blk00000003/sig000002f1 ) + ); + LUT3 #( + .INIT ( 8'hBF )) + \blk00000003/blk00000590 ( + .I0(\blk00000003/sig0000030b ), + .I1(coef_we), + .I2(\blk00000003/sig00000309 ), + .O(\blk00000003/sig000002ee ) + ); + LUT5 #( + .INIT ( 32'hFFFF2AAA )) + \blk00000003/blk0000058f ( + .I0(\blk00000003/sig0000030b ), + .I1(coef_we), + .I2(\blk00000003/sig000002f9 ), + .I3(\blk00000003/sig000002f3 ), + .I4(coef_ld), + .O(\blk00000003/sig0000030a ) + ); + LUT4 #( + .INIT ( 16'hFF8A )) + \blk00000003/blk0000058e ( + .I0(\blk00000003/sig00000309 ), + .I1(\blk00000003/sig0000030b ), + .I2(coef_we), + .I3(coef_ld), + .O(\blk00000003/sig00000308 ) + ); + LUT3 #( + .INIT ( 8'h80 )) + \blk00000003/blk0000058d ( + .I0(nd), + .I1(\blk00000003/sig00000366 ), + .I2(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig000002b6 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000058c ( + .I0(\blk00000003/sig0000016b ), + .I1(\blk00000003/sig000002ae ), + .O(\blk00000003/sig000002b4 ) + ); + LUT3 #( + .INIT ( 8'h10 )) + \blk00000003/blk0000058b ( + .I0(\blk00000003/sig0000016b ), + .I1(\blk00000003/sig00000795 ), + .I2(\blk00000003/sig000002ae ), + .O(\blk00000003/sig0000016c ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk0000058a ( + .I0(sclr), + .I1(ce), + .I2(\blk00000003/sig00000795 ), + .O(\blk00000003/sig000002af ) + ); + LUT2 #( + .INIT ( 4'hD )) + \blk00000003/blk00000589 ( + .I0(NlwRenamedSig_OI_rfd), + .I1(nd), + .O(\blk00000003/sig0000029b ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000588 ( + .I0(\blk00000003/sig0000032b ), + .I1(\blk00000003/sig0000032e ), + .O(\blk00000003/sig00000295 ) + ); + LUT5 #( + .INIT ( 32'h00002000 )) + \blk00000003/blk00000587 ( + .I0(\blk00000003/sig00000808 ), + .I1(\blk00000003/sig00000809 ), + .I2(\blk00000003/sig0000080a ), + .I3(\blk00000003/sig0000080b ), + .I4(\blk00000003/sig0000080c ), + .O(\blk00000003/sig0000016f ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk00000586 ( + .I0(\blk00000003/sig000002a7 ), + .I1(\blk00000003/sig00000294 ), + .I2(\blk00000003/sig000002b5 ), + .O(\blk00000003/sig000002a6 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000585 ( + .I0(\blk00000003/sig0000037c ), + .I1(\blk00000003/sig000002b3 ), + .O(\blk00000003/sig000002ac ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00000584 ( + .I0(ce), + .I1(\blk00000003/sig0000080e ), + .I2(\blk00000003/sig00000161 ), + .O(\blk00000003/sig00000160 ) + ); + LUT3 #( + .INIT ( 8'h72 )) + \blk00000003/blk00000583 ( + .I0(ce), + .I1(\blk00000003/sig0000080e ), + .I2(\blk00000003/sig0000015f ), + .O(\blk00000003/sig0000015e ) + ); + LUT4 #( + .INIT ( 16'h8F88 )) + \blk00000003/blk00000582 ( + .I0(NlwRenamedSig_OI_rfd), + .I1(nd), + .I2(\blk00000003/sig000002a9 ), + .I3(\blk00000003/sig00000296 ), + .O(\blk00000003/sig000002a8 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000581 ( + .I0(\blk00000003/sig00000159 ), + .I1(\blk00000003/sig00000296 ), + .O(\blk00000003/sig0000015a ) + ); + LUT5 #( + .INIT ( 32'hCEEE8AAA )) + \blk00000003/blk00000580 ( + .I0(\blk00000003/sig00000294 ), + .I1(\blk00000003/sig000002b5 ), + .I2(\blk00000003/sig000002a5 ), + .I3(\blk00000003/sig000002a7 ), + .I4(\blk00000003/sig000002a3 ), + .O(\blk00000003/sig000002a4 ) + ); + LUT4 #( + .INIT ( 16'h8808 )) + \blk00000003/blk0000057f ( + .I0(\blk00000003/sig000002a5 ), + .I1(\blk00000003/sig00000810 ), + .I2(\blk00000003/sig000002a7 ), + .I3(\blk00000003/sig000002b5 ), + .O(\blk00000003/sig000002a0 ) + ); + LUT4 #( + .INIT ( 16'h5540 )) + \blk00000003/blk0000057e ( + .I0(\blk00000003/sig000002b5 ), + .I1(\blk00000003/sig000002a5 ), + .I2(\blk00000003/sig000002a7 ), + .I3(\blk00000003/sig000002a3 ), + .O(\blk00000003/sig000002a2 ) + ); + LUT3 #( + .INIT ( 8'h9A )) + \blk00000003/blk0000057d ( + .I0(\blk00000003/sig0000037b ), + .I1(\blk00000003/sig0000037c ), + .I2(\blk00000003/sig000002b3 ), + .O(\blk00000003/sig000002aa ) + ); + LUT4 #( + .INIT ( 16'hFDA8 )) + \blk00000003/blk0000057c ( + .I0(ce), + .I1(\blk00000003/sig0000080e ), + .I2(\blk00000003/sig0000080f ), + .I3(\blk00000003/sig0000015d ), + .O(\blk00000003/sig0000015c ) + ); + MUXCY \blk00000003/blk0000057b ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig0000080d ), + .O(\blk00000003/sig00000805 ) + ); + MUXCY_L \blk00000003/blk0000057a ( + .CI(\blk00000003/sig00000805 ), + .DI(\blk00000003/sig0000080c ), + .S(\blk00000003/sig00000806 ), + .LO(\blk00000003/sig00000802 ) + ); + MUXCY_L \blk00000003/blk00000579 ( + .CI(\blk00000003/sig00000802 ), + .DI(\blk00000003/sig0000080b ), + .S(\blk00000003/sig00000803 ), + .LO(\blk00000003/sig000007ff ) + ); + MUXCY_L \blk00000003/blk00000578 ( + .CI(\blk00000003/sig000007ff ), + .DI(\blk00000003/sig0000080a ), + .S(\blk00000003/sig00000800 ), + .LO(\blk00000003/sig000007fc ) + ); + MUXCY_L \blk00000003/blk00000577 ( + .CI(\blk00000003/sig000007fc ), + .DI(\blk00000003/sig00000809 ), + .S(\blk00000003/sig000007fd ), + .LO(\blk00000003/sig000007f9 ) + ); + MUXCY_D \blk00000003/blk00000576 ( + .CI(\blk00000003/sig000007f9 ), + .DI(\blk00000003/sig00000808 ), + .S(\blk00000003/sig000007fa ), + .O(\NLW_blk00000003/blk00000576_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk00000576_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000575 ( + .CI(\blk00000003/sig00000805 ), + .LI(\blk00000003/sig00000806 ), + .O(\blk00000003/sig00000807 ) + ); + XORCY \blk00000003/blk00000574 ( + .CI(\blk00000003/sig00000802 ), + .LI(\blk00000003/sig00000803 ), + .O(\blk00000003/sig00000804 ) + ); + XORCY \blk00000003/blk00000573 ( + .CI(\blk00000003/sig000007ff ), + .LI(\blk00000003/sig00000800 ), + .O(\blk00000003/sig00000801 ) + ); + XORCY \blk00000003/blk00000572 ( + .CI(\blk00000003/sig000007fc ), + .LI(\blk00000003/sig000007fd ), + .O(\blk00000003/sig000007fe ) + ); + XORCY \blk00000003/blk00000571 ( + .CI(\blk00000003/sig000007f9 ), + .LI(\blk00000003/sig000007fa ), + .O(\blk00000003/sig000007fb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000570 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f8 ), + .R(sclr), + .Q(\blk00000003/sig0000004a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f7 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f6 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f5 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f4 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f3 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f2 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f1 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000568 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f0 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000567 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ef ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000566 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ee ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000565 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ed ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000564 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ec ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000563 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007eb ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000562 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ea ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000561 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e9 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000560 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e8 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e7 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e6 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e5 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e4 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e3 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e2 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000559 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e1 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000558 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e0 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000557 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007df ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000556 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007de ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000555 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007dd ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000554 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007dc ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000553 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007db ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000552 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007da ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000551 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d9 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000550 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d8 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d7 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d6 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d5 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d4 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d3 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d2 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000549 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d1 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000548 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d0 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000547 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007cf ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000546 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ce ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000545 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007cd ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000544 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007cc ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000543 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007cb ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000542 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ca ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000541 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c9 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[0]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000540 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c8 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c7 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c6 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c5 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c4 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c3 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c2 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000539 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c1 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000538 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c0 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000537 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007bf ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000536 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007be ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000535 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007bd ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000534 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007bc ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000533 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007bb ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000532 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ba ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000531 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b9 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b8 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b7 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b6 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b5 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b4 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b3 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b2 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000529 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b1 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000528 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b0 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000527 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007af ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000526 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ae ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000525 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ad ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000524 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ac ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000523 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ab ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000522 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007aa ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000521 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a9 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000520 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a8 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a7 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a6 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a5 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a4 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a3 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a2 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000519 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a1 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000518 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a0 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000517 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000079f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000516 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000079e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000515 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000079d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000514 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000079c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000513 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000079b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000512 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000079a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[0]) + ); + MUXCY_L \blk00000003/blk00000511 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000799 ), + .S(\blk00000003/sig00000787 ), + .LO(\blk00000003/sig00000792 ) + ); + MUXCY_L \blk00000003/blk00000510 ( + .CI(\blk00000003/sig00000792 ), + .DI(\blk00000003/sig00000798 ), + .S(\blk00000003/sig00000793 ), + .LO(\blk00000003/sig0000078f ) + ); + MUXCY_L \blk00000003/blk0000050f ( + .CI(\blk00000003/sig0000078f ), + .DI(\blk00000003/sig00000797 ), + .S(\blk00000003/sig00000790 ), + .LO(\blk00000003/sig0000078c ) + ); + MUXCY_L \blk00000003/blk0000050e ( + .CI(\blk00000003/sig0000078c ), + .DI(\blk00000003/sig00000796 ), + .S(\blk00000003/sig0000078d ), + .LO(\blk00000003/sig00000789 ) + ); + MUXCY_D \blk00000003/blk0000050d ( + .CI(\blk00000003/sig00000789 ), + .DI(\blk00000003/sig00000795 ), + .S(\blk00000003/sig0000078a ), + .O(\NLW_blk00000003/blk0000050d_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk0000050d_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000050c ( + .CI(\blk00000003/sig00000792 ), + .LI(\blk00000003/sig00000793 ), + .O(\blk00000003/sig00000794 ) + ); + XORCY \blk00000003/blk0000050b ( + .CI(\blk00000003/sig0000078f ), + .LI(\blk00000003/sig00000790 ), + .O(\blk00000003/sig00000791 ) + ); + XORCY \blk00000003/blk0000050a ( + .CI(\blk00000003/sig0000078c ), + .LI(\blk00000003/sig0000078d ), + .O(\blk00000003/sig0000078e ) + ); + XORCY \blk00000003/blk00000509 ( + .CI(\blk00000003/sig00000789 ), + .LI(\blk00000003/sig0000078a ), + .O(\blk00000003/sig0000078b ) + ); + XORCY \blk00000003/blk00000508 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000787 ), + .O(\blk00000003/sig00000788 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e0 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005e0 ), + .R(sclr), + .Q(\blk00000003/sig0000069c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004df ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005df ), + .R(sclr), + .Q(\blk00000003/sig0000069b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004de ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005de ), + .R(sclr), + .Q(\blk00000003/sig0000069a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004dd ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005dd ), + .R(sclr), + .Q(\blk00000003/sig00000699 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004dc ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005dc ), + .R(sclr), + .Q(\blk00000003/sig00000698 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004db ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005db ), + .R(sclr), + .Q(\blk00000003/sig00000697 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004da ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005da ), + .R(sclr), + .Q(\blk00000003/sig00000696 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d9 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d9 ), + .R(sclr), + .Q(\blk00000003/sig00000695 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d8 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d8 ), + .R(sclr), + .Q(\blk00000003/sig00000694 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d7 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d7 ), + .R(sclr), + .Q(\blk00000003/sig00000693 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d6 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d6 ), + .R(sclr), + .Q(\blk00000003/sig00000692 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d5 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d5 ), + .R(sclr), + .Q(\blk00000003/sig00000691 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d4 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d4 ), + .R(sclr), + .Q(\blk00000003/sig00000690 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d3 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d3 ), + .R(sclr), + .Q(\blk00000003/sig0000068f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d2 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d2 ), + .R(sclr), + .Q(\blk00000003/sig0000068e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d1 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d1 ), + .R(sclr), + .Q(\blk00000003/sig0000068d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d0 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000050c ), + .R(sclr), + .Q(\blk00000003/sig0000074c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004cf ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000050b ), + .R(sclr), + .Q(\blk00000003/sig0000074b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ce ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000050a ), + .R(sclr), + .Q(\blk00000003/sig0000074a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004cd ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000509 ), + .R(sclr), + .Q(\blk00000003/sig00000749 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004cc ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000508 ), + .R(sclr), + .Q(\blk00000003/sig00000748 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004cb ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000507 ), + .R(sclr), + .Q(\blk00000003/sig00000747 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ca ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000506 ), + .R(sclr), + .Q(\blk00000003/sig00000746 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c9 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000505 ), + .R(sclr), + .Q(\blk00000003/sig00000745 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c8 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000630 ), + .R(sclr), + .Q(\blk00000003/sig000006ac ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c7 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000062f ), + .R(sclr), + .Q(\blk00000003/sig000006ab ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c6 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000062e ), + .R(sclr), + .Q(\blk00000003/sig000006aa ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c5 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000062d ), + .R(sclr), + .Q(\blk00000003/sig000006a9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c4 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000062c ), + .R(sclr), + .Q(\blk00000003/sig000006a8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c3 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000062b ), + .R(sclr), + .Q(\blk00000003/sig000006a7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c2 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000062a ), + .R(sclr), + .Q(\blk00000003/sig000006a6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c1 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000629 ), + .R(sclr), + .Q(\blk00000003/sig000006a5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c0 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000628 ), + .R(sclr), + .Q(\blk00000003/sig000006a4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004bf ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000627 ), + .R(sclr), + .Q(\blk00000003/sig000006a3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000626 ), + .R(sclr), + .Q(\blk00000003/sig000006a2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004bd ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000625 ), + .R(sclr), + .Q(\blk00000003/sig000006a1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004bc ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000624 ), + .R(sclr), + .Q(\blk00000003/sig000006a0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004bb ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000623 ), + .R(sclr), + .Q(\blk00000003/sig0000069f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ba ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000622 ), + .R(sclr), + .Q(\blk00000003/sig0000069e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b9 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000621 ), + .R(sclr), + .Q(\blk00000003/sig0000069d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b8 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000055e ), + .R(sclr), + .Q(\blk00000003/sig00000754 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b7 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000055d ), + .R(sclr), + .Q(\blk00000003/sig00000753 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000055c ), + .R(sclr), + .Q(\blk00000003/sig00000752 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b5 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000055b ), + .R(sclr), + .Q(\blk00000003/sig00000751 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b4 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000055a ), + .R(sclr), + .Q(\blk00000003/sig00000750 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b3 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000559 ), + .R(sclr), + .Q(\blk00000003/sig0000074f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b2 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000558 ), + .R(sclr), + .Q(\blk00000003/sig0000074e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b1 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000557 ), + .R(sclr), + .Q(\blk00000003/sig0000074d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b0 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000566 ), + .R(sclr), + .Q(\blk00000003/sig00000774 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004af ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000565 ), + .R(sclr), + .Q(\blk00000003/sig00000773 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ae ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000564 ), + .R(sclr), + .Q(\blk00000003/sig00000772 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ad ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000563 ), + .R(sclr), + .Q(\blk00000003/sig00000771 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ac ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000562 ), + .R(sclr), + .Q(\blk00000003/sig00000770 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ab ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000561 ), + .R(sclr), + .Q(\blk00000003/sig0000076f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004aa ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000560 ), + .R(sclr), + .Q(\blk00000003/sig0000076e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a9 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000055f ), + .R(sclr), + .Q(\blk00000003/sig0000076d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a8 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000004d4 ), + .R(sclr), + .Q(\blk00000003/sig0000075c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a7 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000004d3 ), + .R(sclr), + .Q(\blk00000003/sig0000075b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a6 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000004d2 ), + .R(sclr), + .Q(\blk00000003/sig0000075a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a5 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000004d1 ), + .R(sclr), + .Q(\blk00000003/sig00000759 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000004d0 ), + .R(sclr), + .Q(\blk00000003/sig00000758 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a3 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000004cf ), + .R(sclr), + .Q(\blk00000003/sig00000757 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a2 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000004ce ), + .R(sclr), + .Q(\blk00000003/sig00000756 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a1 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000004cd ), + .R(sclr), + .Q(\blk00000003/sig00000755 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a0 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000588 ), + .R(sclr), + .Q(\blk00000003/sig00000784 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049f ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000587 ), + .R(sclr), + .Q(\blk00000003/sig00000783 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049e ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000586 ), + .R(sclr), + .Q(\blk00000003/sig00000782 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049d ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000585 ), + .R(sclr), + .Q(\blk00000003/sig00000781 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049c ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000584 ), + .R(sclr), + .Q(\blk00000003/sig00000780 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049b ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000583 ), + .R(sclr), + .Q(\blk00000003/sig0000077f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049a ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000582 ), + .R(sclr), + .Q(\blk00000003/sig0000077e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000499 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000581 ), + .R(sclr), + .Q(\blk00000003/sig0000077d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000498 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000526 ), + .R(sclr), + .Q(\blk00000003/sig00000764 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000497 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000525 ), + .R(sclr), + .Q(\blk00000003/sig00000763 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000496 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000524 ), + .R(sclr), + .Q(\blk00000003/sig00000762 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000495 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000523 ), + .R(sclr), + .Q(\blk00000003/sig00000761 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000494 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000522 ), + .R(sclr), + .Q(\blk00000003/sig00000760 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000493 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000521 ), + .R(sclr), + .Q(\blk00000003/sig0000075f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000492 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000520 ), + .R(sclr), + .Q(\blk00000003/sig0000075e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000491 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig0000051f ), + .R(sclr), + .Q(\blk00000003/sig0000075d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000385 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000640 ), + .R(sclr), + .Q(\blk00000003/sig000006ec ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000063f ), + .R(sclr), + .Q(\blk00000003/sig000006eb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000383 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000063e ), + .R(sclr), + .Q(\blk00000003/sig000006ea ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000382 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000063d ), + .R(sclr), + .Q(\blk00000003/sig000006e9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000381 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000063c ), + .R(sclr), + .Q(\blk00000003/sig000006e8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000380 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000063b ), + .R(sclr), + .Q(\blk00000003/sig000006e7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037f ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000063a ), + .R(sclr), + .Q(\blk00000003/sig000006e6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037e ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000639 ), + .R(sclr), + .Q(\blk00000003/sig000006e5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037d ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000638 ), + .R(sclr), + .Q(\blk00000003/sig000006e4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037c ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000637 ), + .R(sclr), + .Q(\blk00000003/sig000006e3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000636 ), + .R(sclr), + .Q(\blk00000003/sig000006e2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037a ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000635 ), + .R(sclr), + .Q(\blk00000003/sig000006e1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000379 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000634 ), + .R(sclr), + .Q(\blk00000003/sig000006e0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000378 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000633 ), + .R(sclr), + .Q(\blk00000003/sig000006df ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000377 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000632 ), + .R(sclr), + .Q(\blk00000003/sig000006de ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000376 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000631 ), + .R(sclr), + .Q(\blk00000003/sig000006dd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000375 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005a0 ), + .R(sclr), + .Q(\blk00000003/sig000006bc ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000374 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig0000059f ), + .R(sclr), + .Q(\blk00000003/sig000006bb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000373 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig0000059e ), + .R(sclr), + .Q(\blk00000003/sig000006ba ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000372 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig0000059d ), + .R(sclr), + .Q(\blk00000003/sig000006b9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig0000059c ), + .R(sclr), + .Q(\blk00000003/sig000006b8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000370 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig0000059b ), + .R(sclr), + .Q(\blk00000003/sig000006b7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036f ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig0000059a ), + .R(sclr), + .Q(\blk00000003/sig000006b6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036e ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000599 ), + .R(sclr), + .Q(\blk00000003/sig000006b5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000598 ), + .R(sclr), + .Q(\blk00000003/sig000006b4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036c ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000597 ), + .R(sclr), + .Q(\blk00000003/sig000006b3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036b ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000596 ), + .R(sclr), + .Q(\blk00000003/sig000006b2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036a ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000595 ), + .R(sclr), + .Q(\blk00000003/sig000006b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000369 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000594 ), + .R(sclr), + .Q(\blk00000003/sig000006b0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000368 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000593 ), + .R(sclr), + .Q(\blk00000003/sig000006af ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000367 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000592 ), + .R(sclr), + .Q(\blk00000003/sig000006ae ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000366 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000591 ), + .R(sclr), + .Q(\blk00000003/sig000006ad ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000365 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000660 ), + .R(sclr), + .Q(\blk00000003/sig0000070c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000364 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000065f ), + .R(sclr), + .Q(\blk00000003/sig0000070b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000363 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000065e ), + .R(sclr), + .Q(\blk00000003/sig0000070a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000362 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000065d ), + .R(sclr), + .Q(\blk00000003/sig00000709 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000361 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000065c ), + .R(sclr), + .Q(\blk00000003/sig00000708 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000360 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000065b ), + .R(sclr), + .Q(\blk00000003/sig00000707 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035f ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000065a ), + .R(sclr), + .Q(\blk00000003/sig00000706 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035e ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000659 ), + .R(sclr), + .Q(\blk00000003/sig00000705 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035d ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000658 ), + .R(sclr), + .Q(\blk00000003/sig00000704 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035c ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000657 ), + .R(sclr), + .Q(\blk00000003/sig00000703 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035b ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000656 ), + .R(sclr), + .Q(\blk00000003/sig00000702 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035a ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000655 ), + .R(sclr), + .Q(\blk00000003/sig00000701 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000359 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000654 ), + .R(sclr), + .Q(\blk00000003/sig00000700 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000358 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000653 ), + .R(sclr), + .Q(\blk00000003/sig000006ff ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000357 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000652 ), + .R(sclr), + .Q(\blk00000003/sig000006fe ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000356 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000651 ), + .R(sclr), + .Q(\blk00000003/sig000006fd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000355 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005f0 ), + .R(sclr), + .Q(\blk00000003/sig000006cc ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000354 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005ef ), + .R(sclr), + .Q(\blk00000003/sig000006cb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000353 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005ee ), + .R(sclr), + .Q(\blk00000003/sig000006ca ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000352 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005ed ), + .R(sclr), + .Q(\blk00000003/sig000006c9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005ec ), + .R(sclr), + .Q(\blk00000003/sig000006c8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000350 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005eb ), + .R(sclr), + .Q(\blk00000003/sig000006c7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034f ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005ea ), + .R(sclr), + .Q(\blk00000003/sig000006c6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034e ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e9 ), + .R(sclr), + .Q(\blk00000003/sig000006c5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034d ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e8 ), + .R(sclr), + .Q(\blk00000003/sig000006c4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034c ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e7 ), + .R(sclr), + .Q(\blk00000003/sig000006c3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034b ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e6 ), + .R(sclr), + .Q(\blk00000003/sig000006c2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e5 ), + .R(sclr), + .Q(\blk00000003/sig000006c1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000349 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e4 ), + .R(sclr), + .Q(\blk00000003/sig000006c0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e3 ), + .R(sclr), + .Q(\blk00000003/sig000006bf ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000347 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e2 ), + .R(sclr), + .Q(\blk00000003/sig000006be ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000346 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e1 ), + .R(sclr), + .Q(\blk00000003/sig000006bd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000038e ), + .R(sclr), + .Q(\blk00000003/sig00000685 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000038d ), + .R(sclr), + .Q(\blk00000003/sig00000683 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000390 ), + .R(sclr), + .Q(\blk00000003/sig00000681 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000394 ), + .R(sclr), + .Q(\blk00000003/sig0000067f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000039a ), + .R(sclr), + .Q(\blk00000003/sig0000067d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000068c ), + .R(sclr), + .Q(\blk00000003/sig0000067b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000129 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000068b ), + .R(sclr), + .Q(\blk00000003/sig00000679 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000128 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000387 ), + .R(sclr), + .Q(\blk00000003/sig00000689 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000127 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000386 ), + .R(sclr), + .Q(\blk00000003/sig00000687 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000126 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000689 ), + .R(sclr), + .Q(\blk00000003/sig0000068a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000125 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000687 ), + .R(sclr), + .Q(\blk00000003/sig00000688 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000124 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000685 ), + .R(sclr), + .Q(\blk00000003/sig00000686 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000123 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000683 ), + .R(sclr), + .Q(\blk00000003/sig00000684 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000122 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000681 ), + .R(sclr), + .Q(\blk00000003/sig00000682 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000121 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000067f ), + .R(sclr), + .Q(\blk00000003/sig00000680 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000067d ), + .R(sclr), + .Q(\blk00000003/sig0000067e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000067b ), + .R(sclr), + .Q(\blk00000003/sig0000067c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000679 ), + .R(sclr), + .Q(\blk00000003/sig0000067a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000677 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000678 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000307 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000677 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000673 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000676 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000672 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000675 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000671 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000674 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000118 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000340 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000673 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000033d ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000672 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000116 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000339 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000671 ) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000115 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000115_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000115_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000651 , \blk00000003/sig00000652 , \blk00000003/sig00000653 , +\blk00000003/sig00000654 , \blk00000003/sig00000655 , \blk00000003/sig00000656 , \blk00000003/sig00000657 , \blk00000003/sig00000658 , +\blk00000003/sig00000659 , \blk00000003/sig0000065a , \blk00000003/sig0000065b , \blk00000003/sig0000065c , \blk00000003/sig0000065d , +\blk00000003/sig0000065e , \blk00000003/sig0000065f , \blk00000003/sig00000660 }), + .BCOUT({\NLW_blk00000003/blk00000115_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000115_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000115_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000115_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000115_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000115_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000115_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000115_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000115_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig0000049d , \blk00000003/sig0000049e , \blk00000003/sig0000049f , \blk00000003/sig000004a0 , \blk00000003/sig000004a1 , +\blk00000003/sig000004a2 , \blk00000003/sig000004a3 , \blk00000003/sig000004a4 , \blk00000003/sig000004a5 , \blk00000003/sig000004a6 , +\blk00000003/sig000004a7 , \blk00000003/sig000004a8 , \blk00000003/sig000004a9 , \blk00000003/sig000004aa , \blk00000003/sig000004ab , +\blk00000003/sig000004ac , \blk00000003/sig000004ad , \blk00000003/sig000004ae , \blk00000003/sig000004af , \blk00000003/sig000004b0 , +\blk00000003/sig000004b1 , \blk00000003/sig000004b2 , \blk00000003/sig000004b3 , \blk00000003/sig000004b4 , \blk00000003/sig000004b5 , +\blk00000003/sig000004b6 , \blk00000003/sig000004b7 , \blk00000003/sig000004b8 , \blk00000003/sig000004b9 , \blk00000003/sig000004ba , +\blk00000003/sig000004bb , \blk00000003/sig000004bc , \blk00000003/sig000004bd , \blk00000003/sig000004be , \blk00000003/sig000004bf , +\blk00000003/sig000004c0 , \blk00000003/sig000004c1 , \blk00000003/sig000004c2 , \blk00000003/sig000004c3 , \blk00000003/sig000004c4 , +\blk00000003/sig000004c5 , \blk00000003/sig000004c6 , \blk00000003/sig000004c7 , \blk00000003/sig000004c8 , \blk00000003/sig000004c9 , +\blk00000003/sig000004ca , \blk00000003/sig000004cb , \blk00000003/sig000004cc }), + .C({\NLW_blk00000003/blk00000115_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000115_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000661 , \blk00000003/sig00000662 , \blk00000003/sig00000663 , +\blk00000003/sig00000664 , \blk00000003/sig00000665 , \blk00000003/sig00000666 , \blk00000003/sig00000667 , \blk00000003/sig00000668 , +\blk00000003/sig00000669 , \blk00000003/sig0000066a , \blk00000003/sig0000066b , \blk00000003/sig0000066c , \blk00000003/sig0000066d , +\blk00000003/sig0000066e , \blk00000003/sig0000066f , \blk00000003/sig00000670 }), + .PCOUT({\blk00000003/sig000005f1 , \blk00000003/sig000005f2 , \blk00000003/sig000005f3 , \blk00000003/sig000005f4 , \blk00000003/sig000005f5 , +\blk00000003/sig000005f6 , \blk00000003/sig000005f7 , \blk00000003/sig000005f8 , \blk00000003/sig000005f9 , \blk00000003/sig000005fa , +\blk00000003/sig000005fb , \blk00000003/sig000005fc , \blk00000003/sig000005fd , \blk00000003/sig000005fe , \blk00000003/sig000005ff , +\blk00000003/sig00000600 , \blk00000003/sig00000601 , \blk00000003/sig00000602 , \blk00000003/sig00000603 , \blk00000003/sig00000604 , +\blk00000003/sig00000605 , \blk00000003/sig00000606 , \blk00000003/sig00000607 , \blk00000003/sig00000608 , \blk00000003/sig00000609 , +\blk00000003/sig0000060a , \blk00000003/sig0000060b , \blk00000003/sig0000060c , \blk00000003/sig0000060d , \blk00000003/sig0000060e , +\blk00000003/sig0000060f , \blk00000003/sig00000610 , \blk00000003/sig00000611 , \blk00000003/sig00000612 , \blk00000003/sig00000613 , +\blk00000003/sig00000614 , \blk00000003/sig00000615 , \blk00000003/sig00000616 , \blk00000003/sig00000617 , \blk00000003/sig00000618 , +\blk00000003/sig00000619 , \blk00000003/sig0000061a , \blk00000003/sig0000061b , \blk00000003/sig0000061c , \blk00000003/sig0000061d , +\blk00000003/sig0000061e , \blk00000003/sig0000061f , \blk00000003/sig00000620 }), + .A({\blk00000003/sig0000056f , \blk00000003/sig00000570 , \blk00000003/sig00000571 , \blk00000003/sig00000572 , \blk00000003/sig00000573 , +\blk00000003/sig00000574 , \blk00000003/sig00000575 , \blk00000003/sig00000576 , \blk00000003/sig00000577 , \blk00000003/sig00000578 , +\blk00000003/sig00000579 , \blk00000003/sig0000057a , \blk00000003/sig0000057b , \blk00000003/sig0000057c , \blk00000003/sig0000057d , +\blk00000003/sig0000057e , \blk00000003/sig0000057f , \blk00000003/sig00000580 }), + .M({\NLW_blk00000003/blk00000115_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000114 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000114_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000114_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000631 , \blk00000003/sig00000632 , \blk00000003/sig00000633 , +\blk00000003/sig00000634 , \blk00000003/sig00000635 , \blk00000003/sig00000636 , \blk00000003/sig00000637 , \blk00000003/sig00000638 , +\blk00000003/sig00000639 , \blk00000003/sig0000063a , \blk00000003/sig0000063b , \blk00000003/sig0000063c , \blk00000003/sig0000063d , +\blk00000003/sig0000063e , \blk00000003/sig0000063f , \blk00000003/sig00000640 }), + .BCOUT({\NLW_blk00000003/blk00000114_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000114_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000114_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000114_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000114_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000114_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000114_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000114_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000114_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig0000044d , \blk00000003/sig0000044e , \blk00000003/sig0000044f , \blk00000003/sig00000450 , \blk00000003/sig00000451 , +\blk00000003/sig00000452 , \blk00000003/sig00000453 , \blk00000003/sig00000454 , \blk00000003/sig00000455 , \blk00000003/sig00000456 , +\blk00000003/sig00000457 , \blk00000003/sig00000458 , \blk00000003/sig00000459 , \blk00000003/sig0000045a , \blk00000003/sig0000045b , +\blk00000003/sig0000045c , \blk00000003/sig0000045d , \blk00000003/sig0000045e , \blk00000003/sig0000045f , \blk00000003/sig00000460 , +\blk00000003/sig00000461 , \blk00000003/sig00000462 , \blk00000003/sig00000463 , \blk00000003/sig00000464 , \blk00000003/sig00000465 , +\blk00000003/sig00000466 , \blk00000003/sig00000467 , \blk00000003/sig00000468 , \blk00000003/sig00000469 , \blk00000003/sig0000046a , +\blk00000003/sig0000046b , \blk00000003/sig0000046c , \blk00000003/sig0000046d , \blk00000003/sig0000046e , \blk00000003/sig0000046f , +\blk00000003/sig00000470 , \blk00000003/sig00000471 , \blk00000003/sig00000472 , \blk00000003/sig00000473 , \blk00000003/sig00000474 , +\blk00000003/sig00000475 , \blk00000003/sig00000476 , \blk00000003/sig00000477 , \blk00000003/sig00000478 , \blk00000003/sig00000479 , +\blk00000003/sig0000047a , \blk00000003/sig0000047b , \blk00000003/sig0000047c }), + .C({\NLW_blk00000003/blk00000114_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<43>_UNCONNECTED , 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\NLW_blk00000003/blk00000114_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000114_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<31>_UNCONNECTED , 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\NLW_blk00000003/blk00000113_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000113_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000113_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000621 , \blk00000003/sig00000622 , \blk00000003/sig00000623 , +\blk00000003/sig00000624 , \blk00000003/sig00000625 , \blk00000003/sig00000626 , \blk00000003/sig00000627 , \blk00000003/sig00000628 , +\blk00000003/sig00000629 , \blk00000003/sig0000062a , \blk00000003/sig0000062b , \blk00000003/sig0000062c , \blk00000003/sig0000062d , +\blk00000003/sig0000062e , \blk00000003/sig0000062f , \blk00000003/sig00000630 }), + .PCOUT({\blk00000003/sig000001ca , \blk00000003/sig000001cb , \blk00000003/sig000001cc , \blk00000003/sig000001cd , \blk00000003/sig000001ce , +\blk00000003/sig000001cf , \blk00000003/sig000001d0 , \blk00000003/sig000001d1 , \blk00000003/sig000001d2 , \blk00000003/sig000001d3 , +\blk00000003/sig000001d4 , \blk00000003/sig000001d5 , \blk00000003/sig000001d6 , \blk00000003/sig000001d7 , \blk00000003/sig000001d8 , +\blk00000003/sig000001d9 , \blk00000003/sig000001da , \blk00000003/sig000001db , \blk00000003/sig000001dc , \blk00000003/sig000001dd , +\blk00000003/sig000001de , \blk00000003/sig000001df , \blk00000003/sig000001e0 , \blk00000003/sig000001e1 , \blk00000003/sig000001e2 , +\blk00000003/sig000001e3 , \blk00000003/sig000001e4 , \blk00000003/sig000001e5 , \blk00000003/sig000001e6 , \blk00000003/sig000001e7 , +\blk00000003/sig000001e8 , \blk00000003/sig000001e9 , \blk00000003/sig000001ea , \blk00000003/sig000001eb , \blk00000003/sig000001ec , +\blk00000003/sig000001ed , \blk00000003/sig000001ee , \blk00000003/sig000001ef , \blk00000003/sig000001f0 , \blk00000003/sig000001f1 , +\blk00000003/sig000001f2 , \blk00000003/sig000001f3 , \blk00000003/sig000001f4 , \blk00000003/sig000001f5 , \blk00000003/sig000001f6 , +\blk00000003/sig000001f7 , \blk00000003/sig000001f8 , \blk00000003/sig000001f9 }), + .A({\blk00000003/sig0000050d , \blk00000003/sig0000050e , \blk00000003/sig0000050f , \blk00000003/sig00000510 , \blk00000003/sig00000511 , +\blk00000003/sig00000512 , \blk00000003/sig00000513 , \blk00000003/sig00000514 , \blk00000003/sig00000515 , \blk00000003/sig00000516 , +\blk00000003/sig00000517 , \blk00000003/sig00000518 , \blk00000003/sig00000519 , \blk00000003/sig0000051a , \blk00000003/sig0000051b , +\blk00000003/sig0000051c , \blk00000003/sig0000051d , \blk00000003/sig0000051e }), + .M({\NLW_blk00000003/blk00000113_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000112 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000112_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000112_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000591 , \blk00000003/sig00000592 , \blk00000003/sig00000593 , +\blk00000003/sig00000594 , \blk00000003/sig00000595 , \blk00000003/sig00000596 , \blk00000003/sig00000597 , \blk00000003/sig00000598 , +\blk00000003/sig00000599 , \blk00000003/sig0000059a , \blk00000003/sig0000059b , \blk00000003/sig0000059c , \blk00000003/sig0000059d , +\blk00000003/sig0000059e , \blk00000003/sig0000059f , \blk00000003/sig000005a0 }), + .BCOUT({\NLW_blk00000003/blk00000112_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000112_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000112_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000112_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000112_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000112_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000112_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000112_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000112_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000005a1 , \blk00000003/sig000005a2 , \blk00000003/sig000005a3 , \blk00000003/sig000005a4 , \blk00000003/sig000005a5 , +\blk00000003/sig000005a6 , \blk00000003/sig000005a7 , \blk00000003/sig000005a8 , \blk00000003/sig000005a9 , \blk00000003/sig000005aa , +\blk00000003/sig000005ab , \blk00000003/sig000005ac , \blk00000003/sig000005ad , \blk00000003/sig000005ae , \blk00000003/sig000005af , +\blk00000003/sig000005b0 , \blk00000003/sig000005b1 , \blk00000003/sig000005b2 , \blk00000003/sig000005b3 , \blk00000003/sig000005b4 , +\blk00000003/sig000005b5 , \blk00000003/sig000005b6 , \blk00000003/sig000005b7 , \blk00000003/sig000005b8 , \blk00000003/sig000005b9 , +\blk00000003/sig000005ba , \blk00000003/sig000005bb , \blk00000003/sig000005bc , \blk00000003/sig000005bd , \blk00000003/sig000005be , +\blk00000003/sig000005bf , \blk00000003/sig000005c0 , \blk00000003/sig000005c1 , \blk00000003/sig000005c2 , \blk00000003/sig000005c3 , +\blk00000003/sig000005c4 , \blk00000003/sig000005c5 , \blk00000003/sig000005c6 , \blk00000003/sig000005c7 , \blk00000003/sig000005c8 , +\blk00000003/sig000005c9 , \blk00000003/sig000005ca , \blk00000003/sig000005cb , \blk00000003/sig000005cc , \blk00000003/sig000005cd , +\blk00000003/sig000005ce , \blk00000003/sig000005cf , \blk00000003/sig000005d0 }), + .C({\NLW_blk00000003/blk00000112_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000112_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000005d1 , \blk00000003/sig000005d2 , \blk00000003/sig000005d3 , +\blk00000003/sig000005d4 , \blk00000003/sig000005d5 , \blk00000003/sig000005d6 , \blk00000003/sig000005d7 , \blk00000003/sig000005d8 , +\blk00000003/sig000005d9 , \blk00000003/sig000005da , \blk00000003/sig000005db , \blk00000003/sig000005dc , \blk00000003/sig000005dd , +\blk00000003/sig000005de , \blk00000003/sig000005df , \blk00000003/sig000005e0 }), + .PCOUT({\blk00000003/sig00000252 , \blk00000003/sig00000253 , \blk00000003/sig00000254 , \blk00000003/sig00000255 , \blk00000003/sig00000256 , +\blk00000003/sig00000257 , \blk00000003/sig00000258 , \blk00000003/sig00000259 , \blk00000003/sig0000025a , \blk00000003/sig0000025b , +\blk00000003/sig0000025c , \blk00000003/sig0000025d , \blk00000003/sig0000025e , \blk00000003/sig0000025f , \blk00000003/sig00000260 , +\blk00000003/sig00000261 , \blk00000003/sig00000262 , \blk00000003/sig00000263 , \blk00000003/sig00000264 , \blk00000003/sig00000265 , +\blk00000003/sig00000266 , \blk00000003/sig00000267 , \blk00000003/sig00000268 , \blk00000003/sig00000269 , \blk00000003/sig0000026a , +\blk00000003/sig0000026b , \blk00000003/sig0000026c , \blk00000003/sig0000026d , \blk00000003/sig0000026e , \blk00000003/sig0000026f , +\blk00000003/sig00000270 , \blk00000003/sig00000271 , \blk00000003/sig00000272 , \blk00000003/sig00000273 , \blk00000003/sig00000274 , +\blk00000003/sig00000275 , \blk00000003/sig00000276 , \blk00000003/sig00000277 , \blk00000003/sig00000278 , \blk00000003/sig00000279 , +\blk00000003/sig0000027a , \blk00000003/sig0000027b , \blk00000003/sig0000027c , \blk00000003/sig0000027d , \blk00000003/sig0000027e , +\blk00000003/sig0000027f , \blk00000003/sig00000280 , \blk00000003/sig00000281 }), + .A({\blk00000003/sig0000050d , \blk00000003/sig0000050e , \blk00000003/sig0000050f , \blk00000003/sig00000510 , \blk00000003/sig00000511 , +\blk00000003/sig00000512 , \blk00000003/sig00000513 , \blk00000003/sig00000514 , \blk00000003/sig00000515 , \blk00000003/sig00000516 , +\blk00000003/sig00000517 , \blk00000003/sig00000518 , \blk00000003/sig00000519 , \blk00000003/sig0000051a , \blk00000003/sig0000051b , +\blk00000003/sig0000051c , \blk00000003/sig0000051d , \blk00000003/sig0000051e }), + .M({\NLW_blk00000003/blk00000112_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<15>_UNCONNECTED , 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\blk00000003/blk00000111 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000111_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000111_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000581 , \blk00000003/sig00000581 , \blk00000003/sig00000581 , \blk00000003/sig00000581 , \blk00000003/sig00000581 , +\blk00000003/sig00000581 , \blk00000003/sig00000581 , \blk00000003/sig00000581 , \blk00000003/sig00000581 , \blk00000003/sig00000581 , +\blk00000003/sig00000581 , \blk00000003/sig00000582 , \blk00000003/sig00000583 , \blk00000003/sig00000584 , \blk00000003/sig00000585 , +\blk00000003/sig00000586 , \blk00000003/sig00000587 , \blk00000003/sig00000588 }), + .BCOUT({\NLW_blk00000003/blk00000111_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000111_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000111_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000111_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000111_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000111_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000111_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000111_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000111_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000003fd , \blk00000003/sig000003fe , \blk00000003/sig000003ff , \blk00000003/sig00000400 , \blk00000003/sig00000401 , +\blk00000003/sig00000402 , \blk00000003/sig00000403 , \blk00000003/sig00000404 , \blk00000003/sig00000405 , \blk00000003/sig00000406 , +\blk00000003/sig00000407 , \blk00000003/sig00000408 , \blk00000003/sig00000409 , \blk00000003/sig0000040a , \blk00000003/sig0000040b , +\blk00000003/sig0000040c , \blk00000003/sig0000040d , \blk00000003/sig0000040e , \blk00000003/sig0000040f , \blk00000003/sig00000410 , +\blk00000003/sig00000411 , \blk00000003/sig00000412 , \blk00000003/sig00000413 , \blk00000003/sig00000414 , \blk00000003/sig00000415 , +\blk00000003/sig00000416 , \blk00000003/sig00000417 , \blk00000003/sig00000418 , \blk00000003/sig00000419 , \blk00000003/sig0000041a , +\blk00000003/sig0000041b , \blk00000003/sig0000041c , \blk00000003/sig0000041d , \blk00000003/sig0000041e , \blk00000003/sig0000041f , +\blk00000003/sig00000420 , \blk00000003/sig00000421 , \blk00000003/sig00000422 , \blk00000003/sig00000423 , \blk00000003/sig00000424 , +\blk00000003/sig00000425 , \blk00000003/sig00000426 , \blk00000003/sig00000427 , \blk00000003/sig00000428 , \blk00000003/sig00000429 , +\blk00000003/sig0000042a , \blk00000003/sig0000042b , \blk00000003/sig0000042c }), + .C({\NLW_blk00000003/blk00000111_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000111_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000111_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000111_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<37>_UNCONNECTED , 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\NLW_blk00000003/blk00000111_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000111_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000111_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig00000589 , \blk00000003/sig00000589 , \blk00000003/sig00000589 , \blk00000003/sig00000589 , \blk00000003/sig00000589 , +\blk00000003/sig00000589 , \blk00000003/sig00000589 , \blk00000003/sig00000589 , \blk00000003/sig00000589 , \blk00000003/sig00000589 , +\blk00000003/sig00000589 , \blk00000003/sig0000058a , \blk00000003/sig0000058b , \blk00000003/sig0000058c , \blk00000003/sig0000058d , +\blk00000003/sig0000058e , \blk00000003/sig0000058f , \blk00000003/sig00000590 }), + .PCOUT({\blk00000003/sig00000527 , \blk00000003/sig00000528 , \blk00000003/sig00000529 , \blk00000003/sig0000052a , \blk00000003/sig0000052b , +\blk00000003/sig0000052c , \blk00000003/sig0000052d , \blk00000003/sig0000052e , \blk00000003/sig0000052f , \blk00000003/sig00000530 , +\blk00000003/sig00000531 , \blk00000003/sig00000532 , \blk00000003/sig00000533 , \blk00000003/sig00000534 , \blk00000003/sig00000535 , +\blk00000003/sig00000536 , \blk00000003/sig00000537 , \blk00000003/sig00000538 , \blk00000003/sig00000539 , \blk00000003/sig0000053a , +\blk00000003/sig0000053b , \blk00000003/sig0000053c , \blk00000003/sig0000053d , \blk00000003/sig0000053e , \blk00000003/sig0000053f , +\blk00000003/sig00000540 , \blk00000003/sig00000541 , \blk00000003/sig00000542 , \blk00000003/sig00000543 , \blk00000003/sig00000544 , +\blk00000003/sig00000545 , \blk00000003/sig00000546 , \blk00000003/sig00000547 , \blk00000003/sig00000548 , \blk00000003/sig00000549 , +\blk00000003/sig0000054a , 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.RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000110_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000110_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig0000055f , \blk00000003/sig0000055f , \blk00000003/sig0000055f , \blk00000003/sig0000055f , \blk00000003/sig0000055f , +\blk00000003/sig0000055f , \blk00000003/sig0000055f , \blk00000003/sig0000055f , \blk00000003/sig0000055f , \blk00000003/sig0000055f , +\blk00000003/sig0000055f , \blk00000003/sig00000560 , \blk00000003/sig00000561 , \blk00000003/sig00000562 , \blk00000003/sig00000563 , +\blk00000003/sig00000564 , \blk00000003/sig00000565 , \blk00000003/sig00000566 }), + .BCOUT({\NLW_blk00000003/blk00000110_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000110_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000110_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000110_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000110_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000110_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000110_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000110_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000110_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000110_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000110_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000110_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000110_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000110_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000110_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000110_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000110_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000110_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000003ab , \blk00000003/sig000003ac , \blk00000003/sig000003ad , \blk00000003/sig000003ae , \blk00000003/sig000003af , +\blk00000003/sig000003b0 , \blk00000003/sig000003b1 , \blk00000003/sig000003b2 , \blk00000003/sig000003b3 , \blk00000003/sig000003b4 , +\blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , \blk00000003/sig000003b8 , \blk00000003/sig000003b9 , +\blk00000003/sig000003ba , \blk00000003/sig000003bb , \blk00000003/sig000003bc , \blk00000003/sig000003bd , \blk00000003/sig000003be , +\blk00000003/sig000003bf , \blk00000003/sig000003c0 , \blk00000003/sig000003c1 , \blk00000003/sig000003c2 , \blk00000003/sig000003c3 , +\blk00000003/sig000003c4 , \blk00000003/sig000003c5 , \blk00000003/sig000003c6 , \blk00000003/sig000003c7 , \blk00000003/sig000003c8 , +\blk00000003/sig000003c9 , \blk00000003/sig000003ca , \blk00000003/sig000003cb , \blk00000003/sig000003cc , \blk00000003/sig000003cd , +\blk00000003/sig000003ce , \blk00000003/sig000003cf , \blk00000003/sig000003d0 , \blk00000003/sig000003d1 , \blk00000003/sig000003d2 , +\blk00000003/sig000003d3 , \blk00000003/sig000003d4 , \blk00000003/sig000003d5 , \blk00000003/sig000003d6 , \blk00000003/sig000003d7 , +\blk00000003/sig000003d8 , \blk00000003/sig000003d9 , \blk00000003/sig000003da }), + .C({\NLW_blk00000003/blk00000110_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000110_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig00000567 , \blk00000003/sig00000567 , \blk00000003/sig00000567 , \blk00000003/sig00000567 , \blk00000003/sig00000567 , +\blk00000003/sig00000567 , \blk00000003/sig00000567 , \blk00000003/sig00000567 , \blk00000003/sig00000567 , \blk00000003/sig00000567 , +\blk00000003/sig00000567 , \blk00000003/sig00000568 , \blk00000003/sig00000569 , \blk00000003/sig0000056a , \blk00000003/sig0000056b , +\blk00000003/sig0000056c , \blk00000003/sig0000056d , \blk00000003/sig0000056e }), + .PCOUT({\blk00000003/sig000004d5 , \blk00000003/sig000004d6 , \blk00000003/sig000004d7 , \blk00000003/sig000004d8 , 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+\NLW_blk00000003/blk00000110_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010f ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010f_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010f_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig0000051f , \blk00000003/sig0000051f , \blk00000003/sig0000051f , \blk00000003/sig0000051f , \blk00000003/sig0000051f , +\blk00000003/sig0000051f , \blk00000003/sig0000051f , \blk00000003/sig0000051f , \blk00000003/sig0000051f , \blk00000003/sig0000051f , +\blk00000003/sig0000051f , \blk00000003/sig00000520 , \blk00000003/sig00000521 , \blk00000003/sig00000522 , \blk00000003/sig00000523 , +\blk00000003/sig00000524 , \blk00000003/sig00000525 , \blk00000003/sig00000526 }), + .BCOUT({\NLW_blk00000003/blk0000010f_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000527 , \blk00000003/sig00000528 , \blk00000003/sig00000529 , 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\NLW_blk00000003/blk0000010f_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<13>_UNCONNECTED , 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\NLW_blk00000003/blk0000010f_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<30>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<29>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<27>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<26>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<24>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<23>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<21>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<20>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig00000557 , \blk00000003/sig00000557 , \blk00000003/sig00000557 , \blk00000003/sig00000557 , \blk00000003/sig00000557 , +\blk00000003/sig00000557 , \blk00000003/sig00000557 , \blk00000003/sig00000557 , \blk00000003/sig00000557 , \blk00000003/sig00000557 , +\blk00000003/sig00000557 , \blk00000003/sig00000558 , \blk00000003/sig00000559 , \blk00000003/sig0000055a , \blk00000003/sig0000055b , +\blk00000003/sig0000055c , \blk00000003/sig0000055d , \blk00000003/sig0000055e }), + .PCOUT({\blk00000003/sig00000178 , \blk00000003/sig00000179 , \blk00000003/sig0000017a , \blk00000003/sig0000017b , \blk00000003/sig0000017c , +\blk00000003/sig0000017d , \blk00000003/sig0000017e , \blk00000003/sig0000017f , \blk00000003/sig00000180 , \blk00000003/sig00000181 , +\blk00000003/sig00000182 , \blk00000003/sig00000183 , \blk00000003/sig00000184 , \blk00000003/sig00000185 , \blk00000003/sig00000186 , +\blk00000003/sig00000187 , \blk00000003/sig00000188 , \blk00000003/sig00000189 , \blk00000003/sig0000018a , \blk00000003/sig0000018b , +\blk00000003/sig0000018c , \blk00000003/sig0000018d , \blk00000003/sig0000018e , \blk00000003/sig0000018f , \blk00000003/sig00000190 , +\blk00000003/sig00000191 , \blk00000003/sig00000192 , \blk00000003/sig00000193 , \blk00000003/sig00000194 , \blk00000003/sig00000195 , +\blk00000003/sig00000196 , \blk00000003/sig00000197 , \blk00000003/sig00000198 , \blk00000003/sig00000199 , \blk00000003/sig0000019a , +\blk00000003/sig0000019b , \blk00000003/sig0000019c , \blk00000003/sig0000019d , \blk00000003/sig0000019e , \blk00000003/sig0000019f , +\blk00000003/sig000001a0 , \blk00000003/sig000001a1 , \blk00000003/sig000001a2 , \blk00000003/sig000001a3 , \blk00000003/sig000001a4 , +\blk00000003/sig000001a5 , \blk00000003/sig000001a6 , \blk00000003/sig000001a7 }), + .A({\blk00000003/sig0000050d , \blk00000003/sig0000050e , \blk00000003/sig0000050f , \blk00000003/sig00000510 , \blk00000003/sig00000511 , +\blk00000003/sig00000512 , \blk00000003/sig00000513 , \blk00000003/sig00000514 , \blk00000003/sig00000515 , \blk00000003/sig00000516 , +\blk00000003/sig00000517 , \blk00000003/sig00000518 , \blk00000003/sig00000519 , \blk00000003/sig0000051a , \blk00000003/sig0000051b , +\blk00000003/sig0000051c , \blk00000003/sig0000051d , \blk00000003/sig0000051e }), + .M({\NLW_blk00000003/blk0000010f_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010e ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010e_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010e_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig000004cd , \blk00000003/sig000004cd , \blk00000003/sig000004cd , \blk00000003/sig000004cd , \blk00000003/sig000004cd , +\blk00000003/sig000004cd , \blk00000003/sig000004cd , \blk00000003/sig000004cd , \blk00000003/sig000004cd , \blk00000003/sig000004cd , +\blk00000003/sig000004cd , \blk00000003/sig000004ce , \blk00000003/sig000004cf , \blk00000003/sig000004d0 , \blk00000003/sig000004d1 , +\blk00000003/sig000004d2 , \blk00000003/sig000004d3 , \blk00000003/sig000004d4 }), + .BCOUT({\NLW_blk00000003/blk0000010e_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000004d5 , \blk00000003/sig000004d6 , \blk00000003/sig000004d7 , \blk00000003/sig000004d8 , \blk00000003/sig000004d9 , +\blk00000003/sig000004da , \blk00000003/sig000004db , \blk00000003/sig000004dc , \blk00000003/sig000004dd , \blk00000003/sig000004de , +\blk00000003/sig000004df , \blk00000003/sig000004e0 , \blk00000003/sig000004e1 , \blk00000003/sig000004e2 , \blk00000003/sig000004e3 , +\blk00000003/sig000004e4 , \blk00000003/sig000004e5 , \blk00000003/sig000004e6 , \blk00000003/sig000004e7 , \blk00000003/sig000004e8 , +\blk00000003/sig000004e9 , \blk00000003/sig000004ea , \blk00000003/sig000004eb , \blk00000003/sig000004ec , \blk00000003/sig000004ed , +\blk00000003/sig000004ee , \blk00000003/sig000004ef , \blk00000003/sig000004f0 , \blk00000003/sig000004f1 , \blk00000003/sig000004f2 , +\blk00000003/sig000004f3 , \blk00000003/sig000004f4 , \blk00000003/sig000004f5 , \blk00000003/sig000004f6 , \blk00000003/sig000004f7 , +\blk00000003/sig000004f8 , \blk00000003/sig000004f9 , \blk00000003/sig000004fa , \blk00000003/sig000004fb , \blk00000003/sig000004fc , +\blk00000003/sig000004fd , \blk00000003/sig000004fe , \blk00000003/sig000004ff , \blk00000003/sig00000500 , \blk00000003/sig00000501 , +\blk00000003/sig00000502 , \blk00000003/sig00000503 , \blk00000003/sig00000504 }), + .C({\NLW_blk00000003/blk0000010e_C<47>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<45>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<44>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<42>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<41>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<39>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<38>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<36>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010e_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<30>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<29>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<27>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<26>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<24>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<23>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<21>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<20>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig00000505 , \blk00000003/sig00000505 , \blk00000003/sig00000505 , \blk00000003/sig00000505 , \blk00000003/sig00000505 , +\blk00000003/sig00000505 , \blk00000003/sig00000505 , \blk00000003/sig00000505 , \blk00000003/sig00000505 , \blk00000003/sig00000505 , +\blk00000003/sig00000505 , \blk00000003/sig00000506 , \blk00000003/sig00000507 , \blk00000003/sig00000508 , \blk00000003/sig00000509 , +\blk00000003/sig0000050a , \blk00000003/sig0000050b , \blk00000003/sig0000050c }), + .PCOUT({\blk00000003/sig00000212 , \blk00000003/sig00000213 , \blk00000003/sig00000214 , \blk00000003/sig00000215 , \blk00000003/sig00000216 , +\blk00000003/sig00000217 , \blk00000003/sig00000218 , \blk00000003/sig00000219 , \blk00000003/sig0000021a , \blk00000003/sig0000021b , +\blk00000003/sig0000021c , \blk00000003/sig0000021d , \blk00000003/sig0000021e , \blk00000003/sig0000021f , \blk00000003/sig00000220 , +\blk00000003/sig00000221 , \blk00000003/sig00000222 , \blk00000003/sig00000223 , \blk00000003/sig00000224 , \blk00000003/sig00000225 , +\blk00000003/sig00000226 , \blk00000003/sig00000227 , \blk00000003/sig00000228 , \blk00000003/sig00000229 , \blk00000003/sig0000022a , +\blk00000003/sig0000022b , \blk00000003/sig0000022c , \blk00000003/sig0000022d , \blk00000003/sig0000022e , \blk00000003/sig0000022f , +\blk00000003/sig00000230 , \blk00000003/sig00000231 , \blk00000003/sig00000232 , \blk00000003/sig00000233 , \blk00000003/sig00000234 , +\blk00000003/sig00000235 , \blk00000003/sig00000236 , \blk00000003/sig00000237 , \blk00000003/sig00000238 , \blk00000003/sig00000239 , +\blk00000003/sig0000023a , \blk00000003/sig0000023b , \blk00000003/sig0000023c , \blk00000003/sig0000023d , \blk00000003/sig0000023e , +\blk00000003/sig0000023f , \blk00000003/sig00000240 , \blk00000003/sig00000241 }), + .A({\blk00000003/sig0000050d , \blk00000003/sig0000050e , \blk00000003/sig0000050f , \blk00000003/sig00000510 , \blk00000003/sig00000511 , +\blk00000003/sig00000512 , \blk00000003/sig00000513 , \blk00000003/sig00000514 , \blk00000003/sig00000515 , \blk00000003/sig00000516 , +\blk00000003/sig00000517 , \blk00000003/sig00000518 , \blk00000003/sig00000519 , \blk00000003/sig0000051a , \blk00000003/sig0000051b , +\blk00000003/sig0000051c , \blk00000003/sig0000051d , \blk00000003/sig0000051e }), + .M({\NLW_blk00000003/blk0000010e_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010d ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010d_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010d_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig0000047d , \blk00000003/sig0000047e , \blk00000003/sig0000047f , +\blk00000003/sig00000480 , \blk00000003/sig00000481 , \blk00000003/sig00000482 , \blk00000003/sig00000483 , \blk00000003/sig00000484 , +\blk00000003/sig00000485 , \blk00000003/sig00000486 , \blk00000003/sig00000487 , \blk00000003/sig00000488 , \blk00000003/sig00000489 , +\blk00000003/sig0000048a , \blk00000003/sig0000048b , \blk00000003/sig0000048c }), + .BCOUT({\NLW_blk00000003/blk0000010d_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , 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\blk00000003/sig00000049 }), + .C({\NLW_blk00000003/blk0000010d_C<47>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<45>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<44>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<42>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<41>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<39>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<38>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<36>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010d_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<37>_UNCONNECTED , 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\NLW_blk00000003/blk0000010d_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig0000048d , \blk00000003/sig0000048e , \blk00000003/sig0000048f , +\blk00000003/sig00000490 , \blk00000003/sig00000491 , \blk00000003/sig00000492 , \blk00000003/sig00000493 , \blk00000003/sig00000494 , +\blk00000003/sig00000495 , \blk00000003/sig00000496 , \blk00000003/sig00000497 , \blk00000003/sig00000498 , \blk00000003/sig00000499 , +\blk00000003/sig0000049a , \blk00000003/sig0000049b , \blk00000003/sig0000049c }), + .PCOUT({\blk00000003/sig0000049d , \blk00000003/sig0000049e , \blk00000003/sig0000049f , \blk00000003/sig000004a0 , \blk00000003/sig000004a1 , +\blk00000003/sig000004a2 , \blk00000003/sig000004a3 , \blk00000003/sig000004a4 , \blk00000003/sig000004a5 , \blk00000003/sig000004a6 , +\blk00000003/sig000004a7 , \blk00000003/sig000004a8 , \blk00000003/sig000004a9 , \blk00000003/sig000004aa , \blk00000003/sig000004ab , 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+\NLW_blk00000003/blk0000010d_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010c ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010c_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010c_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig0000042d , \blk00000003/sig0000042e , \blk00000003/sig0000042f , +\blk00000003/sig00000430 , \blk00000003/sig00000431 , \blk00000003/sig00000432 , \blk00000003/sig00000433 , \blk00000003/sig00000434 , +\blk00000003/sig00000435 , \blk00000003/sig00000436 , \blk00000003/sig00000437 , \blk00000003/sig00000438 , \blk00000003/sig00000439 , +\blk00000003/sig0000043a , \blk00000003/sig0000043b , \blk00000003/sig0000043c }), + .BCOUT({\NLW_blk00000003/blk0000010c_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010c_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010c_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010c_BCOUT<12>_UNCONNECTED , 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.C({\NLW_blk00000003/blk0000010c_C<47>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<45>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<44>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<42>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<41>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<39>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<38>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<36>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<28>_UNCONNECTED , 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\NLW_blk00000003/blk0000010c_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010c_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<36>_UNCONNECTED , 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\blk00000003/sig000000ac }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig0000043d , \blk00000003/sig0000043e , \blk00000003/sig0000043f , +\blk00000003/sig00000440 , \blk00000003/sig00000441 , \blk00000003/sig00000442 , \blk00000003/sig00000443 , \blk00000003/sig00000444 , +\blk00000003/sig00000445 , \blk00000003/sig00000446 , \blk00000003/sig00000447 , \blk00000003/sig00000448 , \blk00000003/sig00000449 , +\blk00000003/sig0000044a , \blk00000003/sig0000044b , \blk00000003/sig0000044c }), + .PCOUT({\blk00000003/sig0000044d , \blk00000003/sig0000044e , \blk00000003/sig0000044f , \blk00000003/sig00000450 , \blk00000003/sig00000451 , +\blk00000003/sig00000452 , \blk00000003/sig00000453 , \blk00000003/sig00000454 , \blk00000003/sig00000455 , \blk00000003/sig00000456 , +\blk00000003/sig00000457 , \blk00000003/sig00000458 , \blk00000003/sig00000459 , \blk00000003/sig0000045a , \blk00000003/sig0000045b , +\blk00000003/sig0000045c , \blk00000003/sig0000045d , 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\NLW_blk00000003/blk0000010b_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010b_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<30>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<29>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<27>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<26>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<24>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<23>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<21>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<20>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig000003f5 , \blk00000003/sig000003f5 , \blk00000003/sig000003f5 , \blk00000003/sig000003f5 , \blk00000003/sig000003f5 , +\blk00000003/sig000003f5 , \blk00000003/sig000003f5 , \blk00000003/sig000003f5 , \blk00000003/sig000003f5 , \blk00000003/sig000003f5 , +\blk00000003/sig000003f5 , \blk00000003/sig000003f6 , \blk00000003/sig000003f7 , \blk00000003/sig000003f8 , \blk00000003/sig000003f9 , +\blk00000003/sig000003fa , \blk00000003/sig000003fb , \blk00000003/sig000003fc }), + .PCOUT({\blk00000003/sig000003fd , \blk00000003/sig000003fe , \blk00000003/sig000003ff , \blk00000003/sig00000400 , \blk00000003/sig00000401 , +\blk00000003/sig00000402 , \blk00000003/sig00000403 , \blk00000003/sig00000404 , \blk00000003/sig00000405 , \blk00000003/sig00000406 , +\blk00000003/sig00000407 , \blk00000003/sig00000408 , \blk00000003/sig00000409 , \blk00000003/sig0000040a , \blk00000003/sig0000040b , +\blk00000003/sig0000040c , \blk00000003/sig0000040d , \blk00000003/sig0000040e , \blk00000003/sig0000040f , \blk00000003/sig00000410 , +\blk00000003/sig00000411 , \blk00000003/sig00000412 , \blk00000003/sig00000413 , \blk00000003/sig00000414 , \blk00000003/sig00000415 , +\blk00000003/sig00000416 , \blk00000003/sig00000417 , \blk00000003/sig00000418 , \blk00000003/sig00000419 , \blk00000003/sig0000041a , +\blk00000003/sig0000041b , \blk00000003/sig0000041c , \blk00000003/sig0000041d , \blk00000003/sig0000041e , \blk00000003/sig0000041f , +\blk00000003/sig00000420 , \blk00000003/sig00000421 , \blk00000003/sig00000422 , \blk00000003/sig00000423 , \blk00000003/sig00000424 , +\blk00000003/sig00000425 , \blk00000003/sig00000426 , \blk00000003/sig00000427 , \blk00000003/sig00000428 , \blk00000003/sig00000429 , +\blk00000003/sig0000042a , \blk00000003/sig0000042b , \blk00000003/sig0000042c }), + .A({\blk00000003/sig000003db , \blk00000003/sig000003dc , \blk00000003/sig000003dd , \blk00000003/sig000003de , \blk00000003/sig000003df , +\blk00000003/sig000003e0 , \blk00000003/sig000003e1 , \blk00000003/sig000003e2 , \blk00000003/sig000003e3 , \blk00000003/sig000003e4 , +\blk00000003/sig000003e5 , \blk00000003/sig000003e6 , \blk00000003/sig000003e7 , \blk00000003/sig000003e8 , \blk00000003/sig000003e9 , +\blk00000003/sig000003ea , \blk00000003/sig000003eb , \blk00000003/sig000003ec }), + .M({\NLW_blk00000003/blk0000010b_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010a ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010a_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010a_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig0000039b , \blk00000003/sig0000039b , \blk00000003/sig0000039b , \blk00000003/sig0000039b , \blk00000003/sig0000039b , +\blk00000003/sig0000039b , \blk00000003/sig0000039b , \blk00000003/sig0000039b , \blk00000003/sig0000039b , \blk00000003/sig0000039b , +\blk00000003/sig0000039b , \blk00000003/sig0000039c , \blk00000003/sig0000039d , \blk00000003/sig0000039e , \blk00000003/sig0000039f , +\blk00000003/sig000003a0 , \blk00000003/sig000003a1 , \blk00000003/sig000003a2 }), + .BCOUT({\NLW_blk00000003/blk0000010a_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\NLW_blk00000003/blk0000010a_C<47>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<45>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<44>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<42>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<41>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<39>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<38>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<36>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010a_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<30>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<29>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<27>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<26>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<24>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<23>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<21>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<20>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig000003a3 , \blk00000003/sig000003a3 , \blk00000003/sig000003a3 , \blk00000003/sig000003a3 , \blk00000003/sig000003a3 , +\blk00000003/sig000003a3 , \blk00000003/sig000003a3 , \blk00000003/sig000003a3 , \blk00000003/sig000003a3 , \blk00000003/sig000003a3 , +\blk00000003/sig000003a3 , \blk00000003/sig000003a4 , \blk00000003/sig000003a5 , \blk00000003/sig000003a6 , \blk00000003/sig000003a7 , +\blk00000003/sig000003a8 , \blk00000003/sig000003a9 , \blk00000003/sig000003aa }), + .PCOUT({\blk00000003/sig000003ab , \blk00000003/sig000003ac , \blk00000003/sig000003ad , \blk00000003/sig000003ae , \blk00000003/sig000003af , +\blk00000003/sig000003b0 , \blk00000003/sig000003b1 , \blk00000003/sig000003b2 , \blk00000003/sig000003b3 , \blk00000003/sig000003b4 , +\blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , \blk00000003/sig000003b8 , \blk00000003/sig000003b9 , +\blk00000003/sig000003ba , \blk00000003/sig000003bb , \blk00000003/sig000003bc , \blk00000003/sig000003bd , \blk00000003/sig000003be , +\blk00000003/sig000003bf , \blk00000003/sig000003c0 , \blk00000003/sig000003c1 , \blk00000003/sig000003c2 , \blk00000003/sig000003c3 , +\blk00000003/sig000003c4 , \blk00000003/sig000003c5 , \blk00000003/sig000003c6 , \blk00000003/sig000003c7 , \blk00000003/sig000003c8 , +\blk00000003/sig000003c9 , \blk00000003/sig000003ca , \blk00000003/sig000003cb , \blk00000003/sig000003cc , \blk00000003/sig000003cd , +\blk00000003/sig000003ce , \blk00000003/sig000003cf , \blk00000003/sig000003d0 , \blk00000003/sig000003d1 , \blk00000003/sig000003d2 , +\blk00000003/sig000003d3 , \blk00000003/sig000003d4 , \blk00000003/sig000003d5 , \blk00000003/sig000003d6 , \blk00000003/sig000003d7 , +\blk00000003/sig000003d8 , \blk00000003/sig000003d9 , \blk00000003/sig000003da }), + .A({\blk00000003/sig000003db , \blk00000003/sig000003dc , \blk00000003/sig000003dd , \blk00000003/sig000003de , \blk00000003/sig000003df , +\blk00000003/sig000003e0 , \blk00000003/sig000003e1 , \blk00000003/sig000003e2 , \blk00000003/sig000003e3 , \blk00000003/sig000003e4 , +\blk00000003/sig000003e5 , \blk00000003/sig000003e6 , \blk00000003/sig000003e7 , \blk00000003/sig000003e8 , \blk00000003/sig000003e9 , +\blk00000003/sig000003ea , \blk00000003/sig000003eb , \blk00000003/sig000003ec }), + .M({\NLW_blk00000003/blk0000010a_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<0>_UNCONNECTED }) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000109 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029e ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000039a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000108 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000398 ), + .Q(\blk00000003/sig00000399 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000107 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000397 ), + .Q(\blk00000003/sig0000038f ) + ); + XORCY \blk00000003/blk00000106 ( + .CI(\blk00000003/sig00000392 ), + .LI(\blk00000003/sig00000395 ), + .O(\blk00000003/sig00000396 ) + ); + MUXCY_D \blk00000003/blk00000105 ( + .CI(\blk00000003/sig00000392 ), + .DI(\blk00000003/sig00000394 ), + .S(\blk00000003/sig00000395 ), + .O(\NLW_blk00000003/blk00000105_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk00000105_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000104 ( + .CI(\blk00000003/sig0000038f ), + .LI(\blk00000003/sig00000391 ), + .O(\blk00000003/sig00000393 ) + ); + MUXCY_L \blk00000003/blk00000103 ( + .CI(\blk00000003/sig0000038f ), + .DI(\blk00000003/sig00000390 ), + .S(\blk00000003/sig00000391 ), + .LO(\blk00000003/sig00000392 ) + ); + MUXCY_L \blk00000003/blk00000102 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig0000038e ), + .S(\blk00000003/sig00000388 ), + .LO(\blk00000003/sig0000038a ) + ); + MUXCY_D \blk00000003/blk00000101 ( + .CI(\blk00000003/sig0000038a ), + .DI(\blk00000003/sig0000038d ), + .S(\blk00000003/sig0000038b ), + .O(\NLW_blk00000003/blk00000101_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk00000101_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000100 ( + .CI(\blk00000003/sig0000038a ), + .LI(\blk00000003/sig0000038b ), + .O(\blk00000003/sig0000038c ) + ); + XORCY \blk00000003/blk000000ff ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000388 ), + .O(\blk00000003/sig00000389 ) + ); + MUXCY_L \blk00000003/blk000000fe ( + .CI(\blk00000003/sig0000037f ), + .DI(\blk00000003/sig00000387 ), + .S(\blk00000003/sig00000380 ), + .LO(\blk00000003/sig00000382 ) + ); + MUXCY_D \blk00000003/blk000000fd ( + .CI(\blk00000003/sig00000382 ), + .DI(\blk00000003/sig00000386 ), + .S(\blk00000003/sig00000383 ), + .O(\NLW_blk00000003/blk000000fd_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000fd_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000fc ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig00000385 ), + .O(\blk00000003/sig0000037f ) + ); + XORCY \blk00000003/blk000000fb ( + .CI(\blk00000003/sig00000382 ), + .LI(\blk00000003/sig00000383 ), + .O(\blk00000003/sig00000384 ) + ); + XORCY \blk00000003/blk000000fa ( + .CI(\blk00000003/sig0000037f ), + .LI(\blk00000003/sig00000380 ), + .O(\blk00000003/sig00000381 ) + ); + FDE \blk00000003/blk000000f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000037d ), + .Q(\blk00000003/sig0000037e ) + ); + MUXCY_L \blk00000003/blk000000f8 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig0000037c ), + .S(\blk00000003/sig00000376 ), + .LO(\blk00000003/sig00000378 ) + ); + MUXCY_D \blk00000003/blk000000f7 ( + .CI(\blk00000003/sig00000378 ), + .DI(\blk00000003/sig0000037b ), + .S(\blk00000003/sig00000379 ), + .O(\NLW_blk00000003/blk000000f7_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000f7_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000f6 ( + .CI(\blk00000003/sig00000378 ), + .LI(\blk00000003/sig00000379 ), + .O(\blk00000003/sig0000037a ) + ); + XORCY \blk00000003/blk000000f5 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000376 ), + .O(\blk00000003/sig00000377 ) + ); + MUXCY_L \blk00000003/blk000000f4 ( + .CI(\blk00000003/sig0000036f ), + .DI(\blk00000003/sig000002b8 ), + .S(\blk00000003/sig00000370 ), + .LO(\blk00000003/sig00000372 ) + ); + MUXCY_D \blk00000003/blk000000f3 ( + .CI(\blk00000003/sig00000372 ), + .DI(\blk00000003/sig000002b7 ), + .S(\blk00000003/sig00000373 ), + .O(\NLW_blk00000003/blk000000f3_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000f3_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000f2 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig00000375 ), + .O(\blk00000003/sig0000036f ) + ); + XORCY \blk00000003/blk000000f1 ( + .CI(\blk00000003/sig00000372 ), + .LI(\blk00000003/sig00000373 ), + .O(\blk00000003/sig00000374 ) + ); + XORCY \blk00000003/blk000000f0 ( + .CI(\blk00000003/sig0000036f ), + .LI(\blk00000003/sig00000370 ), + .O(\blk00000003/sig00000371 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000036d ), + .R(sclr), + .Q(\blk00000003/sig0000036e ) + ); + MUXCY_D \blk00000003/blk000000ee ( + .CI(\blk00000003/sig0000036a ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000036c ), + .O(\NLW_blk00000003/blk000000ee_O_UNCONNECTED ), + .LO(\blk00000003/sig0000036d ) + ); + MUXCY_D \blk00000003/blk000000ed ( + .CI(\blk00000003/sig000000ac ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000036b ), + .O(\blk00000003/sig00000367 ), + .LO(\NLW_blk00000003/blk000000ed_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000ec ( + .CI(\blk00000003/sig00000369 ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000365 ) + ); + MUXCY \blk00000003/blk000000eb ( + .CI(\blk00000003/sig00000369 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000ac ), + .O(\blk00000003/sig0000036a ) + ); + MUXCY_D \blk00000003/blk000000ea ( + .CI(\blk00000003/sig00000367 ), + .DI(\blk00000003/sig00000366 ), + .S(\blk00000003/sig00000368 ), + .O(\blk00000003/sig00000369 ), + .LO(\NLW_blk00000003/blk000000ea_LO_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000365 ), + .R(sclr), + .Q(\blk00000003/sig00000366 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000356 ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002f0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000355 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002ed ) + ); + MUXCY_D \blk00000003/blk000000e6 ( + .CI(\blk00000003/sig000002ed ), + .DI(\blk00000003/sig00000363 ), + .S(\blk00000003/sig00000364 ), + .O(\blk00000003/sig00000360 ), + .LO(\NLW_blk00000003/blk000000e6_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000e5 ( + .CI(\blk00000003/sig00000360 ), + .DI(\blk00000003/sig00000361 ), + .S(\blk00000003/sig00000362 ), + .O(\blk00000003/sig0000035e ), + .LO(\NLW_blk00000003/blk000000e5_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000e4 ( + .CI(\blk00000003/sig0000035e ), + .DI(\blk00000003/sig00000354 ), + .S(\blk00000003/sig0000035f ), + .O(\blk00000003/sig0000035b ), + .LO(\NLW_blk00000003/blk000000e4_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000e3 ( + .CI(\blk00000003/sig0000035b ), + .DI(\blk00000003/sig0000035c ), + .S(\blk00000003/sig0000035d ), + .O(\blk00000003/sig00000359 ), + .LO(\NLW_blk00000003/blk000000e3_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000e2 ( + .CI(\blk00000003/sig00000359 ), + .DI(\blk00000003/sig00000319 ), + .S(\blk00000003/sig0000035a ), + .O(\blk00000003/sig00000357 ), + .LO(\NLW_blk00000003/blk000000e2_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000e1 ( + .CI(\blk00000003/sig00000357 ), + .DI(\blk00000003/sig000002ea ), + .S(\blk00000003/sig00000358 ), + .O(\NLW_blk00000003/blk000000e1_O_UNCONNECTED ), + .LO(\blk00000003/sig00000355 ) + ); + XORCY \blk00000003/blk000000e0 ( + .CI(\blk00000003/sig00000355 ), + .LI(\blk00000003/sig000000ac ), + .O(\blk00000003/sig00000356 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000df ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000344 ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000354 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000de ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000343 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000029e ) + ); + MUXCY_D \blk00000003/blk000000dd ( + .CI(\blk00000003/sig0000029e ), + .DI(\blk00000003/sig00000352 ), + .S(\blk00000003/sig00000353 ), + .O(\blk00000003/sig00000350 ), + .LO(\NLW_blk00000003/blk000000dd_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000dc ( + .CI(\blk00000003/sig00000350 ), + .DI(\blk00000003/sig0000029f ), + .S(\blk00000003/sig00000351 ), + .O(\blk00000003/sig0000034e ), + .LO(\NLW_blk00000003/blk000000dc_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000db ( + .CI(\blk00000003/sig0000034e ), + .DI(\blk00000003/sig0000029e ), + .S(\blk00000003/sig0000034f ), + .O(\blk00000003/sig0000034b ), + .LO(\NLW_blk00000003/blk000000db_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000da ( + .CI(\blk00000003/sig0000034b ), + .DI(\blk00000003/sig0000034c ), + .S(\blk00000003/sig0000034d ), + .O(\blk00000003/sig00000349 ), + .LO(\NLW_blk00000003/blk000000da_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d9 ( + .CI(\blk00000003/sig00000349 ), + .DI(\blk00000003/sig000002f0 ), + .S(\blk00000003/sig0000034a ), + .O(\blk00000003/sig00000345 ), + .LO(\NLW_blk00000003/blk000000d9_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d8 ( + .CI(\blk00000003/sig00000347 ), + .DI(\blk00000003/sig000002f0 ), + .S(\blk00000003/sig00000348 ), + .O(\NLW_blk00000003/blk000000d8_O_UNCONNECTED ), + .LO(\blk00000003/sig00000343 ) + ); + MUXCY_D \blk00000003/blk000000d7 ( + .CI(\blk00000003/sig00000345 ), + .DI(\blk00000003/sig0000030e ), + .S(\blk00000003/sig00000346 ), + .O(\blk00000003/sig00000347 ), + .LO(\NLW_blk00000003/blk000000d7_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000d6 ( + .CI(\blk00000003/sig00000343 ), + .LI(\blk00000003/sig000000ac ), + .O(\blk00000003/sig00000344 ) + ); + FDE \blk00000003/blk000000d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000341 ), + .Q(\blk00000003/sig00000342 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ed ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000340 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000031f ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000338 ) + ); + XORCY \blk00000003/blk000000d2 ( + .CI(\blk00000003/sig0000033b ), + .LI(\blk00000003/sig0000033e ), + .O(\blk00000003/sig0000033f ) + ); + MUXCY_D \blk00000003/blk000000d1 ( + .CI(\blk00000003/sig0000033b ), + .DI(\blk00000003/sig0000033d ), + .S(\blk00000003/sig0000033e ), + .O(\NLW_blk00000003/blk000000d1_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000d1_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000d0 ( + .CI(\blk00000003/sig00000338 ), + .LI(\blk00000003/sig0000033a ), + .O(\blk00000003/sig0000033c ) + ); + MUXCY_L \blk00000003/blk000000cf ( + .CI(\blk00000003/sig00000338 ), + .DI(\blk00000003/sig00000339 ), + .S(\blk00000003/sig0000033a ), + .LO(\blk00000003/sig0000033b ) + ); + MUXCY_L \blk00000003/blk000000ce ( + .CI(\blk00000003/sig0000032f ), + .DI(\blk00000003/sig00000337 ), + .S(\blk00000003/sig00000330 ), + .LO(\blk00000003/sig00000332 ) + ); + MUXCY_D \blk00000003/blk000000cd ( + .CI(\blk00000003/sig00000332 ), + .DI(\blk00000003/sig00000336 ), + .S(\blk00000003/sig00000333 ), + .O(\NLW_blk00000003/blk000000cd_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000cd_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000cc ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig00000335 ), + .O(\blk00000003/sig0000032f ) + ); + XORCY \blk00000003/blk000000cb ( + .CI(\blk00000003/sig00000332 ), + .LI(\blk00000003/sig00000333 ), + .O(\blk00000003/sig00000334 ) + ); + XORCY \blk00000003/blk000000ca ( + .CI(\blk00000003/sig0000032f ), + .LI(\blk00000003/sig00000330 ), + .O(\blk00000003/sig00000331 ) + ); + MUXCY_L \blk00000003/blk000000c9 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig0000032e ), + .S(\blk00000003/sig0000032c ), + .LO(\blk00000003/sig00000328 ) + ); + XORCY \blk00000003/blk000000c8 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig0000032c ), + .O(\blk00000003/sig0000032d ) + ); + MUXCY_D \blk00000003/blk000000c7 ( + .CI(\blk00000003/sig00000328 ), + .DI(\blk00000003/sig0000032b ), + .S(\blk00000003/sig00000329 ), + .O(\NLW_blk00000003/blk000000c7_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000c7_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000c6 ( + .CI(\blk00000003/sig00000328 ), + .LI(\blk00000003/sig00000329 ), + .O(\blk00000003/sig0000032a ) + ); + MUXCY_L \blk00000003/blk000000c5 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000327 ), + .S(\blk00000003/sig00000325 ), + .LO(\blk00000003/sig00000321 ) + ); + XORCY \blk00000003/blk000000c4 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000325 ), + .O(\blk00000003/sig00000326 ) + ); + MUXCY_D \blk00000003/blk000000c3 ( + .CI(\blk00000003/sig00000321 ), + .DI(\blk00000003/sig00000324 ), + .S(\blk00000003/sig00000322 ), + .O(\NLW_blk00000003/blk000000c3_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000c3_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000c2 ( + .CI(\blk00000003/sig00000321 ), + .LI(\blk00000003/sig00000322 ), + .O(\blk00000003/sig00000323 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c1 ( + .C(clk), + .CE(ce), + .D(coef_ld), + .Q(\blk00000003/sig00000320 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c0 ( + .C(clk), + .CE(ce), + .D(coef_we), + .Q(\blk00000003/sig0000031f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b1 ), + .Q(\blk00000003/sig00000313 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000031e ), + .Q(\blk00000003/sig00000306 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000031c ), + .Q(\blk00000003/sig0000031d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000031b ), + .Q(\blk00000003/sig00000304 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000031a ), + .Q(\blk00000003/sig00000311 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000318 ), + .Q(\blk00000003/sig00000319 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000316 ), + .Q(\blk00000003/sig00000317 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000314 ), + .Q(\blk00000003/sig00000315 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000313 ), + .Q(\blk00000003/sig0000030f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000311 ), + .Q(\blk00000003/sig00000312 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000030f ), + .Q(\blk00000003/sig00000310 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ec ), + .Q(\blk00000003/sig0000030e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000309 ), + .Q(\blk00000003/sig0000030d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000303 ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000b2_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000300 ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000b1_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002fb ), + .R(coef_ld), + .Q(\blk00000003/sig000002f9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000af ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002f6 ), + .R(coef_ld), + .Q(\blk00000003/sig000002f3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ed ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000030c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000030a ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000030b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000308 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000309 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000306 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000307 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000304 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000305 ) + ); + XORCY \blk00000003/blk000000a9 ( + .CI(\blk00000003/sig00000302 ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000303 ) + ); + MUXCY \blk00000003/blk000000a8 ( + .CI(\blk00000003/sig00000302 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000ac ), + .O(\NLW_blk00000003/blk000000a8_O_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000a7 ( + .CI(\blk00000003/sig000002ff ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000301 ), + .O(\blk00000003/sig00000302 ), + .LO(\NLW_blk00000003/blk000000a7_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000a6 ( + .CI(\blk00000003/sig000002fe ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000300 ) + ); + MUXCY \blk00000003/blk000000a5 ( + .CI(\blk00000003/sig000002fe ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000ac ), + .O(\blk00000003/sig000002ff ) + ); + MUXCY_D \blk00000003/blk000000a4 ( + .CI(coef_we), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000002fd ), + .O(\blk00000003/sig000002fe ), + .LO(\NLW_blk00000003/blk000000a4_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000a3 ( + .CI(\blk00000003/sig000000ac ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000002fc ), + .O(\blk00000003/sig000002f8 ), + .LO(\NLW_blk00000003/blk000000a3_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000a2 ( + .CI(\blk00000003/sig000002fa ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig000002fb ) + ); + MUXCY \blk00000003/blk000000a1 ( + .CI(\blk00000003/sig000002fa ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000ac ), + .O(\NLW_blk00000003/blk000000a1_O_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000a0 ( + .CI(\blk00000003/sig000002f8 ), + .DI(\blk00000003/sig000002f9 ), + .S(coef_we), + .O(\blk00000003/sig000002fa ), + .LO(\NLW_blk00000003/blk000000a0_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk0000009f ( + .CI(\blk00000003/sig000000ac ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000002f7 ), + .O(\blk00000003/sig000002f2 ), + .LO(\NLW_blk00000003/blk0000009f_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000009e ( + .CI(\blk00000003/sig000002f5 ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig000002f6 ) + ); + MUXCY \blk00000003/blk0000009d ( + .CI(\blk00000003/sig000002f5 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000ac ), + .O(\NLW_blk00000003/blk0000009d_O_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk0000009c ( + .CI(\blk00000003/sig000002f2 ), + .DI(\blk00000003/sig000002f3 ), + .S(\blk00000003/sig000002f4 ), + .O(\blk00000003/sig000002f5 ), + .LO(\NLW_blk00000003/blk0000009c_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000009b ( + .CI(\blk00000003/sig000002eb ), + .LI(\blk00000003/sig000000ac ), + .O(\blk00000003/sig000002e9 ) + ); + MUXCY_D \blk00000003/blk0000009a ( + .CI(\blk00000003/sig000002ef ), + .DI(\blk00000003/sig000002f0 ), + .S(\blk00000003/sig000002f1 ), + .O(\NLW_blk00000003/blk0000009a_O_UNCONNECTED ), + .LO(\blk00000003/sig000002eb ) + ); + MUXCY_D \blk00000003/blk00000099 ( + .CI(\blk00000003/sig000002ec ), + .DI(\blk00000003/sig000002ed ), + .S(\blk00000003/sig000002ee ), + .O(\blk00000003/sig000002ef ), + .LO(\NLW_blk00000003/blk00000099_LO_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000098 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002eb ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002ec ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000097 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002e9 ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002ea ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000033 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b6 ), + .R(sclr), + .Q(\blk00000003/sig000002b5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000032 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b5 ), + .R(sclr), + .Q(\blk00000003/sig000002b2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000031 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b4 ), + .R(\blk00000003/sig000002af ), + .Q(data_valid) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000030 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b2 ), + .R(sclr), + .Q(\blk00000003/sig000002b3 ) + ); + FDRE \blk00000003/blk0000002f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b0 ), + .R(sclr), + .Q(\blk00000003/sig000002b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ae ), + .R(\blk00000003/sig000002af ), + .Q(rdy) + ); + FDSE \blk00000003/blk0000002d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ac ), + .S(sclr), + .Q(\blk00000003/sig000002ad ) + ); + FDRE \blk00000003/blk0000002c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002aa ), + .R(sclr), + .Q(\blk00000003/sig000002ab ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000002b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029c ), + .S(sclr), + .Q(NlwRenamedSig_OI_rfd) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029a ), + .R(sclr), + .Q(\blk00000003/sig000002a9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000029 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a8 ), + .R(sclr), + .Q(\blk00000003/sig00000296 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000028 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000293 ), + .R(sclr), + .Q(\blk00000003/sig000002a7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000027 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a6 ), + .R(sclr), + .Q(\blk00000003/sig00000294 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000026 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a4 ), + .R(sclr), + .Q(\blk00000003/sig000002a5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000025 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a2 ), + .R(sclr), + .Q(\blk00000003/sig000002a3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000024 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a0 ), + .R(sclr), + .Q(\NLW_blk00000003/blk00000024_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000023 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a0 ), + .R(sclr), + .Q(\blk00000003/sig000002a1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000022 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029e ), + .Q(\blk00000003/sig0000029f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000021 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000016e ), + .R(sclr), + .Q(\blk00000003/sig0000016b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000020 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000168 ), + .R(sclr), + .Q(\NLW_blk00000003/blk00000020_Q_UNCONNECTED ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000001f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000169 ), + .S(sclr), + .Q(\blk00000003/sig0000029d ) + ); + MUXCY \blk00000003/blk0000001e ( + .CI(\blk00000003/sig00000299 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig0000029b ), + .O(\blk00000003/sig0000029c ) + ); + XORCY \blk00000003/blk0000001d ( + .CI(\blk00000003/sig00000298 ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig0000029a ) + ); + MUXCY \blk00000003/blk0000001c ( + .CI(\blk00000003/sig00000298 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000ac ), + .O(\blk00000003/sig00000299 ) + ); + MUXCY_D \blk00000003/blk0000001b ( + .CI(\blk00000003/sig00000296 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000297 ), + .O(\blk00000003/sig00000298 ), + .LO(\NLW_blk00000003/blk0000001b_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk0000001a ( + .CI(\blk00000003/sig00000294 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000295 ), + .O(\blk00000003/sig00000292 ), + .LO(\NLW_blk00000003/blk0000001a_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk00000019 ( + .CI(\blk00000003/sig00000292 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000ac ), + .O(\NLW_blk00000003/blk00000019_O_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000018 ( + .CI(\blk00000003/sig00000292 ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000293 ) + ); + DSP48A1 #( + .A0REG ( 1 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000017 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000017_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000017_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000242 , \blk00000003/sig00000243 , \blk00000003/sig00000244 , +\blk00000003/sig00000245 , \blk00000003/sig00000246 , \blk00000003/sig00000247 , \blk00000003/sig00000248 , \blk00000003/sig00000249 , +\blk00000003/sig0000024a , \blk00000003/sig0000024b , \blk00000003/sig0000024c , \blk00000003/sig0000024d , \blk00000003/sig0000024e , +\blk00000003/sig0000024f , \blk00000003/sig00000250 , \blk00000003/sig00000251 }), + .BCOUT({\NLW_blk00000003/blk00000017_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000017_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000017_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000017_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000017_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000017_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000017_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000017_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000017_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000017_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000017_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000017_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000017_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000017_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000017_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000017_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000017_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000017_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000252 , \blk00000003/sig00000253 , \blk00000003/sig00000254 , \blk00000003/sig00000255 , \blk00000003/sig00000256 , +\blk00000003/sig00000257 , \blk00000003/sig00000258 , \blk00000003/sig00000259 , \blk00000003/sig0000025a , \blk00000003/sig0000025b , +\blk00000003/sig0000025c , \blk00000003/sig0000025d , \blk00000003/sig0000025e , \blk00000003/sig0000025f , \blk00000003/sig00000260 , +\blk00000003/sig00000261 , \blk00000003/sig00000262 , \blk00000003/sig00000263 , \blk00000003/sig00000264 , \blk00000003/sig00000265 , +\blk00000003/sig00000266 , \blk00000003/sig00000267 , \blk00000003/sig00000268 , \blk00000003/sig00000269 , \blk00000003/sig0000026a , +\blk00000003/sig0000026b , \blk00000003/sig0000026c , \blk00000003/sig0000026d , \blk00000003/sig0000026e , \blk00000003/sig0000026f , +\blk00000003/sig00000270 , \blk00000003/sig00000271 , \blk00000003/sig00000272 , \blk00000003/sig00000273 , \blk00000003/sig00000274 , +\blk00000003/sig00000275 , \blk00000003/sig00000276 , \blk00000003/sig00000277 , \blk00000003/sig00000278 , \blk00000003/sig00000279 , +\blk00000003/sig0000027a , \blk00000003/sig0000027b , \blk00000003/sig0000027c , \blk00000003/sig0000027d , \blk00000003/sig0000027e , +\blk00000003/sig0000027f , \blk00000003/sig00000280 , \blk00000003/sig00000281 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk00000017_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000017_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000017_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000017_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000017_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000017_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000017_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000017_P<40>_UNCONNECTED , +\blk00000003/sig00000153 , \blk00000003/sig00000154 , \blk00000003/sig00000155 , \blk00000003/sig00000156 , \blk00000003/sig00000157 , +\blk00000003/sig00000158 , \blk00000003/sig00000103 , \blk00000003/sig00000104 , \blk00000003/sig00000105 , \blk00000003/sig00000106 , +\blk00000003/sig00000107 , \blk00000003/sig00000108 , \blk00000003/sig00000109 , \blk00000003/sig0000010a , \blk00000003/sig0000010b , +\blk00000003/sig0000010c , \blk00000003/sig0000010d , \blk00000003/sig0000010e , \blk00000003/sig0000010f , \blk00000003/sig00000110 , +\blk00000003/sig00000111 , \blk00000003/sig00000112 , \blk00000003/sig00000113 , \blk00000003/sig00000114 , \blk00000003/sig00000282 , +\blk00000003/sig00000283 , \blk00000003/sig00000284 , \blk00000003/sig00000285 , \blk00000003/sig00000286 , \blk00000003/sig00000287 , +\blk00000003/sig00000288 , \blk00000003/sig00000289 , \blk00000003/sig0000028a , \blk00000003/sig0000028b , \blk00000003/sig0000028c , +\blk00000003/sig0000028d , \blk00000003/sig0000028e , \blk00000003/sig0000028f , \blk00000003/sig00000290 , \blk00000003/sig00000291 }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig0000015d , \blk00000003/sig0000015f , \blk00000003/sig00000161 }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .PCOUT({\NLW_blk00000003/blk00000017_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<6>_UNCONNECTED , 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.RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000016_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000016_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig0000020a , \blk00000003/sig0000020a , \blk00000003/sig0000020a , \blk00000003/sig0000020a , \blk00000003/sig0000020a , +\blk00000003/sig0000020a , \blk00000003/sig0000020a , \blk00000003/sig0000020a , \blk00000003/sig0000020a , \blk00000003/sig0000020a , +\blk00000003/sig0000020a , \blk00000003/sig0000020b , \blk00000003/sig0000020c , \blk00000003/sig0000020d , \blk00000003/sig0000020e , +\blk00000003/sig0000020f , \blk00000003/sig00000210 , \blk00000003/sig00000211 }), + .BCOUT({\NLW_blk00000003/blk00000016_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<0>_UNCONNECTED }), + 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+\NLW_blk00000003/blk00000015_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000001ca , \blk00000003/sig000001cb , \blk00000003/sig000001cc , \blk00000003/sig000001cd , \blk00000003/sig000001ce , +\blk00000003/sig000001cf , \blk00000003/sig000001d0 , \blk00000003/sig000001d1 , \blk00000003/sig000001d2 , \blk00000003/sig000001d3 , +\blk00000003/sig000001d4 , \blk00000003/sig000001d5 , \blk00000003/sig000001d6 , \blk00000003/sig000001d7 , \blk00000003/sig000001d8 , +\blk00000003/sig000001d9 , \blk00000003/sig000001da , \blk00000003/sig000001db , \blk00000003/sig000001dc , \blk00000003/sig000001dd , +\blk00000003/sig000001de , \blk00000003/sig000001df , \blk00000003/sig000001e0 , \blk00000003/sig000001e1 , \blk00000003/sig000001e2 , +\blk00000003/sig000001e3 , \blk00000003/sig000001e4 , \blk00000003/sig000001e5 , \blk00000003/sig000001e6 , \blk00000003/sig000001e7 , +\blk00000003/sig000001e8 , \blk00000003/sig000001e9 , \blk00000003/sig000001ea , \blk00000003/sig000001eb , \blk00000003/sig000001ec , +\blk00000003/sig000001ed , \blk00000003/sig000001ee , \blk00000003/sig000001ef , \blk00000003/sig000001f0 , \blk00000003/sig000001f1 , +\blk00000003/sig000001f2 , \blk00000003/sig000001f3 , \blk00000003/sig000001f4 , \blk00000003/sig000001f5 , \blk00000003/sig000001f6 , +\blk00000003/sig000001f7 , \blk00000003/sig000001f8 , \blk00000003/sig000001f9 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk00000015_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000015_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000015_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000015_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000015_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000015_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000015_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000015_P<40>_UNCONNECTED , +\blk00000003/sig000000fd , \blk00000003/sig000000fe , \blk00000003/sig000000ff , \blk00000003/sig00000100 , \blk00000003/sig00000101 , +\blk00000003/sig00000102 , \blk00000003/sig000000ad , \blk00000003/sig000000ae , \blk00000003/sig000000af , \blk00000003/sig000000b0 , +\blk00000003/sig000000b1 , \blk00000003/sig000000b2 , \blk00000003/sig000000b3 , \blk00000003/sig000000b4 , \blk00000003/sig000000b5 , +\blk00000003/sig000000b6 , \blk00000003/sig000000b7 , \blk00000003/sig000000b8 , \blk00000003/sig000000b9 , \blk00000003/sig000000ba , +\blk00000003/sig000000bb , \blk00000003/sig000000bc , \blk00000003/sig000000bd , \blk00000003/sig000000be , \blk00000003/sig000001fa , +\blk00000003/sig000001fb , \blk00000003/sig000001fc , \blk00000003/sig000001fd , \blk00000003/sig000001fe , \blk00000003/sig000001ff , +\blk00000003/sig00000200 , \blk00000003/sig00000201 , \blk00000003/sig00000202 , \blk00000003/sig00000203 , \blk00000003/sig00000204 , +\blk00000003/sig00000205 , \blk00000003/sig00000206 , \blk00000003/sig00000207 , \blk00000003/sig00000208 , \blk00000003/sig00000209 }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig0000015d , \blk00000003/sig0000015f , \blk00000003/sig00000161 }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .PCOUT({\NLW_blk00000003/blk00000015_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig000001a8 , \blk00000003/sig000001a9 , \blk00000003/sig000001aa , \blk00000003/sig000001ab , \blk00000003/sig000001ac , +\blk00000003/sig000001ad , \blk00000003/sig000001ae , \blk00000003/sig000001af , \blk00000003/sig000001b0 , \blk00000003/sig000001b1 , +\blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , \blk00000003/sig000001b5 , \blk00000003/sig000001b6 , +\blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 }), + .M({\NLW_blk00000003/blk00000015_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000015_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000015_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000015_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<26>_UNCONNECTED , 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\NLW_blk00000003/blk00000015_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000015_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000015_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 1 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000014 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000014_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000014_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000170 , \blk00000003/sig00000170 , \blk00000003/sig00000170 , \blk00000003/sig00000170 , \blk00000003/sig00000170 , +\blk00000003/sig00000170 , \blk00000003/sig00000170 , \blk00000003/sig00000170 , \blk00000003/sig00000170 , \blk00000003/sig00000170 , +\blk00000003/sig00000170 , \blk00000003/sig00000171 , \blk00000003/sig00000172 , \blk00000003/sig00000173 , \blk00000003/sig00000174 , +\blk00000003/sig00000175 , \blk00000003/sig00000176 , \blk00000003/sig00000177 }), + .BCOUT({\NLW_blk00000003/blk00000014_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000014_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000014_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000014_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000014_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000014_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000014_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000014_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000014_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000178 , \blk00000003/sig00000179 , \blk00000003/sig0000017a , \blk00000003/sig0000017b , \blk00000003/sig0000017c , +\blk00000003/sig0000017d , \blk00000003/sig0000017e , \blk00000003/sig0000017f , \blk00000003/sig00000180 , \blk00000003/sig00000181 , +\blk00000003/sig00000182 , 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\blk00000003/sig000001a7 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk00000014_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000014_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000014_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000014_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000014_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000014_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<31>_UNCONNECTED , +\blk00000003/sig000000bf , \blk00000003/sig000000c0 , \blk00000003/sig000000c1 , \blk00000003/sig000000c2 , \blk00000003/sig000000c3 , +\blk00000003/sig000000c4 , \blk00000003/sig000000c5 , \blk00000003/sig000000c6 , \blk00000003/sig000000c7 , \blk00000003/sig000000c8 , +\blk00000003/sig000000c9 , \blk00000003/sig000000ca , \blk00000003/sig000000cb , \blk00000003/sig000000cc , \blk00000003/sig000000cd , +\blk00000003/sig000000ce , \blk00000003/sig000000cf , \blk00000003/sig000000d0 , \blk00000003/sig000000d1 , \blk00000003/sig000000d2 , +\blk00000003/sig000000d3 , \blk00000003/sig000000d4 , \blk00000003/sig000000d5 , \blk00000003/sig000000d6 , \blk00000003/sig000000d7 , +\blk00000003/sig000000d8 , \blk00000003/sig000000d9 , \blk00000003/sig000000da , \blk00000003/sig000000db , \blk00000003/sig000000dc , +\blk00000003/sig000000dd }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig0000015d , \blk00000003/sig0000015f , \blk00000003/sig00000161 }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .PCOUT({\NLW_blk00000003/blk00000014_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<45>_UNCONNECTED , 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\NLW_blk00000003/blk00000014_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig000001a8 , \blk00000003/sig000001a9 , \blk00000003/sig000001aa , \blk00000003/sig000001ab , \blk00000003/sig000001ac , +\blk00000003/sig000001ad , \blk00000003/sig000001ae , \blk00000003/sig000001af , \blk00000003/sig000001b0 , \blk00000003/sig000001b1 , +\blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , \blk00000003/sig000001b5 , \blk00000003/sig000001b6 , +\blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 }), + 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.LO(\NLW_blk00000003/blk00000013_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000012 ( + .CI(\blk00000003/sig0000016d ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig0000016e ) + ); + MUXCY \blk00000003/blk00000011 ( + .CI(\blk00000003/sig0000016d ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000ac ), + .O(\blk00000003/sig00000162 ) + ); + MUXCY_D \blk00000003/blk00000010 ( + .CI(\blk00000003/sig0000016a ), + .DI(\blk00000003/sig0000016b ), + .S(\blk00000003/sig0000016c ), + .O(\blk00000003/sig0000016d ), + .LO(\NLW_blk00000003/blk00000010_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000000f ( + .CI(\blk00000003/sig00000168 ), + .LI(\blk00000003/sig000000ac ), + .O(\blk00000003/sig00000169 ) + ); + MUXCY_D \blk00000003/blk0000000e ( + .CI(\blk00000003/sig00000165 ), + .DI(\blk00000003/sig00000166 ), + .S(\blk00000003/sig00000167 ), + .O(\NLW_blk00000003/blk0000000e_O_UNCONNECTED ), + .LO(\blk00000003/sig00000168 ) + ); + MUXCY_D \blk00000003/blk0000000d ( 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\NLW_blk00000003/blk00000006_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000006_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000006_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<31>_UNCONNECTED , +\blk00000003/sig000000de , \blk00000003/sig000000df , \blk00000003/sig000000e0 , \blk00000003/sig000000e1 , \blk00000003/sig000000e2 , +\blk00000003/sig000000e3 , \blk00000003/sig000000e4 , \blk00000003/sig000000e5 , \blk00000003/sig000000e6 , \blk00000003/sig000000e7 , +\blk00000003/sig000000e8 , \blk00000003/sig000000e9 , \blk00000003/sig000000ea , \blk00000003/sig000000eb , \blk00000003/sig000000ec , +\blk00000003/sig000000ed , \blk00000003/sig000000ee , \blk00000003/sig000000ef , \blk00000003/sig000000f0 , \blk00000003/sig000000f1 , +\blk00000003/sig000000f2 , \blk00000003/sig000000f3 , \blk00000003/sig000000f4 , \blk00000003/sig000000f5 , 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\NLW_blk00000003/blk00000006_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig000000fd , \blk00000003/sig000000fd , \blk00000003/sig000000fd , \blk00000003/sig000000fd , \blk00000003/sig000000fd , +\blk00000003/sig000000fd , \blk00000003/sig000000fd , \blk00000003/sig000000fd , \blk00000003/sig000000fd , \blk00000003/sig000000fd , +\blk00000003/sig000000fd , \blk00000003/sig000000fd , \blk00000003/sig000000fd , \blk00000003/sig000000fe , \blk00000003/sig000000ff , +\blk00000003/sig00000100 , \blk00000003/sig00000101 , \blk00000003/sig00000102 }), + .M({\NLW_blk00000003/blk00000006_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<0>_UNCONNECTED }) + ); + VCC \blk00000003/blk00000005 ( + .P(\blk00000003/sig000000ac ) + ); + GND \blk00000003/blk00000004 ( + .G(\blk00000003/sig00000049 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000034/blk00000096 ( + .I0(nd), + .I1(ce), + .O(\blk00000003/blk00000034/sig000009d5 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000095 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[22]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000095_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009d3 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000094 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[21]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000094_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009d2 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000093 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[23]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000093_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009d4 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000092 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[19]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000092_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009d0 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000091 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[18]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000091_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009cf ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000090 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[20]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000090_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009d1 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000008f ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[16]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000008f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009cd ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000008e ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[15]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000008e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009cc ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000008d ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[17]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000008d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009ce ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000008c ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[13]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000008c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009ca ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000008b ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[12]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000008b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c9 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000008a ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[14]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000008a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009cb ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000089 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[10]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000089_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c7 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000088 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[9]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000088_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c6 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000087 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[11]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000087_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c8 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000086 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[7]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000086_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c4 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000085 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[6]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000085_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c3 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000084 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[8]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000084_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c5 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000083 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[4]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000083_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c1 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000082 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[3]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000082_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c0 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000081 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[5]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000081_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c2 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000080 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[1]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000080_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009be ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000007f ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[0]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000007f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009bd ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000007e ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[2]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000007e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009bf ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000007d ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[22]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000007d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009bb ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000007c ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[21]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000007c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009ba ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000007b ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[23]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000007b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009bc ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000007a ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[19]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000007a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b8 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000079 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[18]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000079_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b7 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000078 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[20]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000078_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b9 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000077 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[16]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000077_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b5 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000076 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[15]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000076_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b4 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000075 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[17]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000075_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b6 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000074 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[13]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000074_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b2 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000073 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[12]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000073_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b1 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000072 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[14]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000072_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b3 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000071 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[10]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000071_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009af ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000070 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[9]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000070_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009ae ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000006f ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[11]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000006f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b0 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000006e ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[7]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000006e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009ac ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000006d ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[6]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000006d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009ab ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000006c ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[8]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000006c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009ad ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000006b ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[4]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000006b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009a9 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000006a ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[3]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000006a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009a8 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000069 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[5]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000069_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009aa ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000068 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[1]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000068_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009a6 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000067 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[0]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000067_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009a5 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000066 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[2]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000066_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000065 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009d4 ), + .Q(\blk00000003/sig000002b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000064 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009d3 ), + .Q(\blk00000003/sig000002ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000063 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009d2 ), + .Q(\blk00000003/sig000002bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000062 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009d1 ), + .Q(\blk00000003/sig000002bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000061 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009d0 ), + .Q(\blk00000003/sig000002bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000060 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009cf ), + .Q(\blk00000003/sig000002be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000005f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009ce ), + .Q(\blk00000003/sig000002bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000005e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009cd ), + .Q(\blk00000003/sig000002c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000005d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009cc ), + .Q(\blk00000003/sig000002c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000005c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009cb ), + .Q(\blk00000003/sig000002c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000005b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009ca ), + .Q(\blk00000003/sig000002c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000005a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c9 ), + .Q(\blk00000003/sig000002c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000059 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c8 ), + .Q(\blk00000003/sig000002c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000058 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c7 ), + .Q(\blk00000003/sig000002c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000057 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c6 ), + .Q(\blk00000003/sig000002c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000056 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c5 ), + .Q(\blk00000003/sig000002c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000055 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c4 ), + .Q(\blk00000003/sig000002c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000054 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c3 ), + .Q(\blk00000003/sig000002ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000053 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c2 ), + .Q(\blk00000003/sig000002cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000052 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c1 ), + .Q(\blk00000003/sig000002cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000051 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c0 ), + .Q(\blk00000003/sig000002cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000050 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009bf ), + .Q(\blk00000003/sig000002ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000004f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009be ), + .Q(\blk00000003/sig000002cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000004e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009bd ), + .Q(\blk00000003/sig000002d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000004d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009bc ), + .Q(\blk00000003/sig000002d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000004c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009bb ), + .Q(\blk00000003/sig000002d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000004b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009ba ), + .Q(\blk00000003/sig000002d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000004a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b9 ), + .Q(\blk00000003/sig000002d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000049 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b8 ), + .Q(\blk00000003/sig000002d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000048 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b7 ), + .Q(\blk00000003/sig000002d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000047 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b6 ), + .Q(\blk00000003/sig000002d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000046 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b5 ), + .Q(\blk00000003/sig000002d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000045 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b4 ), + .Q(\blk00000003/sig000002d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000044 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b3 ), + .Q(\blk00000003/sig000002da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000043 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b2 ), + .Q(\blk00000003/sig000002db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000042 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b1 ), + .Q(\blk00000003/sig000002dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000041 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b0 ), + .Q(\blk00000003/sig000002dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000040 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009af ), + .Q(\blk00000003/sig000002de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000003f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009ae ), + .Q(\blk00000003/sig000002df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000003e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009ad ), + .Q(\blk00000003/sig000002e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000003d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009ac ), + .Q(\blk00000003/sig000002e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000003c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009ab ), + .Q(\blk00000003/sig000002e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000003b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009aa ), + .Q(\blk00000003/sig000002e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000003a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009a9 ), + .Q(\blk00000003/sig000002e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000039 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009a8 ), + .Q(\blk00000003/sig000002e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000038 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009a7 ), + .Q(\blk00000003/sig000002e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000037 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009a6 ), + .Q(\blk00000003/sig000002e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000036 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009a5 ), + .Q(\blk00000003/sig000002e8 ) + ); + GND \blk00000003/blk00000034/blk00000035 ( + .G(\blk00000003/blk00000034/sig000009a4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000130/blk00000152 ( + .I0(\blk00000003/sig0000067c ), + .I1(ce), + .O(\blk00000003/blk00000130/sig00000a0c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000151 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000641 ), + .Q(\blk00000003/blk00000130/sig00000a0b ), + .Q15(\NLW_blk00000003/blk00000130/blk00000151_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000150 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000642 ), + .Q(\blk00000003/blk00000130/sig00000a0a ), + .Q15(\NLW_blk00000003/blk00000130/blk00000150_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk0000014f ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000643 ), + .Q(\blk00000003/blk00000130/sig00000a09 ), + .Q15(\NLW_blk00000003/blk00000130/blk0000014f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk0000014e ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000644 ), + .Q(\blk00000003/blk00000130/sig00000a08 ), + .Q15(\NLW_blk00000003/blk00000130/blk0000014e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk0000014d ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000645 ), + .Q(\blk00000003/blk00000130/sig00000a07 ), + .Q15(\NLW_blk00000003/blk00000130/blk0000014d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk0000014c ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000646 ), + .Q(\blk00000003/blk00000130/sig00000a06 ), + .Q15(\NLW_blk00000003/blk00000130/blk0000014c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk0000014b ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000647 ), + .Q(\blk00000003/blk00000130/sig00000a05 ), + .Q15(\NLW_blk00000003/blk00000130/blk0000014b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk0000014a ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000648 ), + .Q(\blk00000003/blk00000130/sig00000a04 ), + .Q15(\NLW_blk00000003/blk00000130/blk0000014a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000149 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000649 ), + .Q(\blk00000003/blk00000130/sig00000a03 ), + .Q15(\NLW_blk00000003/blk00000130/blk00000149_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000148 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig0000064a ), + .Q(\blk00000003/blk00000130/sig00000a02 ), + .Q15(\NLW_blk00000003/blk00000130/blk00000148_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000147 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig0000064b ), + .Q(\blk00000003/blk00000130/sig00000a01 ), + .Q15(\NLW_blk00000003/blk00000130/blk00000147_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000146 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig0000064c ), + .Q(\blk00000003/blk00000130/sig00000a00 ), + .Q15(\NLW_blk00000003/blk00000130/blk00000146_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000145 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig0000064d ), + .Q(\blk00000003/blk00000130/sig000009ff ), + .Q15(\NLW_blk00000003/blk00000130/blk00000145_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000144 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig0000064e ), + .Q(\blk00000003/blk00000130/sig000009fe ), + .Q15(\NLW_blk00000003/blk00000130/blk00000144_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000143 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig0000064f ), + .Q(\blk00000003/blk00000130/sig000009fd ), + .Q15(\NLW_blk00000003/blk00000130/blk00000143_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000142 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000650 ), + .Q(\blk00000003/blk00000130/sig000009fc ), + .Q15(\NLW_blk00000003/blk00000130/blk00000142_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000141 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a0b ), + .Q(\blk00000003/sig000005d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000140 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a0a ), + .Q(\blk00000003/sig000005d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk0000013f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a09 ), + .Q(\blk00000003/sig000005d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk0000013e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a08 ), + .Q(\blk00000003/sig000005d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk0000013d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a07 ), + .Q(\blk00000003/sig000005d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk0000013c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a06 ), + .Q(\blk00000003/sig000005d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk0000013b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a05 ), + .Q(\blk00000003/sig000005d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk0000013a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a04 ), + .Q(\blk00000003/sig000005d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000139 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a03 ), + .Q(\blk00000003/sig000005d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000138 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a02 ), + .Q(\blk00000003/sig000005da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000137 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a01 ), + .Q(\blk00000003/sig000005db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000136 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a00 ), + .Q(\blk00000003/sig000005dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000135 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig000009ff ), + .Q(\blk00000003/sig000005dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000134 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig000009fe ), + .Q(\blk00000003/sig000005de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000133 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig000009fd ), + .Q(\blk00000003/sig000005df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000132 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig000009fc ), + .Q(\blk00000003/sig000005e0 ) + ); + GND \blk00000003/blk00000130/blk00000131 ( + .G(\blk00000003/blk00000130/sig000009fb ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000153/blk00000175 ( + .I0(\blk00000003/sig0000067a ), + .I1(ce), + .O(\blk00000003/blk00000153/sig00000a43 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000174 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig0000068d ), + .Q(\blk00000003/blk00000153/sig00000a42 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000174_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000173 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig0000068e ), + .Q(\blk00000003/blk00000153/sig00000a41 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000173_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000172 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig0000068f ), + .Q(\blk00000003/blk00000153/sig00000a40 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000172_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000171 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000690 ), + .Q(\blk00000003/blk00000153/sig00000a3f ), + .Q15(\NLW_blk00000003/blk00000153/blk00000171_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000170 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000691 ), + .Q(\blk00000003/blk00000153/sig00000a3e ), + .Q15(\NLW_blk00000003/blk00000153/blk00000170_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016f ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000692 ), + .Q(\blk00000003/blk00000153/sig00000a3d ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016e ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000693 ), + .Q(\blk00000003/blk00000153/sig00000a3c ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016d ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000694 ), + .Q(\blk00000003/blk00000153/sig00000a3b ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016c ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000695 ), + .Q(\blk00000003/blk00000153/sig00000a3a ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016b ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000696 ), + .Q(\blk00000003/blk00000153/sig00000a39 ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016a ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000697 ), + .Q(\blk00000003/blk00000153/sig00000a38 ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000169 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000698 ), + .Q(\blk00000003/blk00000153/sig00000a37 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000169_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000168 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000699 ), + .Q(\blk00000003/blk00000153/sig00000a36 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000168_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000167 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig0000069a ), + .Q(\blk00000003/blk00000153/sig00000a35 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000167_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000166 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig0000069b ), + .Q(\blk00000003/blk00000153/sig00000a34 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000166_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000165 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig0000069c ), + .Q(\blk00000003/blk00000153/sig00000a33 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000165_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000164 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a42 ), + .Q(\blk00000003/sig00000591 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000163 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a41 ), + .Q(\blk00000003/sig00000592 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000162 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a40 ), + .Q(\blk00000003/sig00000593 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000161 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a3f ), + .Q(\blk00000003/sig00000594 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000160 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a3e ), + .Q(\blk00000003/sig00000595 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a3d ), + .Q(\blk00000003/sig00000596 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a3c ), + .Q(\blk00000003/sig00000597 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a3b ), + .Q(\blk00000003/sig00000598 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a3a ), + .Q(\blk00000003/sig00000599 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a39 ), + .Q(\blk00000003/sig0000059a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a38 ), + .Q(\blk00000003/sig0000059b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000159 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a37 ), + .Q(\blk00000003/sig0000059c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000158 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a36 ), + .Q(\blk00000003/sig0000059d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000157 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a35 ), + .Q(\blk00000003/sig0000059e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000156 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a34 ), + .Q(\blk00000003/sig0000059f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000155 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a33 ), + .Q(\blk00000003/sig000005a0 ) + ); + GND \blk00000003/blk00000153/blk00000154 ( + .G(\blk00000003/blk00000153/sig00000a32 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000176/blk00000198 ( + .I0(\blk00000003/sig0000067c ), + .I1(ce), + .O(\blk00000003/blk00000176/sig00000a7a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000197 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000661 ), + .Q(\blk00000003/blk00000176/sig00000a79 ), + .Q15(\NLW_blk00000003/blk00000176/blk00000197_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000196 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000662 ), + .Q(\blk00000003/blk00000176/sig00000a78 ), + .Q15(\NLW_blk00000003/blk00000176/blk00000196_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000195 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000663 ), + .Q(\blk00000003/blk00000176/sig00000a77 ), + .Q15(\NLW_blk00000003/blk00000176/blk00000195_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000194 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000664 ), + .Q(\blk00000003/blk00000176/sig00000a76 ), + .Q15(\NLW_blk00000003/blk00000176/blk00000194_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000193 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000665 ), + .Q(\blk00000003/blk00000176/sig00000a75 ), + .Q15(\NLW_blk00000003/blk00000176/blk00000193_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000192 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000666 ), + .Q(\blk00000003/blk00000176/sig00000a74 ), + .Q15(\NLW_blk00000003/blk00000176/blk00000192_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000191 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000667 ), + .Q(\blk00000003/blk00000176/sig00000a73 ), + .Q15(\NLW_blk00000003/blk00000176/blk00000191_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000190 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000668 ), + .Q(\blk00000003/blk00000176/sig00000a72 ), + .Q15(\NLW_blk00000003/blk00000176/blk00000190_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk0000018f ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000669 ), + .Q(\blk00000003/blk00000176/sig00000a71 ), + .Q15(\NLW_blk00000003/blk00000176/blk0000018f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk0000018e ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig0000066a ), + .Q(\blk00000003/blk00000176/sig00000a70 ), + .Q15(\NLW_blk00000003/blk00000176/blk0000018e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk0000018d ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig0000066b ), + .Q(\blk00000003/blk00000176/sig00000a6f ), + .Q15(\NLW_blk00000003/blk00000176/blk0000018d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk0000018c ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig0000066c ), + .Q(\blk00000003/blk00000176/sig00000a6e ), + .Q15(\NLW_blk00000003/blk00000176/blk0000018c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk0000018b ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig0000066d ), + .Q(\blk00000003/blk00000176/sig00000a6d ), + .Q15(\NLW_blk00000003/blk00000176/blk0000018b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk0000018a ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig0000066e ), + .Q(\blk00000003/blk00000176/sig00000a6c ), + .Q15(\NLW_blk00000003/blk00000176/blk0000018a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000189 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig0000066f ), + .Q(\blk00000003/blk00000176/sig00000a6b ), + .Q15(\NLW_blk00000003/blk00000176/blk00000189_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000188 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000670 ), + .Q(\blk00000003/blk00000176/sig00000a6a ), + .Q15(\NLW_blk00000003/blk00000176/blk00000188_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000187 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a79 ), + .Q(\blk00000003/sig00000621 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000186 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a78 ), + .Q(\blk00000003/sig00000622 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000185 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a77 ), + .Q(\blk00000003/sig00000623 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000184 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a76 ), + .Q(\blk00000003/sig00000624 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000183 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a75 ), + .Q(\blk00000003/sig00000625 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000182 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a74 ), + .Q(\blk00000003/sig00000626 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000181 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a73 ), + .Q(\blk00000003/sig00000627 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000180 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a72 ), + .Q(\blk00000003/sig00000628 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk0000017f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a71 ), + .Q(\blk00000003/sig00000629 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk0000017e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a70 ), + .Q(\blk00000003/sig0000062a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk0000017d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a6f ), + .Q(\blk00000003/sig0000062b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk0000017c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a6e ), + .Q(\blk00000003/sig0000062c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk0000017b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a6d ), + .Q(\blk00000003/sig0000062d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk0000017a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a6c ), + .Q(\blk00000003/sig0000062e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000179 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a6b ), + .Q(\blk00000003/sig0000062f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000178 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a6a ), + .Q(\blk00000003/sig00000630 ) + ); + GND \blk00000003/blk00000176/blk00000177 ( + .G(\blk00000003/blk00000176/sig00000a69 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000199/blk000001bb ( + .I0(\blk00000003/sig0000067a ), + .I1(ce), + .O(\blk00000003/blk00000199/sig00000ab1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001ba ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig0000069d ), + .Q(\blk00000003/blk00000199/sig00000ab0 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001ba_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b9 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig0000069e ), + .Q(\blk00000003/blk00000199/sig00000aaf ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b8 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig0000069f ), + .Q(\blk00000003/blk00000199/sig00000aae ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b7 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a0 ), + .Q(\blk00000003/blk00000199/sig00000aad ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b6 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a1 ), + .Q(\blk00000003/blk00000199/sig00000aac ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b5 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a2 ), + .Q(\blk00000003/blk00000199/sig00000aab ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b4 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a3 ), + .Q(\blk00000003/blk00000199/sig00000aaa ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b3 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a4 ), + .Q(\blk00000003/blk00000199/sig00000aa9 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b2 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a5 ), + .Q(\blk00000003/blk00000199/sig00000aa8 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b1 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a6 ), + .Q(\blk00000003/blk00000199/sig00000aa7 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b0 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a7 ), + .Q(\blk00000003/blk00000199/sig00000aa6 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001af ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a8 ), + .Q(\blk00000003/blk00000199/sig00000aa5 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001ae ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a9 ), + .Q(\blk00000003/blk00000199/sig00000aa4 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001ad ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006aa ), + .Q(\blk00000003/blk00000199/sig00000aa3 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001ac ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006ab ), + .Q(\blk00000003/blk00000199/sig00000aa2 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001ab ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006ac ), + .Q(\blk00000003/blk00000199/sig00000aa1 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001ab_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000ab0 ), + .Q(\blk00000003/sig000005e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aaf ), + .Q(\blk00000003/sig000005e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aae ), + .Q(\blk00000003/sig000005e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aad ), + .Q(\blk00000003/sig000005e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aac ), + .Q(\blk00000003/sig000005e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aab ), + .Q(\blk00000003/sig000005e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aaa ), + .Q(\blk00000003/sig000005e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa9 ), + .Q(\blk00000003/sig000005e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa8 ), + .Q(\blk00000003/sig000005e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa7 ), + .Q(\blk00000003/sig000005ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa6 ), + .Q(\blk00000003/sig000005eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk0000019f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa5 ), + .Q(\blk00000003/sig000005ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk0000019e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa4 ), + .Q(\blk00000003/sig000005ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk0000019d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa3 ), + .Q(\blk00000003/sig000005ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk0000019c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa2 ), + .Q(\blk00000003/sig000005ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk0000019b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa1 ), + .Q(\blk00000003/sig000005f0 ) + ); + GND \blk00000003/blk00000199/blk0000019a ( + .G(\blk00000003/blk00000199/sig00000aa0 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001bc/blk000001de ( + .I0(\blk00000003/sig0000067b ), + .I1(ce), + .O(\blk00000003/blk000001bc/sig00000ae8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001dd ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig0000043d ), + .Q(\blk00000003/blk000001bc/sig00000ae7 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001dc ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig0000043e ), + .Q(\blk00000003/blk000001bc/sig00000ae6 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001db ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig0000043f ), + .Q(\blk00000003/blk000001bc/sig00000ae5 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001da ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000440 ), + .Q(\blk00000003/blk000001bc/sig00000ae4 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d9 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000441 ), + .Q(\blk00000003/blk000001bc/sig00000ae3 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d8 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000442 ), + .Q(\blk00000003/blk000001bc/sig00000ae2 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d7 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000443 ), + .Q(\blk00000003/blk000001bc/sig00000ae1 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d6 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000444 ), + .Q(\blk00000003/blk000001bc/sig00000ae0 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d5 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000445 ), + .Q(\blk00000003/blk000001bc/sig00000adf ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d4 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000446 ), + .Q(\blk00000003/blk000001bc/sig00000ade ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d3 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000447 ), + .Q(\blk00000003/blk000001bc/sig00000add ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d2 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000448 ), + .Q(\blk00000003/blk000001bc/sig00000adc ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d1 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000449 ), + .Q(\blk00000003/blk000001bc/sig00000adb ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d0 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig0000044a ), + .Q(\blk00000003/blk000001bc/sig00000ada ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001cf ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig0000044b ), + .Q(\blk00000003/blk000001bc/sig00000ad9 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001cf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001ce ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig0000044c ), + .Q(\blk00000003/blk000001bc/sig00000ad8 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001ce_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ae7 ), + .Q(\blk00000003/sig00000641 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ae6 ), + .Q(\blk00000003/sig00000642 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ae5 ), + .Q(\blk00000003/sig00000643 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ae4 ), + .Q(\blk00000003/sig00000644 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ae3 ), + .Q(\blk00000003/sig00000645 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ae2 ), + .Q(\blk00000003/sig00000646 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ae1 ), + .Q(\blk00000003/sig00000647 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ae0 ), + .Q(\blk00000003/sig00000648 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000adf ), + .Q(\blk00000003/sig00000649 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ade ), + .Q(\blk00000003/sig0000064a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000add ), + .Q(\blk00000003/sig0000064b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000adc ), + .Q(\blk00000003/sig0000064c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000adb ), + .Q(\blk00000003/sig0000064d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ada ), + .Q(\blk00000003/sig0000064e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ad9 ), + .Q(\blk00000003/sig0000064f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ad8 ), + .Q(\blk00000003/sig00000650 ) + ); + GND \blk00000003/blk000001bc/blk000001bd ( + .G(\blk00000003/blk000001bc/sig00000ad7 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001df/blk00000201 ( + .I0(\blk00000003/sig00000679 ), + .I1(ce), + .O(\blk00000003/blk000001df/sig00000b1f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk00000200 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006ad ), + .Q(\blk00000003/blk000001df/sig00000b1e ), + .Q15(\NLW_blk00000003/blk000001df/blk00000200_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001ff ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006ae ), + .Q(\blk00000003/blk000001df/sig00000b1d ), + .Q15(\NLW_blk00000003/blk000001df/blk000001ff_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001fe ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006af ), + .Q(\blk00000003/blk000001df/sig00000b1c ), + .Q15(\NLW_blk00000003/blk000001df/blk000001fe_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001fd ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b0 ), + .Q(\blk00000003/blk000001df/sig00000b1b ), + .Q15(\NLW_blk00000003/blk000001df/blk000001fd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001fc ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b1 ), + .Q(\blk00000003/blk000001df/sig00000b1a ), + .Q15(\NLW_blk00000003/blk000001df/blk000001fc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001fb ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b2 ), + .Q(\blk00000003/blk000001df/sig00000b19 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001fb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001fa ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b3 ), + .Q(\blk00000003/blk000001df/sig00000b18 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001fa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f9 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b4 ), + .Q(\blk00000003/blk000001df/sig00000b17 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f8 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b5 ), + .Q(\blk00000003/blk000001df/sig00000b16 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f7 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b6 ), + .Q(\blk00000003/blk000001df/sig00000b15 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f6 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b7 ), + .Q(\blk00000003/blk000001df/sig00000b14 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f5 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b8 ), + .Q(\blk00000003/blk000001df/sig00000b13 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f4 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b9 ), + .Q(\blk00000003/blk000001df/sig00000b12 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f3 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006ba ), + .Q(\blk00000003/blk000001df/sig00000b11 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f2 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006bb ), + .Q(\blk00000003/blk000001df/sig00000b10 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f1 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006bc ), + .Q(\blk00000003/blk000001df/sig00000b0f ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b1e ), + .Q(\blk00000003/sig00000631 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b1d ), + .Q(\blk00000003/sig00000632 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b1c ), + .Q(\blk00000003/sig00000633 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b1b ), + .Q(\blk00000003/sig00000634 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b1a ), + .Q(\blk00000003/sig00000635 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b19 ), + .Q(\blk00000003/sig00000636 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b18 ), + .Q(\blk00000003/sig00000637 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b17 ), + .Q(\blk00000003/sig00000638 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b16 ), + .Q(\blk00000003/sig00000639 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b15 ), + .Q(\blk00000003/sig0000063a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b14 ), + .Q(\blk00000003/sig0000063b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b13 ), + .Q(\blk00000003/sig0000063c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b12 ), + .Q(\blk00000003/sig0000063d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b11 ), + .Q(\blk00000003/sig0000063e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b10 ), + .Q(\blk00000003/sig0000063f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b0f ), + .Q(\blk00000003/sig00000640 ) + ); + GND \blk00000003/blk000001df/blk000001e0 ( + .G(\blk00000003/blk000001df/sig00000b0e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000202/blk00000224 ( + .I0(\blk00000003/sig0000067b ), + .I1(ce), + .O(\blk00000003/blk00000202/sig00000b56 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000223 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig0000048d ), + .Q(\blk00000003/blk00000202/sig00000b55 ), + .Q15(\NLW_blk00000003/blk00000202/blk00000223_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000222 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig0000048e ), + .Q(\blk00000003/blk00000202/sig00000b54 ), + .Q15(\NLW_blk00000003/blk00000202/blk00000222_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000221 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig0000048f ), + .Q(\blk00000003/blk00000202/sig00000b53 ), + .Q15(\NLW_blk00000003/blk00000202/blk00000221_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000220 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000490 ), + .Q(\blk00000003/blk00000202/sig00000b52 ), + .Q15(\NLW_blk00000003/blk00000202/blk00000220_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk0000021f ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000491 ), + .Q(\blk00000003/blk00000202/sig00000b51 ), + .Q15(\NLW_blk00000003/blk00000202/blk0000021f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk0000021e ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000492 ), + .Q(\blk00000003/blk00000202/sig00000b50 ), + .Q15(\NLW_blk00000003/blk00000202/blk0000021e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk0000021d ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000493 ), + .Q(\blk00000003/blk00000202/sig00000b4f ), + .Q15(\NLW_blk00000003/blk00000202/blk0000021d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk0000021c ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000494 ), + .Q(\blk00000003/blk00000202/sig00000b4e ), + .Q15(\NLW_blk00000003/blk00000202/blk0000021c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk0000021b ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000495 ), + .Q(\blk00000003/blk00000202/sig00000b4d ), + .Q15(\NLW_blk00000003/blk00000202/blk0000021b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk0000021a ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000496 ), + .Q(\blk00000003/blk00000202/sig00000b4c ), + .Q15(\NLW_blk00000003/blk00000202/blk0000021a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000219 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000497 ), + .Q(\blk00000003/blk00000202/sig00000b4b ), + .Q15(\NLW_blk00000003/blk00000202/blk00000219_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000218 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000498 ), + .Q(\blk00000003/blk00000202/sig00000b4a ), + .Q15(\NLW_blk00000003/blk00000202/blk00000218_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000217 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000499 ), + .Q(\blk00000003/blk00000202/sig00000b49 ), + .Q15(\NLW_blk00000003/blk00000202/blk00000217_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000216 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig0000049a ), + .Q(\blk00000003/blk00000202/sig00000b48 ), + .Q15(\NLW_blk00000003/blk00000202/blk00000216_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000215 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig0000049b ), + .Q(\blk00000003/blk00000202/sig00000b47 ), + .Q15(\NLW_blk00000003/blk00000202/blk00000215_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000214 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig0000049c ), + .Q(\blk00000003/blk00000202/sig00000b46 ), + .Q15(\NLW_blk00000003/blk00000202/blk00000214_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000213 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b55 ), + .Q(\blk00000003/sig00000661 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000212 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b54 ), + .Q(\blk00000003/sig00000662 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000211 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b53 ), + .Q(\blk00000003/sig00000663 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000210 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b52 ), + .Q(\blk00000003/sig00000664 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk0000020f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b51 ), + .Q(\blk00000003/sig00000665 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk0000020e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b50 ), + .Q(\blk00000003/sig00000666 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk0000020d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b4f ), + .Q(\blk00000003/sig00000667 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk0000020c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b4e ), + .Q(\blk00000003/sig00000668 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk0000020b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b4d ), + .Q(\blk00000003/sig00000669 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk0000020a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b4c ), + .Q(\blk00000003/sig0000066a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000209 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b4b ), + .Q(\blk00000003/sig0000066b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000208 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b4a ), + .Q(\blk00000003/sig0000066c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000207 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b49 ), + .Q(\blk00000003/sig0000066d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000206 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b48 ), + .Q(\blk00000003/sig0000066e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000205 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b47 ), + .Q(\blk00000003/sig0000066f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000204 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b46 ), + .Q(\blk00000003/sig00000670 ) + ); + GND \blk00000003/blk00000202/blk00000203 ( + .G(\blk00000003/blk00000202/sig00000b45 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000225/blk00000247 ( + .I0(\blk00000003/sig00000679 ), + .I1(ce), + .O(\blk00000003/blk00000225/sig00000b8d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000246 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006bd ), + .Q(\blk00000003/blk00000225/sig00000b8c ), + .Q15(\NLW_blk00000003/blk00000225/blk00000246_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000245 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006be ), + .Q(\blk00000003/blk00000225/sig00000b8b ), + .Q15(\NLW_blk00000003/blk00000225/blk00000245_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000244 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006bf ), + .Q(\blk00000003/blk00000225/sig00000b8a ), + .Q15(\NLW_blk00000003/blk00000225/blk00000244_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000243 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c0 ), + .Q(\blk00000003/blk00000225/sig00000b89 ), + .Q15(\NLW_blk00000003/blk00000225/blk00000243_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000242 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c1 ), + .Q(\blk00000003/blk00000225/sig00000b88 ), + .Q15(\NLW_blk00000003/blk00000225/blk00000242_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000241 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c2 ), + .Q(\blk00000003/blk00000225/sig00000b87 ), + .Q15(\NLW_blk00000003/blk00000225/blk00000241_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000240 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c3 ), + .Q(\blk00000003/blk00000225/sig00000b86 ), + .Q15(\NLW_blk00000003/blk00000225/blk00000240_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk0000023f ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c4 ), + .Q(\blk00000003/blk00000225/sig00000b85 ), + .Q15(\NLW_blk00000003/blk00000225/blk0000023f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk0000023e ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c5 ), + .Q(\blk00000003/blk00000225/sig00000b84 ), + .Q15(\NLW_blk00000003/blk00000225/blk0000023e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk0000023d ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c6 ), + .Q(\blk00000003/blk00000225/sig00000b83 ), + .Q15(\NLW_blk00000003/blk00000225/blk0000023d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk0000023c ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c7 ), + .Q(\blk00000003/blk00000225/sig00000b82 ), + .Q15(\NLW_blk00000003/blk00000225/blk0000023c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk0000023b ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c8 ), + .Q(\blk00000003/blk00000225/sig00000b81 ), + .Q15(\NLW_blk00000003/blk00000225/blk0000023b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk0000023a ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c9 ), + .Q(\blk00000003/blk00000225/sig00000b80 ), + .Q15(\NLW_blk00000003/blk00000225/blk0000023a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000239 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006ca ), + .Q(\blk00000003/blk00000225/sig00000b7f ), + .Q15(\NLW_blk00000003/blk00000225/blk00000239_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000238 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006cb ), + .Q(\blk00000003/blk00000225/sig00000b7e ), + .Q15(\NLW_blk00000003/blk00000225/blk00000238_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000237 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006cc ), + .Q(\blk00000003/blk00000225/sig00000b7d ), + .Q15(\NLW_blk00000003/blk00000225/blk00000237_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000236 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b8c ), + .Q(\blk00000003/sig00000651 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000235 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b8b ), + .Q(\blk00000003/sig00000652 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000234 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b8a ), + .Q(\blk00000003/sig00000653 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000233 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b89 ), + .Q(\blk00000003/sig00000654 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000232 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b88 ), + .Q(\blk00000003/sig00000655 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000231 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b87 ), + .Q(\blk00000003/sig00000656 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000230 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b86 ), + .Q(\blk00000003/sig00000657 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk0000022f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b85 ), + .Q(\blk00000003/sig00000658 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk0000022e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b84 ), + .Q(\blk00000003/sig00000659 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk0000022d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b83 ), + .Q(\blk00000003/sig0000065a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk0000022c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b82 ), + .Q(\blk00000003/sig0000065b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk0000022b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b81 ), + .Q(\blk00000003/sig0000065c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk0000022a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b80 ), + .Q(\blk00000003/sig0000065d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000229 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b7f ), + .Q(\blk00000003/sig0000065e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000228 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b7e ), + .Q(\blk00000003/sig0000065f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000227 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b7d ), + .Q(\blk00000003/sig00000660 ) + ); + GND \blk00000003/blk00000225/blk00000226 ( + .G(\blk00000003/blk00000225/sig00000b7c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000248/blk0000026a ( + .I0(\blk00000003/sig0000068c ), + .I1(ce), + .O(\blk00000003/blk00000248/sig00000bc4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000269 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006cd ), + .Q(\blk00000003/blk00000248/sig00000bc3 ), + .Q15(\NLW_blk00000003/blk00000248/blk00000269_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000268 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006ce ), + .Q(\blk00000003/blk00000248/sig00000bc2 ), + .Q15(\NLW_blk00000003/blk00000248/blk00000268_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000267 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006cf ), + .Q(\blk00000003/blk00000248/sig00000bc1 ), + .Q15(\NLW_blk00000003/blk00000248/blk00000267_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000266 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d0 ), + .Q(\blk00000003/blk00000248/sig00000bc0 ), + .Q15(\NLW_blk00000003/blk00000248/blk00000266_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000265 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d1 ), + .Q(\blk00000003/blk00000248/sig00000bbf ), + .Q15(\NLW_blk00000003/blk00000248/blk00000265_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000264 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d2 ), + .Q(\blk00000003/blk00000248/sig00000bbe ), + .Q15(\NLW_blk00000003/blk00000248/blk00000264_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000263 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d3 ), + .Q(\blk00000003/blk00000248/sig00000bbd ), + .Q15(\NLW_blk00000003/blk00000248/blk00000263_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000262 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d4 ), + .Q(\blk00000003/blk00000248/sig00000bbc ), + .Q15(\NLW_blk00000003/blk00000248/blk00000262_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000261 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d5 ), + .Q(\blk00000003/blk00000248/sig00000bbb ), + .Q15(\NLW_blk00000003/blk00000248/blk00000261_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000260 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d6 ), + .Q(\blk00000003/blk00000248/sig00000bba ), + .Q15(\NLW_blk00000003/blk00000248/blk00000260_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk0000025f ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d7 ), + .Q(\blk00000003/blk00000248/sig00000bb9 ), + .Q15(\NLW_blk00000003/blk00000248/blk0000025f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk0000025e ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d8 ), + .Q(\blk00000003/blk00000248/sig00000bb8 ), + .Q15(\NLW_blk00000003/blk00000248/blk0000025e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk0000025d ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d9 ), + .Q(\blk00000003/blk00000248/sig00000bb7 ), + .Q15(\NLW_blk00000003/blk00000248/blk0000025d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk0000025c ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006da ), + .Q(\blk00000003/blk00000248/sig00000bb6 ), + .Q15(\NLW_blk00000003/blk00000248/blk0000025c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk0000025b ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006db ), + .Q(\blk00000003/blk00000248/sig00000bb5 ), + .Q15(\NLW_blk00000003/blk00000248/blk0000025b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk0000025a ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006dc ), + .Q(\blk00000003/blk00000248/sig00000bb4 ), + .Q15(\NLW_blk00000003/blk00000248/blk0000025a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000259 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bc3 ), + .Q(\blk00000003/sig0000043d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000258 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bc2 ), + .Q(\blk00000003/sig0000043e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000257 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bc1 ), + .Q(\blk00000003/sig0000043f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000256 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bc0 ), + .Q(\blk00000003/sig00000440 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000255 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bbf ), + .Q(\blk00000003/sig00000441 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000254 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bbe ), + .Q(\blk00000003/sig00000442 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000253 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bbd ), + .Q(\blk00000003/sig00000443 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000252 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bbc ), + .Q(\blk00000003/sig00000444 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000251 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bbb ), + .Q(\blk00000003/sig00000445 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000250 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bba ), + .Q(\blk00000003/sig00000446 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk0000024f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bb9 ), + .Q(\blk00000003/sig00000447 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk0000024e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bb8 ), + .Q(\blk00000003/sig00000448 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk0000024d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bb7 ), + .Q(\blk00000003/sig00000449 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk0000024c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bb6 ), + .Q(\blk00000003/sig0000044a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk0000024b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bb5 ), + .Q(\blk00000003/sig0000044b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk0000024a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bb4 ), + .Q(\blk00000003/sig0000044c ) + ); + GND \blk00000003/blk00000248/blk00000249 ( + .G(\blk00000003/blk00000248/sig00000bb3 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000026b/blk0000028d ( + .I0(\blk00000003/sig0000068b ), + .I1(ce), + .O(\blk00000003/blk0000026b/sig00000bfb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk0000028c ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006dd ), + .Q(\blk00000003/blk0000026b/sig00000bfa ), + .Q15(\NLW_blk00000003/blk0000026b/blk0000028c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk0000028b ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006de ), + .Q(\blk00000003/blk0000026b/sig00000bf9 ), + .Q15(\NLW_blk00000003/blk0000026b/blk0000028b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk0000028a ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006df ), + .Q(\blk00000003/blk0000026b/sig00000bf8 ), + .Q15(\NLW_blk00000003/blk0000026b/blk0000028a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000289 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e0 ), + .Q(\blk00000003/blk0000026b/sig00000bf7 ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000289_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000288 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e1 ), + .Q(\blk00000003/blk0000026b/sig00000bf6 ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000288_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000287 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e2 ), + .Q(\blk00000003/blk0000026b/sig00000bf5 ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000287_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000286 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e3 ), + .Q(\blk00000003/blk0000026b/sig00000bf4 ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000286_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000285 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e4 ), + .Q(\blk00000003/blk0000026b/sig00000bf3 ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000285_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000284 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e5 ), + .Q(\blk00000003/blk0000026b/sig00000bf2 ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000284_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000283 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e6 ), + .Q(\blk00000003/blk0000026b/sig00000bf1 ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000283_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000282 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e7 ), + .Q(\blk00000003/blk0000026b/sig00000bf0 ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000282_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000281 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e8 ), + .Q(\blk00000003/blk0000026b/sig00000bef ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000281_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000280 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e9 ), + .Q(\blk00000003/blk0000026b/sig00000bee ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000280_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk0000027f ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006ea ), + .Q(\blk00000003/blk0000026b/sig00000bed ), + .Q15(\NLW_blk00000003/blk0000026b/blk0000027f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk0000027e ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006eb ), + .Q(\blk00000003/blk0000026b/sig00000bec ), + .Q15(\NLW_blk00000003/blk0000026b/blk0000027e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk0000027d ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006ec ), + .Q(\blk00000003/blk0000026b/sig00000beb ), + .Q15(\NLW_blk00000003/blk0000026b/blk0000027d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk0000027c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bfa ), + .Q(\blk00000003/sig0000042d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk0000027b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf9 ), + .Q(\blk00000003/sig0000042e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk0000027a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf8 ), + .Q(\blk00000003/sig0000042f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000279 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf7 ), + .Q(\blk00000003/sig00000430 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000278 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf6 ), + .Q(\blk00000003/sig00000431 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000277 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf5 ), + .Q(\blk00000003/sig00000432 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000276 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf4 ), + .Q(\blk00000003/sig00000433 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000275 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf3 ), + .Q(\blk00000003/sig00000434 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000274 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf2 ), + .Q(\blk00000003/sig00000435 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000273 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf1 ), + .Q(\blk00000003/sig00000436 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000272 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf0 ), + .Q(\blk00000003/sig00000437 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000271 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bef ), + .Q(\blk00000003/sig00000438 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000270 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bee ), + .Q(\blk00000003/sig00000439 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk0000026f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bed ), + .Q(\blk00000003/sig0000043a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk0000026e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bec ), + .Q(\blk00000003/sig0000043b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk0000026d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000beb ), + .Q(\blk00000003/sig0000043c ) + ); + GND \blk00000003/blk0000026b/blk0000026c ( + .G(\blk00000003/blk0000026b/sig00000bea ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000028e/blk000002b0 ( + .I0(\blk00000003/sig0000068c ), + .I1(ce), + .O(\blk00000003/blk0000028e/sig00000c32 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002af ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006ed ), + .Q(\blk00000003/blk0000028e/sig00000c31 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002ae ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006ee ), + .Q(\blk00000003/blk0000028e/sig00000c30 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002ad ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006ef ), + .Q(\blk00000003/blk0000028e/sig00000c2f ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002ac ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f0 ), + .Q(\blk00000003/blk0000028e/sig00000c2e ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002ab ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f1 ), + .Q(\blk00000003/blk0000028e/sig00000c2d ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002aa ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f2 ), + .Q(\blk00000003/blk0000028e/sig00000c2c ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a9 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f3 ), + .Q(\blk00000003/blk0000028e/sig00000c2b ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a8 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f4 ), + .Q(\blk00000003/blk0000028e/sig00000c2a ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a7 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f5 ), + .Q(\blk00000003/blk0000028e/sig00000c29 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a6 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f6 ), + .Q(\blk00000003/blk0000028e/sig00000c28 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a5 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f7 ), + .Q(\blk00000003/blk0000028e/sig00000c27 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a4 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f8 ), + .Q(\blk00000003/blk0000028e/sig00000c26 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a3 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f9 ), + .Q(\blk00000003/blk0000028e/sig00000c25 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a2 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006fa ), + .Q(\blk00000003/blk0000028e/sig00000c24 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a1 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006fb ), + .Q(\blk00000003/blk0000028e/sig00000c23 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a0 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006fc ), + .Q(\blk00000003/blk0000028e/sig00000c22 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk0000029f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c31 ), + .Q(\blk00000003/sig0000048d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk0000029e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c30 ), + .Q(\blk00000003/sig0000048e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk0000029d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c2f ), + .Q(\blk00000003/sig0000048f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk0000029c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c2e ), + .Q(\blk00000003/sig00000490 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk0000029b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c2d ), + .Q(\blk00000003/sig00000491 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk0000029a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c2c ), + .Q(\blk00000003/sig00000492 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000299 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c2b ), + .Q(\blk00000003/sig00000493 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000298 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c2a ), + .Q(\blk00000003/sig00000494 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000297 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c29 ), + .Q(\blk00000003/sig00000495 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000296 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c28 ), + .Q(\blk00000003/sig00000496 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000295 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c27 ), + .Q(\blk00000003/sig00000497 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000294 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c26 ), + .Q(\blk00000003/sig00000498 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000293 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c25 ), + .Q(\blk00000003/sig00000499 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000292 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c24 ), + .Q(\blk00000003/sig0000049a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000291 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c23 ), + .Q(\blk00000003/sig0000049b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000290 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c22 ), + .Q(\blk00000003/sig0000049c ) + ); + GND \blk00000003/blk0000028e/blk0000028f ( + .G(\blk00000003/blk0000028e/sig00000c21 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002b1/blk000002d3 ( + .I0(\blk00000003/sig0000068b ), + .I1(ce), + .O(\blk00000003/blk000002b1/sig00000c69 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002d2 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig000006fd ), + .Q(\blk00000003/blk000002b1/sig00000c68 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002d1 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig000006fe ), + .Q(\blk00000003/blk000002b1/sig00000c67 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002d0 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig000006ff ), + .Q(\blk00000003/blk000002b1/sig00000c66 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002cf ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000700 ), + .Q(\blk00000003/blk000002b1/sig00000c65 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002cf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002ce ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000701 ), + .Q(\blk00000003/blk000002b1/sig00000c64 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002ce_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002cd ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000702 ), + .Q(\blk00000003/blk000002b1/sig00000c63 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002cd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002cc ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000703 ), + .Q(\blk00000003/blk000002b1/sig00000c62 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002cc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002cb ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000704 ), + .Q(\blk00000003/blk000002b1/sig00000c61 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002cb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002ca ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000705 ), + .Q(\blk00000003/blk000002b1/sig00000c60 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002ca_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002c9 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000706 ), + .Q(\blk00000003/blk000002b1/sig00000c5f ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002c9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002c8 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000707 ), + .Q(\blk00000003/blk000002b1/sig00000c5e ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002c8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002c7 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000708 ), + .Q(\blk00000003/blk000002b1/sig00000c5d ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002c7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002c6 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000709 ), + .Q(\blk00000003/blk000002b1/sig00000c5c ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002c6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002c5 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig0000070a ), + .Q(\blk00000003/blk000002b1/sig00000c5b ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002c5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002c4 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig0000070b ), + .Q(\blk00000003/blk000002b1/sig00000c5a ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002c4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002c3 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig0000070c ), + .Q(\blk00000003/blk000002b1/sig00000c59 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002c3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c68 ), + .Q(\blk00000003/sig0000047d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c67 ), + .Q(\blk00000003/sig0000047e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c66 ), + .Q(\blk00000003/sig0000047f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c65 ), + .Q(\blk00000003/sig00000480 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c64 ), + .Q(\blk00000003/sig00000481 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c63 ), + .Q(\blk00000003/sig00000482 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c62 ), + .Q(\blk00000003/sig00000483 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c61 ), + .Q(\blk00000003/sig00000484 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c60 ), + .Q(\blk00000003/sig00000485 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c5f ), + .Q(\blk00000003/sig00000486 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c5e ), + .Q(\blk00000003/sig00000487 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c5d ), + .Q(\blk00000003/sig00000488 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c5c ), + .Q(\blk00000003/sig00000489 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c5b ), + .Q(\blk00000003/sig0000048a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c5a ), + .Q(\blk00000003/sig0000048b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c59 ), + .Q(\blk00000003/sig0000048c ) + ); + GND \blk00000003/blk000002b1/blk000002b2 ( + .G(\blk00000003/blk000002b1/sig00000c58 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002d4/blk0000030c ( + .I0(\blk00000003/sig00000307 ), + .I1(ce), + .O(\blk00000003/blk000002d4/sig00000cce ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk000002d4/blk0000030b ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig0000070d ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cbb ), + .DPO(\blk00000003/blk000002d4/sig00000ccd ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk000002d4/blk0000030a ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig0000070e ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cba ), + .DPO(\blk00000003/blk000002d4/sig00000ccc ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk000002d4/blk00000309 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig0000070f ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb9 ), + .DPO(\blk00000003/blk000002d4/sig00000ccb ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk000002d4/blk00000308 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000710 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb8 ), + .DPO(\blk00000003/blk000002d4/sig00000cca ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk000002d4/blk00000307 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000711 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb7 ), + .DPO(\blk00000003/blk000002d4/sig00000cc9 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk000002d4/blk00000306 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000712 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb6 ), + .DPO(\blk00000003/blk000002d4/sig00000cc8 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk000002d4/blk00000305 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000714 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb4 ), + .DPO(\blk00000003/blk000002d4/sig00000cc6 ) + ); + RAM16X1D #( + .INIT ( 16'h000D )) + \blk00000003/blk000002d4/blk00000304 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000715 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb3 ), + .DPO(\blk00000003/blk000002d4/sig00000cc5 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk000002d4/blk00000303 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000713 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb5 ), + .DPO(\blk00000003/blk000002d4/sig00000cc7 ) + ); + RAM16X1D #( + .INIT ( 16'h0009 )) + \blk00000003/blk000002d4/blk00000302 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000716 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb2 ), + .DPO(\blk00000003/blk000002d4/sig00000cc4 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000002d4/blk00000301 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000717 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb1 ), + .DPO(\blk00000003/blk000002d4/sig00000cc3 ) + ); + RAM16X1D #( + .INIT ( 16'h000F )) + \blk00000003/blk000002d4/blk00000300 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000718 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb0 ), + .DPO(\blk00000003/blk000002d4/sig00000cc2 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002d4/blk000002ff ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000719 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000caf ), + .DPO(\blk00000003/blk000002d4/sig00000cc1 ) + ); + RAM16X1D #( + .INIT ( 16'h0008 )) + \blk00000003/blk000002d4/blk000002fe ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig0000071a ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cae ), + .DPO(\blk00000003/blk000002d4/sig00000cc0 ) + ); + RAM16X1D #( + .INIT ( 16'h0004 )) + \blk00000003/blk000002d4/blk000002fd ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig0000071b ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cad ), + .DPO(\blk00000003/blk000002d4/sig00000cbf ) + ); + RAM16X1D #( + .INIT ( 16'h000B )) + \blk00000003/blk000002d4/blk000002fc ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig0000071d ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cab ), + .DPO(\blk00000003/blk000002d4/sig00000cbd ) + ); + RAM16X1D #( + .INIT ( 16'h0008 )) + \blk00000003/blk000002d4/blk000002fb ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig0000071e ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000caa ), + .DPO(\blk00000003/blk000002d4/sig00000cbc ) + ); + RAM16X1D #( + .INIT ( 16'h0008 )) + \blk00000003/blk000002d4/blk000002fa ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig0000071c ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cac ), + .DPO(\blk00000003/blk000002d4/sig00000cbe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000ccd ), + .Q(\blk00000003/sig000003db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000ccc ), + .Q(\blk00000003/sig000003dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000ccb ), + .Q(\blk00000003/sig000003dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cca ), + .Q(\blk00000003/sig000003de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc9 ), + .Q(\blk00000003/sig000003df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc8 ), + .Q(\blk00000003/sig000003e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc7 ), + .Q(\blk00000003/sig000003e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc6 ), + .Q(\blk00000003/sig000003e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc5 ), + .Q(\blk00000003/sig000003e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc4 ), + .Q(\blk00000003/sig000003e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc3 ), + .Q(\blk00000003/sig000003e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc2 ), + .Q(\blk00000003/sig000003e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc1 ), + .Q(\blk00000003/sig000003e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc0 ), + .Q(\blk00000003/sig000003e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cbf ), + .Q(\blk00000003/sig000003e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cbe ), + .Q(\blk00000003/sig000003ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cbd ), + .Q(\blk00000003/sig000003eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cbc ), + .Q(\blk00000003/sig000003ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cbb ), + .Q(\blk00000003/sig0000071f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cba ), + .Q(\blk00000003/sig00000720 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb9 ), + .Q(\blk00000003/sig00000721 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb8 ), + .Q(\blk00000003/sig00000722 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb7 ), + .Q(\blk00000003/sig00000723 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb6 ), + .Q(\blk00000003/sig00000724 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb5 ), + .Q(\blk00000003/sig00000725 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb4 ), + .Q(\blk00000003/sig00000726 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002df ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb3 ), + .Q(\blk00000003/sig00000727 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002de ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb2 ), + .Q(\blk00000003/sig00000728 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb1 ), + .Q(\blk00000003/sig00000729 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb0 ), + .Q(\blk00000003/sig0000072a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002db ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000caf ), + .Q(\blk00000003/sig0000072b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002da ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cae ), + .Q(\blk00000003/sig0000072c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cad ), + .Q(\blk00000003/sig0000072d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cac ), + .Q(\blk00000003/sig0000072e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cab ), + .Q(\blk00000003/sig0000072f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000caa ), + .Q(\blk00000003/sig00000730 ) + ); + GND \blk00000003/blk000002d4/blk000002d5 ( + .G(\blk00000003/blk000002d4/sig00000ca9 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000030d/blk00000345 ( + .I0(\blk00000003/sig00000677 ), + .I1(ce), + .O(\blk00000003/blk0000030d/sig00000d33 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk0000030d/blk00000344 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig0000071f ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d20 ), + .DPO(\blk00000003/blk0000030d/sig00000d32 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk0000030d/blk00000343 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000720 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d1f ), + .DPO(\blk00000003/blk0000030d/sig00000d31 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk0000030d/blk00000342 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000721 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d1e ), + .DPO(\blk00000003/blk0000030d/sig00000d30 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk0000030d/blk00000341 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000722 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d1d ), + .DPO(\blk00000003/blk0000030d/sig00000d2f ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk0000030d/blk00000340 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000723 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d1c ), + .DPO(\blk00000003/blk0000030d/sig00000d2e ) + ); + RAM16X1D #( + .INIT ( 16'h000D )) + \blk00000003/blk0000030d/blk0000033f ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000724 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d1b ), + .DPO(\blk00000003/blk0000030d/sig00000d2d ) + ); + RAM16X1D #( + .INIT ( 16'h0008 )) + \blk00000003/blk0000030d/blk0000033e ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000726 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d19 ), + .DPO(\blk00000003/blk0000030d/sig00000d2b ) + ); + RAM16X1D #( + .INIT ( 16'h0009 )) + \blk00000003/blk0000030d/blk0000033d ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000727 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d18 ), + .DPO(\blk00000003/blk0000030d/sig00000d2a ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk0000030d/blk0000033c ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000725 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d1a ), + .DPO(\blk00000003/blk0000030d/sig00000d2c ) + ); + RAM16X1D #( + .INIT ( 16'h000A )) + \blk00000003/blk0000030d/blk0000033b ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000728 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d17 ), + .DPO(\blk00000003/blk0000030d/sig00000d29 ) + ); + RAM16X1D #( + .INIT ( 16'h0006 )) + \blk00000003/blk0000030d/blk0000033a ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000729 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d16 ), + .DPO(\blk00000003/blk0000030d/sig00000d28 ) + ); + RAM16X1D #( + .INIT ( 16'h000C )) + \blk00000003/blk0000030d/blk00000339 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig0000072a ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d15 ), + .DPO(\blk00000003/blk0000030d/sig00000d27 ) + ); + RAM16X1D #( + .INIT ( 16'h000A )) + \blk00000003/blk0000030d/blk00000338 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig0000072b ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d14 ), + .DPO(\blk00000003/blk0000030d/sig00000d26 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk0000030d/blk00000337 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig0000072c ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d13 ), + .DPO(\blk00000003/blk0000030d/sig00000d25 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk0000030d/blk00000336 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig0000072d ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d12 ), + .DPO(\blk00000003/blk0000030d/sig00000d24 ) + ); + RAM16X1D #( + .INIT ( 16'h000B )) + \blk00000003/blk0000030d/blk00000335 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig0000072f ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d10 ), + .DPO(\blk00000003/blk0000030d/sig00000d22 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk0000030d/blk00000334 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000730 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d0f ), + .DPO(\blk00000003/blk0000030d/sig00000d21 ) + ); + RAM16X1D #( + .INIT ( 16'h000F )) + \blk00000003/blk0000030d/blk00000333 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig0000072e ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d11 ), + .DPO(\blk00000003/blk0000030d/sig00000d23 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000332 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d32 ), + .Q(\blk00000003/sig0000056f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000331 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d31 ), + .Q(\blk00000003/sig00000570 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000330 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d30 ), + .Q(\blk00000003/sig00000571 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000032f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d2f ), + .Q(\blk00000003/sig00000572 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000032e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d2e ), + .Q(\blk00000003/sig00000573 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000032d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d2d ), + .Q(\blk00000003/sig00000574 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000032c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d2c ), + .Q(\blk00000003/sig00000575 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000032b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d2b ), + .Q(\blk00000003/sig00000576 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000032a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d2a ), + .Q(\blk00000003/sig00000577 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000329 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d29 ), + .Q(\blk00000003/sig00000578 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000328 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d28 ), + .Q(\blk00000003/sig00000579 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000327 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d27 ), + .Q(\blk00000003/sig0000057a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000326 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d26 ), + .Q(\blk00000003/sig0000057b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000325 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d25 ), + .Q(\blk00000003/sig0000057c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000324 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d24 ), + .Q(\blk00000003/sig0000057d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000323 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d23 ), + .Q(\blk00000003/sig0000057e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000322 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d22 ), + .Q(\blk00000003/sig0000057f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000321 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d21 ), + .Q(\blk00000003/sig00000580 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000320 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d20 ), + .Q(\blk00000003/sig00000731 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000031f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d1f ), + .Q(\blk00000003/sig00000732 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000031e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d1e ), + .Q(\blk00000003/sig00000733 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000031d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d1d ), + .Q(\blk00000003/sig00000734 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000031c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d1c ), + .Q(\blk00000003/sig00000735 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000031b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d1b ), + .Q(\blk00000003/sig00000736 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000031a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d1a ), + .Q(\blk00000003/sig00000737 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000319 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d19 ), + .Q(\blk00000003/sig00000738 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000318 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d18 ), + .Q(\blk00000003/sig00000739 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000317 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d17 ), + .Q(\blk00000003/sig0000073a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000316 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d16 ), + .Q(\blk00000003/sig0000073b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000315 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d15 ), + .Q(\blk00000003/sig0000073c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000314 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d14 ), + .Q(\blk00000003/sig0000073d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000313 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d13 ), + .Q(\blk00000003/sig0000073e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000312 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d12 ), + .Q(\blk00000003/sig0000073f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000311 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d11 ), + .Q(\blk00000003/sig00000740 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000310 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d10 ), + .Q(\blk00000003/sig00000741 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000030f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d0f ), + .Q(\blk00000003/sig00000742 ) + ); + GND \blk00000003/blk0000030d/blk0000030e ( + .G(\blk00000003/blk0000030d/sig00000d0e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000386/blk000003ac ( + .I0(\blk00000003/sig00000678 ), + .I1(ce), + .O(\blk00000003/blk00000386/sig00000d74 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk00000386/blk000003ab ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000731 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003ab_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d73 ) + ); + RAM16X1D #( + .INIT ( 16'h000D )) + \blk00000003/blk00000386/blk000003aa ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000732 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003aa_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d72 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk00000386/blk000003a9 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000733 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a9_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d71 ) + ); + RAM16X1D #( + .INIT ( 16'h0009 )) + \blk00000003/blk00000386/blk000003a8 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000734 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a8_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d70 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000386/blk000003a7 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000735 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a7_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d6f ) + ); + RAM16X1D #( + .INIT ( 16'h0007 )) + \blk00000003/blk00000386/blk000003a6 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000736 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a6_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d6e ) + ); + RAM16X1D #( + .INIT ( 16'h0009 )) + \blk00000003/blk00000386/blk000003a5 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000738 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a5_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d6c ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000386/blk000003a4 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000739 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a4_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d6b ) + ); + RAM16X1D #( + .INIT ( 16'h0007 )) + \blk00000003/blk00000386/blk000003a3 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000737 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a3_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d6d ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000386/blk000003a2 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig0000073a ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a2_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d6a ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000386/blk000003a1 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig0000073b ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a1_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d69 ) + ); + RAM16X1D #( + .INIT ( 16'h000C )) + \blk00000003/blk00000386/blk000003a0 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig0000073c ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a0_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d68 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000386/blk0000039f ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig0000073d ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk0000039f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d67 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk00000386/blk0000039e ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig0000073e ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk0000039e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d66 ) + ); + RAM16X1D #( + .INIT ( 16'h0007 )) + \blk00000003/blk00000386/blk0000039d ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig0000073f ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk0000039d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d65 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000386/blk0000039c ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000741 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk0000039c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d63 ) + ); + RAM16X1D #( + .INIT ( 16'h0009 )) + \blk00000003/blk00000386/blk0000039b ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000742 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk0000039b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d62 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000386/blk0000039a ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000740 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk0000039a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d64 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000399 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d73 ), + .Q(\blk00000003/sig0000050d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000398 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d72 ), + .Q(\blk00000003/sig0000050e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000397 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d71 ), + .Q(\blk00000003/sig0000050f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000396 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d70 ), + .Q(\blk00000003/sig00000510 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000395 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d6f ), + .Q(\blk00000003/sig00000511 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000394 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d6e ), + .Q(\blk00000003/sig00000512 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000393 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d6d ), + .Q(\blk00000003/sig00000513 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000392 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d6c ), + .Q(\blk00000003/sig00000514 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000391 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d6b ), + .Q(\blk00000003/sig00000515 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000390 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d6a ), + .Q(\blk00000003/sig00000516 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk0000038f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d69 ), + .Q(\blk00000003/sig00000517 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk0000038e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d68 ), + .Q(\blk00000003/sig00000518 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk0000038d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d67 ), + .Q(\blk00000003/sig00000519 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk0000038c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d66 ), + .Q(\blk00000003/sig0000051a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk0000038b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d65 ), + .Q(\blk00000003/sig0000051b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk0000038a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d64 ), + .Q(\blk00000003/sig0000051c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000389 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d63 ), + .Q(\blk00000003/sig0000051d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000388 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d62 ), + .Q(\blk00000003/sig0000051e ) + ); + GND \blk00000003/blk00000386/blk00000387 ( + .G(\blk00000003/blk00000386/sig00000d61 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003ad/blk000003bf ( + .I0(\blk00000003/sig0000067c ), + .I1(ce), + .O(\blk00000003/blk000003ad/sig00000d93 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ad/blk000003be ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003ad/sig00000d8a ), + .A3(\blk00000003/blk000003ad/sig00000d8a ), + .CE(\blk00000003/blk000003ad/sig00000d93 ), + .CLK(clk), + .D(\blk00000003/sig00000567 ), + .Q(\blk00000003/blk000003ad/sig00000d92 ), + .Q15(\NLW_blk00000003/blk000003ad/blk000003be_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ad/blk000003bd ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003ad/sig00000d8a ), + .A3(\blk00000003/blk000003ad/sig00000d8a ), + .CE(\blk00000003/blk000003ad/sig00000d93 ), + .CLK(clk), + .D(\blk00000003/sig00000568 ), + .Q(\blk00000003/blk000003ad/sig00000d91 ), + .Q15(\NLW_blk00000003/blk000003ad/blk000003bd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ad/blk000003bc ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003ad/sig00000d8a ), + .A3(\blk00000003/blk000003ad/sig00000d8a ), + .CE(\blk00000003/blk000003ad/sig00000d93 ), + .CLK(clk), + .D(\blk00000003/sig00000569 ), + .Q(\blk00000003/blk000003ad/sig00000d90 ), + .Q15(\NLW_blk00000003/blk000003ad/blk000003bc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ad/blk000003bb ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003ad/sig00000d8a ), + .A3(\blk00000003/blk000003ad/sig00000d8a ), + .CE(\blk00000003/blk000003ad/sig00000d93 ), + .CLK(clk), + .D(\blk00000003/sig0000056a ), + .Q(\blk00000003/blk000003ad/sig00000d8f ), + .Q15(\NLW_blk00000003/blk000003ad/blk000003bb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ad/blk000003ba ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003ad/sig00000d8a ), + .A3(\blk00000003/blk000003ad/sig00000d8a ), + .CE(\blk00000003/blk000003ad/sig00000d93 ), + .CLK(clk), + .D(\blk00000003/sig0000056b ), + .Q(\blk00000003/blk000003ad/sig00000d8e ), + .Q15(\NLW_blk00000003/blk000003ad/blk000003ba_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ad/blk000003b9 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003ad/sig00000d8a ), + .A3(\blk00000003/blk000003ad/sig00000d8a ), + .CE(\blk00000003/blk000003ad/sig00000d93 ), + .CLK(clk), + .D(\blk00000003/sig0000056c ), + .Q(\blk00000003/blk000003ad/sig00000d8d ), + .Q15(\NLW_blk00000003/blk000003ad/blk000003b9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ad/blk000003b8 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003ad/sig00000d8a ), + .A3(\blk00000003/blk000003ad/sig00000d8a ), + .CE(\blk00000003/blk000003ad/sig00000d93 ), + .CLK(clk), + .D(\blk00000003/sig0000056d ), + .Q(\blk00000003/blk000003ad/sig00000d8c ), + .Q15(\NLW_blk00000003/blk000003ad/blk000003b8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ad/blk000003b7 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003ad/sig00000d8a ), + .A3(\blk00000003/blk000003ad/sig00000d8a ), + .CE(\blk00000003/blk000003ad/sig00000d93 ), + .CLK(clk), + .D(\blk00000003/sig0000056e ), + .Q(\blk00000003/blk000003ad/sig00000d8b ), + .Q15(\NLW_blk00000003/blk000003ad/blk000003b7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad/blk000003b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ad/sig00000d92 ), + .Q(\blk00000003/sig00000505 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad/blk000003b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ad/sig00000d91 ), + .Q(\blk00000003/sig00000506 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad/blk000003b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ad/sig00000d90 ), + .Q(\blk00000003/sig00000507 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad/blk000003b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ad/sig00000d8f ), + .Q(\blk00000003/sig00000508 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad/blk000003b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ad/sig00000d8e ), + .Q(\blk00000003/sig00000509 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad/blk000003b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ad/sig00000d8d ), + .Q(\blk00000003/sig0000050a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad/blk000003b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ad/sig00000d8c ), + .Q(\blk00000003/sig0000050b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad/blk000003af ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ad/sig00000d8b ), + .Q(\blk00000003/sig0000050c ) + ); + GND \blk00000003/blk000003ad/blk000003ae ( + .G(\blk00000003/blk000003ad/sig00000d8a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003c0/blk000003d2 ( + .I0(\blk00000003/sig0000067a ), + .I1(ce), + .O(\blk00000003/blk000003c0/sig00000db2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003c0/blk000003d1 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003c0/sig00000da9 ), + .A3(\blk00000003/blk000003c0/sig00000da9 ), + .CE(\blk00000003/blk000003c0/sig00000db2 ), + .CLK(clk), + .D(\blk00000003/sig00000745 ), + .Q(\blk00000003/blk000003c0/sig00000db1 ), + .Q15(\NLW_blk00000003/blk000003c0/blk000003d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003c0/blk000003d0 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003c0/sig00000da9 ), + .A3(\blk00000003/blk000003c0/sig00000da9 ), + .CE(\blk00000003/blk000003c0/sig00000db2 ), + .CLK(clk), + .D(\blk00000003/sig00000746 ), + .Q(\blk00000003/blk000003c0/sig00000db0 ), + .Q15(\NLW_blk00000003/blk000003c0/blk000003d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003c0/blk000003cf ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003c0/sig00000da9 ), + .A3(\blk00000003/blk000003c0/sig00000da9 ), + .CE(\blk00000003/blk000003c0/sig00000db2 ), + .CLK(clk), + .D(\blk00000003/sig00000747 ), + .Q(\blk00000003/blk000003c0/sig00000daf ), + .Q15(\NLW_blk00000003/blk000003c0/blk000003cf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003c0/blk000003ce ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003c0/sig00000da9 ), + .A3(\blk00000003/blk000003c0/sig00000da9 ), + .CE(\blk00000003/blk000003c0/sig00000db2 ), + .CLK(clk), + .D(\blk00000003/sig00000748 ), + .Q(\blk00000003/blk000003c0/sig00000dae ), + .Q15(\NLW_blk00000003/blk000003c0/blk000003ce_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003c0/blk000003cd ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003c0/sig00000da9 ), + .A3(\blk00000003/blk000003c0/sig00000da9 ), + .CE(\blk00000003/blk000003c0/sig00000db2 ), + .CLK(clk), + .D(\blk00000003/sig00000749 ), + .Q(\blk00000003/blk000003c0/sig00000dad ), + .Q15(\NLW_blk00000003/blk000003c0/blk000003cd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003c0/blk000003cc ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003c0/sig00000da9 ), + .A3(\blk00000003/blk000003c0/sig00000da9 ), + .CE(\blk00000003/blk000003c0/sig00000db2 ), + .CLK(clk), + .D(\blk00000003/sig0000074a ), + .Q(\blk00000003/blk000003c0/sig00000dac ), + .Q15(\NLW_blk00000003/blk000003c0/blk000003cc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003c0/blk000003cb ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003c0/sig00000da9 ), + .A3(\blk00000003/blk000003c0/sig00000da9 ), + .CE(\blk00000003/blk000003c0/sig00000db2 ), + .CLK(clk), + .D(\blk00000003/sig0000074b ), + .Q(\blk00000003/blk000003c0/sig00000dab ), + .Q15(\NLW_blk00000003/blk000003c0/blk000003cb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003c0/blk000003ca ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003c0/sig00000da9 ), + .A3(\blk00000003/blk000003c0/sig00000da9 ), + .CE(\blk00000003/blk000003c0/sig00000db2 ), + .CLK(clk), + .D(\blk00000003/sig0000074c ), + .Q(\blk00000003/blk000003c0/sig00000daa ), + .Q15(\NLW_blk00000003/blk000003c0/blk000003ca_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0/blk000003c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003c0/sig00000db1 ), + .Q(\blk00000003/sig000004cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0/blk000003c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003c0/sig00000db0 ), + .Q(\blk00000003/sig000004ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0/blk000003c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003c0/sig00000daf ), + .Q(\blk00000003/sig000004cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0/blk000003c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003c0/sig00000dae ), + .Q(\blk00000003/sig000004d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0/blk000003c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003c0/sig00000dad ), + .Q(\blk00000003/sig000004d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0/blk000003c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003c0/sig00000dac ), + .Q(\blk00000003/sig000004d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0/blk000003c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003c0/sig00000dab ), + .Q(\blk00000003/sig000004d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0/blk000003c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003c0/sig00000daa ), + .Q(\blk00000003/sig000004d4 ) + ); + GND \blk00000003/blk000003c0/blk000003c1 ( + .G(\blk00000003/blk000003c0/sig00000da9 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003d3/blk000003e5 ( + .I0(\blk00000003/sig0000067c ), + .I1(ce), + .O(\blk00000003/blk000003d3/sig00000dd1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d3/blk000003e4 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003d3/sig00000dc8 ), + .A3(\blk00000003/blk000003d3/sig00000dc8 ), + .CE(\blk00000003/blk000003d3/sig00000dd1 ), + .CLK(clk), + .D(\blk00000003/sig00000589 ), + .Q(\blk00000003/blk000003d3/sig00000dd0 ), + .Q15(\NLW_blk00000003/blk000003d3/blk000003e4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d3/blk000003e3 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003d3/sig00000dc8 ), + .A3(\blk00000003/blk000003d3/sig00000dc8 ), + .CE(\blk00000003/blk000003d3/sig00000dd1 ), + .CLK(clk), + .D(\blk00000003/sig0000058a ), + .Q(\blk00000003/blk000003d3/sig00000dcf ), + .Q15(\NLW_blk00000003/blk000003d3/blk000003e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d3/blk000003e2 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003d3/sig00000dc8 ), + .A3(\blk00000003/blk000003d3/sig00000dc8 ), + .CE(\blk00000003/blk000003d3/sig00000dd1 ), + .CLK(clk), + .D(\blk00000003/sig0000058b ), + .Q(\blk00000003/blk000003d3/sig00000dce ), + .Q15(\NLW_blk00000003/blk000003d3/blk000003e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d3/blk000003e1 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003d3/sig00000dc8 ), + .A3(\blk00000003/blk000003d3/sig00000dc8 ), + .CE(\blk00000003/blk000003d3/sig00000dd1 ), + .CLK(clk), + .D(\blk00000003/sig0000058c ), + .Q(\blk00000003/blk000003d3/sig00000dcd ), + .Q15(\NLW_blk00000003/blk000003d3/blk000003e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d3/blk000003e0 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003d3/sig00000dc8 ), + .A3(\blk00000003/blk000003d3/sig00000dc8 ), + .CE(\blk00000003/blk000003d3/sig00000dd1 ), + .CLK(clk), + .D(\blk00000003/sig0000058d ), + .Q(\blk00000003/blk000003d3/sig00000dcc ), + .Q15(\NLW_blk00000003/blk000003d3/blk000003e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d3/blk000003df ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003d3/sig00000dc8 ), + .A3(\blk00000003/blk000003d3/sig00000dc8 ), + .CE(\blk00000003/blk000003d3/sig00000dd1 ), + .CLK(clk), + .D(\blk00000003/sig0000058e ), + .Q(\blk00000003/blk000003d3/sig00000dcb ), + .Q15(\NLW_blk00000003/blk000003d3/blk000003df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d3/blk000003de ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003d3/sig00000dc8 ), + .A3(\blk00000003/blk000003d3/sig00000dc8 ), + .CE(\blk00000003/blk000003d3/sig00000dd1 ), + .CLK(clk), + .D(\blk00000003/sig0000058f ), + .Q(\blk00000003/blk000003d3/sig00000dca ), + .Q15(\NLW_blk00000003/blk000003d3/blk000003de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d3/blk000003dd ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003d3/sig00000dc8 ), + .A3(\blk00000003/blk000003d3/sig00000dc8 ), + .CE(\blk00000003/blk000003d3/sig00000dd1 ), + .CLK(clk), + .D(\blk00000003/sig00000590 ), + .Q(\blk00000003/blk000003d3/sig00000dc9 ), + .Q15(\NLW_blk00000003/blk000003d3/blk000003dd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3/blk000003dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d3/sig00000dd0 ), + .Q(\blk00000003/sig00000557 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3/blk000003db ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d3/sig00000dcf ), + .Q(\blk00000003/sig00000558 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3/blk000003da ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d3/sig00000dce ), + .Q(\blk00000003/sig00000559 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3/blk000003d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d3/sig00000dcd ), + .Q(\blk00000003/sig0000055a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3/blk000003d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d3/sig00000dcc ), + .Q(\blk00000003/sig0000055b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3/blk000003d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d3/sig00000dcb ), + .Q(\blk00000003/sig0000055c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3/blk000003d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d3/sig00000dca ), + .Q(\blk00000003/sig0000055d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3/blk000003d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d3/sig00000dc9 ), + .Q(\blk00000003/sig0000055e ) + ); + GND \blk00000003/blk000003d3/blk000003d4 ( + .G(\blk00000003/blk000003d3/sig00000dc8 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003e6/blk000003f8 ( + .I0(\blk00000003/sig0000067a ), + .I1(ce), + .O(\blk00000003/blk000003e6/sig00000df0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003e6/blk000003f7 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003e6/sig00000de7 ), + .A3(\blk00000003/blk000003e6/sig00000de7 ), + .CE(\blk00000003/blk000003e6/sig00000df0 ), + .CLK(clk), + .D(\blk00000003/sig0000074d ), + .Q(\blk00000003/blk000003e6/sig00000def ), + .Q15(\NLW_blk00000003/blk000003e6/blk000003f7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003e6/blk000003f6 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003e6/sig00000de7 ), + .A3(\blk00000003/blk000003e6/sig00000de7 ), + .CE(\blk00000003/blk000003e6/sig00000df0 ), + .CLK(clk), + .D(\blk00000003/sig0000074e ), + .Q(\blk00000003/blk000003e6/sig00000dee ), + .Q15(\NLW_blk00000003/blk000003e6/blk000003f6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003e6/blk000003f5 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003e6/sig00000de7 ), + .A3(\blk00000003/blk000003e6/sig00000de7 ), + .CE(\blk00000003/blk000003e6/sig00000df0 ), + .CLK(clk), + .D(\blk00000003/sig0000074f ), + .Q(\blk00000003/blk000003e6/sig00000ded ), + .Q15(\NLW_blk00000003/blk000003e6/blk000003f5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003e6/blk000003f4 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003e6/sig00000de7 ), + .A3(\blk00000003/blk000003e6/sig00000de7 ), + .CE(\blk00000003/blk000003e6/sig00000df0 ), + .CLK(clk), + .D(\blk00000003/sig00000750 ), + .Q(\blk00000003/blk000003e6/sig00000dec ), + .Q15(\NLW_blk00000003/blk000003e6/blk000003f4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003e6/blk000003f3 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003e6/sig00000de7 ), + .A3(\blk00000003/blk000003e6/sig00000de7 ), + .CE(\blk00000003/blk000003e6/sig00000df0 ), + .CLK(clk), + .D(\blk00000003/sig00000751 ), + .Q(\blk00000003/blk000003e6/sig00000deb ), + .Q15(\NLW_blk00000003/blk000003e6/blk000003f3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003e6/blk000003f2 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003e6/sig00000de7 ), + .A3(\blk00000003/blk000003e6/sig00000de7 ), + .CE(\blk00000003/blk000003e6/sig00000df0 ), + .CLK(clk), + .D(\blk00000003/sig00000752 ), + .Q(\blk00000003/blk000003e6/sig00000dea ), + .Q15(\NLW_blk00000003/blk000003e6/blk000003f2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003e6/blk000003f1 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003e6/sig00000de7 ), + .A3(\blk00000003/blk000003e6/sig00000de7 ), + .CE(\blk00000003/blk000003e6/sig00000df0 ), + .CLK(clk), + .D(\blk00000003/sig00000753 ), + .Q(\blk00000003/blk000003e6/sig00000de9 ), + .Q15(\NLW_blk00000003/blk000003e6/blk000003f1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003e6/blk000003f0 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003e6/sig00000de7 ), + .A3(\blk00000003/blk000003e6/sig00000de7 ), + .CE(\blk00000003/blk000003e6/sig00000df0 ), + .CLK(clk), + .D(\blk00000003/sig00000754 ), + .Q(\blk00000003/blk000003e6/sig00000de8 ), + .Q15(\NLW_blk00000003/blk000003e6/blk000003f0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6/blk000003ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003e6/sig00000def ), + .Q(\blk00000003/sig0000051f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6/blk000003ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003e6/sig00000dee ), + .Q(\blk00000003/sig00000520 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6/blk000003ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003e6/sig00000ded ), + .Q(\blk00000003/sig00000521 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6/blk000003ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003e6/sig00000dec ), + .Q(\blk00000003/sig00000522 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6/blk000003eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003e6/sig00000deb ), + .Q(\blk00000003/sig00000523 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6/blk000003ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003e6/sig00000dea ), + .Q(\blk00000003/sig00000524 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6/blk000003e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003e6/sig00000de9 ), + .Q(\blk00000003/sig00000525 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6/blk000003e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003e6/sig00000de8 ), + .Q(\blk00000003/sig00000526 ) + ); + GND \blk00000003/blk000003e6/blk000003e7 ( + .G(\blk00000003/blk000003e6/sig00000de7 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003f9/blk0000040b ( + .I0(\blk00000003/sig0000067b ), + .I1(ce), + .O(\blk00000003/blk000003f9/sig00000e0f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk0000040a ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000003f9/sig00000e06 ), + .A3(\blk00000003/blk000003f9/sig00000e06 ), + .CE(\blk00000003/blk000003f9/sig00000e0f ), + .CLK(clk), + .D(\blk00000003/sig000003a3 ), + .Q(\blk00000003/blk000003f9/sig00000e0e ), + .Q15(\NLW_blk00000003/blk000003f9/blk0000040a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000409 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000003f9/sig00000e06 ), + .A3(\blk00000003/blk000003f9/sig00000e06 ), + .CE(\blk00000003/blk000003f9/sig00000e0f ), + .CLK(clk), + .D(\blk00000003/sig000003a4 ), + .Q(\blk00000003/blk000003f9/sig00000e0d ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000409_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000408 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000003f9/sig00000e06 ), + .A3(\blk00000003/blk000003f9/sig00000e06 ), + .CE(\blk00000003/blk000003f9/sig00000e0f ), + .CLK(clk), + .D(\blk00000003/sig000003a5 ), + .Q(\blk00000003/blk000003f9/sig00000e0c ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000408_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000407 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000003f9/sig00000e06 ), + .A3(\blk00000003/blk000003f9/sig00000e06 ), + .CE(\blk00000003/blk000003f9/sig00000e0f ), + .CLK(clk), + .D(\blk00000003/sig000003a6 ), + .Q(\blk00000003/blk000003f9/sig00000e0b ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000407_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000406 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000003f9/sig00000e06 ), + .A3(\blk00000003/blk000003f9/sig00000e06 ), + .CE(\blk00000003/blk000003f9/sig00000e0f ), + .CLK(clk), + .D(\blk00000003/sig000003a7 ), + .Q(\blk00000003/blk000003f9/sig00000e0a ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000406_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000405 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000003f9/sig00000e06 ), + .A3(\blk00000003/blk000003f9/sig00000e06 ), + .CE(\blk00000003/blk000003f9/sig00000e0f ), + .CLK(clk), + .D(\blk00000003/sig000003a8 ), + .Q(\blk00000003/blk000003f9/sig00000e09 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000405_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000404 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000003f9/sig00000e06 ), + .A3(\blk00000003/blk000003f9/sig00000e06 ), + .CE(\blk00000003/blk000003f9/sig00000e0f ), + .CLK(clk), + .D(\blk00000003/sig000003a9 ), + .Q(\blk00000003/blk000003f9/sig00000e08 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000404_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000403 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000003f9/sig00000e06 ), + .A3(\blk00000003/blk000003f9/sig00000e06 ), + .CE(\blk00000003/blk000003f9/sig00000e0f ), + .CLK(clk), + .D(\blk00000003/sig000003aa ), + .Q(\blk00000003/blk000003f9/sig00000e07 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000403_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000402 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00000e0e ), + .Q(\blk00000003/sig00000567 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000401 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00000e0d ), + .Q(\blk00000003/sig00000568 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000400 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00000e0c ), + .Q(\blk00000003/sig00000569 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00000e0b ), + .Q(\blk00000003/sig0000056a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00000e0a ), + .Q(\blk00000003/sig0000056b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00000e09 ), + .Q(\blk00000003/sig0000056c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00000e08 ), + .Q(\blk00000003/sig0000056d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00000e07 ), + .Q(\blk00000003/sig0000056e ) + ); + GND \blk00000003/blk000003f9/blk000003fa ( + .G(\blk00000003/blk000003f9/sig00000e06 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000040c/blk0000041e ( + .I0(\blk00000003/sig00000679 ), + .I1(ce), + .O(\blk00000003/blk0000040c/sig00000e2e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000040c/blk0000041d ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk0000040c/sig00000e25 ), + .A3(\blk00000003/blk0000040c/sig00000e25 ), + .CE(\blk00000003/blk0000040c/sig00000e2e ), + .CLK(clk), + .D(\blk00000003/sig00000755 ), + .Q(\blk00000003/blk0000040c/sig00000e2d ), + .Q15(\NLW_blk00000003/blk0000040c/blk0000041d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000040c/blk0000041c ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk0000040c/sig00000e25 ), + .A3(\blk00000003/blk0000040c/sig00000e25 ), + .CE(\blk00000003/blk0000040c/sig00000e2e ), + .CLK(clk), + .D(\blk00000003/sig00000756 ), + .Q(\blk00000003/blk0000040c/sig00000e2c ), + .Q15(\NLW_blk00000003/blk0000040c/blk0000041c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000040c/blk0000041b ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk0000040c/sig00000e25 ), + .A3(\blk00000003/blk0000040c/sig00000e25 ), + .CE(\blk00000003/blk0000040c/sig00000e2e ), + .CLK(clk), + .D(\blk00000003/sig00000757 ), + .Q(\blk00000003/blk0000040c/sig00000e2b ), + .Q15(\NLW_blk00000003/blk0000040c/blk0000041b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000040c/blk0000041a ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk0000040c/sig00000e25 ), + .A3(\blk00000003/blk0000040c/sig00000e25 ), + .CE(\blk00000003/blk0000040c/sig00000e2e ), + .CLK(clk), + .D(\blk00000003/sig00000758 ), + .Q(\blk00000003/blk0000040c/sig00000e2a ), + .Q15(\NLW_blk00000003/blk0000040c/blk0000041a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000040c/blk00000419 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk0000040c/sig00000e25 ), + .A3(\blk00000003/blk0000040c/sig00000e25 ), + .CE(\blk00000003/blk0000040c/sig00000e2e ), + .CLK(clk), + .D(\blk00000003/sig00000759 ), + .Q(\blk00000003/blk0000040c/sig00000e29 ), + .Q15(\NLW_blk00000003/blk0000040c/blk00000419_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000040c/blk00000418 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk0000040c/sig00000e25 ), + .A3(\blk00000003/blk0000040c/sig00000e25 ), + .CE(\blk00000003/blk0000040c/sig00000e2e ), + .CLK(clk), + .D(\blk00000003/sig0000075a ), + .Q(\blk00000003/blk0000040c/sig00000e28 ), + .Q15(\NLW_blk00000003/blk0000040c/blk00000418_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000040c/blk00000417 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk0000040c/sig00000e25 ), + .A3(\blk00000003/blk0000040c/sig00000e25 ), + .CE(\blk00000003/blk0000040c/sig00000e2e ), + .CLK(clk), + .D(\blk00000003/sig0000075b ), + .Q(\blk00000003/blk0000040c/sig00000e27 ), + .Q15(\NLW_blk00000003/blk0000040c/blk00000417_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000040c/blk00000416 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk0000040c/sig00000e25 ), + .A3(\blk00000003/blk0000040c/sig00000e25 ), + .CE(\blk00000003/blk0000040c/sig00000e2e ), + .CLK(clk), + .D(\blk00000003/sig0000075c ), + .Q(\blk00000003/blk0000040c/sig00000e26 ), + .Q15(\NLW_blk00000003/blk0000040c/blk00000416_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c/blk00000415 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000040c/sig00000e2d ), + .Q(\blk00000003/sig0000055f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c/blk00000414 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000040c/sig00000e2c ), + .Q(\blk00000003/sig00000560 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c/blk00000413 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000040c/sig00000e2b ), + .Q(\blk00000003/sig00000561 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c/blk00000412 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000040c/sig00000e2a ), + .Q(\blk00000003/sig00000562 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c/blk00000411 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000040c/sig00000e29 ), + .Q(\blk00000003/sig00000563 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c/blk00000410 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000040c/sig00000e28 ), + .Q(\blk00000003/sig00000564 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c/blk0000040f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000040c/sig00000e27 ), + .Q(\blk00000003/sig00000565 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c/blk0000040e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000040c/sig00000e26 ), + .Q(\blk00000003/sig00000566 ) + ); + GND \blk00000003/blk0000040c/blk0000040d ( + .G(\blk00000003/blk0000040c/sig00000e25 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000041f/blk00000431 ( + .I0(\blk00000003/sig0000067b ), + .I1(ce), + .O(\blk00000003/blk0000041f/sig00000e4d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041f/blk00000430 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk0000041f/sig00000e44 ), + .A3(\blk00000003/blk0000041f/sig00000e44 ), + .CE(\blk00000003/blk0000041f/sig00000e4d ), + .CLK(clk), + .D(\blk00000003/sig000003f5 ), + .Q(\blk00000003/blk0000041f/sig00000e4c ), + .Q15(\NLW_blk00000003/blk0000041f/blk00000430_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041f/blk0000042f ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk0000041f/sig00000e44 ), + .A3(\blk00000003/blk0000041f/sig00000e44 ), + .CE(\blk00000003/blk0000041f/sig00000e4d ), + .CLK(clk), + .D(\blk00000003/sig000003f6 ), + .Q(\blk00000003/blk0000041f/sig00000e4b ), + .Q15(\NLW_blk00000003/blk0000041f/blk0000042f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041f/blk0000042e ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk0000041f/sig00000e44 ), + .A3(\blk00000003/blk0000041f/sig00000e44 ), + .CE(\blk00000003/blk0000041f/sig00000e4d ), + .CLK(clk), + .D(\blk00000003/sig000003f7 ), + .Q(\blk00000003/blk0000041f/sig00000e4a ), + .Q15(\NLW_blk00000003/blk0000041f/blk0000042e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041f/blk0000042d ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk0000041f/sig00000e44 ), + .A3(\blk00000003/blk0000041f/sig00000e44 ), + .CE(\blk00000003/blk0000041f/sig00000e4d ), + .CLK(clk), + .D(\blk00000003/sig000003f8 ), + .Q(\blk00000003/blk0000041f/sig00000e49 ), + .Q15(\NLW_blk00000003/blk0000041f/blk0000042d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041f/blk0000042c ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk0000041f/sig00000e44 ), + .A3(\blk00000003/blk0000041f/sig00000e44 ), + .CE(\blk00000003/blk0000041f/sig00000e4d ), + .CLK(clk), + .D(\blk00000003/sig000003f9 ), + .Q(\blk00000003/blk0000041f/sig00000e48 ), + .Q15(\NLW_blk00000003/blk0000041f/blk0000042c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041f/blk0000042b ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk0000041f/sig00000e44 ), + .A3(\blk00000003/blk0000041f/sig00000e44 ), + .CE(\blk00000003/blk0000041f/sig00000e4d ), + .CLK(clk), + .D(\blk00000003/sig000003fa ), + .Q(\blk00000003/blk0000041f/sig00000e47 ), + .Q15(\NLW_blk00000003/blk0000041f/blk0000042b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041f/blk0000042a ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk0000041f/sig00000e44 ), + .A3(\blk00000003/blk0000041f/sig00000e44 ), + .CE(\blk00000003/blk0000041f/sig00000e4d ), + .CLK(clk), + .D(\blk00000003/sig000003fb ), + .Q(\blk00000003/blk0000041f/sig00000e46 ), + .Q15(\NLW_blk00000003/blk0000041f/blk0000042a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041f/blk00000429 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk0000041f/sig00000e44 ), + .A3(\blk00000003/blk0000041f/sig00000e44 ), + .CE(\blk00000003/blk0000041f/sig00000e4d ), + .CLK(clk), + .D(\blk00000003/sig000003fc ), + .Q(\blk00000003/blk0000041f/sig00000e45 ), + .Q15(\NLW_blk00000003/blk0000041f/blk00000429_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f/blk00000428 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041f/sig00000e4c ), + .Q(\blk00000003/sig00000589 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f/blk00000427 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041f/sig00000e4b ), + .Q(\blk00000003/sig0000058a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f/blk00000426 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041f/sig00000e4a ), + .Q(\blk00000003/sig0000058b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f/blk00000425 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041f/sig00000e49 ), + .Q(\blk00000003/sig0000058c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f/blk00000424 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041f/sig00000e48 ), + .Q(\blk00000003/sig0000058d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f/blk00000423 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041f/sig00000e47 ), + .Q(\blk00000003/sig0000058e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f/blk00000422 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041f/sig00000e46 ), + .Q(\blk00000003/sig0000058f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f/blk00000421 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041f/sig00000e45 ), + .Q(\blk00000003/sig00000590 ) + ); + GND \blk00000003/blk0000041f/blk00000420 ( + .G(\blk00000003/blk0000041f/sig00000e44 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000432/blk00000444 ( + .I0(\blk00000003/sig00000679 ), + .I1(ce), + .O(\blk00000003/blk00000432/sig00000e6c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000432/blk00000443 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000432/sig00000e63 ), + .A3(\blk00000003/blk00000432/sig00000e63 ), + .CE(\blk00000003/blk00000432/sig00000e6c ), + .CLK(clk), + .D(\blk00000003/sig0000075d ), + .Q(\blk00000003/blk00000432/sig00000e6b ), + .Q15(\NLW_blk00000003/blk00000432/blk00000443_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000432/blk00000442 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000432/sig00000e63 ), + .A3(\blk00000003/blk00000432/sig00000e63 ), + .CE(\blk00000003/blk00000432/sig00000e6c ), + .CLK(clk), + .D(\blk00000003/sig0000075e ), + .Q(\blk00000003/blk00000432/sig00000e6a ), + .Q15(\NLW_blk00000003/blk00000432/blk00000442_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000432/blk00000441 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000432/sig00000e63 ), + .A3(\blk00000003/blk00000432/sig00000e63 ), + .CE(\blk00000003/blk00000432/sig00000e6c ), + .CLK(clk), + .D(\blk00000003/sig0000075f ), + .Q(\blk00000003/blk00000432/sig00000e69 ), + .Q15(\NLW_blk00000003/blk00000432/blk00000441_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000432/blk00000440 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000432/sig00000e63 ), + .A3(\blk00000003/blk00000432/sig00000e63 ), + .CE(\blk00000003/blk00000432/sig00000e6c ), + .CLK(clk), + .D(\blk00000003/sig00000760 ), + .Q(\blk00000003/blk00000432/sig00000e68 ), + .Q15(\NLW_blk00000003/blk00000432/blk00000440_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000432/blk0000043f ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000432/sig00000e63 ), + .A3(\blk00000003/blk00000432/sig00000e63 ), + .CE(\blk00000003/blk00000432/sig00000e6c ), + .CLK(clk), + .D(\blk00000003/sig00000761 ), + .Q(\blk00000003/blk00000432/sig00000e67 ), + .Q15(\NLW_blk00000003/blk00000432/blk0000043f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000432/blk0000043e ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000432/sig00000e63 ), + .A3(\blk00000003/blk00000432/sig00000e63 ), + .CE(\blk00000003/blk00000432/sig00000e6c ), + .CLK(clk), + .D(\blk00000003/sig00000762 ), + .Q(\blk00000003/blk00000432/sig00000e66 ), + .Q15(\NLW_blk00000003/blk00000432/blk0000043e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000432/blk0000043d ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000432/sig00000e63 ), + .A3(\blk00000003/blk00000432/sig00000e63 ), + .CE(\blk00000003/blk00000432/sig00000e6c ), + .CLK(clk), + .D(\blk00000003/sig00000763 ), + .Q(\blk00000003/blk00000432/sig00000e65 ), + .Q15(\NLW_blk00000003/blk00000432/blk0000043d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000432/blk0000043c ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000432/sig00000e63 ), + .A3(\blk00000003/blk00000432/sig00000e63 ), + .CE(\blk00000003/blk00000432/sig00000e6c ), + .CLK(clk), + .D(\blk00000003/sig00000764 ), + .Q(\blk00000003/blk00000432/sig00000e64 ), + .Q15(\NLW_blk00000003/blk00000432/blk0000043c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432/blk0000043b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000432/sig00000e6b ), + .Q(\blk00000003/sig00000581 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432/blk0000043a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000432/sig00000e6a ), + .Q(\blk00000003/sig00000582 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432/blk00000439 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000432/sig00000e69 ), + .Q(\blk00000003/sig00000583 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432/blk00000438 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000432/sig00000e68 ), + .Q(\blk00000003/sig00000584 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432/blk00000437 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000432/sig00000e67 ), + .Q(\blk00000003/sig00000585 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432/blk00000436 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000432/sig00000e66 ), + .Q(\blk00000003/sig00000586 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432/blk00000435 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000432/sig00000e65 ), + .Q(\blk00000003/sig00000587 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432/blk00000434 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000432/sig00000e64 ), + .Q(\blk00000003/sig00000588 ) + ); + GND \blk00000003/blk00000432/blk00000433 ( + .G(\blk00000003/blk00000432/sig00000e63 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000445/blk00000457 ( + .I0(\blk00000003/sig0000068c ), + .I1(ce), + .O(\blk00000003/blk00000445/sig00000e8b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000445/blk00000456 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000445/sig00000e82 ), + .A3(\blk00000003/blk00000445/sig00000e82 ), + .CE(\blk00000003/blk00000445/sig00000e8b ), + .CLK(clk), + .D(\blk00000003/sig00000765 ), + .Q(\blk00000003/blk00000445/sig00000e8a ), + .Q15(\NLW_blk00000003/blk00000445/blk00000456_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000445/blk00000455 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000445/sig00000e82 ), + .A3(\blk00000003/blk00000445/sig00000e82 ), + .CE(\blk00000003/blk00000445/sig00000e8b ), + .CLK(clk), + .D(\blk00000003/sig00000766 ), + .Q(\blk00000003/blk00000445/sig00000e89 ), + .Q15(\NLW_blk00000003/blk00000445/blk00000455_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000445/blk00000454 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000445/sig00000e82 ), + .A3(\blk00000003/blk00000445/sig00000e82 ), + .CE(\blk00000003/blk00000445/sig00000e8b ), + .CLK(clk), + .D(\blk00000003/sig00000767 ), + .Q(\blk00000003/blk00000445/sig00000e88 ), + .Q15(\NLW_blk00000003/blk00000445/blk00000454_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000445/blk00000453 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000445/sig00000e82 ), + .A3(\blk00000003/blk00000445/sig00000e82 ), + .CE(\blk00000003/blk00000445/sig00000e8b ), + .CLK(clk), + .D(\blk00000003/sig00000768 ), + .Q(\blk00000003/blk00000445/sig00000e87 ), + .Q15(\NLW_blk00000003/blk00000445/blk00000453_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000445/blk00000452 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000445/sig00000e82 ), + .A3(\blk00000003/blk00000445/sig00000e82 ), + .CE(\blk00000003/blk00000445/sig00000e8b ), + .CLK(clk), + .D(\blk00000003/sig00000769 ), + .Q(\blk00000003/blk00000445/sig00000e86 ), + .Q15(\NLW_blk00000003/blk00000445/blk00000452_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000445/blk00000451 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000445/sig00000e82 ), + .A3(\blk00000003/blk00000445/sig00000e82 ), + .CE(\blk00000003/blk00000445/sig00000e8b ), + .CLK(clk), + .D(\blk00000003/sig0000076a ), + .Q(\blk00000003/blk00000445/sig00000e85 ), + .Q15(\NLW_blk00000003/blk00000445/blk00000451_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000445/blk00000450 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000445/sig00000e82 ), + .A3(\blk00000003/blk00000445/sig00000e82 ), + .CE(\blk00000003/blk00000445/sig00000e8b ), + .CLK(clk), + .D(\blk00000003/sig0000076b ), + .Q(\blk00000003/blk00000445/sig00000e84 ), + .Q15(\NLW_blk00000003/blk00000445/blk00000450_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000445/blk0000044f ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000445/sig00000e82 ), + .A3(\blk00000003/blk00000445/sig00000e82 ), + .CE(\blk00000003/blk00000445/sig00000e8b ), + .CLK(clk), + .D(\blk00000003/sig0000076c ), + .Q(\blk00000003/blk00000445/sig00000e83 ), + .Q15(\NLW_blk00000003/blk00000445/blk0000044f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445/blk0000044e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000445/sig00000e8a ), + .Q(\blk00000003/sig000003a3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445/blk0000044d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000445/sig00000e89 ), + .Q(\blk00000003/sig000003a4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445/blk0000044c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000445/sig00000e88 ), + .Q(\blk00000003/sig000003a5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445/blk0000044b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000445/sig00000e87 ), + .Q(\blk00000003/sig000003a6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445/blk0000044a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000445/sig00000e86 ), + .Q(\blk00000003/sig000003a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445/blk00000449 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000445/sig00000e85 ), + .Q(\blk00000003/sig000003a8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445/blk00000448 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000445/sig00000e84 ), + .Q(\blk00000003/sig000003a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445/blk00000447 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000445/sig00000e83 ), + .Q(\blk00000003/sig000003aa ) + ); + GND \blk00000003/blk00000445/blk00000446 ( + .G(\blk00000003/blk00000445/sig00000e82 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000458/blk0000046a ( + .I0(\blk00000003/sig0000068b ), + .I1(ce), + .O(\blk00000003/blk00000458/sig00000eaa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000458/blk00000469 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk00000458/sig00000ea1 ), + .A3(\blk00000003/blk00000458/sig00000ea1 ), + .CE(\blk00000003/blk00000458/sig00000eaa ), + .CLK(clk), + .D(\blk00000003/sig0000076d ), + .Q(\blk00000003/blk00000458/sig00000ea9 ), + .Q15(\NLW_blk00000003/blk00000458/blk00000469_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000458/blk00000468 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk00000458/sig00000ea1 ), + .A3(\blk00000003/blk00000458/sig00000ea1 ), + .CE(\blk00000003/blk00000458/sig00000eaa ), + .CLK(clk), + .D(\blk00000003/sig0000076e ), + .Q(\blk00000003/blk00000458/sig00000ea8 ), + .Q15(\NLW_blk00000003/blk00000458/blk00000468_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000458/blk00000467 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk00000458/sig00000ea1 ), + .A3(\blk00000003/blk00000458/sig00000ea1 ), + .CE(\blk00000003/blk00000458/sig00000eaa ), + .CLK(clk), + .D(\blk00000003/sig0000076f ), + .Q(\blk00000003/blk00000458/sig00000ea7 ), + .Q15(\NLW_blk00000003/blk00000458/blk00000467_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000458/blk00000466 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk00000458/sig00000ea1 ), + .A3(\blk00000003/blk00000458/sig00000ea1 ), + .CE(\blk00000003/blk00000458/sig00000eaa ), + .CLK(clk), + .D(\blk00000003/sig00000770 ), + .Q(\blk00000003/blk00000458/sig00000ea6 ), + .Q15(\NLW_blk00000003/blk00000458/blk00000466_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000458/blk00000465 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk00000458/sig00000ea1 ), + .A3(\blk00000003/blk00000458/sig00000ea1 ), + .CE(\blk00000003/blk00000458/sig00000eaa ), + .CLK(clk), + .D(\blk00000003/sig00000771 ), + .Q(\blk00000003/blk00000458/sig00000ea5 ), + .Q15(\NLW_blk00000003/blk00000458/blk00000465_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000458/blk00000464 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk00000458/sig00000ea1 ), + .A3(\blk00000003/blk00000458/sig00000ea1 ), + .CE(\blk00000003/blk00000458/sig00000eaa ), + .CLK(clk), + .D(\blk00000003/sig00000772 ), + .Q(\blk00000003/blk00000458/sig00000ea4 ), + .Q15(\NLW_blk00000003/blk00000458/blk00000464_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000458/blk00000463 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk00000458/sig00000ea1 ), + .A3(\blk00000003/blk00000458/sig00000ea1 ), + .CE(\blk00000003/blk00000458/sig00000eaa ), + .CLK(clk), + .D(\blk00000003/sig00000773 ), + .Q(\blk00000003/blk00000458/sig00000ea3 ), + .Q15(\NLW_blk00000003/blk00000458/blk00000463_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000458/blk00000462 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk00000458/sig00000ea1 ), + .A3(\blk00000003/blk00000458/sig00000ea1 ), + .CE(\blk00000003/blk00000458/sig00000eaa ), + .CLK(clk), + .D(\blk00000003/sig00000774 ), + .Q(\blk00000003/blk00000458/sig00000ea2 ), + .Q15(\NLW_blk00000003/blk00000458/blk00000462_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000458/blk00000461 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000458/sig00000ea9 ), + .Q(\blk00000003/sig0000039b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000458/blk00000460 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000458/sig00000ea8 ), + .Q(\blk00000003/sig0000039c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000458/blk0000045f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000458/sig00000ea7 ), + .Q(\blk00000003/sig0000039d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000458/blk0000045e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000458/sig00000ea6 ), + .Q(\blk00000003/sig0000039e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000458/blk0000045d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000458/sig00000ea5 ), + .Q(\blk00000003/sig0000039f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000458/blk0000045c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000458/sig00000ea4 ), + .Q(\blk00000003/sig000003a0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000458/blk0000045b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000458/sig00000ea3 ), + .Q(\blk00000003/sig000003a1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000458/blk0000045a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000458/sig00000ea2 ), + .Q(\blk00000003/sig000003a2 ) + ); + GND \blk00000003/blk00000458/blk00000459 ( + .G(\blk00000003/blk00000458/sig00000ea1 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000046b/blk0000047d ( + .I0(\blk00000003/sig0000068c ), + .I1(ce), + .O(\blk00000003/blk0000046b/sig00000ec9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000046b/blk0000047c ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000046b/sig00000ec0 ), + .A3(\blk00000003/blk0000046b/sig00000ec0 ), + .CE(\blk00000003/blk0000046b/sig00000ec9 ), + .CLK(clk), + .D(\blk00000003/sig00000775 ), + .Q(\blk00000003/blk0000046b/sig00000ec8 ), + .Q15(\NLW_blk00000003/blk0000046b/blk0000047c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000046b/blk0000047b ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000046b/sig00000ec0 ), + .A3(\blk00000003/blk0000046b/sig00000ec0 ), + .CE(\blk00000003/blk0000046b/sig00000ec9 ), + .CLK(clk), + .D(\blk00000003/sig00000776 ), + .Q(\blk00000003/blk0000046b/sig00000ec7 ), + .Q15(\NLW_blk00000003/blk0000046b/blk0000047b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000046b/blk0000047a ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000046b/sig00000ec0 ), + .A3(\blk00000003/blk0000046b/sig00000ec0 ), + .CE(\blk00000003/blk0000046b/sig00000ec9 ), + .CLK(clk), + .D(\blk00000003/sig00000777 ), + .Q(\blk00000003/blk0000046b/sig00000ec6 ), + .Q15(\NLW_blk00000003/blk0000046b/blk0000047a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000046b/blk00000479 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000046b/sig00000ec0 ), + .A3(\blk00000003/blk0000046b/sig00000ec0 ), + .CE(\blk00000003/blk0000046b/sig00000ec9 ), + .CLK(clk), + .D(\blk00000003/sig00000778 ), + .Q(\blk00000003/blk0000046b/sig00000ec5 ), + .Q15(\NLW_blk00000003/blk0000046b/blk00000479_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000046b/blk00000478 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000046b/sig00000ec0 ), + .A3(\blk00000003/blk0000046b/sig00000ec0 ), + .CE(\blk00000003/blk0000046b/sig00000ec9 ), + .CLK(clk), + .D(\blk00000003/sig00000779 ), + .Q(\blk00000003/blk0000046b/sig00000ec4 ), + .Q15(\NLW_blk00000003/blk0000046b/blk00000478_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000046b/blk00000477 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000046b/sig00000ec0 ), + .A3(\blk00000003/blk0000046b/sig00000ec0 ), + .CE(\blk00000003/blk0000046b/sig00000ec9 ), + .CLK(clk), + .D(\blk00000003/sig0000077a ), + .Q(\blk00000003/blk0000046b/sig00000ec3 ), + .Q15(\NLW_blk00000003/blk0000046b/blk00000477_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000046b/blk00000476 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000046b/sig00000ec0 ), + .A3(\blk00000003/blk0000046b/sig00000ec0 ), + .CE(\blk00000003/blk0000046b/sig00000ec9 ), + .CLK(clk), + .D(\blk00000003/sig0000077b ), + .Q(\blk00000003/blk0000046b/sig00000ec2 ), + .Q15(\NLW_blk00000003/blk0000046b/blk00000476_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000046b/blk00000475 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000046b/sig00000ec0 ), + .A3(\blk00000003/blk0000046b/sig00000ec0 ), + .CE(\blk00000003/blk0000046b/sig00000ec9 ), + .CLK(clk), + .D(\blk00000003/sig0000077c ), + .Q(\blk00000003/blk0000046b/sig00000ec1 ), + .Q15(\NLW_blk00000003/blk0000046b/blk00000475_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046b/blk00000474 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000046b/sig00000ec8 ), + .Q(\blk00000003/sig000003f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046b/blk00000473 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000046b/sig00000ec7 ), + .Q(\blk00000003/sig000003f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046b/blk00000472 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000046b/sig00000ec6 ), + .Q(\blk00000003/sig000003f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046b/blk00000471 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000046b/sig00000ec5 ), + .Q(\blk00000003/sig000003f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046b/blk00000470 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000046b/sig00000ec4 ), + .Q(\blk00000003/sig000003f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046b/blk0000046f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000046b/sig00000ec3 ), + .Q(\blk00000003/sig000003fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046b/blk0000046e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000046b/sig00000ec2 ), + .Q(\blk00000003/sig000003fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046b/blk0000046d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000046b/sig00000ec1 ), + .Q(\blk00000003/sig000003fc ) + ); + GND \blk00000003/blk0000046b/blk0000046c ( + .G(\blk00000003/blk0000046b/sig00000ec0 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000047e/blk00000490 ( + .I0(\blk00000003/sig0000068b ), + .I1(ce), + .O(\blk00000003/blk0000047e/sig00000ee8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000047e/blk0000048f ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000047e/sig00000edf ), + .A3(\blk00000003/blk0000047e/sig00000edf ), + .CE(\blk00000003/blk0000047e/sig00000ee8 ), + .CLK(clk), + .D(\blk00000003/sig0000077d ), + .Q(\blk00000003/blk0000047e/sig00000ee7 ), + .Q15(\NLW_blk00000003/blk0000047e/blk0000048f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000047e/blk0000048e ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000047e/sig00000edf ), + .A3(\blk00000003/blk0000047e/sig00000edf ), + .CE(\blk00000003/blk0000047e/sig00000ee8 ), + .CLK(clk), + .D(\blk00000003/sig0000077e ), + .Q(\blk00000003/blk0000047e/sig00000ee6 ), + .Q15(\NLW_blk00000003/blk0000047e/blk0000048e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000047e/blk0000048d ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000047e/sig00000edf ), + .A3(\blk00000003/blk0000047e/sig00000edf ), + .CE(\blk00000003/blk0000047e/sig00000ee8 ), + .CLK(clk), + .D(\blk00000003/sig0000077f ), + .Q(\blk00000003/blk0000047e/sig00000ee5 ), + .Q15(\NLW_blk00000003/blk0000047e/blk0000048d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000047e/blk0000048c ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000047e/sig00000edf ), + .A3(\blk00000003/blk0000047e/sig00000edf ), + .CE(\blk00000003/blk0000047e/sig00000ee8 ), + .CLK(clk), + .D(\blk00000003/sig00000780 ), + .Q(\blk00000003/blk0000047e/sig00000ee4 ), + .Q15(\NLW_blk00000003/blk0000047e/blk0000048c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000047e/blk0000048b ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000047e/sig00000edf ), + .A3(\blk00000003/blk0000047e/sig00000edf ), + .CE(\blk00000003/blk0000047e/sig00000ee8 ), + .CLK(clk), + .D(\blk00000003/sig00000781 ), + .Q(\blk00000003/blk0000047e/sig00000ee3 ), + .Q15(\NLW_blk00000003/blk0000047e/blk0000048b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000047e/blk0000048a ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000047e/sig00000edf ), + .A3(\blk00000003/blk0000047e/sig00000edf ), + .CE(\blk00000003/blk0000047e/sig00000ee8 ), + .CLK(clk), + .D(\blk00000003/sig00000782 ), + .Q(\blk00000003/blk0000047e/sig00000ee2 ), + .Q15(\NLW_blk00000003/blk0000047e/blk0000048a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000047e/blk00000489 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000047e/sig00000edf ), + .A3(\blk00000003/blk0000047e/sig00000edf ), + .CE(\blk00000003/blk0000047e/sig00000ee8 ), + .CLK(clk), + .D(\blk00000003/sig00000783 ), + .Q(\blk00000003/blk0000047e/sig00000ee1 ), + .Q15(\NLW_blk00000003/blk0000047e/blk00000489_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000047e/blk00000488 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000047e/sig00000edf ), + .A3(\blk00000003/blk0000047e/sig00000edf ), + .CE(\blk00000003/blk0000047e/sig00000ee8 ), + .CLK(clk), + .D(\blk00000003/sig00000784 ), + .Q(\blk00000003/blk0000047e/sig00000ee0 ), + .Q15(\NLW_blk00000003/blk0000047e/blk00000488_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e/blk00000487 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000047e/sig00000ee7 ), + .Q(\blk00000003/sig000003ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e/blk00000486 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000047e/sig00000ee6 ), + .Q(\blk00000003/sig000003ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e/blk00000485 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000047e/sig00000ee5 ), + .Q(\blk00000003/sig000003ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e/blk00000484 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000047e/sig00000ee4 ), + .Q(\blk00000003/sig000003f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e/blk00000483 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000047e/sig00000ee3 ), + .Q(\blk00000003/sig000003f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e/blk00000482 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000047e/sig00000ee2 ), + .Q(\blk00000003/sig000003f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e/blk00000481 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000047e/sig00000ee1 ), + .Q(\blk00000003/sig000003f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e/blk00000480 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000047e/sig00000ee0 ), + .Q(\blk00000003/sig000003f4 ) + ); + GND \blk00000003/blk0000047e/blk0000047f ( + .G(\blk00000003/blk0000047e/sig00000edf ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000004e1/blk00000507 ( + .I0(\blk00000003/sig00000305 ), + .I1(ce), + .O(\blk00000003/blk000004e1/sig00000f25 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e1/blk00000506 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig0000070d ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk00000506_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f24 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk00000505 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig0000070e ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk00000505_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f23 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk00000504 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig0000070f ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk00000504_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f22 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk00000503 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000710 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk00000503_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f21 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk00000502 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000711 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk00000502_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f20 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk00000501 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000712 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk00000501_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f1f ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk00000500 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000714 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk00000500_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f1d ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004ff ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000715 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004ff_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f1c ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004fe ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000713 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004fe_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f1e ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004fd ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000716 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004fd_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f1b ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004fc ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000717 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004fc_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f1a ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004fb ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000718 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004fb_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f19 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004fa ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000719 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004fa_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f18 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004f9 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig0000071a ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004f9_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f17 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004f8 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig0000071b ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004f8_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f16 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004f7 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig0000071d ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004f7_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f14 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004f6 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig0000071e ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004f6_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f13 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004f5 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig0000071c ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004f5_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f15 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f24 ), + .Q(\blk00000003/sig000001a8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f23 ), + .Q(\blk00000003/sig000001a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f22 ), + .Q(\blk00000003/sig000001aa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f21 ), + .Q(\blk00000003/sig000001ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f20 ), + .Q(\blk00000003/sig000001ac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f1f ), + .Q(\blk00000003/sig000001ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f1e ), + .Q(\blk00000003/sig000001ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f1d ), + .Q(\blk00000003/sig000001af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f1c ), + .Q(\blk00000003/sig000001b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f1b ), + .Q(\blk00000003/sig000001b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f1a ), + .Q(\blk00000003/sig000001b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f19 ), + .Q(\blk00000003/sig000001b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f18 ), + .Q(\blk00000003/sig000001b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f17 ), + .Q(\blk00000003/sig000001b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f16 ), + .Q(\blk00000003/sig000001b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f15 ), + .Q(\blk00000003/sig000001b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f14 ), + .Q(\blk00000003/sig000001b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f13 ), + .Q(\blk00000003/sig000001b9 ) + ); + GND \blk00000003/blk000004e1/blk000004e2 ( + .G(\blk00000003/blk000004e1/sig00000f12 ) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2.veo b/fpga/usrp3/top/b200/coregen_dsp/hbdec2.veo new file mode 100644 index 000000000..ce561daa2 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2.veo @@ -0,0 +1,79 @@ +/******************************************************************************* +* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. * +* * +* This file contains confidential and proprietary information * +* of Xilinx, Inc. and is protected under U.S. and * +* international copyright and other intellectual property * +* laws. * +* * +* DISCLAIMER * +* This disclaimer is not a license and does not grant any * +* rights to the materials distributed herewith. Except as * +* otherwise provided in a valid license issued to you by * +* Xilinx, and to the maximum extent permitted by applicable * +* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND * +* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES * +* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING * +* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- * +* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and * +* (2) Xilinx shall not be liable (whether in contract or tort, * +* including negligence, or under any other theory of * +* liability) for any loss or damage of any kind or nature * +* related to, arising under or in connection with these * +* materials, including for any direct, or any indirect, * +* special, incidental, or consequential loss or damage * +* (including loss of data, profits, goodwill, or any type of * +* loss or damage suffered as a result of any action brought * +* by a third party) even if such damage or loss was * +* reasonably foreseeable or Xilinx had been advised of the * +* possibility of the same. * +* * +* CRITICAL APPLICATIONS * +* Xilinx products are not designed or intended to be fail- * +* safe, or for use in any application requiring fail-safe * +* performance, such as life-support or safety devices or * +* systems, Class III medical devices, nuclear facilities, * +* applications related to the deployment of airbags, or any * +* other applications that could lead to death, personal * +* injury, or severe property or environmental damage * +* (individually and collectively, "Critical * +* Applications"). Customer assumes the sole risk and * +* liability of any use of Xilinx products in Critical * +* Applications, subject only to applicable laws and * +* regulations governing limitations on product liability. * +* * +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS * +* PART OF THIS FILE AT ALL TIMES. * +*******************************************************************************/ + +// Generated from component ID: xilinx.com:ip:fir_compiler:5.0 + + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +hbdec2 YourInstanceName ( + .sclr(sclr), // input sclr + .clk(clk), // input clk + .ce(ce), // input ce + .nd(nd), // input nd + .coef_ld(coef_ld), // input coef_ld + .coef_we(coef_we), // input coef_we + .coef_din(coef_din), // input [17 : 0] coef_din + .rfd(rfd), // output rfd + .rdy(rdy), // output rdy + .data_valid(data_valid), // output data_valid + .din_1(din_1), // input [23 : 0] din_1 + .din_2(din_2), // input [23 : 0] din_2 + .dout_1(dout_1), // output [46 : 0] dout_1 + .dout_2(dout_2)); // output [46 : 0] dout_2 + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file hbdec2.v when simulating +// the core, hbdec2. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2.xco b/fpga/usrp3/top/b200/coregen_dsp/hbdec2.xco new file mode 100644 index 000000000..1a4ba91f8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2.xco @@ -0,0 +1,102 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Fri Jan 9 20:45:11 2015 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fir_compiler:5.0 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx150t +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT FIR_Compiler family Xilinx,_Inc. 5.0 +# END Select +# BEGIN Parameters +CSET allow_rounding_approximation=false +CSET bestprecision=false +CSET chan_in_adv=0 +CSET clock_frequency=64 +CSET coefficient_buffer_type=Automatic +CSET coefficient_file=./hb47.coe +CSET coefficient_fractional_bits=0 +CSET coefficient_reload=true +CSET coefficient_sets=1 +CSET coefficient_sign=Signed +CSET coefficient_structure=Half_Band +CSET coefficient_width=18 +CSET coefficientsource=COE_File +CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 +CSET columnconfig=4 +CSET component_name=hbdec2 +CSET data_buffer_type=Automatic +CSET data_fractional_bits=0 +CSET data_sign=Signed +CSET data_width=24 +CSET decimation_rate=2 +CSET displayreloadorder=false +CSET filter_architecture=Systolic_Multiply_Accumulate +CSET filter_selection=1 +CSET filter_type=Decimation +CSET gui_behaviour=Coregen +CSET hardwareoversamplingrate=1 +CSET has_ce=true +CSET has_data_valid=true +CSET has_nd=true +CSET has_sclr=true +CSET input_buffer_type=Automatic +CSET inter_column_pipe_length=4 +CSET interpolation_rate=1 +CSET multi_column_support=Disabled +CSET number_channels=1 +CSET number_paths=2 +CSET optimization_goal=Area +CSET output_buffer_type=Automatic +CSET output_rounding_mode=Full_Precision +CSET output_width=47 +CSET passband_max=0.5 +CSET passband_min=0.0 +CSET preference_for_other_storage=Automatic +CSET quantization=Integer_Coefficients +CSET rate_change_type=Integer +CSET ratespecification=Frequency_Specification +CSET registered_output=true +CSET sample_frequency=32 +CSET sampleperiod=1 +CSET sclr_deterministic=true +CSET stopband_max=1.0 +CSET stopband_min=0.5 +CSET usechan_in_adv=false +CSET zero_pack_factor=1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-12-18T05:23:34Z +# END Extra information +GENERATE +# CRC: 80021ddf diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2COEFF_auto0_0.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec2COEFF_auto0_0.mif new file mode 100644 index 000000000..079623297 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2COEFF_auto0_0.mif @@ -0,0 +1,9 @@ +111111111111000010 +000000000011000010 +111111111001001000 +000000001101010111 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2COEFF_auto0_1.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec2COEFF_auto0_1.mif new file mode 100644 index 000000000..d4a0b357e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2COEFF_auto0_1.mif @@ -0,0 +1,9 @@ +111111101000011111 +000000100110101110 +111111000011000100 +000001011101100110 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2COEFF_auto0_2.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec2COEFF_auto0_2.mif new file mode 100644 index 000000000..6d9d6044f --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2COEFF_auto0_2.mif @@ -0,0 +1,9 @@ +111101110000011101 +000011100100101000 +111001100001011000 +010100010001000001 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2COEFF_auto_HALFBAND_CENTRE0.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec2COEFF_auto_HALFBAND_CENTRE0.mif new file mode 100644 index 000000000..ca072e0fc --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2COEFF_auto_HALFBAND_CENTRE0.mif @@ -0,0 +1,3 @@ +011111111111111111 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2_flist.txt b/fpga/usrp3/top/b200/coregen_dsp/hbdec2_flist.txt new file mode 100644 index 000000000..d0a6a5443 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2_flist.txt @@ -0,0 +1,19 @@ +# Output products list for +hbdec2.asy +hbdec2.gise +hbdec2.mif +hbdec2.ngc +hbdec2.v +hbdec2.veo +hbdec2.xco +hbdec2.xise +hbdec2COEFF_auto0_0.mif +hbdec2COEFF_auto0_1.mif +hbdec2COEFF_auto0_2.mif +hbdec2COEFF_auto_HALFBAND_CENTRE0.mif +hbdec2_flist.txt +hbdec2_readme.txt +hbdec2_reload_addrfilt_decode_rom.mif +hbdec2_reload_order.txt +hbdec2_xmdf.tcl +hbdec2filt_decode_rom.mif diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2_readme.txt b/fpga/usrp3/top/b200/coregen_dsp/hbdec2_readme.txt new file mode 100644 index 000000000..bcda9c01c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2_readme.txt @@ -0,0 +1,75 @@ +The following files were generated for 'hbdec2' in directory +/disk2/ianb/ettus/fpgadev2/fpgadev/usrp3/top/b200/coregen_dsp/ + +Model Parameter Resolution: + Resolves generated model parameter values on the component instance. + + * hbdec2.mif + * hbdec2_reload_order.txt + +ISE file generator: + Add description here... + + * hbdec2_flist.txt + +Opens the IP Customization GUI: + Allows the user to customize or recustomize the IP instance. + + * hbdec2.mif + * hbdec2_reload_order.txt + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * hbdec2.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * hbdec2.ngc + * hbdec2.v + * hbdec2.veo + * hbdec2COEFF_auto0_0.mif + * hbdec2COEFF_auto0_1.mif + * hbdec2COEFF_auto0_2.mif + * hbdec2COEFF_auto_HALFBAND_CENTRE0.mif + * hbdec2_reload_addrfilt_decode_rom.mif + * hbdec2filt_decode_rom.mif + +Creates an HDL instantiation template: + Creates an HDL instantiation template for the IP. + + * hbdec2.veo + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * hbdec2.asy + * hbdec2.mif + * hbdec2_reload_order.txt + +Generate ISE metadata: + Create a metadata file for use when including this core in ISE designs + + * hbdec2_xmdf.tcl + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * hbdec2.gise + * hbdec2.xise + +Deliver Readme: + Readme file for the IP. + + * hbdec2_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * hbdec2_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2_reload_addrfilt_decode_rom.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec2_reload_addrfilt_decode_rom.mif new file mode 100644 index 000000000..92e61d005 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2_reload_addrfilt_decode_rom.mif @@ -0,0 +1,17 @@ +000 +100 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2_reload_order.txt b/fpga/usrp3/top/b200/coregen_dsp/hbdec2_reload_order.txt new file mode 100644 index 000000000..071b84e5b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2_reload_order.txt @@ -0,0 +1,25 @@ +Reload index 0 = Index 16 +Reload index 1 = Index 18 +Reload index 2 = Index 20 +Reload index 3 = Index 22 +Reload index 4 = Index 8 +Reload index 5 = Index 10 +Reload index 6 = Index 12 +Reload index 7 = Index 14 +Reload index 8 = Index 0 +Reload index 9 = Index 2 +Reload index 10 = Index 4 +Reload index 11 = Index 6 +Reload index 12 = Index 23 +Reload index 13 = Index 0 +Reload index 14 = Index 0 +Reload index 15 = Index 0 +Reload index 16 = Index 0 +Reload index 17 = Index 0 +Reload index 18 = Index 0 +Reload index 19 = Index 0 +Reload index 20 = Index 0 +Reload index 21 = Index 0 +Reload index 22 = Index 0 +Reload index 23 = Index 0 + diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2_xmdf.tcl b/fpga/usrp3/top/b200/coregen_dsp/hbdec2_xmdf.tcl new file mode 100644 index 000000000..efebbe070 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2_xmdf.tcl @@ -0,0 +1,99 @@ +# The package naming convention is _xmdf +package provide hbdec2_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::hbdec2_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::hbdec2_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name hbdec2 +} +# ::hbdec2_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::hbdec2_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto0_0.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto0_1.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto0_2.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto_HALFBAND_CENTRE0.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2_reload_addrfilt_decode_rom.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2_reload_order.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type text +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2filt_decode_rom.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module hbdec2 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2filt_decode_rom.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec2filt_decode_rom.mif new file mode 100644 index 000000000..92e61d005 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2filt_decode_rom.mif @@ -0,0 +1,17 @@ +000 +100 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 diff --git a/fpga/usrp3/top/b200/gpio.ucf b/fpga/usrp3/top/b200/gpio.ucf new file mode 100644 index 000000000..1bccafe0d --- /dev/null +++ b/fpga/usrp3/top/b200/gpio.ucf @@ -0,0 +1,12 @@ + + +## GPIO bus - These pins are N/C on the LX75 +NET "fp_gpio<0>" LOC = "F8" | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "fp_gpio<1>" LOC = "E8" | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "fp_gpio<2>" LOC = "F9" | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "fp_gpio<3>" LOC = "G8" | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "fp_gpio<4>" LOC = "H10" | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "fp_gpio<5>" LOC = "G9" | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "fp_gpio<6>" LOC = "F10" | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "fp_gpio<7>" LOC = "E10" | IOSTANDARD = LVCMOS33 | PULLUP ; + diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/cache/b200_ngc_d1c0f267.edif b/fpga/usrp3/top/b200/planahead/planahead.data/cache/b200_ngc_d1c0f267.edif new file mode 100644 index 000000000..897eebbf3 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/cache/b200_ngc_d1c0f267.edif @@ -0,0 +1,59025 @@ +(edif b200 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2013 1 29 17 25 52) + (program "Xilinx ngc2edif" (version "P.49d")) + (author "Xilinx. Inc ") + (comment "This EDIF netlist is to be used within supported synthesis tools") + (comment "for determining resource/timing estimates of the design component") + (comment "represented by this netlist.") + (comment "Command line: -mdp2sp -w -secure b200.ngc b200.edif "))) + (external UNISIMS + (edifLevel 0) + (technology (numberDefinition)) + (cell GND + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port G + (direction OUTPUT) + ) + ) + ) + ) + (cell VCC + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port P + (direction OUTPUT) + ) + ) + ) + ) + (cell FDP + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port PRE + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell IBUFG + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell ODDR2 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT) + ) + (port D1 + (direction INPUT) + ) + (port C0 + (direction INPUT) + ) + (port C1 + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port R + (direction INPUT) + ) + (port S + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell BUFG + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port O + (direction OUTPUT) + ) + (port I + (direction INPUT) + ) + ) + ) + ) + (cell DCM_SP + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CLK2X180 + (direction OUTPUT) + ) + (port PSCLK + (direction INPUT) + ) + (port CLK2X + (direction OUTPUT) + ) + (port CLKFX + (direction OUTPUT) + ) + (port CLK180 + (direction OUTPUT) + ) + (port CLK270 + (direction OUTPUT) + ) + (port RST + (direction INPUT) + ) + (port PSINCDEC + (direction INPUT) + ) + (port CLKIN + (direction INPUT) + ) + (port CLKFB + (direction INPUT) + ) + (port PSEN + (direction INPUT) + ) + (port CLK0 + (direction OUTPUT) + ) + (port CLKFX180 + (direction OUTPUT) + ) + (port CLKDV + (direction OUTPUT) + ) + (port PSDONE + (direction OUTPUT) + ) + (port CLK90 + (direction OUTPUT) + ) + (port LOCKED + (direction OUTPUT) + ) + (port DSSEN + (direction INPUT) + ) + (port (rename STATUS_7_ "STATUS<7>") + (direction OUTPUT) + (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename STATUS_6_ "STATUS<6>") + (direction OUTPUT) + (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename STATUS_5_ "STATUS<5>") + (direction OUTPUT) + (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename STATUS_4_ "STATUS<4>") + (direction OUTPUT) + (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename STATUS_3_ "STATUS<3>") + (direction OUTPUT) + (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename STATUS_2_ "STATUS<2>") + (direction OUTPUT) + (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename STATUS_1_ "STATUS<1>") + (direction OUTPUT) + (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename STATUS_0_ "STATUS<0>") + (direction OUTPUT) + (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 7) (owner "Xilinx")) + ) + ) + ) + ) + (cell IBUFGDS + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port IB + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell FDRE + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port R + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell FDR + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port R + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell FD + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell FDSE + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port S + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell SRLC32E + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CLK + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + (port Q31 + (direction OUTPUT) + ) + (port (array (rename A "A<4:0>") 5) + (direction INPUT)) + ) + ) + ) + (cell MUXCY + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT) + ) + (port DI + (direction INPUT) + ) + (port S + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT2 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT6 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port I4 + (direction INPUT) + ) + (port I5 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell XORCY + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT) + ) + (port LI + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell FDE + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT3 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT4 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT5 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port I4 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell IBUF + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell OBUF + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell FDS + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port S + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT1 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell MUXF7 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port S + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell INV + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell IOBUF + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port T + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + (port IO + (direction OUTPUT) + ) + ) + ) + ) + (cell RAMB8BWER + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port RSTBRST + (direction INPUT) + ) + (port ENBRDEN + (direction INPUT) + ) + (port REGCEA + (direction INPUT) + ) + (port ENAWREN + (direction INPUT) + ) + (port CLKAWRCLK + (direction INPUT) + ) + (port CLKBRDCLK + (direction INPUT) + ) + (port REGCEBREGCE + (direction INPUT) + ) + (port RSTA + (direction INPUT) + ) + (port (array (rename WEAWEL "WEAWEL<1:0>") 2) + (direction INPUT)) + (port (array (rename DOADO "DOADO<15:0>") 16) + (direction OUTPUT)) + (port (array (rename DOPADOP "DOPADOP<1:0>") 2) + (direction OUTPUT)) + (port (array (rename DOPBDOP "DOPBDOP<1:0>") 2) + (direction OUTPUT)) + (port (array (rename WEBWEU "WEBWEU<1:0>") 2) + (direction INPUT)) + (port (array (rename ADDRAWRADDR "ADDRAWRADDR<12:0>") 13) + (direction INPUT)) + (port (array (rename DIPBDIP "DIPBDIP<1:0>") 2) + (direction INPUT)) + (port (array (rename DIBDI "DIBDI<15:0>") 16) + (direction INPUT)) + (port (array (rename DIADI "DIADI<15:0>") 16) + (direction INPUT)) + (port (array (rename ADDRBRDADDR "ADDRBRDADDR<12:0>") 13) + (direction INPUT)) + (port (array (rename DOBDO "DOBDO<15:0>") 16) + (direction OUTPUT)) + (port (array (rename DIPADIP "DIPADIP<1:0>") 2) + (direction INPUT)) + ) + ) + ) + (cell RAMB16BWER + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port REGCEA + (direction INPUT) + ) + (port CLKA + (direction INPUT) + ) + (port ENB + (direction INPUT) + ) + (port RSTB + (direction INPUT) + ) + (port CLKB + (direction INPUT) + ) + (port REGCEB + (direction INPUT) + ) + (port RSTA + (direction INPUT) + ) + (port ENA + (direction INPUT) + ) + (port (array (rename DIPA "DIPA<3:0>") 4) + (direction INPUT)) + (port (array (rename WEA "WEA<3:0>") 4) + (direction INPUT)) + (port (array (rename DOA "DOA<31:0>") 32) + (direction OUTPUT)) + (port (array (rename ADDRA "ADDRA<13:0>") 14) + (direction INPUT)) + (port (array (rename ADDRB "ADDRB<13:0>") 14) + (direction INPUT)) + (port (array (rename DIB "DIB<31:0>") 32) + (direction INPUT)) + (port (array (rename DOPA "DOPA<3:0>") 4) + (direction OUTPUT)) + (port (array (rename DIPB "DIPB<3:0>") 4) + (direction INPUT)) + (port (array (rename DOPB "DOPB<3:0>") 4) + (direction OUTPUT)) + (port (array (rename DOB "DOB<31:0>") 32) + (direction OUTPUT)) + (port (array (rename WEB "WEB<3:0>") 4) + (direction INPUT)) + (port (array (rename DIA "DIA<31:0>") 32) + (direction INPUT)) + ) + ) + ) + ) + + (library b200_lib + (edifLevel 0) + (technology (numberDefinition)) + (cell fifo_4k_2clk + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port rst + (direction INPUT) + ) + (port wr_clk + (direction INPUT) + ) + (port rd_clk + (direction INPUT) + ) + (port wr_en + (direction INPUT) + ) + (port rd_en + (direction INPUT) + ) + (port full + (direction OUTPUT) + ) + (port empty + (direction OUTPUT) + ) + (port (array (rename din "din<71:0>") 72) + (direction INPUT)) + (port (array (rename dout "dout<71:0>") 72) + (direction OUTPUT)) + (port (array (rename rd_data_count "rd_data_count<9:0>") 10) + (direction OUTPUT)) + (port (array (rename wr_data_count "wr_data_count<9:0>") 10) + (direction OUTPUT)) + ) + ) + ) + (cell b200 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port cat_miso + (direction INPUT) + ) + (port fx3_ce + (direction INPUT) + ) + (port fx3_mosi + (direction INPUT) + ) + (port fx3_sclk + (direction INPUT) + ) + (port FPGA_RXD0 + (direction INPUT) + ) + (port FPGA_TXD0 + (direction INPUT) + ) + (port SCL_FPGA + (direction INPUT) + ) + (port SDA_FPGA + (direction INPUT) + ) + (port codec_data_clk_p + (direction INPUT) + ) + (port rx_frame_p + (direction INPUT) + ) + (port cat_clkout_fpga + (direction INPUT) + ) + (port codec_main_clk_p + (direction INPUT) + ) + (port codec_main_clk_n + (direction INPUT) + ) + (port GPIF_CTL4 + (direction INPUT) + ) + (port GPIF_CTL5 + (direction INPUT) + ) + (port GPIF_CTL6 + (direction INPUT) + ) + (port GPIF_CTL8 + (direction INPUT) + ) + (port GPIF_CTL9 + (direction INPUT) + ) + (port gps_lock + (direction INPUT) + ) + (port gps_rxd + (direction INPUT) + ) + (port gps_txd + (direction INPUT) + ) + (port gps_txd_nmea + (direction INPUT) + ) + (port pll_lock + (direction INPUT) + ) + (port FPGA_CFG_CS + (direction INPUT) + ) + (port AUX_PWR_ON + (direction INPUT) + ) + (port PPS_IN_EXT + (direction INPUT) + ) + (port PPS_IN_INT + (direction INPUT) + ) + (port pps_out + (direction INPUT) + ) + (port cat_ce + (direction OUTPUT) + ) + (port cat_mosi + (direction OUTPUT) + ) + (port cat_sclk + (direction OUTPUT) + ) + (port fx3_miso + (direction OUTPUT) + ) + (port pll_ce + (direction OUTPUT) + ) + (port pll_mosi + (direction OUTPUT) + ) + (port pll_sclk + (direction OUTPUT) + ) + (port codec_enable + (direction OUTPUT) + ) + (port codec_en_agc + (direction OUTPUT) + ) + (port codec_reset + (direction OUTPUT) + ) + (port codec_sync + (direction OUTPUT) + ) + (port codec_txrx + (direction OUTPUT) + ) + (port codec_fb_clk_p + (direction OUTPUT) + ) + (port tx_frame_p + (direction OUTPUT) + ) + (port IFCLK + (direction OUTPUT) + ) + (port FX3_EXTINT + (direction OUTPUT) + ) + (port GPIF_CTL0 + (direction OUTPUT) + ) + (port GPIF_CTL1 + (direction OUTPUT) + ) + (port GPIF_CTL2 + (direction OUTPUT) + ) + (port GPIF_CTL3 + (direction OUTPUT) + ) + (port GPIF_CTL7 + (direction OUTPUT) + ) + (port GPIF_CTL11 + (direction OUTPUT) + ) + (port GPIF_CTL12 + (direction OUTPUT) + ) + (port gps_out_enable + (direction OUTPUT) + ) + (port gps_ref_enable + (direction OUTPUT) + ) + (port LED_RX1 + (direction OUTPUT) + ) + (port LED_RX2 + (direction OUTPUT) + ) + (port LED_TXRX1_RX + (direction OUTPUT) + ) + (port LED_TXRX1_TX + (direction OUTPUT) + ) + (port LED_TXRX2_RX + (direction OUTPUT) + ) + (port LED_TXRX2_TX + (direction OUTPUT) + ) + (port ext_ref_enable + (direction OUTPUT) + ) + (port pps_fpga_out_enable + (direction OUTPUT) + ) + (port SFDX1_RX + (direction OUTPUT) + ) + (port SFDX1_TX + (direction OUTPUT) + ) + (port SFDX2_RX + (direction OUTPUT) + ) + (port SFDX2_TX + (direction OUTPUT) + ) + (port SRX1_RX + (direction OUTPUT) + ) + (port SRX1_TX + (direction OUTPUT) + ) + (port SRX2_RX + (direction OUTPUT) + ) + (port SRX2_TX + (direction OUTPUT) + ) + (port tx_bandsel_a + (direction OUTPUT) + ) + (port tx_bandsel_b + (direction OUTPUT) + ) + (port tx_enable1 + (direction OUTPUT) + ) + (port tx_enable2 + (direction OUTPUT) + ) + (port rx_bandsel_a + (direction OUTPUT) + ) + (port rx_bandsel_b + (direction OUTPUT) + ) + (port rx_bandsel_c + (direction OUTPUT) + ) + (port (array (rename codec_ctrl_out "codec_ctrl_out<7:0>") 8) + (direction INPUT)) + (port (array (rename rx_codec_d "rx_codec_d<11:0>") 12) + (direction INPUT)) + (port (array (rename codec_ctrl_in "codec_ctrl_in<3:0>") 4) + (direction OUTPUT)) + (port (array (rename tx_codec_d "tx_codec_d<11:0>") 12) + (direction OUTPUT)) + (port (array (rename debug "debug<31:0>") 32) + (direction OUTPUT)) + (port (array (rename debug_clk "debug_clk<1:0>") 2) + (direction OUTPUT)) + (port (array (rename GPIF_D "GPIF_D<31:0>") 32) + (direction INOUT)) + (designator "xc6slx75-3-fgg484") + (property TYPE (string "b200") (owner "Xilinx")) + (property BUS_INFO (string "8:INPUT:codec_ctrl_out<7:0>") (owner "Xilinx")) + (property BUS_INFO (string "12:INPUT:rx_codec_d<11:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:codec_ctrl_in<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "12:OUTPUT:tx_codec_d<11:0>") (owner "Xilinx")) + (property BUS_INFO (string "32:OUTPUT:debug<31:0>") (owner "Xilinx")) + (property BUS_INFO (string "2:OUTPUT:debug_clk<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "32:INOUT:GPIF_D<31:0>") (owner "Xilinx")) + (property SHREG_MIN_SIZE (string "2") (owner "Xilinx")) + (property X_CORE_INFO (string "fifo_generator_v9_3, Xilinx CORE Generator 14.4") (owner "Xilinx")) + (property CORE_GENERATION_INFO (string "b200_clk_gen,clk_wiz_v3_6,{component_name=b200_clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=3,clkin1_period=25.0,clkin2_period=25.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}") (owner "Xilinx")) + (property SHREG_EXTRACT_NGC (string "YES") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 0) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "b200_b200") (owner "Xilinx")) + ) + (contents + (instance XST_GND + (viewRef view_1 (cellRef GND (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance XST_VCC + (viewRef view_1 (cellRef VCC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename bus_sync_reset_out_renamed_0 "bus_sync/reset_out") + (viewRef view_1 (cellRef FDP (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename bus_sync_reset_int_renamed_1 "bus_sync/reset_int") + (viewRef view_1 (cellRef FDP (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename gpif_sync_reset_out_renamed_2 "gpif_sync/reset_out") + (viewRef view_1 (cellRef FDP (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename gpif_sync_reset_int_renamed_3 "gpif_sync/reset_int") + (viewRef view_1 (cellRef FDP (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance codec_data_clk_bufg + (viewRef view_1 (cellRef IBUFG (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property CAPACITANCE (string "DONT_CARE") (owner "Xilinx")) + (property IBUF_DELAY_VALUE (string "0") (owner "Xilinx")) + (property IBUF_LOW_PWR (string "TRUE") (owner "Xilinx")) + (property IOSTANDARD (string "DEFAULT") (owner "Xilinx")) + ) + (instance ODDR2_ifclk + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "NONE") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance ODDR2_ifclk_dbg + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "NONE") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename gen_clks_clkout3_buf "gen_clks/clkout3_buf") + (viewRef view_1 (cellRef BUFG (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename gen_clks_clkout2_buf "gen_clks/clkout2_buf") + (viewRef view_1 (cellRef BUFG (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename gen_clks_clkout1_buf "gen_clks/clkout1_buf") + (viewRef view_1 (cellRef BUFG (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename gen_clks_dcm_sp_inst "gen_clks/dcm_sp_inst") + (viewRef view_1 (cellRef DCM_SP (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "8:OUTPUT:STATUS<7:0>") (owner "Xilinx")) + (property CLKIN_DIVIDE_BY_2 (string "FALSE") (owner "Xilinx")) + (property CLKOUT_PHASE_SHIFT (string "NONE") (owner "Xilinx")) + (property CLK_FEEDBACK (string "1X") (owner "Xilinx")) + (property DESKEW_ADJUST (string "SYSTEM_SYNCHRONOUS") (owner "Xilinx")) + (property DFS_FREQUENCY_MODE (string "LOW") (owner "Xilinx")) + (property DLL_FREQUENCY_MODE (string "LOW") (owner "Xilinx")) + (property DSS_MODE (string "NONE") (owner "Xilinx")) + (property DUTY_CYCLE_CORRECTION (string "TRUE") (owner "Xilinx")) + (property FACTORY_JF (string "16'B1100000010000000") (owner "Xilinx")) + (property STARTUP_WAIT (string "FALSE") (owner "Xilinx")) + (property CLKFX_DIVIDE (integer 2) (owner "Xilinx")) + (property CLKFX_MULTIPLY (integer 5) (owner "Xilinx")) + (property PHASE_SHIFT (integer 0) (owner "Xilinx")) + (property CLKDV_DIVIDE (number (e 2 0)) (owner "Xilinx")) + (property CLKIN_PERIOD (string "25.000000") (owner "Xilinx")) + (property VERY_HIGH_FREQUENCY (string "FALSE") (owner "Xilinx")) + ) + (instance (rename gen_clks_clkin1_buf "gen_clks/clkin1_buf") + (viewRef view_1 (cellRef IBUFGDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property CAPACITANCE (string "DONT_CARE") (owner "Xilinx")) + (property DIFF_TERM (string "FALSE") (owner "Xilinx")) + (property IBUF_DELAY_VALUE (string "0") (owner "Xilinx")) + (property IBUF_LOW_PWR (string "TRUE") (owner "Xilinx")) + (property IOSTANDARD (string "DEFAULT") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_idle_cycles_2 "slave_fifo32/idle_cycles_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_idle_cycles_1 "slave_fifo32/idle_cycles_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_idle_cycles_0 "slave_fifo32/idle_cycles_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifoadr_1 "slave_fifo32/fifoadr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifoadr_0 "slave_fifo32/fifoadr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_state_FSM_FFd1_renamed_4 "slave_fifo32/state_FSM_FFd1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_state_FSM_FFd2_renamed_5 "slave_fifo32/state_FSM_FFd2") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_31 "slave_fifo32/debug2_31") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_29 "slave_fifo32/debug2_29") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_28 "slave_fifo32/debug2_28") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_27 "slave_fifo32/debug2_27") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_26 "slave_fifo32/debug2_26") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_23 "slave_fifo32/debug2_23") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_22 "slave_fifo32/debug2_22") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_21 "slave_fifo32/debug2_21") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_19 "slave_fifo32/debug2_19") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_18 "slave_fifo32/debug2_18") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_17 "slave_fifo32/debug2_17") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_16 "slave_fifo32/debug2_16") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_15 "slave_fifo32/debug2_15") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_14 "slave_fifo32/debug2_14") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_13 "slave_fifo32/debug2_13") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_12 "slave_fifo32/debug2_12") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_11 "slave_fifo32/debug2_11") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_10 "slave_fifo32/debug2_10") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_9 "slave_fifo32/debug2_9") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_8 "slave_fifo32/debug2_8") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_7 "slave_fifo32/debug2_7") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_6 "slave_fifo32/debug2_6") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_5 "slave_fifo32/debug2_5") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_4 "slave_fifo32/debug2_4") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_3 "slave_fifo32/debug2_3") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_2 "slave_fifo32/debug2_2") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_1 "slave_fifo32/debug2_1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_0 "slave_fifo32/debug2_0") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_31 "slave_fifo32/debug1_31") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_29 "slave_fifo32/debug1_29") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_28 "slave_fifo32/debug1_28") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_27 "slave_fifo32/debug1_27") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_26 "slave_fifo32/debug1_26") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_23 "slave_fifo32/debug1_23") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_22 "slave_fifo32/debug1_22") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_21 "slave_fifo32/debug1_21") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_19 "slave_fifo32/debug1_19") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_18 "slave_fifo32/debug1_18") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_15 "slave_fifo32/debug1_15") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_14 "slave_fifo32/debug1_14") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_13 "slave_fifo32/debug1_13") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_12 "slave_fifo32/debug1_12") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_11 "slave_fifo32/debug1_11") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_10 "slave_fifo32/debug1_10") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_9 "slave_fifo32/debug1_9") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_8 "slave_fifo32/debug1_8") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_7 "slave_fifo32/debug1_7") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_6 "slave_fifo32/debug1_6") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_5 "slave_fifo32/debug1_5") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_4 "slave_fifo32/debug1_4") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_3 "slave_fifo32/debug1_3") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_2 "slave_fifo32/debug1_2") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_1 "slave_fifo32/debug1_1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_0 "slave_fifo32/debug1_0") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_31 "slave_fifo32/gpif_data_in_31") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_30 "slave_fifo32/gpif_data_in_30") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_29 "slave_fifo32/gpif_data_in_29") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_28 "slave_fifo32/gpif_data_in_28") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_27 "slave_fifo32/gpif_data_in_27") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_26 "slave_fifo32/gpif_data_in_26") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_25 "slave_fifo32/gpif_data_in_25") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_24 "slave_fifo32/gpif_data_in_24") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_23 "slave_fifo32/gpif_data_in_23") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_22 "slave_fifo32/gpif_data_in_22") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_21 "slave_fifo32/gpif_data_in_21") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_20 "slave_fifo32/gpif_data_in_20") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_19 "slave_fifo32/gpif_data_in_19") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_18 "slave_fifo32/gpif_data_in_18") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_17 "slave_fifo32/gpif_data_in_17") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_16 "slave_fifo32/gpif_data_in_16") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_15 "slave_fifo32/gpif_data_in_15") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_14 "slave_fifo32/gpif_data_in_14") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_13 "slave_fifo32/gpif_data_in_13") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_12 "slave_fifo32/gpif_data_in_12") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_11 "slave_fifo32/gpif_data_in_11") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_10 "slave_fifo32/gpif_data_in_10") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_9 "slave_fifo32/gpif_data_in_9") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_8 "slave_fifo32/gpif_data_in_8") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_7 "slave_fifo32/gpif_data_in_7") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_6 "slave_fifo32/gpif_data_in_6") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_5 "slave_fifo32/gpif_data_in_5") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_4 "slave_fifo32/gpif_data_in_4") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_3 "slave_fifo32/gpif_data_in_3") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_2 "slave_fifo32/gpif_data_in_2") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_1 "slave_fifo32/gpif_data_in_1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_0 "slave_fifo32/gpif_data_in_0") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_pktend_renamed_6 "slave_fifo32/pktend") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_slwr_renamed_7 "slave_fifo32/slwr") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_slrd3_renamed_8 "slave_fifo32/slrd3") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_slrd2_renamed_9 "slave_fifo32/slrd2") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_slrd1_renamed_10 "slave_fifo32/slrd1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_EP_WMARK1_renamed_11 "slave_fifo32/EP_WMARK1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_EP_READY1_renamed_12 "slave_fifo32/EP_READY1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_EP_READY_renamed_13 "slave_fifo32/EP_READY") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_write_ready_go_renamed_14 "slave_fifo32/write_ready_go") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_read_ready_go_renamed_15 "slave_fifo32/read_ready_go") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_EP_WMARK_renamed_16 "slave_fifo32/EP_WMARK") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename catgen_oddr2_clk "catgen/oddr2_clk") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_oddr2_frame "catgen/oddr2_frame") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_gen_pins_11__oddr2 "catgen/gen_pins[11].oddr2") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_gen_pins_10__oddr2 "catgen/gen_pins[10].oddr2") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_gen_pins_9__oddr2 "catgen/gen_pins[9].oddr2") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_gen_pins_8__oddr2 "catgen/gen_pins[8].oddr2") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_gen_pins_7__oddr2 "catgen/gen_pins[7].oddr2") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_gen_pins_6__oddr2 "catgen/gen_pins[6].oddr2") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_gen_pins_5__oddr2 "catgen/gen_pins[5].oddr2") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_gen_pins_4__oddr2 "catgen/gen_pins[4].oddr2") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_gen_pins_3__oddr2 "catgen/gen_pins[3].oddr2") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_gen_pins_2__oddr2 "catgen/gen_pins[2].oddr2") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_gen_pins_1__oddr2 "catgen/gen_pins[1].oddr2") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_gen_pins_0__oddr2 "catgen/gen_pins[0].oddr2") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_64__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[64].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_63__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[63].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_62__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[62].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_61__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[61].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_60__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[60].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_59__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[59].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_58__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[58].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_57__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[57].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_56__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[56].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_55__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[55].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_54__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[54].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_53__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[53].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_52__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[52].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_51__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[51].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_50__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[50].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_49__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[49].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_48__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[48].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_47__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[47].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_46__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[46].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_45__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[45].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_44__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[44].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_43__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[43].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_42__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[42].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_41__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[41].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_40__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[40].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_39__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[39].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_38__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[38].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_37__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[37].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_36__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[36].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_35__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[35].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_34__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[34].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_33__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[33].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_32__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[32].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_31__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[31].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_30__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[30].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_29__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[29].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_28__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[28].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_27__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[27].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_26__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[26].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_25__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[25].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_24__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[24].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_23__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[23].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_22__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[22].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_21__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[21].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_20__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[20].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_19__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[19].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_18__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[18].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_17__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[17].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_16__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[16].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_15__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[15].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_14__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[14].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_13__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[13].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_12__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[12].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_11__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[11].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_10__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[10].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_9__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[9].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_8__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[8].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_7__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[7].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_6__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[6].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_5__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[5].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_4__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[4].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_3__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[3].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_2__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[2].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_1__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[1].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_0__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[0].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_4 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_3 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_2 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_1 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_0 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_64__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[64].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_63__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[63].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_62__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[62].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_61__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[61].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_60__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[60].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_59__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[59].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_58__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[58].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_57__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[57].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_56__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[56].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_55__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[55].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_54__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[54].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_53__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[53].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_52__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[52].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_51__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[51].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_50__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[50].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_49__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[49].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_48__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[48].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_47__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[47].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_46__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[46].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_45__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[45].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_44__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[44].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_43__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[43].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_42__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[42].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_41__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[41].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_40__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[40].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_39__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[39].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_38__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[38].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_37__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[37].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_36__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[36].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_35__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[35].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_34__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[34].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_33__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[33].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_32__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[32].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_31__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[31].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_30__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[30].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_29__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[29].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_28__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[28].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_27__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[27].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_26__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[26].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_25__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[25].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_24__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[24].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_23__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[23].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_22__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[22].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_21__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[21].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_20__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[20].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_19__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[19].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_18__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[18].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_17__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[17].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_16__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[16].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_15__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[15].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_14__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[14].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_13__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[13].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_12__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[12].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_11__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[11].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_10__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[10].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_9__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[9].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_8__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[8].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_7__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[7].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_6__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[6].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_5__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[5].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_4__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[4].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_3__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[3].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_2__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[2].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_1__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[1].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_0__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[0].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_4 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_3 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_2 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_1 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_0 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_6 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_5 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_4 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_3 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_2 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<4>") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<3>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<2>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<1>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<0>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_12__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_11__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_11__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_10__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_10__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_9__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_9__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_8__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_8__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_7__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_7__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_6__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_6__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_5__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_5__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_renamed_17 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_12 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_10 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_9 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_renamed_18 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_12 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_10 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_9 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_12__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_11__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_10__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_9__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_9__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_12__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_11__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_11__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_10__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_6 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_5 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_4 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_3 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_renamed_19 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_9 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_renamed_20 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_9__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_1 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_2 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_3 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_4 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_0__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[0].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_1__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[1].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_2__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[2].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_3__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[3].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_4__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[4].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_5__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[5].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_6__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[6].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_7__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[7].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_8__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[8].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_9__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[9].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_10__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[10].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_11__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[11].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_12__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[12].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_13__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[13].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_14__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[14].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_15__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[15].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_16__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[16].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_17__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[17].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_18__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[18].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_19__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[19].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_20__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[20].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_21__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[21].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_22__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[22].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_23__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[23].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_24__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[24].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_25__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[25].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_26__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[26].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_27__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[27].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_28__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[28].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_29__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[29].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_30__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[30].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_31__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[31].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_32__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[32].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_33__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[33].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_34__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[34].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_35__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[35].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_36__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[36].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_37__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[37].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_38__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[38].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_39__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[39].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_40__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[40].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_41__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[41].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_42__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[42].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_43__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[43].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_44__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[44].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_45__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[45].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_46__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[46].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_47__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[47].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_48__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[48].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_49__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[49].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_50__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[50].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_51__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[51].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_52__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[52].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_53__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[53].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_54__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[54].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_55__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[55].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_56__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[56].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_57__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[57].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_58__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[58].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_59__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[59].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_60__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[60].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_61__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[61].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_62__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[62].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_63__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[63].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_64__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[64].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<15>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<14>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<14>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<13>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<13>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<12>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1_renamed_21 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_0 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_0") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_1 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_2 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_2") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_3 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_3") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_4 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_4") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_5 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_5") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_6 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_6") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_7 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_7") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_8 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_8") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_9 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_9") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_10 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_10") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_11 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_11") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_12 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_12") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_13 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_13") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_14 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_14") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_15 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_15") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_16 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_16") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_17 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_17") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_18 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_18") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_19 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_19") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_20 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_20") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_21 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_21") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_22 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_22") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_23 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_23") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_24 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_24") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_25 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_25") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_26 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_26") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_27 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_27") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_28 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_28") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_29 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_29") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_30 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_30") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_31 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_31") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_0") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_2 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_2") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_3 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_3") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_4 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_4") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_5 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_5") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_6 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_6") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_7 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_7") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_8 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_8") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_i_tready_renamed_22 "slave_fifo32/fifo64_to_gpmc32_tx/i_tready") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<0>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<1>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<2>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<3>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<4>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<5>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<6>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<7>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<8>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<9>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<10>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<11>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_12__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<12>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_12__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<0>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<1>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<2>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<3>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<4>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<5>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<6>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<7>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<8>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<9>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<10>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<11>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_12__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<12>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_12__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_10 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_10 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_12__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<0>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<1>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<2>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<3>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<4>") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_renamed_23 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_renamed_24 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_15 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_15") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_14 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_14") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_13 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_13") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_10 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_8 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_15__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<15>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_14__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<14>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_14__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<14>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_13__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<13>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_13__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<13>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_12__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_12__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<12>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_0__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[0].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_1__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[1].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_2__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[2].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_3__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[3].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_4__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[4].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_5__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[5].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_6__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[6].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_7__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[7].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_8__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[8].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_9__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[9].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_10__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[10].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_11__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[11].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_12__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[12].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_13__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[13].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_14__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[14].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_15__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[15].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_16__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[16].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_17__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[17].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_18__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[18].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_19__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[19].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_20__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[20].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_21__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[21].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_22__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[22].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_23__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[23].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_24__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[24].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_25__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[25].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_26__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[26].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_27__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[27].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_28__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[28].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_29__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[29].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_30__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[30].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_31__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[31].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[32].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_33__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[33].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_34__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[34].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[35].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_36__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[36].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[37].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_38__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[38].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_39__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[39].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_40__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[40].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_41__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[41].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_42__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[42].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_43__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[43].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_44__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[44].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_45__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[45].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_46__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[46].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_47__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[47].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_48__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[48].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_49__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[49].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_50__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[50].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_51__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[51].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_52__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[52].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[53].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_54__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[54].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_55__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[55].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_56__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[56].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_57__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[57].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_58__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[58].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_59__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[59].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_60__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[60].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_61__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[61].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[62].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[63].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[64].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<15>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<14>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<14>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<13>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<13>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<12>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_renamed_25 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_0") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_2") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_3") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_4") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_5") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_6") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_7") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_8") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_9 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_9") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_10 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_10") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_11") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_12 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_12") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_13 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_13") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_14 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_14") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_15 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_15") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_16 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_16") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_17 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_17") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_18 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_18") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_19 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_19") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_20 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_20") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_21 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_21") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_22 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_22") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_23 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_23") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_24 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_24") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_25 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_25") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_26 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_26") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_27 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_27") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_28 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_28") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_29 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_29") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_30 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_30") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_31 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_31") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_0") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_2") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_3") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_4") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_5") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_6") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_7") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_8") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_i_tready_renamed_26 "slave_fifo32/fifo64_to_gpmc32_ctrl/i_tready") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<0>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<1>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<2>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<3>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<4>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<5>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<6>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<7>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<8>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<9>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<0>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<1>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<2>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<3>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<4>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<5>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<6>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<7>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<8>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<9>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_9 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_renamed_27 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_renamed_28 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_15 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_15") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_14 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_14") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_13 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_13") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_12 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_10 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_9 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_15__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<15>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_14__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<14>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_14__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<14>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_13__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<13>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_13__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<13>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_12__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_12__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<12>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_11__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_11__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_10__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_10__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_becoming_full_cy_4__ "f1/Mcompar_becoming_full_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_becoming_full_lut_4__ "f1/Mcompar_becoming_full_lut<4>") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_becoming_full_cy_3__ "f1/Mcompar_becoming_full_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_becoming_full_lut_3__ "f1/Mcompar_becoming_full_lut<3>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_becoming_full_cy_2__ "f1/Mcompar_becoming_full_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_becoming_full_lut_2__ "f1/Mcompar_becoming_full_lut<2>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_becoming_full_cy_1__ "f1/Mcompar_becoming_full_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_becoming_full_lut_1__ "f1/Mcompar_becoming_full_lut<1>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_becoming_full_cy_0__ "f1/Mcompar_becoming_full_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_becoming_full_lut_0__ "f1/Mcompar_becoming_full_lut<0>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_12__ "f1/Mcount_rd_addr_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_11__ "f1/Mcount_rd_addr_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_cy_11__ "f1/Mcount_rd_addr_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_10__ "f1/Mcount_rd_addr_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_cy_10__ "f1/Mcount_rd_addr_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_9__ "f1/Mcount_rd_addr_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_cy_9__ "f1/Mcount_rd_addr_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_8__ "f1/Mcount_rd_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_cy_8__ "f1/Mcount_rd_addr_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_7__ "f1/Mcount_rd_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_cy_7__ "f1/Mcount_rd_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_6__ "f1/Mcount_rd_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_cy_6__ "f1/Mcount_rd_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_5__ "f1/Mcount_rd_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_cy_5__ "f1/Mcount_rd_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_4__ "f1/Mcount_rd_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_cy_4__ "f1/Mcount_rd_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_3__ "f1/Mcount_rd_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_cy_3__ "f1/Mcount_rd_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_2__ "f1/Mcount_rd_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_cy_2__ "f1/Mcount_rd_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_1__ "f1/Mcount_rd_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_cy_1__ "f1/Mcount_rd_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_0__ "f1/Mcount_rd_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_cy_0__ "f1/Mcount_rd_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_12__ "f1/Mcount_wr_addr_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_11__ "f1/Mcount_wr_addr_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_cy_11__ "f1/Mcount_wr_addr_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_10__ "f1/Mcount_wr_addr_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_cy_10__ "f1/Mcount_wr_addr_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_9__ "f1/Mcount_wr_addr_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_cy_9__ "f1/Mcount_wr_addr_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_8__ "f1/Mcount_wr_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_cy_8__ "f1/Mcount_wr_addr_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_7__ "f1/Mcount_wr_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_cy_7__ "f1/Mcount_wr_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_6__ "f1/Mcount_wr_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_cy_6__ "f1/Mcount_wr_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_5__ "f1/Mcount_wr_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_cy_5__ "f1/Mcount_wr_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_4__ "f1/Mcount_wr_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_cy_4__ "f1/Mcount_wr_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_3__ "f1/Mcount_wr_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_cy_3__ "f1/Mcount_wr_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_2__ "f1/Mcount_wr_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_cy_2__ "f1/Mcount_wr_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_1__ "f1/Mcount_wr_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_cy_1__ "f1/Mcount_wr_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_0__ "f1/Mcount_wr_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_cy_0__ "f1/Mcount_wr_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_12__ "f1/Msub_dont_write_past_me_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_11__ "f1/Msub_dont_write_past_me_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_11__ "f1/Msub_dont_write_past_me_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_10__ "f1/Msub_dont_write_past_me_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_10__ "f1/Msub_dont_write_past_me_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_9__ "f1/Msub_dont_write_past_me_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_9__ "f1/Msub_dont_write_past_me_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_8__ "f1/Msub_dont_write_past_me_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_8__ "f1/Msub_dont_write_past_me_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_7__ 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f1_Msub_dont_write_past_me_cy_5__ "f1/Msub_dont_write_past_me_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_4__ "f1/Msub_dont_write_past_me_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_4__ "f1/Msub_dont_write_past_me_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_3__ "f1/Msub_dont_write_past_me_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_3__ "f1/Msub_dont_write_past_me_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) 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(viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f0_Mcount_rd_addr_xor_12__ "f0/Mcount_rd_addr_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_rd_addr_xor_11__ "f0/Mcount_rd_addr_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_rd_addr_cy_11__ "f0/Mcount_rd_addr_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_rd_addr_xor_10__ "f0/Mcount_rd_addr_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_rd_addr_cy_10__ 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(true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_cy_9__ "f0/Mcount_wr_addr_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_xor_8__ "f0/Mcount_wr_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_cy_8__ "f0/Mcount_wr_addr_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_xor_7__ "f0/Mcount_wr_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_cy_7__ "f0/Mcount_wr_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_xor_6__ "f0/Mcount_wr_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_cy_6__ "f0/Mcount_wr_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_xor_5__ "f0/Mcount_wr_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_cy_5__ "f0/Mcount_wr_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_xor_4__ "f0/Mcount_wr_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_cy_4__ "f0/Mcount_wr_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_xor_3__ "f0/Mcount_wr_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_cy_3__ "f0/Mcount_wr_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_xor_2__ "f0/Mcount_wr_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_cy_2__ "f0/Mcount_wr_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_xor_1__ "f0/Mcount_wr_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_cy_1__ "f0/Mcount_wr_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_xor_0__ "f0/Mcount_wr_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_cy_0__ "f0/Mcount_wr_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_12__ "f0/Msub_dont_write_past_me_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_11__ "f0/Msub_dont_write_past_me_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_11__ "f0/Msub_dont_write_past_me_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_10__ "f0/Msub_dont_write_past_me_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_10__ "f0/Msub_dont_write_past_me_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_9__ "f0/Msub_dont_write_past_me_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_9__ "f0/Msub_dont_write_past_me_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_8__ "f0/Msub_dont_write_past_me_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_8__ "f0/Msub_dont_write_past_me_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_7__ "f0/Msub_dont_write_past_me_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_7__ "f0/Msub_dont_write_past_me_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_6__ "f0/Msub_dont_write_past_me_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_6__ "f0/Msub_dont_write_past_me_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_5__ "f0/Msub_dont_write_past_me_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_5__ "f0/Msub_dont_write_past_me_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_4__ "f0/Msub_dont_write_past_me_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_4__ "f0/Msub_dont_write_past_me_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_3__ "f0/Msub_dont_write_past_me_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_3__ "f0/Msub_dont_write_past_me_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_2__ "f0/Msub_dont_write_past_me_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_2__ "f0/Msub_dont_write_past_me_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_1__ "f0/Msub_dont_write_past_me_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_1__ "f0/Msub_dont_write_past_me_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_0__ "f0/Msub_dont_write_past_me_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_0__ "f0/Msub_dont_write_past_me_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_0 "f0/wr_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_0 "f0/rd_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_read_state_FSM_FFd1_renamed_31 "f0/read_state_FSM_FFd1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_read_state_FSM_FFd2_renamed_32 "f0/read_state_FSM_FFd2") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_12 "f0/wr_addr_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_11 "f0/wr_addr_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_10 "f0/wr_addr_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_9 "f0/wr_addr_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_8 "f0/wr_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_7 "f0/wr_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_6 "f0/wr_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_5 "f0/wr_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_4 "f0/wr_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_3 "f0/wr_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_2 "f0/wr_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_1 "f0/wr_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_12 "f0/rd_addr_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_11 "f0/rd_addr_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_10 "f0/rd_addr_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_9 "f0/rd_addr_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_8 "f0/rd_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_7 "f0/rd_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_6 "f0/rd_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_5 "f0/rd_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_4 "f0/rd_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_3 "f0/rd_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_2 "f0/rd_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_1 "f0/rd_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance fx3_miso1 + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___180___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/write1") (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance cat_mosi1 + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___178___cat_mosi1") (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance cat_sclk1 + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___178___cat_mosi1") (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance reset_global_locked_OR_1_o1 + (viewRef view_1 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view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___21___slave_fifo32/_n0223_inv1") (owner "Xilinx")) + (property INIT (string "82") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o1 "slave_fifo32/ctrl_tx_tready_data_tx_tready_OR_55_o1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5410") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mcount_idle_cycles_xor_1_11 "slave_fifo32/Mcount_idle_cycles_xor<1>11") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___23___slave_fifo32/Mcount_idle_cycles_xor<2>11") (owner "Xilinx")) + (property INIT (string "14") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT110 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT110") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT101 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT101") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT111 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT111") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT121 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT121") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT131 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT131") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT141 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT141") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT151 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT151") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT161 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT161") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT171 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT171") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT181 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT181") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT191 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT191") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT210 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT210") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT201 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT201") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT211 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT211") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT221 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT221") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT231 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT231") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT241 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT241") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT251 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT251") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT261 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT261") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT271 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT271") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT281 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT281") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT291 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT291") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT33 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT33") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT301 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT301") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT311 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT311") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT321 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT321") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT41 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT41") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT51 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT51") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT61 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT61") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT71 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT71") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT81 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT81") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT91 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT91") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___42___slave_fifo32/Mcount_fifoadr_xor<1>11") (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32__n0237_inv1 "slave_fifo32/_n0237_inv1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000100000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32__n0290_inv1 "slave_fifo32/_n0290_inv1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___21___slave_fifo32/_n0223_inv1") (owner "Xilinx")) + (property INIT (string "20002222") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_ctrl_tx_tvalid1 "slave_fifo32/ctrl_tx_tvalid1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "01000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_data_tx_tvalid1 "slave_fifo32/data_tx_tvalid1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "00010000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_2_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<2>11") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___20___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<2>11") (owner "Xilinx")) + (property INIT (string "6AA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_1_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<1>11") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "69") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<3>11") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___20___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<2>11") (owner "Xilinx")) + (property INIT (string "6AAAAAA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_4_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<4>11") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6AAAAAAAAAAAAAA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_2_11 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<2>11") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___18___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<2>11") (owner "Xilinx")) + (property INIT (string "6AA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_1_11 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<1>11") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "69") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<3>11") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___18___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<2>11") (owner "Xilinx")) + (property INIT (string "6AAAAAA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_4_11 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<4>11") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6AAAAAAAAAAAAAA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT511 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___22___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") (owner "Xilinx")) + (property INIT (string "BF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT411 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT411") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT61") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "99AA99A6AAAAAAA6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___36___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") (owner "Xilinx")) + (property INIT (string "7") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/write1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___45___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/write1") (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT511 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___25___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") (owner "Xilinx")) + (property INIT (string "BF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT411 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT411") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT61") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "99AA99A6AAAAAAA6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___34___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") (owner "Xilinx")) + (property INIT (string "7") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/write1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full1021 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1021") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___168___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1021") (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full1011 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1011") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___49___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1011") (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o81 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o81") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o61 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o61") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o71 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o71") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o41 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o41") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_4_11 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<4>11") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6AAAAAAAAAAAAAA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<3>11") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___11___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<3>11") (owner "Xilinx")) + (property INIT (string "6AAAAAA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_1_11 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<1>11") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___117___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<1>11") (owner "Xilinx")) + (property INIT (string "69") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_2_11 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<2>11") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___11___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<3>11") (owner "Xilinx")) + (property INIT (string "6AA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o41") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0121111 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0121111") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___174___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0121111") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full421") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___19___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full421") (owner "Xilinx")) + (property INIT (string "0111") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full411") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___19___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full421") (owner "Xilinx")) + (property INIT (string "FEEE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o71") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full921 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full921") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___116___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full921") (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o61") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___174___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0121111") (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tvalid11") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___127___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tvalid11") (owner "Xilinx")) + (property INIT (string "E0") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT17 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT17") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT21") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT31") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT41") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT51") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT61") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___135___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT91") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___135___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___134___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT111") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property 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INIT (string "C9C9C9C900FFFF00") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tready_int11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_o_tready_int11") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___33___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_o_tready_int11") (owner "Xilinx")) + (property INIT (string "54") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___41___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11") (owner "Xilinx")) + (property INIT (string "FFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT411") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___40___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/write1") (owner "Xilinx")) + (property INIT (string "EFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker__n0131_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/_n0131_inv1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___46___slave_fifo32/fifo64_to_gpmc32_tx/checker/_n0131_inv1") (owner "Xilinx")) + (property INIT (string "0455") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_4_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<4>11") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6AAAAAAAAAAAAAA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<3>11") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___9___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<3>11") (owner "Xilinx")) + (property INIT (string "6AAAAAA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_1_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<1>11") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___115___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<1>11") (owner "Xilinx")) + (property INIT (string "69") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_2_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<2>11") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___9___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<3>11") (owner "Xilinx")) + (property INIT (string "6AA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o41") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0121111 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0121111") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___173___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0121111") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___17___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421") (owner "Xilinx")) + (property INIT (string "0111") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full411") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___17___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421") (owner "Xilinx")) + (property INIT (string "FEEE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o71") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full921 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full921") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___114___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full921") (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o61") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___173___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0121111") (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tvalid11") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___125___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tvalid11") (owner "Xilinx")) + (property INIT (string "E0") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT17 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT17") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___175___slave_fifo32/fifo64_to_gpmc32_resp/fifo_rst_gpif_rst_OR_155_o1") (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT21") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT31") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT41") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT51") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT61") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___131___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT91") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___131___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___130___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT111") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___130___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___129___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT131") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___129___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT141 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___128___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT151 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT151") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___128___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT161") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata110 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata110") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___81___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata110") (owner "Xilinx")) + (property INIT (string "8") (owner "Xilinx")) + ) + (instance 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"___XLNM___43___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full1021") (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/write1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___37___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0154_inv1") (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property 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"___XLNM___39___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11") (owner "Xilinx")) + (property INIT (string "FFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT411") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_6_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<6>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid31 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tvalid31") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker__n0227_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/_n0227_inv1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___4___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/_n0227_inv1") (owner "Xilinx")) + (property INIT (string "0455") (owner "Xilinx")) + ) + (instance (rename f1_write11 "f1/write11") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___123___f1/write11") (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance (rename f0_write11 "f0/write11") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___122___f0/write11") (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/read_SW0") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "80000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_renamed_33 "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/read") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0111111111111111") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/read_SW0") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "80000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read_renamed_34 "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/read") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0111111111111111") (owner "Xilinx")) + ) + (instance (rename slave_fifo32__n0258_inv_SW0 "slave_fifo32/_n0258_inv_SW0") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___121___slave_fifo32/_n0258_inv_SW0") (owner "Xilinx")) + (property INIT (string "BF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1_SW0 "slave_fifo32/Mmux_state[1]_wr_fifo_xfer_Mux_21_o1_SW0") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___24___slave_fifo32/Mmux_state[1]_wr_fifo_xfer_Mux_21_o1_SW0") (owner "Xilinx")) + (property INIT (string "D0") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1 "slave_fifo32/Mmux_state[1]_wr_fifo_xfer_Mux_21_o1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "777FF7FFFFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1_SW0 "slave_fifo32/Mmux_state[1]_wr_fifo_eof_Mux_22_o1_SW0") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___24___slave_fifo32/Mmux_state[1]_wr_fifo_xfer_Mux_21_o1_SW0") (owner "Xilinx")) + (property INIT (string "80008080") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1 "slave_fifo32/Mmux_state[1]_wr_fifo_eof_Mux_22_o1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2A7F7F7FFFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32__n0279_inv_SW0 "slave_fifo32/_n0279_inv_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___121___slave_fifo32/_n0258_inv_SW0") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32__n0279_inv_renamed_35 "slave_fifo32/_n0279_inv") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0020202008282828") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_state_FSM_FFd1_In4 "slave_fifo32/state_FSM_FFd1-In4") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___176___slave_fifo32/state_FSM_FFd1-In4") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_state_FSM_FFd1_In2_renamed_36 "slave_fifo32/state_FSM_FFd1-In2") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2700050022000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_state_FSM_FFd2_In1_renamed_37 "slave_fifo32/state_FSM_FFd2-In1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___177___slave_fifo32/Mcount_idle_cycles_xor<0>11") (owner "Xilinx")) + (property INIT (string "8000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_state_FSM_FFd2_In2_renamed_38 "slave_fifo32/state_FSM_FFd2-In2") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1054101010101010") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_state_FSM_FFd2_In3 "slave_fifo32/state_FSM_FFd2-In3") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___176___slave_fifo32/state_FSM_FFd1-In4") (owner "Xilinx")) + (property INIT (string "FFF4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv_SW0") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___7___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv_SW0") (owner "Xilinx")) + (property INIT (string "FFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv_SW0") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___5___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv_SW0") (owner "Xilinx")) + (property INIT (string "FFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9CCC9CC6CCCCCCC6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tready_int1_SW0") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2F") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tready_int1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "00000C0000000800") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_i_tvalid_int1_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_i_tvalid_int1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1555555555555555") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9CCC9CC6CCCCCCC6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tready_int1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_o_tready_int1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "C000000080000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_i_tvalid_int1_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_i_tvalid_int1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1555555555555555") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o10") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8000000000000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0102_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___117___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<1>11") (owner "Xilinx")) + (property INIT (string "FF57") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv_SW0") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___27___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv_SW0") (owner "Xilinx")) + (property INIT (string "FFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv_renamed_39 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "04040000FF04FF00") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212_renamed_40 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01212") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0010001000000010") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01214_renamed_41 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01214") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "99900000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01216_renamed_42 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01216") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01219 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01219") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FAF8AA0000000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012113_renamed_43 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012113") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012114_renamed_44 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012114") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB33A820A820A820") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Msub_dont_write_past_me_xor<8>1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8A8A8A8A8A8B9A8") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tready1_SW0") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "80000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tready1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0111111111111111") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/clear_dump_OR_131_o_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___126___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/clear_dump_OR_131_o_SW0") (owner "Xilinx")) + (property INIT (string "D") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_renamed_45 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/clear_dump_OR_131_o") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000000000001") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0076_inv_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___41___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_renamed_46 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0076_inv") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "00000001FFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "CCCCCCCC0F5AF05A") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT4") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "CCCCCCCCF05A0F5A") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int11_renamed_47 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int11") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int12") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000000010005") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int14_renamed_48 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int14") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "010F") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int15") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "7FFFFFFFFFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4_renamed_49 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv4") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___33___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_o_tready_int11") (owner "Xilinx")) + (property INIT (string "A8") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror5_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror5") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31_renamed_50 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In31") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32_renamed_51 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In32") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In33 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In33") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FDFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In34") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFB") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2-In11") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFF9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In12_renamed_52 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In12") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFAAB9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0102_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___115___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<1>11") (owner "Xilinx")) + (property INIT (string "FF57") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv_SW0") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___26___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv_SW0") (owner "Xilinx")) + (property INIT (string "FFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_renamed_53 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "04040000FF04FF00") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212_renamed_54 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01212") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0010001000000010") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214_renamed_55 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01214") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "99900000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01216_renamed_56 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01216") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01219") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FAF8AA0000000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012113_renamed_57 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012113") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114_renamed_58 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012114") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB33A820A820A820") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Msub_dont_write_past_me_xor<8>1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8A8A8A8A8A8B9A8") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01219_renamed_59 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01219") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AA08880800008008") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___44___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0") (owner "Xilinx")) + (property INIT (string "BF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tready1_SW0") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "80000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tready1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0111111111111111") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/clear_dump_OR_154_o_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "D") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_renamed_60 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/clear_dump_OR_154_o") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000000000001") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0076_inv_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___39___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_renamed_61 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0076_inv") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "00000001FFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT4") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "CCCCCCCCF0550FAA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int11_renamed_62 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int11") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0307") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12_renamed_63 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int12") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "7FFFFFFFFFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int13 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int13") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F700") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv5_renamed_64 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv5") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FB") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW0") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31_renamed_65 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In31") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32_renamed_66 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In32") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In33 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In33") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FDFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In34") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFB") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror1_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11_renamed_67 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In11") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___4___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/_n0227_inv1") (owner "Xilinx")) + (property INIT (string "DFDDFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12_renamed_68 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In12") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFBEEEA55514440") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In14") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAAAAAA2A080808") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In11") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___118___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In11") (owner "Xilinx")) + (property INIT (string "FFF9") (owner "Xilinx")) + ) + (instance (rename cat_miso_IBUF_renamed_69 "cat_miso_IBUF") + (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename fx3_ce_IBUF_renamed_70 "fx3_ce_IBUF") + (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename fx3_mosi_IBUF_renamed_71 "fx3_mosi_IBUF") + (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename fx3_sclk_IBUF_renamed_72 "fx3_sclk_IBUF") + (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename GPIF_CTL4_IBUF_renamed_73 "GPIF_CTL4_IBUF") + (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename GPIF_CTL5_IBUF_renamed_74 "GPIF_CTL5_IBUF") + (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename GPIF_CTL9_IBUF_renamed_75 "GPIF_CTL9_IBUF") + (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance codec_ctrl_in_3_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance codec_ctrl_in_2_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance codec_ctrl_in_1_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance codec_ctrl_in_0_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_codec_d_11_OBUF_renamed_76 "tx_codec_d_11_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_codec_d_10_OBUF_renamed_77 "tx_codec_d_10_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_codec_d_9_OBUF_renamed_78 "tx_codec_d_9_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_codec_d_8_OBUF_renamed_79 "tx_codec_d_8_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_codec_d_7_OBUF_renamed_80 "tx_codec_d_7_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_codec_d_6_OBUF_renamed_81 "tx_codec_d_6_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_codec_d_5_OBUF_renamed_82 "tx_codec_d_5_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_codec_d_4_OBUF_renamed_83 "tx_codec_d_4_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_codec_d_3_OBUF_renamed_84 "tx_codec_d_3_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_codec_d_2_OBUF_renamed_85 "tx_codec_d_2_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_codec_d_1_OBUF_renamed_86 "tx_codec_d_1_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_codec_d_0_OBUF_renamed_87 "tx_codec_d_0_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_31_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_30_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_29_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_28_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_27_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_26_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_25_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_24_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_23_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_22_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_21_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_20_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_19_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_18_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_17_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_16_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_15_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_14_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_13_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_12_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_11_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_10_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_9_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_8_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_7_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_6_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_5_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_4_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_3_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_2_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_1_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_0_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename debug_clk_1_OBUF_renamed_88 "debug_clk_1_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_clk_0_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance cat_ce_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename cat_mosi_OBUF_renamed_89 "cat_mosi_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename cat_sclk_OBUF_renamed_90 "cat_sclk_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename fx3_miso_OBUF_renamed_91 "fx3_miso_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance pll_ce_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance pll_mosi_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance pll_sclk_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance codec_enable_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance codec_en_agc_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance codec_reset_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance codec_sync_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance codec_txrx_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename codec_fb_clk_p_OBUF_renamed_92 "codec_fb_clk_p_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_frame_p_OBUF_renamed_93 "tx_frame_p_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename IFCLK_OBUF_renamed_94 "IFCLK_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance FX3_EXTINT_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance GPIF_CTL0_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance GPIF_CTL1_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance GPIF_CTL2_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance GPIF_CTL3_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance GPIF_CTL7_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance GPIF_CTL11_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance GPIF_CTL12_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance gps_out_enable_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance gps_ref_enable_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance LED_RX1_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance LED_RX2_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance LED_TXRX1_RX_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance LED_TXRX1_TX_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance LED_TXRX2_RX_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance LED_TXRX2_TX_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance ext_ref_enable_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance pps_fpga_out_enable_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance SFDX1_RX_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance SFDX1_TX_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance SFDX2_RX_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance SFDX2_TX_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance SRX1_RX_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance SRX1_TX_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance SRX2_RX_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance SRX2_TX_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance tx_bandsel_a_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance tx_bandsel_b_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance tx_enable1_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance tx_enable2_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance rx_bandsel_a_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance rx_bandsel_b_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename rx_bandsel_c_OBUF_renamed_95 "rx_bandsel_c_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_renamed_96 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/state") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state_renamed_97 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/state") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_renamed_98 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/full") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_renamed_99 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/empty") + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_renamed_100 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/full") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_renamed_101 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/empty") + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg_renamed_102 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/full_reg") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_renamed_103 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/full_reg") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_renamed_104 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty") + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_renamed_105 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/full") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state_renamed_106 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/state") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg_renamed_107 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_renamed_108 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_renamed_109 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/dump") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_renamed_110 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/empty") + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_renamed_111 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/full") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_renamed_112 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/state") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_renamed_113 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_renamed_114 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/full_reg") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_renamed_115 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/dump") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_full_reg_renamed_116 "f1/full_reg") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_full_reg_renamed_117 "f0/full_reg") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1__rt_renamed_118 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<1>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0__rt_renamed_119 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<0>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11__rt_renamed_120 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<11>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10__rt_renamed_121 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<10>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_9__rt_renamed_122 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<9>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8__rt_renamed_123 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<8>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__rt_renamed_124 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<7>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__rt_renamed_125 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt_renamed_126 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt_renamed_127 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__rt_renamed_128 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__rt_renamed_129 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__rt_renamed_130 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt_renamed_131 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_11__rt_renamed_132 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<11>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10__rt_renamed_133 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<10>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9__rt_renamed_134 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<9>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__rt_renamed_135 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__rt_renamed_136 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__rt_renamed_137 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__rt_renamed_138 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__rt_renamed_139 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__rt_renamed_140 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__rt_renamed_141 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__rt_renamed_142 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0__rt_renamed_143 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<0>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8__rt_renamed_144 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<8>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__rt_renamed_145 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<7>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__rt_renamed_146 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt_renamed_147 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt_renamed_148 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__rt_renamed_149 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__rt_renamed_150 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__rt_renamed_151 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt_renamed_152 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__rt_renamed_153 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__rt_renamed_154 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__rt_renamed_155 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__rt_renamed_156 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__rt_renamed_157 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__rt_renamed_158 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__rt_renamed_159 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__rt_renamed_160 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0__rt_renamed_161 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<0>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_7__rt_renamed_162 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<7>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_6__rt_renamed_163 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<6>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_5__rt_renamed_164 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<5>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4__rt_renamed_165 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<4>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3__rt_renamed_166 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<3>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_2__rt_renamed_167 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<2>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1__rt_renamed_168 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<1>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0__rt_renamed_169 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<0>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_7__rt_renamed_170 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<7>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6__rt_renamed_171 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<6>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_5__rt_renamed_172 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<5>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_4__rt_renamed_173 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<4>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_3__rt_renamed_174 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<3>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_2__rt_renamed_175 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<2>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_1__rt_renamed_176 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<1>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_0__rt_renamed_177 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<0>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0__rt_renamed_178 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<0>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1__rt_renamed_179 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<1>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__rt_renamed_180 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<7>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__rt_renamed_181 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<6>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5__rt_renamed_182 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<5>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__rt_renamed_183 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<4>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3__rt_renamed_184 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<3>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__rt_renamed_185 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<2>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1__rt_renamed_186 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<1>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0__rt_renamed_187 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<0>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7__rt_renamed_188 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<7>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6__rt_renamed_189 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<6>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__rt_renamed_190 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<5>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__rt_renamed_191 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<4>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3__rt_renamed_192 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<3>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2__rt_renamed_193 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<2>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__rt_renamed_194 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<1>_rt") + (viewRef view_1 (cellRef LUT1 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slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB_renamed_264 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr4_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB_renamed_265 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr5_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB_renamed_266 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr6_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr7_FRB_renamed_267 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr7_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr8_FRB_renamed_268 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr8_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr9_FRB_renamed_269 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr9_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr10_FRB_renamed_270 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr10_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr11_FRB_renamed_271 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr11_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr12_FRB_renamed_272 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr12_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_FRB_renamed_273 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_1__FRB_renamed_274 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<1>_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_2__FRB_renamed_275 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<2>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_3__FRB_renamed_276 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<3>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_4__FRB_renamed_277 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<4>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_5__FRB_renamed_278 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<5>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_6__FRB_renamed_279 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<6>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_7__FRB_renamed_280 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<7>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_8__FRB_renamed_281 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<8>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_9__FRB_renamed_282 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<9>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_10__FRB_renamed_283 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<10>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_11__FRB_renamed_284 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<11>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_12__FRB_renamed_285 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<12>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_0__FRB_renamed_286 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<0>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr1_FRB_renamed_287 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr2_FRB_renamed_288 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr2_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr3_FRB_renamed_289 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr3_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr4_FRB_renamed_290 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr4_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr5_FRB_renamed_291 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr5_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr6_FRB_renamed_292 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr6_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr7_FRB_renamed_293 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr7_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr8_FRB_renamed_294 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr8_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr9_FRB_renamed_295 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr9_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr10_FRB_renamed_296 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr10_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename 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slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_FRB_renamed_309 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr1_FRB_renamed_310 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr2_FRB_renamed_311 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr2_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename 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+ (instance (rename f0_Result_5_2_FRB_renamed_381 "f0/Result<5>2_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_6_2_FRB_renamed_382 "f0/Result<6>2_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_7_2_FRB_renamed_383 "f0/Result<7>2_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_8_2_FRB_renamed_384 "f0/Result<8>2_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_9_2_FRB_renamed_385 "f0/Result<9>2_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_10_2_FRB_renamed_386 "f0/Result<10>2_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_11_2_FRB_renamed_387 "f0/Result<11>2_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_12_2_FRB_renamed_388 "f0/Result<12>2_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_0_1_FRB_renamed_389 "f0/Result<0>1_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_1_1_FRB_renamed_390 "f0/Result<1>1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_2_1_FRB_renamed_391 "f0/Result<2>1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_3_1_FRB_renamed_392 "f0/Result<3>1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_4_1_FRB_renamed_393 "f0/Result<4>1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_5_1_FRB_renamed_394 "f0/Result<5>1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_6_1_FRB_renamed_395 "f0/Result<6>1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_7_1_FRB_renamed_396 "f0/Result<7>1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_8_1_FRB_renamed_397 "f0/Result<8>1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_9_1_FRB_renamed_398 "f0/Result<9>1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_10_1_FRB_renamed_399 "f0/Result<10>1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_11_1_FRB_renamed_400 "f0/Result<11>1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_12_1_FRB_renamed_401 "f0/Result<12>1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_0__FRB_renamed_402 "f0/dont_write_past_me<0>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_1__FRB_renamed_403 "f0/dont_write_past_me<1>_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_2__FRB_renamed_404 "f0/dont_write_past_me<2>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_3__FRB_renamed_405 "f0/dont_write_past_me<3>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_4__FRB_renamed_406 "f0/dont_write_past_me<4>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_5__FRB_renamed_407 "f0/dont_write_past_me<5>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_6__FRB_renamed_408 "f0/dont_write_past_me<6>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_7__FRB_renamed_409 "f0/dont_write_past_me<7>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_8__FRB_renamed_410 "f0/dont_write_past_me<8>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_9__FRB_renamed_411 "f0/dont_write_past_me<9>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_10__FRB_renamed_412 "f0/dont_write_past_me<10>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_11__FRB_renamed_413 "f0/dont_write_past_me<11>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_12__FRB_renamed_414 "f0/dont_write_past_me<12>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "55555504FFFFFF5D") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___32___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111_SW0") (owner "Xilinx")) + (property INIT (string "8") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111_SW1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___32___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111_SW0") (owner "Xilinx")) + (property INIT (string "F110") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0303CFCF0203DFCF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A9AAA9A9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<3>1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A9AAA9A9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW0") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "56555656") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8212_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___124___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8212_SW0") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "CCCCCCCCF50A05FA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror5_SW1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFEFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror21") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_space_xor<3>111") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "EFEFEFEEEEEEEEEE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_space_xor<3>111") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "EFEFEFEEEEEEEEEE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT71_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000000000001") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT71") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "54A855AA55AA55AA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_o_tvalid11") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000FFFF0000FEFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_o_tvalid11") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5555555555545555") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW3") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tvalid61") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFF0001FFFE0000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int16") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F0E4D8CC00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___38___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>1") (owner "Xilinx")) + (property INIT (string "A8EA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv1_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2_renamed_415 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv2") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000023003300") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<9>11") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAAAAB9AAAAAAA8") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_4_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<4>1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A9AAA9A9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full621 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full621") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFEFEFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full611 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full611") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000100010001") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full621") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFEFEFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full621") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFEFEFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full611") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000100010001") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT71") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0EE00FF00FF00FF0") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0021FFFF00FFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int16") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "00F7000000F7F7F7") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW0") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FB") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000FFFB0004FFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<5>1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A9AAA9A9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0121211 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n0121211") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8282414141418228") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212211 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212211") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01212211") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8020401008020401") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0121211") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8282414141418228") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01211_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01211_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFF05FF04FF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211_renamed_416 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8211") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0001FFFF00007FFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int14_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF55FF01FF55FF55") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int14_SW1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF55FF00FF55FF54") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_renamed_417 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty_glue_rst") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FBFBFBFFFB00FB00") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_renamed_418 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/empty_glue_rst") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FBFBFBFFFB00FB00") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv6_SW1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AABAAAAA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv6") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4000FBFF4400FFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___1___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531_SW0") (owner "Xilinx")) + (property INIT (string "FFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531_SW1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___1___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531_SW0") (owner "Xilinx")) + (property INIT (string "8000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFB0400FFFA0500") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT73") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00FFE8FF17FFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT73_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5599665556955695") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT73") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFF0000FFFF1000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0102_SW1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___27___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv_SW0") (owner "Xilinx")) + (property INIT (string "80") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set_renamed_419 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/full_glue_set") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8A8FDA8A8A8A8A8") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0102_SW1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___26___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv_SW0") (owner "Xilinx")) + (property INIT (string "80") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set_renamed_420 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/full_glue_set") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8A8FDA8A8A8A8A8") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_space_xor<3>111_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty_glue_rst_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1111000111111111") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_space_xor<3>111_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/empty_glue_rst_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1111000111111111") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11_SW1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_o_tready_int11") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "3333333333323333") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW2") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000100000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tlast1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0C0C0C0C0C0D0C0C") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror21_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0001") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror11") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0404040404040504") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror21_SW1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "01") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_tlast1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0C0C0C0C0C0C0D0C") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01217_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01217_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A521") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n012110_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n012110_SW0") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "00008400") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set_renamed_421 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/full_reg_glue_set") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFF008C008C008C") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT31") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E1E1E1E10FF0F00F") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT52") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A9A9A9A9AA5555AA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set_renamed_422 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/dump_glue_set") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "00400000AAEAAAAA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int16_SW0") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "EEEEFEEE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv6_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFBF8FFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_cy "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_cy") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_cy1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_cy1") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F0F0F0F08877EE11") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01216_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFDBFDDBFDFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01216_SW1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___43___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full1021") (owner "Xilinx")) + (property INIT (string "EFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01216_SW2") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FCBFFBEFFC7FF7DF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_renamed_423 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01216") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "350035F0") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In12_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2-In12_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___46___slave_fifo32/fifo64_to_gpmc32_tx/checker/_n0131_inv1") (owner "Xilinx")) + (property INIT (string "D") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In13 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2-In13") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AA3B8819AA2A8808") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In12_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In12_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___47___slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/read1") (owner "Xilinx")) + (property INIT (string "D") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In13") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AA3B8819AA2A8808") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_9_11 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<9>11") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAAAAB9AAAAAAA8") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o10_SW1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o10") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8000000000000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_111 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_space_xor<3>111") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___29___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_space_xor<3>111") (owner "Xilinx")) + (property INIT (string "FFAEFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_space_xor_3_111 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_space_xor<3>111") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___28___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_space_xor<3>111") (owner "Xilinx")) + (property INIT (string "FFAEFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212111 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01212111") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01212111") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full621 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full621") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFEFEFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012111_renamed_424 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012111") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2002000000002002") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111_renamed_425 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012111") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2002000000002002") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___35___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511_SW0") (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT21") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAAAAAAA9AAAAAA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6_SW1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "01FE00FF00FF807F") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAA8AAAAAAABAAA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<5>1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "999A999999959999") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140514055555140") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140514055555140") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set_renamed_426 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/full_reg_glue_set") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4C4CFF4C4C4C4C4C") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tvalid11") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___171___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tvalid11") (owner "Xilinx")) + (property INIT (string "C8") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_o_tvalid11") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___169___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_o_tvalid11") (owner "Xilinx")) + (property INIT (string "C8") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01217_renamed_427 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01217") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0080000000000080") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217_renamed_428 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01217") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0080000000000080") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv31 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv31") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___14___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv31") (owner "Xilinx")) + (property INIT (string "4500") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv31 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv31") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___12___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv31") (owner "Xilinx")) + (property INIT (string "4500") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01213_renamed_429 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01213") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9090900000900000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213_renamed_430 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01213") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9090900000900000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFF0FFFFFF80FF80") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT21") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9996") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01218_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "7") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_renamed_431 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01218") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4141414141411441") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set_renamed_432 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/dump_glue_set") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "00400000AAEAAAAA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror1_SW1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___118___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In11") (owner "Xilinx")) + (property INIT (string "04") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_0") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int16_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "EFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFF0D2F087F") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv6_SW2") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot_renamed_433 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_0_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6AAA595566AA5555") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg_glue_set_renamed_434 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg_glue_set") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___120___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg_glue_set") (owner "Xilinx")) + (property INIT (string "FFA2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_glue_set_renamed_435 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg_glue_set") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___119___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg_glue_set") (owner "Xilinx")) + (property INIT (string "FFA2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_cy "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0_cy") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11_SW1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "01") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut_renamed_436 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0_lut") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1111111011111111") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_FRB_renamed_437 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr1_FRB_renamed_438 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr2_FRB_renamed_439 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr2_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr3_FRB_renamed_440 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr3_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr4_FRB_renamed_441 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr4_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr5_FRB_renamed_442 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr5_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr6_FRB_renamed_443 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr6_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr7_FRB_renamed_444 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr7_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr8_FRB_renamed_445 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr8_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_FRB_renamed_446 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr1_FRB_renamed_447 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr2_FRB_renamed_448 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr2_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr3_FRB_renamed_449 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr3_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr4_FRB_renamed_450 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr4_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr5_FRB_renamed_451 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr5_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr6_FRB_renamed_452 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr6_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr7_FRB_renamed_453 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr7_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr8_FRB_renamed_454 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr8_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421_FRB_renamed_455 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full421_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411_FRB_renamed_456 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full411_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421_FRB_renamed_457 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411_FRB_renamed_458 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full411_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB_renamed_459 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB_renamed_460 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621_FRB_renamed_461 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full621_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621_FRB_renamed_462 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full621_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0_FRB_renamed_463 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01218_SW0_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB0_renamed_464 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_12_BRB0") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB1_renamed_465 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_12_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_13_BRB1_renamed_466 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_13_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_14_BRB1_renamed_467 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_14_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15_BRB1_renamed_468 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_15_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB0_renamed_469 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_12_BRB0") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB1_renamed_470 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_12_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_13_BRB1_renamed_471 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_13_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_14_BRB1_renamed_472 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_14_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15_BRB1_renamed_473 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_15_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd2_BRB0_renamed_474 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd2_BRB0") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd2_BRB1_renamed_475 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd2_BRB1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB0_renamed_476 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd2_BRB0") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB1_renamed_477 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd2_BRB1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0_renamed_478 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB0") + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1_renamed_479 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2_renamed_480 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB2") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3_renamed_481 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB3") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4_renamed_482 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB4") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5_renamed_483 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB5") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0_renamed_484 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB0") + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1_renamed_485 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2_renamed_486 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB2") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3_renamed_487 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB3") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4_renamed_488 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB4") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5_renamed_489 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB5") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_11_BRB1_renamed_490 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_11_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_11_BRB1_renamed_491 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_11_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_10_BRB1_renamed_492 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_10_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_10_BRB1_renamed_493 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_10_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_9_BRB1_renamed_494 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_9_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_9_BRB1_renamed_495 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_9_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_17_BRB0_renamed_496 "slave_fifo32/debug1_17_BRB0") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_16_BRB0_renamed_497 "slave_fifo32/debug1_16_BRB0") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_rd_one_BRB0_renamed_498 "slave_fifo32/rd_one_BRB0") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_rd_one_BRB1_renamed_499 "slave_fifo32/rd_one_BRB1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012112_renamed_500 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012112") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8822228C80202084") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112_renamed_501 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012112") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8822228C80202084") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB1_renamed_502 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB3_renamed_503 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB3") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB4_renamed_504 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB4") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv6_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___124___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8212_SW0") (owner "Xilinx")) + (property INIT (string "EEEF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv6") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFF0C080C0C0C0C") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_write1 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/write1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___16___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/write1") (owner "Xilinx")) + (property INIT (string "5400") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_write1 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/write1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___15___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/write1") (owner "Xilinx")) + (property INIT (string "5400") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1_renamed_505 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_lut1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFF1110FFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/GND_56_o_read_OR_123_o1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "11101110FFFF1110") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/clear_inv1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o10_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut_renamed_506 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_lut") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000FAFB00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo__n0146_inv1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/_n0146_inv1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___13___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/_n0146_inv1") (owner "Xilinx")) + (property INIT (string "2E22") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0146_inv1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n0146_inv1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___10___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n0146_inv1") (owner "Xilinx")) + (property INIT (string "2E22") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/_n0146_inv1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFB8FF88") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt__n0074_inv1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/_n0074_inv1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "C60ACC000A0A0000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/_n0074_inv1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "C60ACC000A0A0000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_GND_56_o_read_OR_123_o1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/GND_56_o_read_OR_123_o1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___171___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tvalid11") (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_GND_66_o_read_OR_144_o1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/GND_66_o_read_OR_144_o1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___169___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_o_tvalid11") (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename f1__n0161_inv1_lut_renamed_507 "f1/_n0161_inv1_lut") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename f1__n0161_inv1_cy "f1/_n0161_inv1_cy") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1__n0161_inv1_lut1_renamed_508 "f1/_n0161_inv1_lut1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "D") (owner "Xilinx")) + ) + (instance (rename f1__n0161_inv1_cy1 "f1/_n0161_inv1_cy1") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0__n0161_inv1_lut_renamed_509 "f0/_n0161_inv1_lut") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename f0__n0161_inv1_cy "f0/_n0161_inv1_cy") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0__n0161_inv1_lut1_renamed_510 "f0/_n0161_inv1_lut1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "D") (owner "Xilinx")) + ) + (instance (rename f0__n0161_inv1_cy1 "f0/_n0161_inv1_cy1") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW2") + (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_F "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW2_F") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFD") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_G "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW2_G") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01213_SW0") + (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW0") + (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW0_F") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFEFFFFFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW0_G") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "EEFFFEFFFFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW1") + (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW1_F") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "EEFFEFFFFFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW1_G") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFEFFFFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW1") + (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW1_F") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFAAAAFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_G "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW1_G") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FB") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot_renamed_511 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg_rstpot") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___0___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg_rstpot") (owner "Xilinx")) + (property INIT (string "FFFF7222") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_wr_one_rstpot_renamed_512 "slave_fifo32/wr_one_rstpot") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___48___slave_fifo32/_n0230_inv1") (owner "Xilinx")) + (property INIT (string "EEAAA2AA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state_glue_set_renamed_513 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/state_glue_set") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___16___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/write1") (owner "Xilinx")) + (property INIT (string "A2A6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_glue_set_renamed_514 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/state_glue_set") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___15___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/write1") (owner "Xilinx")) + (property INIT (string "A2A6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/empty_glue_rst_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/empty_glue_rst_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_slrd_rstpot_SW0 "slave_fifo32/slrd_rstpot_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_slrd_rstpot_renamed_515 "slave_fifo32/slrd_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AA2AAAFAAA2AFAFA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_renamed_516 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "00000000DD09C000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT31") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E178E1E1E1E1E1E1") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT31") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E178E1E1E1E1E1E1") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01215_renamed_517 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01215") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0220000000000220") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215_renamed_518 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01215") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0220000000000220") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_GND_50_o_read_OR_57_o1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/GND_50_o_read_OR_57_o1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2272") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/GND_50_o_read_OR_57_o1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2272") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8211") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFF7FFFFFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT21") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___22___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") (owner "Xilinx")) + (property INIT (string "BF4040BF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8211") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFF7FFFFFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT21") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___25___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") (owner "Xilinx")) + (property INIT (string "BF4040BF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01218_renamed_519 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01218") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___116___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full921") (owner "Xilinx")) + (property INIT (string "0440") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01218_renamed_520 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01218") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___114___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full921") (owner "Xilinx")) + (property INIT (string "0440") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAAAAAAAAAAAAA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8212_SW1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAAAAAAAAAAAAA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000000000001") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/clear_inv1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_tx/cross_clock_fifo/write1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___120___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg_glue_set") (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/write1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___119___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg_glue_set") (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_inv1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0155115501111111") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<0>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<0>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<1>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<1>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<2>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<2>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___3___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0") (owner "Xilinx")) + (property INIT (string "FFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___2___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0") (owner "Xilinx")) + (property INIT (string "FFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAAAAAAAAAAAAA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT4_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___126___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/clear_dump_OR_131_o_SW0") (owner "Xilinx")) + (property INIT (string "CCC9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAAAAAAAAAAAAA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT4_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___35___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511_SW0") (owner "Xilinx")) + (property INIT (string "CCC9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<3>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<3>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<4>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<4>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<5>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<5>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<6>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<6>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<7>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<7>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<8>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<8>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<9>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<9>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<10>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_10__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<10>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<11>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_11__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<11>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_12__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<12>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_12__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<12>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_13__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<13>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_13__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<13>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_14__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<14>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_14__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<14>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_write1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/write1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000100000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_write1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/write1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0001000000000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_15__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<15>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_15__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<15>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename f1_GND_14_o_read_OR_37_o1 "f1/GND_14_o_read_OR_37_o1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___31___f1/GND_14_o_read_OR_37_o1") (owner "Xilinx")) + (property INIT (string "72") (owner "Xilinx")) + ) + (instance (rename f0_GND_14_o_read_OR_37_o1 "f0/GND_14_o_read_OR_37_o1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___30___f0/GND_14_o_read_OR_37_o1") (owner "Xilinx")) + (property INIT (string "72") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_write1 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/write1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___180___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/write1") (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_write1 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/write1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___179___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/write1") (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51_renamed_521 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT51") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAA9AAAA6A696A6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1-In111") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___13___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/_n0146_inv1") (owner "Xilinx")) + (property INIT (string "7F2A") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51_renamed_522 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT51") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAA9AAAA6A696A6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1-In111") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___10___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n0146_inv1") (owner "Xilinx")) + (property INIT (string "7F2A") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg_glue_set_renamed_523 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/full_reg_glue_set") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___45___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/write1") (owner "Xilinx")) + (property INIT (string "5540FFC0") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1 "slave_fifo32/ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8A8A88820202000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF0040BFBF4000FF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF0040BFBF4000FF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01216_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01216_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFF6FFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217_renamed_524 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01217") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "999F999699999990") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<0>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A6AAA6A6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<0>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A6AAA6A6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<1>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<1>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<2>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<2>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<3>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<3>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<4>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<4>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<5>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<5>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<6>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<6>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<7>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<7>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename f1_read_state_FSM_FFd1_In111 "f1/read_state_FSM_FFd1-In111") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___31___f1/GND_14_o_read_OR_37_o1") (owner "Xilinx")) + (property INIT (string "FDA8") (owner "Xilinx")) + ) + (instance (rename f0_read_state_FSM_FFd1_In111 "f0/read_state_FSM_FFd1-In111") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___30___f0/GND_14_o_read_OR_37_o1") (owner "Xilinx")) + (property INIT (string "FDA8") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0146_inv1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___0___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg_rstpot") (owner "Xilinx")) + (property INIT (string "FFFF8D88") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<8>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<8>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/GND_66_o_read_OR_144_o1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___44___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0") (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1_In11 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd1-In11") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___8___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd1-In11") (owner "Xilinx")) + (property INIT (string "8A8ADF8A") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1-In11") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___6___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1-In11") (owner "Xilinx")) + (property INIT (string "8A8ADF8A") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv_renamed_525 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0004FFFF00040004") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv_renamed_526 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0004FFFF00040004") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01215_SW0") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___49___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1011") (owner "Xilinx")) + (property INIT (string "9F") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215_renamed_527 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01215") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0020000002200200") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o9_SW1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8421000000000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o9") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o9_SW1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8421000000000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o9") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_glue_set_renamed_528 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/state_glue_set") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___28___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_space_xor<3>111") (owner "Xilinx")) + (property INIT (string "A9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state_glue_set_renamed_529 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/state_glue_set") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___29___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_space_xor<3>111") (owner "Xilinx")) + (property INIT (string "A9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0144_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0144_inv1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___8___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd1-In11") (owner "Xilinx")) + (property INIT (string "00440F44") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0144_inv1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___6___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1-In11") (owner "Xilinx")) + (property INIT (string "00440F44") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_G "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01213_SW0_G") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFF5455FFFF5657") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212_SW1_SW0") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___168___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1021") (owner "Xilinx")) + (property INIT (string "EA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212_SW1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF66FF69FFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set_SW1 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/full_glue_set_SW1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___7___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv_SW0") (owner "Xilinx")) + (property INIT (string "FFFF7FFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set_renamed_530 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/full_glue_set") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AA8AAA8AFFCFAA8A") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set_SW1 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/full_glue_set_SW1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___5___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv_SW0") (owner "Xilinx")) + (property INIT (string "FFFF7FFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set_renamed_531 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/full_glue_set") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AA8AAA8AFFCFAA8A") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/GND_49_o_space[15]_LessThan_2_o1_SW1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1 "slave_fifo32/fifo64_to_gpmc32_tx/GND_49_o_space[15]_LessThan_2_o1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFF55555554") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/GND_63_o_space[15]_LessThan_2_o1_SW1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1 "slave_fifo32/fifo64_to_gpmc32_ctrl/GND_63_o_space[15]_LessThan_2_o1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFF55555554") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___3___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0") (owner "Xilinx")) + (property INIT (string "8000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___2___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0") (owner "Xilinx")) + (property INIT (string "8000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_write_AND_42_o_inv2 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_write_AND_42_o_inv2") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "DFCF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_write_AND_42_o_inv2 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_write_AND_42_o_inv2") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "DFCF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41_renamed_532 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT41") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___36___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") (owner "Xilinx")) + (property INIT (string "9AAAAAA6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41_renamed_533 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT41") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___34___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") (owner "Xilinx")) + (property INIT (string "9AAAAAA6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_1_rstpot_renamed_534 "slave_fifo32/sloe_1_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAA2AAAAAAAFFAA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_renamed_535 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/empty_glue_rst") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FC55FC54FF55FF55") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst_renamed_536 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/empty_glue_rst") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FC55FC54FF55FF55") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2-In1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "7FFF7F7F2AFF2A2A") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2-In1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "7FFF7F7F2AFF2A2A") (owner "Xilinx")) + ) + (instance (rename f1_read_state_FSM_FFd2_In1 "f1/read_state_FSM_FFd2-In1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FDFDFDFFA8A8A8FF") (owner "Xilinx")) + ) + (instance (rename f0_read_state_FSM_FFd2_In1 "f0/read_state_FSM_FFd2-In1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FDFDFDFFA8A8A8FF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_F "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01213_SW0_F") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "00FBFB0005FBFB05") (owner "Xilinx")) + ) + (instance (rename f1_full_reg_glue_set_renamed_537 "f1/full_reg_glue_set") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___123___f1/write11") (owner "Xilinx")) + (property INIT (string "F0FF4044") (owner "Xilinx")) + ) + (instance (rename f0_full_reg_glue_set_renamed_538 "f0/full_reg_glue_set") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___122___f0/write11") (owner "Xilinx")) + (property INIT (string "F0FF4044") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___14___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv31") (owner "Xilinx")) + (property INIT (string "FFFF4B44") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___12___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv31") (owner "Xilinx")) + (property INIT (string "FFFF4B44") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<15>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<15>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<9>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<9>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<10>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<10>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<11>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<11>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<12>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<12>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<13>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<13>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<14>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<14>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_1_renamed_539 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2_1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_renamed_540 "slave_fifo32/sloe") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_rstpot_renamed_541 "slave_fifo32/sloe_rstpot") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_31_rstpot_renamed_542 "slave_fifo32/gpif_data_out_31_rstpot") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_12__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<12>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_11__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<11>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_10__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<10>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_9__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<9>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_8__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<8>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_7__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<7>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_6__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<6>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_5__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<5>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_4__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<4>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_3__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<3>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_2__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<2>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_2__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<2>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_3__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<3>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_4__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<4>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_5__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<5>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_6__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<6>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_7__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<7>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_8__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<8>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_9__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<9>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_10__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<10>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_11__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<11>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_12__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<12>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_lut_0__INV_0 "f1/Mcount_rd_addr_lut<0>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_lut_0__INV_0 "f1/Mcount_wr_addr_lut<0>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_12__INV_0 "f1/Msub_dont_write_past_me_lut<12>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_11__INV_0 "f1/Msub_dont_write_past_me_lut<11>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_10__INV_0 "f1/Msub_dont_write_past_me_lut<10>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_9__INV_0 "f1/Msub_dont_write_past_me_lut<9>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_8__INV_0 "f1/Msub_dont_write_past_me_lut<8>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_7__INV_0 "f1/Msub_dont_write_past_me_lut<7>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_6__INV_0 "f1/Msub_dont_write_past_me_lut<6>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_5__INV_0 "f1/Msub_dont_write_past_me_lut<5>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_4__INV_0 "f1/Msub_dont_write_past_me_lut<4>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_3__INV_0 "f1/Msub_dont_write_past_me_lut<3>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_2__INV_0 "f1/Msub_dont_write_past_me_lut<2>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_rd_addr_lut_0__INV_0 "f0/Mcount_rd_addr_lut<0>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_lut_0__INV_0 "f0/Mcount_wr_addr_lut<0>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_12__INV_0 "f0/Msub_dont_write_past_me_lut<12>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_11__INV_0 "f0/Msub_dont_write_past_me_lut<11>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_10__INV_0 "f0/Msub_dont_write_past_me_lut<10>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_9__INV_0 "f0/Msub_dont_write_past_me_lut<9>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_8__INV_0 "f0/Msub_dont_write_past_me_lut<8>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_7__INV_0 "f0/Msub_dont_write_past_me_lut<7>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_6__INV_0 "f0/Msub_dont_write_past_me_lut<6>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_5__INV_0 "f0/Msub_dont_write_past_me_lut<5>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_4__INV_0 "f0/Msub_dont_write_past_me_lut<4>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_3__INV_0 "f0/Msub_dont_write_past_me_lut<3>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_2__INV_0 "f0/Msub_dont_write_past_me_lut<2>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance gpif_clk_INV_4_o1_INV_0 + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mcount_fifoadr_xor_0_11_INV_0 "slave_fifo32/Mcount_fifoadr_xor<0>11_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename catcap_data_clk_INV_6_o1_INV_0 "catcap/data_clk_INV_6_o1_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_0_11_INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<0>11_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_0_11_INV_0 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<0>11_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT11_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT11_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_0_11_INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<0>11_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_0__inv1_INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state<0>_inv1_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_o_tvalid1_INV_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/o_tvalid1_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_0_11_INV_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<0>11_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_0__inv1_INV_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state<0>_inv1_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_i_tready1_INV_0 "f0/i_tready1_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT11_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__inv_INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>_inv_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_state_FSM_FFd1_In3_renamed_543 "slave_fifo32/state_FSM_FFd1-In3") + (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_state_FSM_FFd1_In3_F "slave_fifo32/state_FSM_FFd1-In3_F") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "80808000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_state_FSM_FFd1_In3_G "slave_fifo32/state_FSM_FFd1-In3_G") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "04155555FFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In14") + (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_F "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In14_F") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAA2A22FFAA7F22") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_G "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In14_G") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A2AAA6A6F7FFA6A6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13_SW1") + (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_F "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13_SW1_F") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFF5554") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_G "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13_SW1_G") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW2") + (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_F "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW2_F") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "EFEEEFEEEFEEFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW2_G") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "54555454FCFFFCFC") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_slrd2_1_renamed_544 "slave_fifo32/slrd2_1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_EP_WMARK1_1_renamed_545 "slave_fifo32/EP_WMARK1_1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_EP_READY1_1_renamed_546 "slave_fifo32/EP_READY1_1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_31_1_renamed_547 "slave_fifo32/gpif_data_out_31_1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_slwr_1_renamed_548 "slave_fifo32/slwr_1") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_34_renamed_549 "slave_fifo32/sloe_34") + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_slrd_1_renamed_550 "slave_fifo32/slrd_1") + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_pktend_1_renamed_551 "slave_fifo32/pktend_1") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifoadr_1_1_renamed_552 "slave_fifo32/fifoadr_1_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifoadr_0_1_renamed_553 "slave_fifo32/fifoadr_0_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance GPIF_D_31_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_33_renamed_554 "slave_fifo32/sloe_33") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_31 "slave_fifo32/gpif_data_out_31") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_30_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_32_renamed_555 "slave_fifo32/sloe_32") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_30 "slave_fifo32/gpif_data_out_30") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_29_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_31_renamed_556 "slave_fifo32/sloe_31") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_29 "slave_fifo32/gpif_data_out_29") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_28_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_30_renamed_557 "slave_fifo32/sloe_30") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_28 "slave_fifo32/gpif_data_out_28") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_27_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_29_renamed_558 "slave_fifo32/sloe_29") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_27 "slave_fifo32/gpif_data_out_27") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_26_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_28_renamed_559 "slave_fifo32/sloe_28") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_26 "slave_fifo32/gpif_data_out_26") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_25_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_27_renamed_560 "slave_fifo32/sloe_27") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_25 "slave_fifo32/gpif_data_out_25") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_24_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_26_renamed_561 "slave_fifo32/sloe_26") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_24 "slave_fifo32/gpif_data_out_24") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_23_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_25_renamed_562 "slave_fifo32/sloe_25") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_23 "slave_fifo32/gpif_data_out_23") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_22_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_24_renamed_563 "slave_fifo32/sloe_24") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_22 "slave_fifo32/gpif_data_out_22") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_21_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_23_renamed_564 "slave_fifo32/sloe_23") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_21 "slave_fifo32/gpif_data_out_21") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_20_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_22_renamed_565 "slave_fifo32/sloe_22") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_20 "slave_fifo32/gpif_data_out_20") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_19_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_21_renamed_566 "slave_fifo32/sloe_21") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_19 "slave_fifo32/gpif_data_out_19") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_18_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_20_renamed_567 "slave_fifo32/sloe_20") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_18 "slave_fifo32/gpif_data_out_18") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_17_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_19_renamed_568 "slave_fifo32/sloe_19") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_17 "slave_fifo32/gpif_data_out_17") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_16_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_18_renamed_569 "slave_fifo32/sloe_18") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_16 "slave_fifo32/gpif_data_out_16") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_15_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_17_renamed_570 "slave_fifo32/sloe_17") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_15 "slave_fifo32/gpif_data_out_15") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_14_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_16_renamed_571 "slave_fifo32/sloe_16") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_14 "slave_fifo32/gpif_data_out_14") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_13_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_15_renamed_572 "slave_fifo32/sloe_15") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_13 "slave_fifo32/gpif_data_out_13") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_12_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_14_renamed_573 "slave_fifo32/sloe_14") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_12 "slave_fifo32/gpif_data_out_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_11_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_13_renamed_574 "slave_fifo32/sloe_13") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_11 "slave_fifo32/gpif_data_out_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_10_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_12_renamed_575 "slave_fifo32/sloe_12") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_10 "slave_fifo32/gpif_data_out_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_9_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_11_renamed_576 "slave_fifo32/sloe_11") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_9 "slave_fifo32/gpif_data_out_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_8_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_10_renamed_577 "slave_fifo32/sloe_10") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_8 "slave_fifo32/gpif_data_out_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_7_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_9_renamed_578 "slave_fifo32/sloe_9") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_7 "slave_fifo32/gpif_data_out_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_6_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_8_renamed_579 "slave_fifo32/sloe_8") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_6 "slave_fifo32/gpif_data_out_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_5_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_7_renamed_580 "slave_fifo32/sloe_7") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_5 "slave_fifo32/gpif_data_out_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_4_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_6_renamed_581 "slave_fifo32/sloe_6") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_4 "slave_fifo32/gpif_data_out_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_3_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_5_renamed_582 "slave_fifo32/sloe_5") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_3 "slave_fifo32/gpif_data_out_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_2_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_4_renamed_583 "slave_fifo32/sloe_4") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_2 "slave_fifo32/gpif_data_out_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_1_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_3_renamed_584 "slave_fifo32/sloe_3") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_1 "slave_fifo32/gpif_data_out_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_0_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_2_renamed_585 "slave_fifo32/sloe_2") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_0 "slave_fifo32/gpif_data_out_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram17") + (viewRef view_1 (cellRef RAMB8BWER (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "13:INPUT:ADDRAWRADDR<12:0>") (owner "Xilinx")) + (property BUS_INFO (string "13:INPUT:ADDRBRDADDR<12:0>") (owner "Xilinx")) + (property BUS_INFO (string "2:OUTPUT:DOPADOP<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "2:OUTPUT:DOPBDOP<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "2:INPUT:DIPBDIP<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "2:INPUT:DIPADIP<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "2:INPUT:WEAWEL<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "2:INPUT:WEBWEU<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "16:OUTPUT:DOADO<15:0>") (owner "Xilinx")) + (property BUS_INFO (string "16:INPUT:DIBDI<15:0>") (owner "Xilinx")) + (property BUS_INFO (string "16:INPUT:DIADI<15:0>") (owner "Xilinx")) + (property BUS_INFO (string "16:OUTPUT:DOBDO<15:0>") (owner "Xilinx")) + (property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_01 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_02 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_03 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_04 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_05 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_06 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_07 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_08 (string 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(property INIT_11 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_12 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_13 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_14 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_15 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_16 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_17 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_18 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_19 (string 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"Xilinx")) + (property DOA_REG (integer 0) (owner "Xilinx")) + (property DOB_REG (integer 0) (owner "Xilinx")) + (property EN_RSTRAM_A (string "TRUE") (owner "Xilinx")) + (property EN_RSTRAM_B (string "TRUE") (owner "Xilinx")) + (property INITP_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INITP_01 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INITP_02 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INITP_03 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_A (string "00000") (owner "Xilinx")) + (property INIT_B (string "00000") (owner "Xilinx")) + (property RAM_MODE (string "TDP") (owner "Xilinx")) + (property RST_PRIORITY_A (string "CE") (owner "Xilinx")) + (property RST_PRIORITY_B (string "CE") (owner "Xilinx")) + (property RSTTYPE (string "SYNC") (owner "Xilinx")) + (property SRVAL_A (string "00000") (owner "Xilinx")) + (property SRVAL_B (string "00000") (owner "Xilinx")) + (property INIT_FILE (string "NONE") (owner "Xilinx")) + (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram16") + (viewRef view_1 (cellRef RAMB16BWER (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "14:INPUT:ADDRA<13:0>") (owner "Xilinx")) + (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:INPUT:DIPA<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:DOPA<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx")) + (property BUS_INFO (string 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(property INIT_30 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_31 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_32 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_33 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_34 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_35 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_36 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_37 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_38 (string 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(owner "Xilinx")) + (property DATA_WIDTH_A (integer 2) (owner "Xilinx")) + (property DATA_WIDTH_B (integer 2) (owner "Xilinx")) + (property DOA_REG (integer 0) (owner "Xilinx")) + (property DOB_REG (integer 0) (owner "Xilinx")) + (property EN_RSTRAM_A (string "TRUE") (owner "Xilinx")) + (property EN_RSTRAM_B (string "TRUE") (owner "Xilinx")) + (property INITP_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INITP_01 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INITP_02 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INITP_03 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INITP_04 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INITP_05 (string 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) + ) + (net tx_frame_p_OBUF + (joined + (portRef Q (instanceRef catgen_oddr2_frame)) + (portRef I (instanceRef tx_frame_p_OBUF_renamed_93)) + ) + ) + (net (rename gpif_sync_reset_out "gpif_sync/reset_out") + (joined + (portRef Q (instanceRef gpif_sync_reset_out_renamed_2)) + (portRef S (instanceRef slave_fifo32_slwr_renamed_7)) + (portRef S (instanceRef slave_fifo32_pktend_renamed_6)) + (portRef R (instanceRef slave_fifo32_state_FSM_FFd2_renamed_5)) + (portRef R (instanceRef slave_fifo32_state_FSM_FFd1_renamed_4)) + (portRef R (instanceRef slave_fifo32_fifoadr_0)) + (portRef R (instanceRef slave_fifo32_fifoadr_1)) + (portRef R (instanceRef slave_fifo32_idle_cycles_0)) + (portRef R (instanceRef slave_fifo32_idle_cycles_1)) + (portRef R (instanceRef slave_fifo32_idle_cycles_2)) + (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_0)) + (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_1)) + (portRef R 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(instanceRef f1_ram_Mram_ram18)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram20)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram20)) + (portRef RSTA (instanceRef f1_ram_Mram_ram20)) + (portRef RSTB (instanceRef f1_ram_Mram_ram20)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram20)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram20)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram20)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram20)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram16)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram16)) + (portRef RSTA (instanceRef f1_ram_Mram_ram16)) + (portRef RSTB (instanceRef f1_ram_Mram_ram16)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram16)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram16)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram16)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram16)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram15)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram15)) + (portRef RSTA (instanceRef f1_ram_Mram_ram15)) + (portRef RSTB (instanceRef f1_ram_Mram_ram15)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram15)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram15)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram15)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram15)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram17)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram17)) + (portRef RSTA (instanceRef f1_ram_Mram_ram17)) + (portRef RSTB (instanceRef f1_ram_Mram_ram17)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram17)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram17)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram17)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram17)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram14)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram14)) + (portRef RSTA (instanceRef f1_ram_Mram_ram14)) + (portRef RSTB (instanceRef f1_ram_Mram_ram14)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram14)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram14)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram14)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram14)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram13)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram13)) + (portRef RSTA (instanceRef f1_ram_Mram_ram13)) + (portRef RSTB (instanceRef f1_ram_Mram_ram13)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram13)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram13)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram13)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram13)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram12)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram12)) + (portRef RSTA (instanceRef f1_ram_Mram_ram12)) + (portRef RSTB (instanceRef f1_ram_Mram_ram12)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram12)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram12)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram12)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram12)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram11)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram11)) + (portRef RSTA (instanceRef f1_ram_Mram_ram11)) + (portRef RSTB (instanceRef f1_ram_Mram_ram11)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram11)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram11)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram11)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram11)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram9)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram9)) + (portRef RSTA (instanceRef f1_ram_Mram_ram9)) + (portRef RSTB (instanceRef f1_ram_Mram_ram9)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram9)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram9)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram9)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram9)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram8)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram8)) + (portRef RSTA (instanceRef f1_ram_Mram_ram8)) + (portRef RSTB (instanceRef f1_ram_Mram_ram8)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram8)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram8)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram8)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram8)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram10)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram10)) + (portRef RSTA (instanceRef f1_ram_Mram_ram10)) + (portRef RSTB (instanceRef f1_ram_Mram_ram10)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram10)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram10)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram10)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram10)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram6)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram6)) + (portRef RSTA (instanceRef f1_ram_Mram_ram6)) + (portRef RSTB (instanceRef f1_ram_Mram_ram6)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram6)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram6)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram6)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram6)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram5)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram5)) + (portRef RSTA (instanceRef f1_ram_Mram_ram5)) + (portRef RSTB (instanceRef f1_ram_Mram_ram5)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram5)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram5)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram5)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram5)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram7)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram7)) + (portRef RSTA (instanceRef f1_ram_Mram_ram7)) + (portRef RSTB (instanceRef f1_ram_Mram_ram7)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram7)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram7)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram7)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram7)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram3)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram3)) + (portRef RSTA (instanceRef f1_ram_Mram_ram3)) + (portRef RSTB (instanceRef f1_ram_Mram_ram3)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram3)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram3)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram3)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram3)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram2)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram2)) + (portRef RSTA (instanceRef f1_ram_Mram_ram2)) + (portRef RSTB (instanceRef f1_ram_Mram_ram2)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram2)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram2)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram2)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram2)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram4)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram4)) + (portRef RSTA (instanceRef f1_ram_Mram_ram4)) + (portRef RSTB (instanceRef f1_ram_Mram_ram4)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram4)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram4)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram4)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram4)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram1)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram1)) + (portRef RSTA (instanceRef f1_ram_Mram_ram1)) + (portRef RSTB (instanceRef f1_ram_Mram_ram1)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram1)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram1)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram1)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram1)) + (portRef REGCEA (instanceRef f0_ram_Mram_ram33)) + (portRef REGCEBREGCE (instanceRef f0_ram_Mram_ram33)) + (portRef RSTA (instanceRef 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f0_ram_Mram_ram27)) + (portRef REGCEB (instanceRef f0_ram_Mram_ram27)) + (portRef RSTA (instanceRef f0_ram_Mram_ram27)) + (portRef RSTB (instanceRef f0_ram_Mram_ram27)) + (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram27)) + (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram27)) + (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram27)) + (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram27)) + (portRef REGCEA (instanceRef f0_ram_Mram_ram29)) + (portRef REGCEB (instanceRef f0_ram_Mram_ram29)) + (portRef RSTA (instanceRef f0_ram_Mram_ram29)) + (portRef RSTB (instanceRef f0_ram_Mram_ram29)) + (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram29)) + (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram29)) + (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram29)) + (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram29)) + (portRef REGCEA (instanceRef f0_ram_Mram_ram25)) + (portRef REGCEB (instanceRef f0_ram_Mram_ram25)) + (portRef RSTA (instanceRef f0_ram_Mram_ram25)) + (portRef RSTB (instanceRef f0_ram_Mram_ram25)) + (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram25)) + (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram25)) + (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram25)) + (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram25)) + (portRef REGCEA (instanceRef f0_ram_Mram_ram24)) + (portRef REGCEB (instanceRef f0_ram_Mram_ram24)) + (portRef RSTA (instanceRef f0_ram_Mram_ram24)) + (portRef RSTB (instanceRef f0_ram_Mram_ram24)) + (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram24)) + (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram24)) + (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram24)) + (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram24)) + (portRef REGCEA (instanceRef f0_ram_Mram_ram26)) + (portRef REGCEB (instanceRef f0_ram_Mram_ram26)) + (portRef RSTA (instanceRef f0_ram_Mram_ram26)) + (portRef RSTB (instanceRef f0_ram_Mram_ram26)) + (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram26)) + (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram26)) + (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram26)) + (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram26)) + (portRef REGCEA (instanceRef f0_ram_Mram_ram22)) + (portRef REGCEB (instanceRef f0_ram_Mram_ram22)) + (portRef RSTA (instanceRef f0_ram_Mram_ram22)) + (portRef RSTB (instanceRef f0_ram_Mram_ram22)) + (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram22)) + (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram22)) + (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram22)) + (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram22)) + (portRef REGCEA (instanceRef f0_ram_Mram_ram21)) + (portRef REGCEB (instanceRef f0_ram_Mram_ram21)) + (portRef RSTA (instanceRef f0_ram_Mram_ram21)) + (portRef RSTB (instanceRef f0_ram_Mram_ram21)) + (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram21)) + (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram21)) + (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram21)) + (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram21)) + (portRef REGCEA (instanceRef f0_ram_Mram_ram23)) + (portRef REGCEB (instanceRef f0_ram_Mram_ram23)) + (portRef RSTA (instanceRef f0_ram_Mram_ram23)) + (portRef RSTB (instanceRef f0_ram_Mram_ram23)) + (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram23)) + (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram23)) + (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram23)) + (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram23)) + (portRef REGCEA (instanceRef f0_ram_Mram_ram19)) + (portRef REGCEB (instanceRef f0_ram_Mram_ram19)) + (portRef RSTA (instanceRef f0_ram_Mram_ram19)) + (portRef RSTB (instanceRef f0_ram_Mram_ram19)) + (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram19)) + (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram19)) + (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram19)) + (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram19)) + (portRef REGCEA (instanceRef f0_ram_Mram_ram18)) + (portRef REGCEB (instanceRef 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f1_ram_Mram_ram20)) + ) + ) + (net (rename tx_tdata_37_ "tx_tdata<37>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_37__srlc32e)) + (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram19)) + ) + ) + (net (rename tx_tdata_36_ "tx_tdata<36>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_36__srlc32e)) + (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram19)) + ) + ) + (net (rename tx_tdata_35_ "tx_tdata<35>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_35__srlc32e)) + (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram18)) + ) + ) + (net (rename tx_tdata_34_ "tx_tdata<34>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_34__srlc32e)) + (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram18)) + ) + ) + (net (rename tx_tdata_33_ "tx_tdata<33>") + (joined + (portRef Q (instanceRef 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f1_ram_Mram_ram15)) + ) + ) + (net (rename tx_tdata_28_ "tx_tdata<28>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_28__srlc32e)) + (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram15)) + ) + ) + (net (rename tx_tdata_27_ "tx_tdata<27>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_27__srlc32e)) + (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram14)) + ) + ) + (net (rename tx_tdata_26_ "tx_tdata<26>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_26__srlc32e)) + (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram14)) + ) + ) + (net (rename tx_tdata_25_ "tx_tdata<25>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_25__srlc32e)) + (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram13)) + ) + ) + (net (rename tx_tdata_24_ "tx_tdata<24>") + (joined + (portRef Q (instanceRef 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f1_ram_Mram_ram11)) + ) + ) + (net (rename tx_tdata_19_ "tx_tdata<19>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_19__srlc32e)) + (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram10)) + ) + ) + (net (rename tx_tdata_18_ "tx_tdata<18>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_18__srlc32e)) + (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram10)) + ) + ) + (net (rename tx_tdata_17_ "tx_tdata<17>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_17__srlc32e)) + (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram9)) + ) + ) + (net (rename tx_tdata_16_ "tx_tdata<16>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_16__srlc32e)) + (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram9)) + ) + ) + (net (rename tx_tdata_15_ "tx_tdata<15>") + (joined + (portRef Q (instanceRef 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f1_ram_Mram_ram6)) + ) + ) + (net (rename tx_tdata_10_ "tx_tdata<10>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_10__srlc32e)) + (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram6)) + ) + ) + (net (rename tx_tdata_9_ "tx_tdata<9>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_9__srlc32e)) + (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram5)) + ) + ) + (net (rename tx_tdata_8_ "tx_tdata<8>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_8__srlc32e)) + (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram5)) + ) + ) + (net (rename tx_tdata_7_ "tx_tdata<7>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_7__srlc32e)) + (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram4)) + ) + ) + (net (rename tx_tdata_6_ "tx_tdata<6>") + (joined + (portRef Q (instanceRef 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) + ) + (net (rename tx_tdata_1_ "tx_tdata<1>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_1__srlc32e)) + (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename tx_tdata_0_ "tx_tdata<0>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_0__srlc32e)) + (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename ctrl_tdata_63_ "ctrl_tdata<63>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e)) + (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram32)) + ) + ) + (net (rename ctrl_tdata_62_ "ctrl_tdata<62>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e)) + (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram32)) + ) + ) + (net (rename ctrl_tdata_61_ "ctrl_tdata<61>") + (joined + (portRef Q (instanceRef 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(member DIA 30) (instanceRef f0_ram_Mram_ram29)) + ) + ) + (net (rename ctrl_tdata_56_ "ctrl_tdata<56>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_56__srlc32e)) + (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram29)) + ) + ) + (net (rename ctrl_tdata_55_ "ctrl_tdata<55>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_55__srlc32e)) + (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram28)) + ) + ) + (net (rename ctrl_tdata_54_ "ctrl_tdata<54>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_54__srlc32e)) + (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram28)) + ) + ) + (net (rename ctrl_tdata_53_ "ctrl_tdata<53>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e)) + (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram27)) + ) + ) + (net (rename ctrl_tdata_52_ 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(portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<14>") + (joined + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14__)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<13>") + (joined + (portRef O (instanceRef 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"slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<11>") + (joined + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11__)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<10>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11__)) + (portRef CI (instanceRef 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"slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<7>") + (joined + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7__)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<6>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7__)) + (portRef CI (instanceRef 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slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_renamed_53)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o5 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o5") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212_renamed_54)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213_renamed_430)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o") + (joined + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full92 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full92") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full921)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o7 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o7") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212_renamed_54)) + (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0121211 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0121211") + (joined + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114_renamed_58)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217_renamed_428)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv3 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv3") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv31)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214_renamed_55)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01211 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01211") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114_renamed_58)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012111") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0121111)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114_renamed_58)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217_renamed_428)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421_FRB") + (joined + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212_renamed_54)) + (portRef I3 (instanceRef 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"slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o8") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112_renamed_501)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<15>") + (joined + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15__)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<14>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<14>") + (joined + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14__)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14__)) + ) + ) + (net (rename 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"slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<12>") + (joined + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12__)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<11>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12__)) + (portRef CI (instanceRef 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"slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<8>") + (joined + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8__)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<7>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<7>") + (joined + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7__)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<6>") + (joined + (portRef O (instanceRef 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slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<5>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<5>") + (joined + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5__)) + (portRef LI (instanceRef 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"slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<4>") + (joined + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4__)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<3>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<3>") + (joined + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3__)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<2>") + (joined + (portRef O (instanceRef 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slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<1>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<1>") + (joined + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1__)) + (portRef LI (instanceRef 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"slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<0>") + (joined + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0__)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_write_AND_42_o_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_write_AND_42_o_inv") + (joined + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0__)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_write_AND_42_o_inv2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1-In") + (joined + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_renamed_25)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr<8>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1)) + (portRef (member ADDRB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr8_FRB") + (joined + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8)) + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr8_FRB_renamed_336)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8__rt_renamed_250)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr<7>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_7)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71)) + (portRef I1 (instanceRef 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"slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<6>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_7__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr<6>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_6)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0121111)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213_renamed_430)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112_renamed_501)) + (portRef (member ADDRB 2) (instanceRef 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"slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<13>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13__)) + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_13_BRB1_renamed_471)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<12>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12__)) + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB1_renamed_470)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<11>") + (joined + (portRef O (instanceRef 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"slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<4>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4__)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<3>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3__)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<2>") + (joined + (portRef O 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slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets<5>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_renamed_60)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_renamed_61)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11)) + (portRef I0 + (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12_renamed_63)) + (portRef I3 + (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211_renamed_416)) + (portRef I3 (instanceRef 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(instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_SW0)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12_renamed_63)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW1)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11)) + (portRef I2 (instanceRef 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I0 + (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_SW0)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_SW0)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12_renamed_63)) + (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + (portRef I2 + (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211_renamed_416)) + (portRef I1 (instanceRef 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slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets<2>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2)) + (portRef I0 + (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12_renamed_63)) + (portRef I0 + (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211_renamed_416)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets<1>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW0)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0)) + (portRef I2 (instanceRef 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I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/clear_dump_OR_154_o") + (joined + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2__)) + (portRef I0 (instanceRef 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(net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_i_tvalid_int "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/i_tvalid_int") + (joined + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_write1)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set_renamed_422)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6)) + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4_renamed_488)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0154_inv1)) + (portRef I5 (instanceRef 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"slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/o_tready_int") + (joined + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set_renamed_421)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot_renamed_511)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o1)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2_renamed_415)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<7>") + (joined + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<6>") + (joined + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<5>") + (joined + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<4>") + (joined + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<3>") + (joined + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<2>") + (joined + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<1>") + (joined + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<0>") + (joined + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0076_inv") + (joined + (portRef O (instanceRef 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+ (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0)) + (portRef I (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT311 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT311") + (joined + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + (portRef I5 + (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211_renamed_416)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>") + (joined + (portRef O + (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<3>") + (joined + (portRef O + (instanceRef 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slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<0>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_0)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In33)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_0__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<1>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_1)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In33)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_1__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<2>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_2)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31_renamed_65)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_2__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<3>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_3)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_3__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<4>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_4)) + (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32_renamed_66)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_4__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<5>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_5)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32_renamed_66)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_5__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<6>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_6)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32_renamed_66)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_6__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<7>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_7)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32_renamed_66)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_7__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<8>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_8)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In33)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_8__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<9>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_9)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In33)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_9__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<10>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_10)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31_renamed_65)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_10__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<11>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_11)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31_renamed_65)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_11__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<12>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_12)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31_renamed_65)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_12__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<13>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_13)) + (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_13__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<14>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_14)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32_renamed_66)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_14__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<15>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_15)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32_renamed_66)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_15__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_renamed_28)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker__n0227_inv1)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11_renamed_67)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_0__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_1__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_2__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_3__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_4__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_5__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_6__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_7__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_8__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_9__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_10__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_11__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_12__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_13__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_14__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_15__)) + (portRef I (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_0__inv1_INV_0)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int11_renamed_62)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW0)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast1)) + (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_G)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_renamed_27)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker__n0227_inv1)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int11_renamed_62)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11_renamed_67)) + (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW0)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast1)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_G)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F)) + ) + ) + (net (rename f1_Mcompar_becoming_full_lut_4_ "f1/Mcompar_becoming_full_lut<4>") + (joined + (portRef O (instanceRef f1_Mcompar_becoming_full_lut_4__)) + (portRef S (instanceRef f1_Mcompar_becoming_full_cy_4__)) + ) + ) + (net (rename f1_Mcompar_becoming_full_cy_3_ "f1/Mcompar_becoming_full_cy<3>") + (joined + (portRef O (instanceRef f1_Mcompar_becoming_full_cy_3__)) + (portRef CI (instanceRef f1_Mcompar_becoming_full_cy_4__)) + ) + ) + (net (rename f1_Mcompar_becoming_full_lut_3_ "f1/Mcompar_becoming_full_lut<3>") + (joined + (portRef O (instanceRef f1_Mcompar_becoming_full_lut_3__)) + (portRef S (instanceRef f1_Mcompar_becoming_full_cy_3__)) + ) + ) + (net (rename f1_Mcompar_becoming_full_cy_2_ "f1/Mcompar_becoming_full_cy<2>") + (joined + (portRef O (instanceRef f1_Mcompar_becoming_full_cy_2__)) + (portRef CI (instanceRef f1_Mcompar_becoming_full_cy_3__)) + ) + ) + (net (rename f1_Mcompar_becoming_full_lut_2_ "f1/Mcompar_becoming_full_lut<2>") + (joined + (portRef O (instanceRef f1_Mcompar_becoming_full_lut_2__)) + (portRef S (instanceRef f1_Mcompar_becoming_full_cy_2__)) + ) + ) + (net (rename f1_Mcompar_becoming_full_cy_1_ "f1/Mcompar_becoming_full_cy<1>") + (joined + (portRef O (instanceRef f1_Mcompar_becoming_full_cy_1__)) + (portRef CI (instanceRef f1_Mcompar_becoming_full_cy_2__)) + ) + ) + (net (rename f1_Mcompar_becoming_full_lut_1_ "f1/Mcompar_becoming_full_lut<1>") + (joined + (portRef O (instanceRef f1_Mcompar_becoming_full_lut_1__)) + (portRef S (instanceRef f1_Mcompar_becoming_full_cy_1__)) + ) + ) + (net (rename f1_Mcompar_becoming_full_cy_0_ "f1/Mcompar_becoming_full_cy<0>") + (joined + (portRef O (instanceRef f1_Mcompar_becoming_full_cy_0__)) + (portRef CI (instanceRef f1_Mcompar_becoming_full_cy_1__)) + ) + ) + (net (rename f1_Mcompar_becoming_full_lut_0_ "f1/Mcompar_becoming_full_lut<0>") + (joined + (portRef O (instanceRef f1_Mcompar_becoming_full_lut_0__)) + (portRef S (instanceRef f1_Mcompar_becoming_full_cy_0__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_10_ "f1/Mcount_rd_addr_cy<10>") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_10__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_cy_11__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_xor_11__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_9_ "f1/Mcount_rd_addr_cy<9>") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_9__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_cy_10__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_xor_10__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_8_ "f1/Mcount_rd_addr_cy<8>") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_8__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_cy_9__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_xor_9__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_7_ "f1/Mcount_rd_addr_cy<7>") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_7__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_cy_8__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_xor_8__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_6_ "f1/Mcount_rd_addr_cy<6>") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_6__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_cy_7__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_xor_7__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_5_ "f1/Mcount_rd_addr_cy<5>") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_5__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_cy_6__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_xor_6__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_4_ "f1/Mcount_rd_addr_cy<4>") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_4__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_cy_5__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_xor_5__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_3_ "f1/Mcount_rd_addr_cy<3>") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_3__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_cy_4__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_xor_4__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_2_ "f1/Mcount_rd_addr_cy<2>") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_2__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_cy_3__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_xor_3__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_1_ "f1/Mcount_rd_addr_cy<1>") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_1__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_cy_2__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_xor_2__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_0_ "f1/Mcount_rd_addr_cy<0>") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_0__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_cy_1__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_xor_1__)) + ) + ) + (net (rename f1_Mcount_rd_addr_lut_0_ "f1/Mcount_rd_addr_lut<0>") + (joined + (portRef S (instanceRef f1_Mcount_rd_addr_cy_0__)) + (portRef LI (instanceRef f1_Mcount_rd_addr_xor_0__)) + (portRef O (instanceRef f1_Mcount_rd_addr_lut_0__INV_0)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_10_ "f1/Mcount_wr_addr_cy<10>") + (joined + (portRef O (instanceRef f1_Mcount_wr_addr_cy_10__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_cy_11__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_xor_11__)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_9_ "f1/Mcount_wr_addr_cy<9>") + (joined + (portRef O (instanceRef f1_Mcount_wr_addr_cy_9__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_cy_10__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_xor_10__)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_8_ "f1/Mcount_wr_addr_cy<8>") + (joined + (portRef O (instanceRef f1_Mcount_wr_addr_cy_8__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_cy_9__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_xor_9__)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_7_ "f1/Mcount_wr_addr_cy<7>") + (joined + (portRef O (instanceRef f1_Mcount_wr_addr_cy_7__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_cy_8__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_xor_8__)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_6_ "f1/Mcount_wr_addr_cy<6>") + (joined + (portRef O (instanceRef f1_Mcount_wr_addr_cy_6__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_cy_7__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_xor_7__)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_5_ "f1/Mcount_wr_addr_cy<5>") + (joined + (portRef O (instanceRef f1_Mcount_wr_addr_cy_5__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_cy_6__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_xor_6__)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_4_ "f1/Mcount_wr_addr_cy<4>") + (joined + (portRef O (instanceRef f1_Mcount_wr_addr_cy_4__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_cy_5__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_xor_5__)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_3_ "f1/Mcount_wr_addr_cy<3>") + (joined + (portRef O (instanceRef f1_Mcount_wr_addr_cy_3__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_cy_4__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_xor_4__)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_2_ "f1/Mcount_wr_addr_cy<2>") + (joined + (portRef O (instanceRef f1_Mcount_wr_addr_cy_2__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_cy_3__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_xor_3__)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_1_ "f1/Mcount_wr_addr_cy<1>") + (joined + (portRef O (instanceRef f1_Mcount_wr_addr_cy_1__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_cy_2__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_xor_2__)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_0_ "f1/Mcount_wr_addr_cy<0>") + (joined + (portRef O (instanceRef f1_Mcount_wr_addr_cy_0__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_cy_1__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_xor_1__)) + ) + ) + (net (rename f1_Mcount_wr_addr_lut_0_ "f1/Mcount_wr_addr_lut<0>") + (joined + (portRef S (instanceRef f1_Mcount_wr_addr_cy_0__)) + (portRef LI (instanceRef f1_Mcount_wr_addr_xor_0__)) + (portRef O (instanceRef f1_Mcount_wr_addr_lut_0__INV_0)) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>") + (joined + (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__)) + (portRef S (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__)) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>") + (joined + (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__)) + (portRef CI (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__)) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>") + (joined + (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef S (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__)) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>") + (joined + (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__)) + (portRef CI (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__)) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>") + (joined + (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef S (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__)) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>") + (joined + (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__)) + (portRef CI (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__)) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>") + (joined + (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef S (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__)) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>") + (joined + (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__)) + (portRef CI (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__)) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>") + (joined + (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef S (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_12_ "f1/Msub_dont_write_past_me_lut<12>") + (joined + (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_12__)) + (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_12__INV_0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_11_ "f1/Msub_dont_write_past_me_lut<11>") + (joined + (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_11__)) + (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_11__)) + (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_11__INV_0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_10_ "f1/Msub_dont_write_past_me_cy<10>") + (joined + (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_10__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_11__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_11__)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_10_ "f1/Msub_dont_write_past_me_lut<10>") + (joined + (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_10__)) + (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_10__)) + (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_10__INV_0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_9_ "f1/Msub_dont_write_past_me_cy<9>") + (joined + (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_9__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_10__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_10__)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_9_ "f1/Msub_dont_write_past_me_lut<9>") + (joined + (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_9__)) + (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_9__)) + (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_9__INV_0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_8_ "f1/Msub_dont_write_past_me_cy<8>") + (joined + (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_8__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_9__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_9__)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_8_ "f1/Msub_dont_write_past_me_lut<8>") + (joined + (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_8__)) + (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_8__)) + (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_8__INV_0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_7_ "f1/Msub_dont_write_past_me_cy<7>") + (joined + (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_7__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_8__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_8__)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_7_ "f1/Msub_dont_write_past_me_lut<7>") + (joined + (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_7__)) + (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_7__)) + (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_7__INV_0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_6_ "f1/Msub_dont_write_past_me_cy<6>") + (joined + (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_6__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_7__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_7__)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_6_ "f1/Msub_dont_write_past_me_lut<6>") + (joined + (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_6__)) + (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_6__)) + (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_6__INV_0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_5_ "f1/Msub_dont_write_past_me_cy<5>") + (joined + (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_5__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_6__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_6__)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_5_ "f1/Msub_dont_write_past_me_lut<5>") + (joined + (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_5__)) + (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_5__)) + (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_5__INV_0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_4_ "f1/Msub_dont_write_past_me_cy<4>") + (joined + (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_4__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_5__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_5__)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_4_ "f1/Msub_dont_write_past_me_lut<4>") + (joined + (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_4__)) + (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_4__)) + (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_4__INV_0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_3_ "f1/Msub_dont_write_past_me_cy<3>") + (joined + (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_3__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_4__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_4__)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_3_ "f1/Msub_dont_write_past_me_lut<3>") + (joined + (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_3__)) + (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_3__)) + (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_3__INV_0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_2_ "f1/Msub_dont_write_past_me_cy<2>") + (joined + (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_2__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_3__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_3__)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_2_ "f1/Msub_dont_write_past_me_lut<2>") + (joined + (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_2__)) + (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_2__)) + (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_2__INV_0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_1_ "f1/Msub_dont_write_past_me_cy<1>") + (joined + (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_1__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_2__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_2__)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_0_ "f1/Msub_dont_write_past_me_cy<0>") + (joined + (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_0__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_1__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_1__)) + ) + ) + (net (rename f1_read_state_FSM_FFd2 "f1/read_state_FSM_FFd2") + (joined + (portRef Q (instanceRef f1_read_state_FSM_FFd2_renamed_30)) + (portRef I0 (instanceRef f1__n0161_inv1_lut1_renamed_508)) + (portRef I2 (instanceRef f1_GND_14_o_read_OR_37_o1)) + (portRef I3 (instanceRef f1_read_state_FSM_FFd1_In111)) + (portRef I5 (instanceRef f1_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename f1_read_state_FSM_FFd2_In "f1/read_state_FSM_FFd2-In") + (joined + (portRef D (instanceRef f1_read_state_FSM_FFd2_renamed_30)) + (portRef O (instanceRef f1_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename f1_read_state_FSM_FFd1_In1 "f1/read_state_FSM_FFd1-In1") + (joined + (portRef D (instanceRef f1_read_state_FSM_FFd1_renamed_29)) + (portRef O (instanceRef f1_read_state_FSM_FFd1_In111)) + ) + ) + (net (rename f1_Result_12_2_FRB "f1/Result<12>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_12)) + (portRef Q (instanceRef f1_Result_12_2_FRB_renamed_349)) + (portRef I0 (instanceRef f1_Mcount_wr_addr_xor_12__rt_renamed_253)) + ) + ) + (net (rename f1_Result_11_2_FRB "f1/Result<11>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_11)) + (portRef Q (instanceRef f1_Result_11_2_FRB_renamed_348)) + (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_11__rt_renamed_207)) + ) + ) + (net (rename f1_Result_10_2_FRB "f1/Result<10>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_10)) + (portRef Q (instanceRef f1_Result_10_2_FRB_renamed_347)) + (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_10__rt_renamed_208)) + ) + ) + (net (rename f1_Result_9_2_FRB "f1/Result<9>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_9)) + (portRef Q (instanceRef f1_Result_9_2_FRB_renamed_346)) + (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_9__rt_renamed_209)) + ) + ) + (net (rename f1_Result_8_2_FRB "f1/Result<8>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_8)) + (portRef Q (instanceRef f1_Result_8_2_FRB_renamed_345)) + (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_8__rt_renamed_210)) + ) + ) + (net (rename f1_Result_7_2_FRB "f1/Result<7>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_7)) + (portRef Q (instanceRef f1_Result_7_2_FRB_renamed_344)) + (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_7__rt_renamed_211)) + ) + ) + (net (rename f1_Result_6_2_FRB "f1/Result<6>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_6)) + (portRef Q (instanceRef f1_Result_6_2_FRB_renamed_343)) + (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_6__rt_renamed_212)) + ) + ) + (net (rename f1_Result_5_2_FRB "f1/Result<5>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_5)) + (portRef Q (instanceRef f1_Result_5_2_FRB_renamed_342)) + (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_5__rt_renamed_213)) + ) + ) + (net (rename f1_Result_4_2_FRB "f1/Result<4>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_4)) + (portRef Q (instanceRef f1_Result_4_2_FRB_renamed_341)) + (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_4__rt_renamed_214)) + ) + ) + (net (rename f1_Result_3_2_FRB "f1/Result<3>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_3)) + (portRef Q (instanceRef f1_Result_3_2_FRB_renamed_340)) + (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_3__rt_renamed_215)) + ) + ) + (net (rename f1_Result_2_2_FRB "f1/Result<2>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_2)) + (portRef Q (instanceRef f1_Result_2_2_FRB_renamed_339)) + (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_2__rt_renamed_216)) + ) + ) + (net (rename f1_Result_1_2_FRB "f1/Result<1>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_1)) + (portRef Q (instanceRef f1_Result_1_2_FRB_renamed_338)) + (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_1__rt_renamed_217)) + ) + ) + (net (rename f1_Result_0_2_FRB "f1/Result<0>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_0)) + (portRef Q (instanceRef f1_Result_0_2_FRB_renamed_337)) + (portRef I (instanceRef f1_Mcount_wr_addr_lut_0__INV_0)) + ) + ) + (net (rename f1_Result_12_1_FRB "f1/Result<12>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_12)) + (portRef Q (instanceRef f1_Result_12_1_FRB_renamed_362)) + (portRef I0 (instanceRef f1_Mcount_rd_addr_xor_12__rt_renamed_252)) + (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_12__INV_0)) + ) + ) + (net (rename f1_Result_11_1_FRB "f1/Result<11>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_11)) + (portRef Q (instanceRef f1_Result_11_1_FRB_renamed_361)) + (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_11__rt_renamed_196)) + (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_11__INV_0)) + ) + ) + (net (rename f1_Result_10_1_FRB "f1/Result<10>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_10)) + (portRef Q (instanceRef f1_Result_10_1_FRB_renamed_360)) + (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_10__rt_renamed_197)) + (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_10__INV_0)) + ) + ) + (net (rename f1_Result_9_1_FRB "f1/Result<9>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_9)) + (portRef Q (instanceRef f1_Result_9_1_FRB_renamed_359)) + (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_9__rt_renamed_198)) + (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_9__INV_0)) + ) + ) + (net (rename f1_Result_8_1_FRB "f1/Result<8>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_8)) + (portRef Q (instanceRef f1_Result_8_1_FRB_renamed_358)) + (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_8__rt_renamed_199)) + (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_8__INV_0)) + ) + ) + (net (rename f1_Result_7_1_FRB "f1/Result<7>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_7)) + (portRef Q (instanceRef f1_Result_7_1_FRB_renamed_357)) + (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_7__rt_renamed_200)) + (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_7__INV_0)) + ) + ) + (net (rename f1_Result_6_1_FRB "f1/Result<6>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_6)) + (portRef Q (instanceRef f1_Result_6_1_FRB_renamed_356)) + (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_6__rt_renamed_201)) + (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_6__INV_0)) + ) + ) + (net (rename f1_Result_5_1_FRB "f1/Result<5>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_5)) + (portRef Q (instanceRef f1_Result_5_1_FRB_renamed_355)) + (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_5__rt_renamed_202)) + (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_5__INV_0)) + ) + ) + (net (rename f1_Result_4_1_FRB "f1/Result<4>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_4)) + (portRef Q (instanceRef f1_Result_4_1_FRB_renamed_354)) + (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_4__rt_renamed_203)) + (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_4__INV_0)) + ) + ) + (net (rename f1_Result_3_1_FRB "f1/Result<3>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_3)) + (portRef Q (instanceRef f1_Result_3_1_FRB_renamed_353)) + (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_3__rt_renamed_204)) + (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_3__INV_0)) + ) + ) + (net (rename f1_Result_2_1_FRB "f1/Result<2>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_2)) + (portRef Q (instanceRef f1_Result_2_1_FRB_renamed_352)) + (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_2__rt_renamed_205)) + (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_2__INV_0)) + ) + ) + (net (rename f1_Result_1_1_FRB "f1/Result<1>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_1)) + (portRef Q (instanceRef f1_Result_1_1_FRB_renamed_351)) + (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_1__rt_renamed_206)) + (portRef I0 (instanceRef f1_Msub_dont_write_past_me_cy_1__rt_renamed_218)) + ) + ) + (net (rename f1_Result_0_1_FRB "f1/Result<0>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_0)) + (portRef Q (instanceRef f1_Result_0_1_FRB_renamed_350)) + (portRef I0 (instanceRef f1_Msub_dont_write_past_me_cy_0__rt_renamed_219)) + (portRef I (instanceRef f1_Mcount_rd_addr_lut_0__INV_0)) + ) + ) + (net (rename f1__n0161_inv "f1/_n0161_inv") + (joined + (portRef CE (instanceRef f1_rd_addr_1)) + (portRef CE (instanceRef f1_rd_addr_2)) + (portRef CE (instanceRef f1_rd_addr_3)) + (portRef CE (instanceRef f1_rd_addr_4)) + (portRef CE (instanceRef f1_rd_addr_5)) + (portRef CE (instanceRef f1_rd_addr_6)) + (portRef CE (instanceRef f1_rd_addr_7)) + (portRef CE (instanceRef f1_rd_addr_8)) + (portRef CE (instanceRef f1_rd_addr_9)) + (portRef CE (instanceRef f1_rd_addr_10)) + (portRef CE (instanceRef f1_rd_addr_11)) + (portRef CE (instanceRef f1_rd_addr_12)) + (portRef CE (instanceRef f1_rd_addr_0)) + (portRef CE (instanceRef f1_Result_0_1_FRB_renamed_350)) + (portRef CE (instanceRef f1_Result_1_1_FRB_renamed_351)) + (portRef CE (instanceRef f1_Result_2_1_FRB_renamed_352)) + (portRef CE (instanceRef f1_Result_3_1_FRB_renamed_353)) + (portRef CE (instanceRef f1_Result_4_1_FRB_renamed_354)) + (portRef CE (instanceRef f1_Result_5_1_FRB_renamed_355)) + (portRef CE (instanceRef f1_Result_6_1_FRB_renamed_356)) + (portRef CE (instanceRef f1_Result_7_1_FRB_renamed_357)) + (portRef CE (instanceRef f1_Result_8_1_FRB_renamed_358)) + (portRef CE (instanceRef f1_Result_9_1_FRB_renamed_359)) + (portRef CE (instanceRef f1_Result_10_1_FRB_renamed_360)) + (portRef CE (instanceRef f1_Result_11_1_FRB_renamed_361)) + (portRef CE (instanceRef f1_Result_12_1_FRB_renamed_362)) + (portRef CE (instanceRef f1_dont_write_past_me_0__FRB_renamed_363)) + (portRef CE (instanceRef f1_dont_write_past_me_1__FRB_renamed_364)) + (portRef CE (instanceRef f1_dont_write_past_me_2__FRB_renamed_365)) + (portRef CE (instanceRef f1_dont_write_past_me_3__FRB_renamed_366)) + (portRef CE (instanceRef f1_dont_write_past_me_4__FRB_renamed_367)) + (portRef CE (instanceRef f1_dont_write_past_me_5__FRB_renamed_368)) + (portRef CE (instanceRef f1_dont_write_past_me_6__FRB_renamed_369)) + (portRef CE (instanceRef f1_dont_write_past_me_7__FRB_renamed_370)) + (portRef CE (instanceRef f1_dont_write_past_me_8__FRB_renamed_371)) + (portRef CE (instanceRef f1_dont_write_past_me_9__FRB_renamed_372)) + (portRef CE (instanceRef f1_dont_write_past_me_10__FRB_renamed_373)) + (portRef CE (instanceRef f1_dont_write_past_me_11__FRB_renamed_374)) + (portRef CE (instanceRef f1_dont_write_past_me_12__FRB_renamed_375)) + (portRef O (instanceRef f1__n0161_inv1_cy1)) + ) + ) + (net (rename f1_becoming_full "f1/becoming_full") + (joined + (portRef O (instanceRef f1_Mcompar_becoming_full_cy_4__)) + (portRef I1 (instanceRef f1_full_reg_glue_set_renamed_537)) + ) + ) + (net (rename f1_rd_addr_12__wr_addr_12__equal_11_o "f1/rd_addr[12]_wr_addr[12]_equal_11_o") + (joined + (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__)) + (portRef CI (instanceRef f1__n0161_inv1_cy)) + (portRef I2 (instanceRef f1_read_state_FSM_FFd1_In111)) + (portRef I1 (instanceRef f1_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename f1_dont_write_past_me_0__FRB "f1/dont_write_past_me<0>_FRB") + (joined + (portRef I1 (instanceRef f1_Mcompar_becoming_full_lut_0__)) + (portRef Q (instanceRef f1_dont_write_past_me_0__FRB_renamed_363)) + ) + ) + (net (rename f1_dont_write_past_me_1__FRB "f1/dont_write_past_me<1>_FRB") + (joined + (portRef I3 (instanceRef f1_Mcompar_becoming_full_lut_0__)) + (portRef Q (instanceRef f1_dont_write_past_me_1__FRB_renamed_364)) + ) + ) + (net (rename f1_dont_write_past_me_2__FRB "f1/dont_write_past_me<2>_FRB") + (joined + (portRef I5 (instanceRef f1_Mcompar_becoming_full_lut_0__)) + (portRef Q (instanceRef f1_dont_write_past_me_2__FRB_renamed_365)) + ) + ) + (net (rename f1_dont_write_past_me_3__FRB "f1/dont_write_past_me<3>_FRB") + (joined + (portRef I1 (instanceRef f1_Mcompar_becoming_full_lut_1__)) + (portRef Q (instanceRef f1_dont_write_past_me_3__FRB_renamed_366)) + ) + ) + (net (rename f1_dont_write_past_me_4__FRB "f1/dont_write_past_me<4>_FRB") + (joined + (portRef I3 (instanceRef f1_Mcompar_becoming_full_lut_1__)) + (portRef Q (instanceRef f1_dont_write_past_me_4__FRB_renamed_367)) + ) + ) + (net (rename f1_dont_write_past_me_5__FRB "f1/dont_write_past_me<5>_FRB") + (joined + (portRef I5 (instanceRef f1_Mcompar_becoming_full_lut_1__)) + (portRef Q (instanceRef f1_dont_write_past_me_5__FRB_renamed_368)) + ) + ) + (net (rename f1_dont_write_past_me_6__FRB "f1/dont_write_past_me<6>_FRB") + (joined + (portRef I1 (instanceRef f1_Mcompar_becoming_full_lut_2__)) + (portRef Q (instanceRef f1_dont_write_past_me_6__FRB_renamed_369)) + ) + ) + (net (rename f1_dont_write_past_me_7__FRB "f1/dont_write_past_me<7>_FRB") + (joined + (portRef I3 (instanceRef f1_Mcompar_becoming_full_lut_2__)) + (portRef Q (instanceRef f1_dont_write_past_me_7__FRB_renamed_370)) + ) + ) + (net (rename f1_dont_write_past_me_8__FRB "f1/dont_write_past_me<8>_FRB") + (joined + (portRef I5 (instanceRef f1_Mcompar_becoming_full_lut_2__)) + (portRef Q (instanceRef f1_dont_write_past_me_8__FRB_renamed_371)) + ) + ) + (net (rename f1_dont_write_past_me_9__FRB "f1/dont_write_past_me<9>_FRB") + (joined + (portRef I1 (instanceRef f1_Mcompar_becoming_full_lut_3__)) + (portRef Q (instanceRef f1_dont_write_past_me_9__FRB_renamed_372)) + ) + ) + (net (rename f1_dont_write_past_me_10__FRB "f1/dont_write_past_me<10>_FRB") + (joined + (portRef I3 (instanceRef f1_Mcompar_becoming_full_lut_3__)) + (portRef Q (instanceRef f1_dont_write_past_me_10__FRB_renamed_373)) + ) + ) + (net (rename f1_dont_write_past_me_11__FRB "f1/dont_write_past_me<11>_FRB") + (joined + (portRef I5 (instanceRef f1_Mcompar_becoming_full_lut_3__)) + (portRef Q (instanceRef f1_dont_write_past_me_11__FRB_renamed_374)) + ) + ) + (net (rename f1_dont_write_past_me_12__FRB "f1/dont_write_past_me<12>_FRB") + (joined + (portRef I1 (instanceRef f1_Mcompar_becoming_full_lut_4__)) + (portRef Q (instanceRef f1_dont_write_past_me_12__FRB_renamed_375)) + ) + ) + (net (rename f1_GND_14_o_read_OR_37_o "f1/GND_14_o_read_OR_37_o") + (joined + (portRef O (instanceRef f1_GND_14_o_read_OR_37_o1)) + (portRef ENBRDEN (instanceRef f1_ram_Mram_ram33)) + (portRef ENB (instanceRef f1_ram_Mram_ram31)) + (portRef ENB (instanceRef f1_ram_Mram_ram30)) + (portRef ENB (instanceRef f1_ram_Mram_ram32)) + (portRef ENB (instanceRef f1_ram_Mram_ram28)) + (portRef ENB (instanceRef f1_ram_Mram_ram27)) + (portRef ENB (instanceRef f1_ram_Mram_ram29)) + (portRef ENB (instanceRef f1_ram_Mram_ram25)) + (portRef ENB (instanceRef f1_ram_Mram_ram24)) + (portRef ENB (instanceRef f1_ram_Mram_ram26)) + (portRef ENB (instanceRef f1_ram_Mram_ram22)) + (portRef ENB (instanceRef f1_ram_Mram_ram21)) + (portRef ENB (instanceRef f1_ram_Mram_ram23)) + (portRef ENB (instanceRef f1_ram_Mram_ram19)) + (portRef ENB (instanceRef f1_ram_Mram_ram18)) + (portRef ENB (instanceRef f1_ram_Mram_ram20)) + (portRef ENB (instanceRef f1_ram_Mram_ram16)) + (portRef ENB (instanceRef f1_ram_Mram_ram15)) + (portRef ENB (instanceRef f1_ram_Mram_ram17)) + (portRef ENB (instanceRef f1_ram_Mram_ram14)) + (portRef ENB (instanceRef f1_ram_Mram_ram13)) + (portRef ENB (instanceRef f1_ram_Mram_ram12)) + (portRef ENB (instanceRef f1_ram_Mram_ram11)) + (portRef ENB (instanceRef f1_ram_Mram_ram9)) + (portRef ENB (instanceRef f1_ram_Mram_ram8)) + (portRef ENB (instanceRef f1_ram_Mram_ram10)) + (portRef ENB (instanceRef f1_ram_Mram_ram6)) + (portRef ENB (instanceRef f1_ram_Mram_ram5)) + (portRef ENB (instanceRef f1_ram_Mram_ram7)) + (portRef ENB (instanceRef f1_ram_Mram_ram3)) + (portRef ENB (instanceRef f1_ram_Mram_ram2)) + (portRef ENB (instanceRef f1_ram_Mram_ram4)) + (portRef ENB (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_write "f1/write") + (joined + (portRef CE (instanceRef f1_wr_addr_1)) + (portRef CE (instanceRef f1_wr_addr_2)) + (portRef CE (instanceRef f1_wr_addr_3)) + (portRef CE (instanceRef f1_wr_addr_4)) + (portRef CE (instanceRef f1_wr_addr_5)) + (portRef CE (instanceRef f1_wr_addr_6)) + (portRef CE (instanceRef f1_wr_addr_7)) + (portRef CE (instanceRef f1_wr_addr_8)) + (portRef CE (instanceRef f1_wr_addr_9)) + (portRef CE (instanceRef f1_wr_addr_10)) + (portRef CE (instanceRef f1_wr_addr_11)) + (portRef CE (instanceRef f1_wr_addr_12)) + (portRef CE (instanceRef f1_wr_addr_0)) + (portRef O (instanceRef f1_write11)) + (portRef CE (instanceRef f1_Result_0_2_FRB_renamed_337)) + (portRef CE (instanceRef f1_Result_1_2_FRB_renamed_338)) + (portRef CE (instanceRef f1_Result_2_2_FRB_renamed_339)) + (portRef CE (instanceRef f1_Result_3_2_FRB_renamed_340)) + (portRef CE (instanceRef f1_Result_4_2_FRB_renamed_341)) + (portRef CE (instanceRef f1_Result_5_2_FRB_renamed_342)) + (portRef CE (instanceRef f1_Result_6_2_FRB_renamed_343)) + (portRef CE (instanceRef f1_Result_7_2_FRB_renamed_344)) + (portRef CE (instanceRef f1_Result_8_2_FRB_renamed_345)) + (portRef CE (instanceRef f1_Result_9_2_FRB_renamed_346)) + (portRef CE (instanceRef f1_Result_10_2_FRB_renamed_347)) + (portRef CE (instanceRef f1_Result_11_2_FRB_renamed_348)) + (portRef CE (instanceRef f1_Result_12_2_FRB_renamed_349)) + (portRef (member WEAWEL 1) (instanceRef f1_ram_Mram_ram33)) + (portRef (member WEAWEL 0) (instanceRef f1_ram_Mram_ram33)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram31)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram31)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram31)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram31)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram30)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram30)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram30)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram30)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram32)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram32)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram32)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram32)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram28)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram28)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram28)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram28)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram27)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram27)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram27)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram27)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram29)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram29)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram29)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram29)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram25)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram25)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram25)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram25)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram24)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram24)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram24)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram24)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram26)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram26)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram26)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram26)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram22)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram22)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram22)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram22)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram21)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram21)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram21)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram21)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram23)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram23)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram23)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram23)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram19)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram19)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram19)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram19)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram18)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram18)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram18)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram18)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram20)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram20)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram20)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram20)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram16)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram16)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram16)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram16)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram15)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram15)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram15)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram15)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram17)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram17)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram17)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram17)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram14)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram14)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram14)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram14)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram13)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram13)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram13)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram13)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram12)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram12)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram12)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram12)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram11)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram11)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram11)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram11)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram9)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram9)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram9)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram9)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram8)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram8)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram8)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram8)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram10)) + (portRef (member WEA 2) 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(instanceRef f1_ram_Mram_ram3)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram3)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram2)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram2)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram2)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram2)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram4)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram4)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram4)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram4)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram1)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram1)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram1)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_0_ "f1/wr_addr<0>") + (joined + (portRef Q (instanceRef f1_wr_addr_0)) + (portRef I1 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef I0 (instanceRef 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f1_ram_Mram_ram4)) + (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_1_ "f1/wr_addr<1>") + (joined + (portRef Q (instanceRef f1_wr_addr_1)) + (portRef I3 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef I2 (instanceRef f1_Mcompar_becoming_full_lut_0__)) + (portRef (member ADDRAWRADDR 11) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRA 11) (instanceRef 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(portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_4_ "f1/wr_addr<4>") + (joined + (portRef Q (instanceRef f1_wr_addr_4)) + (portRef I3 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef I2 (instanceRef f1_Mcompar_becoming_full_lut_1__)) + (portRef (member ADDRAWRADDR 8) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_5_ "f1/wr_addr<5>") + (joined + (portRef Q (instanceRef f1_wr_addr_5)) + (portRef I5 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef I4 (instanceRef f1_Mcompar_becoming_full_lut_1__)) + (portRef (member ADDRAWRADDR 7) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_6_ "f1/wr_addr<6>") + (joined + (portRef Q (instanceRef f1_wr_addr_6)) + (portRef I1 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef I0 (instanceRef f1_Mcompar_becoming_full_lut_2__)) + (portRef (member ADDRAWRADDR 6) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_7_ "f1/wr_addr<7>") + (joined + (portRef Q (instanceRef f1_wr_addr_7)) + (portRef I3 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef I2 (instanceRef f1_Mcompar_becoming_full_lut_2__)) + (portRef (member ADDRAWRADDR 5) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_8_ "f1/wr_addr<8>") + (joined + (portRef Q (instanceRef f1_wr_addr_8)) + (portRef I5 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef I4 (instanceRef f1_Mcompar_becoming_full_lut_2__)) + (portRef (member ADDRAWRADDR 4) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_9_ "f1/wr_addr<9>") + (joined + (portRef Q (instanceRef f1_wr_addr_9)) + (portRef I1 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef I0 (instanceRef f1_Mcompar_becoming_full_lut_3__)) + (portRef (member ADDRAWRADDR 3) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_10_ "f1/wr_addr<10>") + (joined + (portRef Q (instanceRef f1_wr_addr_10)) + (portRef I3 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef I2 (instanceRef f1_Mcompar_becoming_full_lut_3__)) + (portRef (member ADDRAWRADDR 2) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_11_ "f1/wr_addr<11>") + (joined + (portRef Q (instanceRef f1_wr_addr_11)) + (portRef I5 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef I4 (instanceRef f1_Mcompar_becoming_full_lut_3__)) + (portRef (member ADDRAWRADDR 1) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_12_ "f1/wr_addr<12>") + (joined + (portRef Q (instanceRef f1_wr_addr_12)) + (portRef I1 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__)) + (portRef I0 (instanceRef f1_Mcompar_becoming_full_lut_4__)) + (portRef (member ADDRAWRADDR 0) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_0_ "f1/rd_addr<0>") + (joined + (portRef Q (instanceRef f1_rd_addr_0)) + (portRef I0 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef (member ADDRBRDADDR 12) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_1_ "f1/rd_addr<1>") + (joined + (portRef Q (instanceRef f1_rd_addr_1)) + (portRef I2 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef (member ADDRBRDADDR 11) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_2_ "f1/rd_addr<2>") + (joined + (portRef Q (instanceRef f1_rd_addr_2)) + (portRef I4 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef (member ADDRBRDADDR 10) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_3_ "f1/rd_addr<3>") + (joined + (portRef Q (instanceRef f1_rd_addr_3)) + (portRef I0 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef (member ADDRBRDADDR 9) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_4_ "f1/rd_addr<4>") + (joined + (portRef Q (instanceRef f1_rd_addr_4)) + (portRef I2 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef (member ADDRBRDADDR 8) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_5_ "f1/rd_addr<5>") + (joined + (portRef Q (instanceRef f1_rd_addr_5)) + (portRef I4 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef (member ADDRBRDADDR 7) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_6_ "f1/rd_addr<6>") + (joined + (portRef Q (instanceRef f1_rd_addr_6)) + (portRef I0 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef (member ADDRBRDADDR 6) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_7_ "f1/rd_addr<7>") + (joined + (portRef Q (instanceRef f1_rd_addr_7)) + (portRef I2 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef (member ADDRBRDADDR 5) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_8_ "f1/rd_addr<8>") + (joined + (portRef Q (instanceRef f1_rd_addr_8)) + (portRef I4 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef (member ADDRBRDADDR 4) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_9_ "f1/rd_addr<9>") + (joined + (portRef Q (instanceRef f1_rd_addr_9)) + (portRef I0 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef (member ADDRBRDADDR 3) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_10_ "f1/rd_addr<10>") + (joined + (portRef Q (instanceRef f1_rd_addr_10)) + (portRef I2 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef (member ADDRBRDADDR 2) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_11_ "f1/rd_addr<11>") + (joined + (portRef Q (instanceRef f1_rd_addr_11)) + (portRef I4 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef (member ADDRBRDADDR 1) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_12_ "f1/rd_addr<12>") + (joined + (portRef Q (instanceRef f1_rd_addr_12)) + (portRef I0 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__)) + (portRef (member ADDRBRDADDR 0) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_full_reg "f1/full_reg") + (joined + (portRef I1 (instanceRef f1_write11)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW0)) + (portRef Q (instanceRef f1_full_reg_renamed_116)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_renamed_417)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set_renamed_419)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111_SW0)) + (portRef I4 (instanceRef f1_read_state_FSM_FFd2_In1)) + (portRef I4 (instanceRef f1_full_reg_glue_set_renamed_537)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv_renamed_39)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111)) + ) + ) + (net (rename f1_read_state_FSM_FFd1 "f1/read_state_FSM_FFd1") + (joined + (portRef Q (instanceRef f1_read_state_FSM_FFd1_renamed_29)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_111)) + (portRef I1 (instanceRef f1__n0161_inv1_lut_renamed_507)) + (portRef I1 (instanceRef f1__n0161_inv1_lut1_renamed_508)) + (portRef I0 (instanceRef f1_GND_14_o_read_OR_37_o1)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_write1)) + (portRef I0 (instanceRef f1_read_state_FSM_FFd1_In111)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv_renamed_525)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set_renamed_530)) + (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_renamed_535)) + (portRef I0 (instanceRef f1_read_state_FSM_FFd2_In1)) + (portRef I3 (instanceRef f1_full_reg_glue_set_renamed_537)) + ) + ) + (net (rename f0_Mcompar_becoming_full_lut_4_ "f0/Mcompar_becoming_full_lut<4>") + (joined + (portRef O (instanceRef f0_Mcompar_becoming_full_lut_4__)) + (portRef S (instanceRef f0_Mcompar_becoming_full_cy_4__)) + ) + ) + (net (rename f0_Mcompar_becoming_full_cy_3_ "f0/Mcompar_becoming_full_cy<3>") + (joined + (portRef O (instanceRef f0_Mcompar_becoming_full_cy_3__)) + (portRef CI (instanceRef f0_Mcompar_becoming_full_cy_4__)) + ) + ) + (net (rename f0_Mcompar_becoming_full_lut_3_ "f0/Mcompar_becoming_full_lut<3>") + (joined + (portRef O (instanceRef f0_Mcompar_becoming_full_lut_3__)) + (portRef S (instanceRef f0_Mcompar_becoming_full_cy_3__)) + ) + ) + (net (rename f0_Mcompar_becoming_full_cy_2_ "f0/Mcompar_becoming_full_cy<2>") + (joined + (portRef O (instanceRef f0_Mcompar_becoming_full_cy_2__)) + (portRef CI (instanceRef f0_Mcompar_becoming_full_cy_3__)) + ) + ) + (net (rename f0_Mcompar_becoming_full_lut_2_ "f0/Mcompar_becoming_full_lut<2>") + (joined + (portRef O (instanceRef f0_Mcompar_becoming_full_lut_2__)) + (portRef S (instanceRef f0_Mcompar_becoming_full_cy_2__)) + ) + ) + (net (rename f0_Mcompar_becoming_full_cy_1_ "f0/Mcompar_becoming_full_cy<1>") + (joined + (portRef O (instanceRef f0_Mcompar_becoming_full_cy_1__)) + (portRef CI (instanceRef f0_Mcompar_becoming_full_cy_2__)) + ) + ) + (net (rename f0_Mcompar_becoming_full_lut_1_ "f0/Mcompar_becoming_full_lut<1>") + (joined + (portRef O (instanceRef f0_Mcompar_becoming_full_lut_1__)) + (portRef S (instanceRef f0_Mcompar_becoming_full_cy_1__)) + ) + ) + (net (rename f0_Mcompar_becoming_full_cy_0_ "f0/Mcompar_becoming_full_cy<0>") + (joined + (portRef O (instanceRef f0_Mcompar_becoming_full_cy_0__)) + (portRef CI (instanceRef f0_Mcompar_becoming_full_cy_1__)) + ) + ) + (net (rename f0_Mcompar_becoming_full_lut_0_ "f0/Mcompar_becoming_full_lut<0>") + (joined + (portRef O (instanceRef f0_Mcompar_becoming_full_lut_0__)) + (portRef S (instanceRef f0_Mcompar_becoming_full_cy_0__)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_10_ "f0/Mcount_rd_addr_cy<10>") + (joined + (portRef O (instanceRef f0_Mcount_rd_addr_cy_10__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_cy_11__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_xor_11__)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_9_ "f0/Mcount_rd_addr_cy<9>") + (joined + (portRef O (instanceRef f0_Mcount_rd_addr_cy_9__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_cy_10__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_xor_10__)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_8_ "f0/Mcount_rd_addr_cy<8>") + (joined + (portRef O (instanceRef f0_Mcount_rd_addr_cy_8__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_cy_9__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_xor_9__)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_7_ "f0/Mcount_rd_addr_cy<7>") + (joined + (portRef O (instanceRef f0_Mcount_rd_addr_cy_7__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_cy_8__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_xor_8__)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_6_ "f0/Mcount_rd_addr_cy<6>") + (joined + (portRef O (instanceRef f0_Mcount_rd_addr_cy_6__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_cy_7__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_xor_7__)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_5_ "f0/Mcount_rd_addr_cy<5>") + (joined + (portRef O (instanceRef f0_Mcount_rd_addr_cy_5__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_cy_6__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_xor_6__)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_4_ "f0/Mcount_rd_addr_cy<4>") + (joined + (portRef O (instanceRef f0_Mcount_rd_addr_cy_4__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_cy_5__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_xor_5__)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_3_ "f0/Mcount_rd_addr_cy<3>") + (joined + (portRef O (instanceRef f0_Mcount_rd_addr_cy_3__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_cy_4__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_xor_4__)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_2_ "f0/Mcount_rd_addr_cy<2>") + (joined + (portRef O (instanceRef f0_Mcount_rd_addr_cy_2__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_cy_3__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_xor_3__)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_1_ "f0/Mcount_rd_addr_cy<1>") + (joined + (portRef O (instanceRef f0_Mcount_rd_addr_cy_1__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_cy_2__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_xor_2__)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_0_ "f0/Mcount_rd_addr_cy<0>") + (joined + (portRef O (instanceRef f0_Mcount_rd_addr_cy_0__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_cy_1__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_xor_1__)) + ) + ) + (net (rename f0_Mcount_rd_addr_lut_0_ "f0/Mcount_rd_addr_lut<0>") + (joined + (portRef S (instanceRef f0_Mcount_rd_addr_cy_0__)) + (portRef LI (instanceRef f0_Mcount_rd_addr_xor_0__)) + (portRef O (instanceRef f0_Mcount_rd_addr_lut_0__INV_0)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_10_ "f0/Mcount_wr_addr_cy<10>") + (joined + (portRef O (instanceRef f0_Mcount_wr_addr_cy_10__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_cy_11__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_xor_11__)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_9_ "f0/Mcount_wr_addr_cy<9>") + (joined + (portRef O (instanceRef f0_Mcount_wr_addr_cy_9__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_cy_10__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_xor_10__)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_8_ "f0/Mcount_wr_addr_cy<8>") + (joined + (portRef O (instanceRef f0_Mcount_wr_addr_cy_8__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_cy_9__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_xor_9__)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_7_ "f0/Mcount_wr_addr_cy<7>") + (joined + (portRef O (instanceRef f0_Mcount_wr_addr_cy_7__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_cy_8__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_xor_8__)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_6_ "f0/Mcount_wr_addr_cy<6>") + (joined + (portRef O (instanceRef f0_Mcount_wr_addr_cy_6__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_cy_7__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_xor_7__)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_5_ "f0/Mcount_wr_addr_cy<5>") + (joined + (portRef O (instanceRef f0_Mcount_wr_addr_cy_5__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_cy_6__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_xor_6__)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_4_ "f0/Mcount_wr_addr_cy<4>") + (joined + (portRef O (instanceRef f0_Mcount_wr_addr_cy_4__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_cy_5__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_xor_5__)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_3_ "f0/Mcount_wr_addr_cy<3>") + (joined + (portRef O (instanceRef f0_Mcount_wr_addr_cy_3__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_cy_4__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_xor_4__)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_2_ "f0/Mcount_wr_addr_cy<2>") + (joined + (portRef O (instanceRef f0_Mcount_wr_addr_cy_2__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_cy_3__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_xor_3__)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_1_ "f0/Mcount_wr_addr_cy<1>") + (joined + (portRef O (instanceRef f0_Mcount_wr_addr_cy_1__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_cy_2__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_xor_2__)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_0_ "f0/Mcount_wr_addr_cy<0>") + (joined + (portRef O (instanceRef f0_Mcount_wr_addr_cy_0__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_cy_1__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_xor_1__)) + ) + ) + (net (rename f0_Mcount_wr_addr_lut_0_ "f0/Mcount_wr_addr_lut<0>") + (joined + (portRef S (instanceRef f0_Mcount_wr_addr_cy_0__)) + (portRef LI (instanceRef f0_Mcount_wr_addr_xor_0__)) + (portRef O (instanceRef f0_Mcount_wr_addr_lut_0__INV_0)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>") + (joined + (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__)) + (portRef S (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>") + (joined + (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__)) + (portRef CI (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>") + (joined + (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef S (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>") + (joined + (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__)) + (portRef CI (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>") + (joined + (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef S (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>") + (joined + (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__)) + (portRef CI (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>") + (joined + (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef S (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>") + (joined + (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__)) + (portRef CI (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>") + (joined + (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef S (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_12_ "f0/Msub_dont_write_past_me_lut<12>") + (joined + (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_12__)) + (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_12__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_11_ "f0/Msub_dont_write_past_me_lut<11>") + (joined + (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_11__)) + (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_11__)) + (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_11__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_10_ "f0/Msub_dont_write_past_me_cy<10>") + (joined + (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_10__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_11__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_11__)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_10_ "f0/Msub_dont_write_past_me_lut<10>") + (joined + (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_10__)) + (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_10__)) + (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_10__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_9_ "f0/Msub_dont_write_past_me_cy<9>") + (joined + (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_9__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_10__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_10__)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_9_ "f0/Msub_dont_write_past_me_lut<9>") + (joined + (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_9__)) + (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_9__)) + (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_9__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_8_ "f0/Msub_dont_write_past_me_cy<8>") + (joined + (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_8__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_9__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_9__)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_8_ "f0/Msub_dont_write_past_me_lut<8>") + (joined + (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_8__)) + (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_8__)) + (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_8__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_7_ "f0/Msub_dont_write_past_me_cy<7>") + (joined + (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_7__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_8__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_8__)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_7_ "f0/Msub_dont_write_past_me_lut<7>") + (joined + (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_7__)) + (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_7__)) + (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_7__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_6_ "f0/Msub_dont_write_past_me_cy<6>") + (joined + (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_6__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_7__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_7__)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_6_ "f0/Msub_dont_write_past_me_lut<6>") + (joined + (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_6__)) + (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_6__)) + (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_6__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_5_ "f0/Msub_dont_write_past_me_cy<5>") + (joined + (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_5__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_6__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_6__)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_5_ "f0/Msub_dont_write_past_me_lut<5>") + (joined + (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_5__)) + (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_5__)) + (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_5__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_4_ "f0/Msub_dont_write_past_me_cy<4>") + (joined + (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_4__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_5__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_5__)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_4_ "f0/Msub_dont_write_past_me_lut<4>") + (joined + (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_4__)) + (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_4__)) + (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_4__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_3_ "f0/Msub_dont_write_past_me_cy<3>") + (joined + (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_3__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_4__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_4__)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_3_ "f0/Msub_dont_write_past_me_lut<3>") + (joined + (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_3__)) + (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_3__)) + (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_3__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_2_ "f0/Msub_dont_write_past_me_cy<2>") + (joined + (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_2__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_3__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_3__)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_2_ "f0/Msub_dont_write_past_me_lut<2>") + (joined + (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_2__)) + (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_2__)) + (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_2__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_1_ "f0/Msub_dont_write_past_me_cy<1>") + (joined + (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_1__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_2__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_2__)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_0_ "f0/Msub_dont_write_past_me_cy<0>") + (joined + (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_0__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_1__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_1__)) + ) + ) + (net (rename f0_read_state_FSM_FFd2 "f0/read_state_FSM_FFd2") + (joined + (portRef Q (instanceRef f0_read_state_FSM_FFd2_renamed_32)) + (portRef I0 (instanceRef f0__n0161_inv1_lut1_renamed_510)) + (portRef I2 (instanceRef f0_GND_14_o_read_OR_37_o1)) + (portRef I3 (instanceRef f0_read_state_FSM_FFd1_In111)) + (portRef I5 (instanceRef f0_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename f0_read_state_FSM_FFd2_In "f0/read_state_FSM_FFd2-In") + (joined + (portRef D (instanceRef f0_read_state_FSM_FFd2_renamed_32)) + (portRef O (instanceRef f0_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename f0_read_state_FSM_FFd1_In1 "f0/read_state_FSM_FFd1-In1") + (joined + (portRef D (instanceRef f0_read_state_FSM_FFd1_renamed_31)) + (portRef O (instanceRef f0_read_state_FSM_FFd1_In111)) + ) + ) + (net (rename f0_Result_12_2_FRB "f0/Result<12>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_12)) + (portRef Q (instanceRef f0_Result_12_2_FRB_renamed_388)) + (portRef I0 (instanceRef f0_Mcount_wr_addr_xor_12__rt_renamed_255)) + ) + ) + (net (rename f0_Result_11_2_FRB "f0/Result<11>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_11)) + (portRef Q (instanceRef f0_Result_11_2_FRB_renamed_387)) + (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_11__rt_renamed_231)) + ) + ) + (net (rename f0_Result_10_2_FRB "f0/Result<10>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_10)) + (portRef Q (instanceRef f0_Result_10_2_FRB_renamed_386)) + (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_10__rt_renamed_232)) + ) + ) + (net (rename f0_Result_9_2_FRB "f0/Result<9>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_9)) + (portRef Q (instanceRef f0_Result_9_2_FRB_renamed_385)) + (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_9__rt_renamed_233)) + ) + ) + (net (rename f0_Result_8_2_FRB "f0/Result<8>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_8)) + (portRef Q (instanceRef f0_Result_8_2_FRB_renamed_384)) + (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_8__rt_renamed_234)) + ) + ) + (net (rename f0_Result_7_2_FRB "f0/Result<7>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_7)) + (portRef Q (instanceRef f0_Result_7_2_FRB_renamed_383)) + (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_7__rt_renamed_235)) + ) + ) + (net (rename f0_Result_6_2_FRB "f0/Result<6>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_6)) + (portRef Q (instanceRef f0_Result_6_2_FRB_renamed_382)) + (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_6__rt_renamed_236)) + ) + ) + (net (rename f0_Result_5_2_FRB "f0/Result<5>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_5)) + (portRef Q (instanceRef f0_Result_5_2_FRB_renamed_381)) + (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_5__rt_renamed_237)) + ) + ) + (net (rename f0_Result_4_2_FRB "f0/Result<4>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_4)) + (portRef Q (instanceRef f0_Result_4_2_FRB_renamed_380)) + (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_4__rt_renamed_238)) + ) + ) + (net (rename f0_Result_3_2_FRB "f0/Result<3>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_3)) + (portRef Q (instanceRef f0_Result_3_2_FRB_renamed_379)) + (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_3__rt_renamed_239)) + ) + ) + (net (rename f0_Result_2_2_FRB "f0/Result<2>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_2)) + (portRef Q (instanceRef f0_Result_2_2_FRB_renamed_378)) + (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_2__rt_renamed_240)) + ) + ) + (net (rename f0_Result_1_2_FRB "f0/Result<1>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_1)) + (portRef Q (instanceRef f0_Result_1_2_FRB_renamed_377)) + (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_1__rt_renamed_241)) + ) + ) + (net (rename f0_Result_0_2_FRB "f0/Result<0>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_0)) + (portRef Q (instanceRef f0_Result_0_2_FRB_renamed_376)) + (portRef I (instanceRef f0_Mcount_wr_addr_lut_0__INV_0)) + ) + ) + (net (rename f0_Result_12_1_FRB "f0/Result<12>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_12)) + (portRef Q (instanceRef f0_Result_12_1_FRB_renamed_401)) + (portRef I0 (instanceRef f0_Mcount_rd_addr_xor_12__rt_renamed_254)) + (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_12__INV_0)) + ) + ) + (net (rename f0_Result_11_1_FRB "f0/Result<11>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_11)) + (portRef Q (instanceRef f0_Result_11_1_FRB_renamed_400)) + (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_11__rt_renamed_220)) + (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_11__INV_0)) + ) + ) + (net (rename f0_Result_10_1_FRB "f0/Result<10>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_10)) + (portRef Q (instanceRef f0_Result_10_1_FRB_renamed_399)) + (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_10__rt_renamed_221)) + (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_10__INV_0)) + ) + ) + (net (rename f0_Result_9_1_FRB "f0/Result<9>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_9)) + (portRef Q (instanceRef f0_Result_9_1_FRB_renamed_398)) + (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_9__rt_renamed_222)) + (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_9__INV_0)) + ) + ) + (net (rename f0_Result_8_1_FRB "f0/Result<8>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_8)) + (portRef Q (instanceRef f0_Result_8_1_FRB_renamed_397)) + (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_8__rt_renamed_223)) + (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_8__INV_0)) + ) + ) + (net (rename f0_Result_7_1_FRB "f0/Result<7>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_7)) + (portRef Q (instanceRef f0_Result_7_1_FRB_renamed_396)) + (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_7__rt_renamed_224)) + (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_7__INV_0)) + ) + ) + (net (rename f0_Result_6_1_FRB "f0/Result<6>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_6)) + (portRef Q (instanceRef f0_Result_6_1_FRB_renamed_395)) + (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_6__rt_renamed_225)) + (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_6__INV_0)) + ) + ) + (net (rename f0_Result_5_1_FRB "f0/Result<5>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_5)) + (portRef Q (instanceRef f0_Result_5_1_FRB_renamed_394)) + (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_5__rt_renamed_226)) + (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_5__INV_0)) + ) + ) + (net (rename f0_Result_4_1_FRB "f0/Result<4>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_4)) + (portRef Q (instanceRef f0_Result_4_1_FRB_renamed_393)) + (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_4__rt_renamed_227)) + (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_4__INV_0)) + ) + ) + (net (rename f0_Result_3_1_FRB "f0/Result<3>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_3)) + (portRef Q (instanceRef f0_Result_3_1_FRB_renamed_392)) + (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_3__rt_renamed_228)) + (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_3__INV_0)) + ) + ) + (net (rename f0_Result_2_1_FRB "f0/Result<2>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_2)) + (portRef Q (instanceRef f0_Result_2_1_FRB_renamed_391)) + (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_2__rt_renamed_229)) + (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_2__INV_0)) + ) + ) + (net (rename f0_Result_1_1_FRB "f0/Result<1>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_1)) + (portRef Q (instanceRef f0_Result_1_1_FRB_renamed_390)) + (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_1__rt_renamed_230)) + (portRef I0 (instanceRef f0_Msub_dont_write_past_me_cy_1__rt_renamed_242)) + ) + ) + (net (rename f0_Result_0_1_FRB "f0/Result<0>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_0)) + (portRef Q (instanceRef f0_Result_0_1_FRB_renamed_389)) + (portRef I0 (instanceRef f0_Msub_dont_write_past_me_cy_0__rt_renamed_243)) + (portRef I (instanceRef f0_Mcount_rd_addr_lut_0__INV_0)) + ) + ) + (net (rename f0__n0161_inv "f0/_n0161_inv") + (joined + (portRef CE (instanceRef f0_rd_addr_1)) + (portRef CE (instanceRef f0_rd_addr_2)) + (portRef CE (instanceRef f0_rd_addr_3)) + (portRef CE (instanceRef f0_rd_addr_4)) + (portRef CE (instanceRef f0_rd_addr_5)) + (portRef CE (instanceRef f0_rd_addr_6)) + (portRef CE (instanceRef f0_rd_addr_7)) + (portRef CE (instanceRef f0_rd_addr_8)) + (portRef CE (instanceRef f0_rd_addr_9)) + (portRef CE (instanceRef f0_rd_addr_10)) + (portRef CE (instanceRef f0_rd_addr_11)) + (portRef CE (instanceRef f0_rd_addr_12)) + (portRef CE (instanceRef f0_rd_addr_0)) + (portRef CE (instanceRef f0_Result_0_1_FRB_renamed_389)) + (portRef CE (instanceRef f0_Result_1_1_FRB_renamed_390)) + (portRef CE (instanceRef f0_Result_2_1_FRB_renamed_391)) + (portRef CE (instanceRef f0_Result_3_1_FRB_renamed_392)) + (portRef CE (instanceRef f0_Result_4_1_FRB_renamed_393)) + (portRef CE (instanceRef f0_Result_5_1_FRB_renamed_394)) + (portRef CE (instanceRef f0_Result_6_1_FRB_renamed_395)) + (portRef CE (instanceRef f0_Result_7_1_FRB_renamed_396)) + (portRef CE (instanceRef f0_Result_8_1_FRB_renamed_397)) + (portRef CE (instanceRef f0_Result_9_1_FRB_renamed_398)) + (portRef CE (instanceRef f0_Result_10_1_FRB_renamed_399)) + (portRef CE (instanceRef f0_Result_11_1_FRB_renamed_400)) + (portRef CE (instanceRef f0_Result_12_1_FRB_renamed_401)) + (portRef CE (instanceRef f0_dont_write_past_me_0__FRB_renamed_402)) + (portRef CE (instanceRef f0_dont_write_past_me_1__FRB_renamed_403)) + (portRef CE (instanceRef f0_dont_write_past_me_2__FRB_renamed_404)) + (portRef CE (instanceRef f0_dont_write_past_me_3__FRB_renamed_405)) + (portRef CE (instanceRef f0_dont_write_past_me_4__FRB_renamed_406)) + (portRef CE (instanceRef f0_dont_write_past_me_5__FRB_renamed_407)) + (portRef CE (instanceRef f0_dont_write_past_me_6__FRB_renamed_408)) + (portRef CE (instanceRef f0_dont_write_past_me_7__FRB_renamed_409)) + (portRef CE (instanceRef f0_dont_write_past_me_8__FRB_renamed_410)) + (portRef CE (instanceRef f0_dont_write_past_me_9__FRB_renamed_411)) + (portRef CE (instanceRef f0_dont_write_past_me_10__FRB_renamed_412)) + (portRef CE (instanceRef f0_dont_write_past_me_11__FRB_renamed_413)) + (portRef CE (instanceRef f0_dont_write_past_me_12__FRB_renamed_414)) + (portRef O (instanceRef f0__n0161_inv1_cy1)) + ) + ) + (net (rename f0_becoming_full "f0/becoming_full") + (joined + (portRef O (instanceRef f0_Mcompar_becoming_full_cy_4__)) + (portRef I1 (instanceRef f0_full_reg_glue_set_renamed_538)) + ) + ) + (net (rename f0_rd_addr_12__wr_addr_12__equal_11_o "f0/rd_addr[12]_wr_addr[12]_equal_11_o") + (joined + (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__)) + (portRef CI (instanceRef f0__n0161_inv1_cy)) + (portRef I2 (instanceRef f0_read_state_FSM_FFd1_In111)) + (portRef I1 (instanceRef f0_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename f0_dont_write_past_me_0__FRB "f0/dont_write_past_me<0>_FRB") + (joined + (portRef I1 (instanceRef f0_Mcompar_becoming_full_lut_0__)) + (portRef Q (instanceRef f0_dont_write_past_me_0__FRB_renamed_402)) + ) + ) + (net (rename f0_dont_write_past_me_1__FRB "f0/dont_write_past_me<1>_FRB") + (joined + (portRef I3 (instanceRef f0_Mcompar_becoming_full_lut_0__)) + (portRef Q (instanceRef f0_dont_write_past_me_1__FRB_renamed_403)) + ) + ) + (net (rename f0_dont_write_past_me_2__FRB "f0/dont_write_past_me<2>_FRB") + (joined + (portRef I5 (instanceRef f0_Mcompar_becoming_full_lut_0__)) + (portRef Q (instanceRef f0_dont_write_past_me_2__FRB_renamed_404)) + ) + ) + (net (rename f0_dont_write_past_me_3__FRB "f0/dont_write_past_me<3>_FRB") + (joined + (portRef I1 (instanceRef f0_Mcompar_becoming_full_lut_1__)) + (portRef Q (instanceRef f0_dont_write_past_me_3__FRB_renamed_405)) + ) + ) + (net (rename f0_dont_write_past_me_4__FRB "f0/dont_write_past_me<4>_FRB") + (joined + (portRef I3 (instanceRef f0_Mcompar_becoming_full_lut_1__)) + (portRef Q (instanceRef f0_dont_write_past_me_4__FRB_renamed_406)) + ) + ) + (net (rename f0_dont_write_past_me_5__FRB "f0/dont_write_past_me<5>_FRB") + (joined + (portRef I5 (instanceRef f0_Mcompar_becoming_full_lut_1__)) + (portRef Q (instanceRef f0_dont_write_past_me_5__FRB_renamed_407)) + ) + ) + (net (rename f0_dont_write_past_me_6__FRB "f0/dont_write_past_me<6>_FRB") + (joined + (portRef I1 (instanceRef f0_Mcompar_becoming_full_lut_2__)) + (portRef Q (instanceRef f0_dont_write_past_me_6__FRB_renamed_408)) + ) + ) + (net (rename f0_dont_write_past_me_7__FRB "f0/dont_write_past_me<7>_FRB") + (joined + (portRef I3 (instanceRef f0_Mcompar_becoming_full_lut_2__)) + (portRef Q (instanceRef f0_dont_write_past_me_7__FRB_renamed_409)) + ) + ) + (net (rename f0_dont_write_past_me_8__FRB "f0/dont_write_past_me<8>_FRB") + (joined + (portRef I5 (instanceRef f0_Mcompar_becoming_full_lut_2__)) + (portRef Q (instanceRef f0_dont_write_past_me_8__FRB_renamed_410)) + ) + ) + (net (rename f0_dont_write_past_me_9__FRB "f0/dont_write_past_me<9>_FRB") + (joined + (portRef I1 (instanceRef f0_Mcompar_becoming_full_lut_3__)) + (portRef Q (instanceRef f0_dont_write_past_me_9__FRB_renamed_411)) + ) + ) + (net (rename f0_dont_write_past_me_10__FRB "f0/dont_write_past_me<10>_FRB") + (joined + (portRef I3 (instanceRef f0_Mcompar_becoming_full_lut_3__)) + (portRef Q (instanceRef f0_dont_write_past_me_10__FRB_renamed_412)) + ) + ) + (net (rename f0_dont_write_past_me_11__FRB "f0/dont_write_past_me<11>_FRB") + (joined + (portRef I5 (instanceRef f0_Mcompar_becoming_full_lut_3__)) + (portRef Q (instanceRef f0_dont_write_past_me_11__FRB_renamed_413)) + ) + ) + (net (rename f0_dont_write_past_me_12__FRB "f0/dont_write_past_me<12>_FRB") + (joined + (portRef I1 (instanceRef f0_Mcompar_becoming_full_lut_4__)) + (portRef Q (instanceRef f0_dont_write_past_me_12__FRB_renamed_414)) + ) + ) + (net (rename f0_GND_14_o_read_OR_37_o "f0/GND_14_o_read_OR_37_o") + (joined + (portRef O (instanceRef f0_GND_14_o_read_OR_37_o1)) + (portRef ENBRDEN (instanceRef f0_ram_Mram_ram33)) + (portRef ENB (instanceRef f0_ram_Mram_ram31)) + (portRef ENB (instanceRef f0_ram_Mram_ram30)) + (portRef ENB (instanceRef f0_ram_Mram_ram32)) + (portRef ENB (instanceRef f0_ram_Mram_ram28)) + (portRef ENB (instanceRef f0_ram_Mram_ram27)) + (portRef ENB (instanceRef f0_ram_Mram_ram29)) + (portRef ENB (instanceRef f0_ram_Mram_ram25)) + (portRef ENB (instanceRef f0_ram_Mram_ram24)) + (portRef ENB (instanceRef f0_ram_Mram_ram26)) + (portRef ENB (instanceRef f0_ram_Mram_ram22)) + (portRef ENB (instanceRef f0_ram_Mram_ram21)) + (portRef ENB (instanceRef f0_ram_Mram_ram23)) + (portRef ENB (instanceRef f0_ram_Mram_ram19)) + (portRef ENB (instanceRef f0_ram_Mram_ram18)) + (portRef ENB (instanceRef f0_ram_Mram_ram20)) + (portRef ENB (instanceRef f0_ram_Mram_ram16)) + (portRef ENB (instanceRef f0_ram_Mram_ram15)) + (portRef ENB (instanceRef f0_ram_Mram_ram17)) + (portRef ENB (instanceRef f0_ram_Mram_ram14)) + (portRef ENB (instanceRef f0_ram_Mram_ram13)) + (portRef ENB (instanceRef f0_ram_Mram_ram12)) + (portRef ENB (instanceRef f0_ram_Mram_ram11)) + (portRef ENB (instanceRef f0_ram_Mram_ram9)) + (portRef ENB (instanceRef f0_ram_Mram_ram8)) + (portRef ENB (instanceRef f0_ram_Mram_ram10)) + (portRef ENB (instanceRef f0_ram_Mram_ram6)) + (portRef ENB (instanceRef f0_ram_Mram_ram5)) + (portRef ENB (instanceRef f0_ram_Mram_ram7)) + (portRef ENB (instanceRef f0_ram_Mram_ram3)) + (portRef ENB (instanceRef f0_ram_Mram_ram2)) + (portRef ENB (instanceRef f0_ram_Mram_ram4)) + (portRef ENB (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_write "f0/write") + (joined + (portRef CE (instanceRef f0_wr_addr_1)) + (portRef CE (instanceRef f0_wr_addr_2)) + (portRef CE (instanceRef f0_wr_addr_3)) + (portRef CE (instanceRef f0_wr_addr_4)) + (portRef CE (instanceRef f0_wr_addr_5)) + (portRef CE (instanceRef f0_wr_addr_6)) + (portRef CE (instanceRef f0_wr_addr_7)) + (portRef CE (instanceRef f0_wr_addr_8)) + (portRef CE (instanceRef f0_wr_addr_9)) + (portRef CE (instanceRef f0_wr_addr_10)) + (portRef CE (instanceRef f0_wr_addr_11)) + (portRef CE (instanceRef f0_wr_addr_12)) + (portRef CE (instanceRef f0_wr_addr_0)) + (portRef O (instanceRef f0_write11)) + (portRef CE (instanceRef f0_Result_0_2_FRB_renamed_376)) + (portRef CE (instanceRef f0_Result_1_2_FRB_renamed_377)) + (portRef CE (instanceRef f0_Result_2_2_FRB_renamed_378)) + (portRef CE (instanceRef f0_Result_3_2_FRB_renamed_379)) + (portRef CE (instanceRef f0_Result_4_2_FRB_renamed_380)) + (portRef CE (instanceRef f0_Result_5_2_FRB_renamed_381)) + (portRef CE (instanceRef f0_Result_6_2_FRB_renamed_382)) + (portRef CE (instanceRef f0_Result_7_2_FRB_renamed_383)) + (portRef CE (instanceRef f0_Result_8_2_FRB_renamed_384)) + (portRef CE (instanceRef f0_Result_9_2_FRB_renamed_385)) + (portRef CE (instanceRef f0_Result_10_2_FRB_renamed_386)) + (portRef CE (instanceRef f0_Result_11_2_FRB_renamed_387)) + (portRef CE (instanceRef f0_Result_12_2_FRB_renamed_388)) + (portRef (member WEAWEL 1) (instanceRef f0_ram_Mram_ram33)) + (portRef (member WEAWEL 0) (instanceRef f0_ram_Mram_ram33)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram31)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram31)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram31)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram31)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram30)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram30)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram30)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram30)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram32)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram32)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram32)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram32)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram28)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram28)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram28)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram28)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram27)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram27)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram27)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram27)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram29)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram29)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram29)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram29)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram25)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram25)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram25)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram25)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram24)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram24)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram24)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram24)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram26)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram26)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram26)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram26)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram22)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram22)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram22)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram22)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram21)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram21)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram21)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram21)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram23)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram23)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram23)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram23)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram19)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram19)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram19)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram19)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram18)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram18)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram18)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram18)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram20)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram20)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram20)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram20)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram16)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram16)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram16)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram16)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram15)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram15)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram15)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram15)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram17)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram17)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram17)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram17)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram14)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram14)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram14)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram14)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram13)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram13)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram13)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram13)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram12)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram12)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram12)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram12)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram11)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram11)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram11)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram11)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram9)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram9)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram9)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram9)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram8)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram8)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram8)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram8)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram10)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram10)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram10)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram10)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram6)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram6)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram6)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram6)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram5)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram5)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram5)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram5)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram7)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram7)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram7)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram7)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram3)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram3)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram3)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram3)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram2)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram2)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram2)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram2)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram4)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram4)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram4)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram4)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram1)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram1)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram1)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_0_ "f0/wr_addr<0>") + (joined + (portRef Q (instanceRef f0_wr_addr_0)) + (portRef I1 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef I0 (instanceRef f0_Mcompar_becoming_full_lut_0__)) + (portRef (member ADDRAWRADDR 12) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_1_ "f0/wr_addr<1>") + (joined + (portRef Q (instanceRef f0_wr_addr_1)) + (portRef I3 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef I2 (instanceRef f0_Mcompar_becoming_full_lut_0__)) + (portRef (member ADDRAWRADDR 11) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_2_ "f0/wr_addr<2>") + (joined + (portRef Q (instanceRef f0_wr_addr_2)) + (portRef I5 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef I4 (instanceRef f0_Mcompar_becoming_full_lut_0__)) + (portRef (member ADDRAWRADDR 10) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_3_ "f0/wr_addr<3>") + (joined + (portRef Q (instanceRef f0_wr_addr_3)) + (portRef I1 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef I0 (instanceRef f0_Mcompar_becoming_full_lut_1__)) + (portRef (member ADDRAWRADDR 9) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_4_ "f0/wr_addr<4>") + (joined + (portRef Q (instanceRef f0_wr_addr_4)) + (portRef I3 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef I2 (instanceRef f0_Mcompar_becoming_full_lut_1__)) + (portRef (member ADDRAWRADDR 8) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_5_ "f0/wr_addr<5>") + (joined + (portRef Q (instanceRef f0_wr_addr_5)) + (portRef I5 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef I4 (instanceRef f0_Mcompar_becoming_full_lut_1__)) + (portRef (member ADDRAWRADDR 7) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_6_ "f0/wr_addr<6>") + (joined + (portRef Q (instanceRef f0_wr_addr_6)) + (portRef I1 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef I0 (instanceRef f0_Mcompar_becoming_full_lut_2__)) + (portRef (member ADDRAWRADDR 6) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_7_ "f0/wr_addr<7>") + (joined + (portRef Q (instanceRef f0_wr_addr_7)) + (portRef I3 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef I2 (instanceRef f0_Mcompar_becoming_full_lut_2__)) + (portRef (member ADDRAWRADDR 5) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_8_ "f0/wr_addr<8>") + (joined + (portRef Q (instanceRef f0_wr_addr_8)) + (portRef I5 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef I4 (instanceRef f0_Mcompar_becoming_full_lut_2__)) + (portRef (member ADDRAWRADDR 4) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_9_ "f0/wr_addr<9>") + (joined + (portRef Q (instanceRef f0_wr_addr_9)) + (portRef I1 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef I0 (instanceRef f0_Mcompar_becoming_full_lut_3__)) + (portRef (member ADDRAWRADDR 3) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_10_ "f0/wr_addr<10>") + (joined + (portRef Q (instanceRef f0_wr_addr_10)) + (portRef I3 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef I2 (instanceRef f0_Mcompar_becoming_full_lut_3__)) + (portRef (member ADDRAWRADDR 2) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_11_ "f0/wr_addr<11>") + (joined + (portRef Q (instanceRef f0_wr_addr_11)) + (portRef I5 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef I4 (instanceRef f0_Mcompar_becoming_full_lut_3__)) + (portRef (member ADDRAWRADDR 1) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_12_ "f0/wr_addr<12>") + (joined + (portRef Q (instanceRef f0_wr_addr_12)) + (portRef I1 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__)) + (portRef I0 (instanceRef f0_Mcompar_becoming_full_lut_4__)) + (portRef (member ADDRAWRADDR 0) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_0_ "f0/rd_addr<0>") + (joined + (portRef Q (instanceRef f0_rd_addr_0)) + (portRef I0 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef (member ADDRBRDADDR 12) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_1_ "f0/rd_addr<1>") + (joined + (portRef Q (instanceRef f0_rd_addr_1)) + (portRef I2 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef (member ADDRBRDADDR 11) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_2_ "f0/rd_addr<2>") + (joined + (portRef Q (instanceRef f0_rd_addr_2)) + (portRef I4 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef (member ADDRBRDADDR 10) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_3_ "f0/rd_addr<3>") + (joined + (portRef Q (instanceRef f0_rd_addr_3)) + (portRef I0 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef (member ADDRBRDADDR 9) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_4_ "f0/rd_addr<4>") + (joined + (portRef Q (instanceRef f0_rd_addr_4)) + (portRef I2 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef (member ADDRBRDADDR 8) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_5_ "f0/rd_addr<5>") + (joined + (portRef Q (instanceRef f0_rd_addr_5)) + (portRef I4 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef (member ADDRBRDADDR 7) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_6_ "f0/rd_addr<6>") + (joined + (portRef Q (instanceRef f0_rd_addr_6)) + (portRef I0 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef (member ADDRBRDADDR 6) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_7_ "f0/rd_addr<7>") + (joined + (portRef Q (instanceRef f0_rd_addr_7)) + (portRef I2 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef (member ADDRBRDADDR 5) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_8_ "f0/rd_addr<8>") + (joined + (portRef Q (instanceRef f0_rd_addr_8)) + (portRef I4 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef (member ADDRBRDADDR 4) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_9_ "f0/rd_addr<9>") + (joined + (portRef Q (instanceRef f0_rd_addr_9)) + (portRef I0 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef (member ADDRBRDADDR 3) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_10_ "f0/rd_addr<10>") + (joined + (portRef Q (instanceRef f0_rd_addr_10)) + (portRef I2 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef (member ADDRBRDADDR 2) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_11_ "f0/rd_addr<11>") + (joined + (portRef Q (instanceRef f0_rd_addr_11)) + (portRef I4 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef (member ADDRBRDADDR 1) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRB 1) (instanceRef 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slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8211") + (joined + (portRef O + (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211_renamed_416)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + ) + ) + (net N88 + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW0)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast1)) + (portRef I2 + (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In3") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31_renamed_65)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In31") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32_renamed_66)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In32") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In33)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34)) + ) + ) + (net N90 + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW0)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In1") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11_renamed_67)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In11") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12_renamed_68)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In12") + (joined + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_read1)) + (portRef rd_en (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In1") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In11)) + (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13)) + ) + ) + (net cat_miso + (joined + (portRef cat_miso) + (portRef I (instanceRef cat_miso_IBUF_renamed_69)) + ) + ) + (net fx3_ce + (joined + (portRef fx3_ce) + (portRef I (instanceRef fx3_ce_IBUF_renamed_70)) + ) + ) + (net fx3_mosi + (joined + (portRef fx3_mosi) + (portRef I (instanceRef fx3_mosi_IBUF_renamed_71)) + ) + ) + (net fx3_sclk + (joined + (portRef fx3_sclk) + (portRef I (instanceRef fx3_sclk_IBUF_renamed_72)) + ) + ) + (net GPIF_CTL4 + (joined + (portRef GPIF_CTL4) + (portRef I (instanceRef GPIF_CTL4_IBUF_renamed_73)) + ) + ) + (net GPIF_CTL5 + (joined + (portRef GPIF_CTL5) + (portRef I (instanceRef GPIF_CTL5_IBUF_renamed_74)) + ) + ) + (net GPIF_CTL9 + (joined + (portRef GPIF_CTL9) + (portRef I (instanceRef GPIF_CTL9_IBUF_renamed_75)) + ) + ) + (net N96 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_31)) + (portRef O (instanceRef GPIF_D_31_IOBUF)) + ) + ) + (net N97 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_30)) + (portRef O (instanceRef GPIF_D_30_IOBUF)) + ) + ) + (net N98 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_29)) + (portRef O (instanceRef GPIF_D_29_IOBUF)) + ) + ) + (net N99 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_28)) + (portRef O (instanceRef GPIF_D_28_IOBUF)) + ) + ) + (net N100 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_27)) + (portRef O (instanceRef GPIF_D_27_IOBUF)) + ) + ) + (net N101 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_26)) + (portRef O (instanceRef GPIF_D_26_IOBUF)) + ) + ) + (net N102 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_25)) + (portRef O (instanceRef GPIF_D_25_IOBUF)) + ) + ) + (net N103 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_24)) + (portRef O (instanceRef GPIF_D_24_IOBUF)) + ) + ) + (net N104 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_23)) + (portRef O (instanceRef GPIF_D_23_IOBUF)) + ) + ) + (net N105 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_22)) + (portRef O (instanceRef GPIF_D_22_IOBUF)) + ) + ) + (net N106 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_21)) + (portRef O (instanceRef GPIF_D_21_IOBUF)) + ) + ) + (net N107 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_20)) + (portRef O (instanceRef GPIF_D_20_IOBUF)) + ) + ) + (net N108 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_19)) + (portRef O (instanceRef GPIF_D_19_IOBUF)) + ) + ) + (net N109 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_18)) + (portRef O (instanceRef GPIF_D_18_IOBUF)) + ) + ) + (net N110 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_17)) + (portRef O (instanceRef GPIF_D_17_IOBUF)) + ) + ) + (net N111 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_16)) + (portRef O (instanceRef GPIF_D_16_IOBUF)) + ) + ) + (net N112 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_15)) + (portRef O (instanceRef GPIF_D_15_IOBUF)) + ) + ) + (net N113 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_14)) + (portRef O (instanceRef GPIF_D_14_IOBUF)) + ) + ) + (net N114 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_13)) + (portRef O (instanceRef GPIF_D_13_IOBUF)) + ) + ) + (net N115 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_12)) + (portRef O (instanceRef GPIF_D_12_IOBUF)) + ) + ) + (net N116 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_11)) + (portRef O (instanceRef GPIF_D_11_IOBUF)) + ) + ) + (net N117 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_10)) + (portRef O (instanceRef GPIF_D_10_IOBUF)) + ) + ) + (net N118 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_9)) + (portRef O (instanceRef GPIF_D_9_IOBUF)) + ) + ) + (net N119 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_8)) + (portRef O (instanceRef GPIF_D_8_IOBUF)) + ) + ) + (net N120 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_7)) + (portRef O (instanceRef GPIF_D_7_IOBUF)) + ) + ) + (net N121 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_6)) + (portRef O (instanceRef GPIF_D_6_IOBUF)) + ) + ) + (net N122 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_5)) + (portRef O (instanceRef GPIF_D_5_IOBUF)) + ) + ) + (net N123 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_4)) + (portRef O (instanceRef GPIF_D_4_IOBUF)) + ) + ) + (net N124 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_3)) + (portRef O (instanceRef GPIF_D_3_IOBUF)) + ) + ) + (net N125 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_2)) + (portRef O (instanceRef GPIF_D_2_IOBUF)) + ) + ) + (net N126 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_1)) + (portRef O (instanceRef GPIF_D_1_IOBUF)) + ) + ) + (net N127 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_0)) + (portRef O (instanceRef GPIF_D_0_IOBUF)) + ) + ) + (net (rename codec_ctrl_in_3_ "codec_ctrl_in<3>") + (joined + (portRef (member codec_ctrl_in 0)) + (portRef O (instanceRef codec_ctrl_in_3_OBUF)) + ) + ) + (net (rename codec_ctrl_in_2_ "codec_ctrl_in<2>") + (joined + (portRef (member codec_ctrl_in 1)) + (portRef O (instanceRef codec_ctrl_in_2_OBUF)) + ) + ) + (net (rename codec_ctrl_in_1_ "codec_ctrl_in<1>") + (joined + (portRef (member codec_ctrl_in 2)) + (portRef O (instanceRef codec_ctrl_in_1_OBUF)) + ) + ) + (net (rename codec_ctrl_in_0_ "codec_ctrl_in<0>") + (joined + (portRef (member codec_ctrl_in 3)) + (portRef O (instanceRef codec_ctrl_in_0_OBUF)) + ) + ) + (net (rename tx_codec_d_11_ "tx_codec_d<11>") + (joined + (portRef (member tx_codec_d 0)) + (portRef O (instanceRef tx_codec_d_11_OBUF_renamed_76)) + ) + ) + (net (rename tx_codec_d_10_ "tx_codec_d<10>") + (joined + (portRef (member tx_codec_d 1)) + (portRef O (instanceRef tx_codec_d_10_OBUF_renamed_77)) + ) + ) + (net (rename tx_codec_d_9_ "tx_codec_d<9>") + (joined + (portRef (member tx_codec_d 2)) + (portRef O (instanceRef tx_codec_d_9_OBUF_renamed_78)) + ) + ) + (net (rename tx_codec_d_8_ "tx_codec_d<8>") + (joined + (portRef (member tx_codec_d 3)) + (portRef O (instanceRef tx_codec_d_8_OBUF_renamed_79)) + ) + ) + (net (rename tx_codec_d_7_ "tx_codec_d<7>") + (joined + (portRef (member tx_codec_d 4)) + (portRef O (instanceRef tx_codec_d_7_OBUF_renamed_80)) + ) + ) + (net (rename tx_codec_d_6_ "tx_codec_d<6>") + (joined + (portRef (member tx_codec_d 5)) + (portRef O (instanceRef tx_codec_d_6_OBUF_renamed_81)) + ) + ) + (net (rename tx_codec_d_5_ "tx_codec_d<5>") + (joined + (portRef (member tx_codec_d 6)) + (portRef O (instanceRef tx_codec_d_5_OBUF_renamed_82)) + ) + ) + (net (rename tx_codec_d_4_ "tx_codec_d<4>") + (joined + (portRef (member tx_codec_d 7)) + (portRef O (instanceRef tx_codec_d_4_OBUF_renamed_83)) + ) + ) + (net (rename tx_codec_d_3_ "tx_codec_d<3>") + (joined + (portRef (member tx_codec_d 8)) + (portRef O (instanceRef tx_codec_d_3_OBUF_renamed_84)) + ) + ) + (net (rename tx_codec_d_2_ "tx_codec_d<2>") + (joined + (portRef (member tx_codec_d 9)) + (portRef O (instanceRef tx_codec_d_2_OBUF_renamed_85)) + ) + ) + (net (rename tx_codec_d_1_ "tx_codec_d<1>") + (joined + (portRef (member tx_codec_d 10)) + (portRef O (instanceRef tx_codec_d_1_OBUF_renamed_86)) + ) + ) + (net (rename tx_codec_d_0_ "tx_codec_d<0>") + (joined + (portRef (member tx_codec_d 11)) + (portRef O (instanceRef tx_codec_d_0_OBUF_renamed_87)) + ) + ) + (net (rename debug_31_ "debug<31>") + (joined + (portRef (member debug 0)) + (portRef O (instanceRef debug_31_OBUF)) + ) + ) + (net (rename debug_30_ "debug<30>") + (joined + (portRef (member debug 1)) + (portRef O (instanceRef debug_30_OBUF)) + ) + ) + (net (rename debug_29_ "debug<29>") + (joined + (portRef (member debug 2)) + (portRef O (instanceRef debug_29_OBUF)) + ) + ) + (net (rename debug_28_ "debug<28>") + (joined + (portRef (member debug 3)) + (portRef O (instanceRef debug_28_OBUF)) + ) + ) + (net (rename debug_27_ "debug<27>") + (joined + (portRef (member debug 4)) + (portRef O (instanceRef debug_27_OBUF)) + ) + ) + (net (rename debug_26_ "debug<26>") + (joined + (portRef (member debug 5)) + (portRef O (instanceRef debug_26_OBUF)) + ) + ) + (net (rename debug_25_ "debug<25>") + (joined + (portRef (member debug 6)) + (portRef O (instanceRef debug_25_OBUF)) + ) + ) + (net (rename debug_24_ "debug<24>") + (joined + (portRef (member debug 7)) + (portRef O (instanceRef debug_24_OBUF)) + ) + ) + (net (rename debug_23_ "debug<23>") + (joined + (portRef (member debug 8)) + (portRef O (instanceRef debug_23_OBUF)) + ) + ) + (net (rename debug_22_ "debug<22>") + (joined + (portRef (member debug 9)) + (portRef O (instanceRef debug_22_OBUF)) + ) + ) + (net (rename debug_21_ "debug<21>") + (joined + (portRef (member debug 10)) + (portRef O (instanceRef debug_21_OBUF)) + ) + ) + (net (rename debug_20_ "debug<20>") + (joined + (portRef (member debug 11)) + (portRef O (instanceRef debug_20_OBUF)) + ) + ) + (net (rename debug_19_ "debug<19>") + (joined + (portRef (member debug 12)) + (portRef O (instanceRef debug_19_OBUF)) + ) + ) + (net (rename debug_18_ "debug<18>") + (joined + (portRef (member debug 13)) + (portRef O (instanceRef debug_18_OBUF)) + ) + ) + (net (rename debug_17_ "debug<17>") + (joined + (portRef (member debug 14)) + (portRef O (instanceRef debug_17_OBUF)) + ) + ) + (net (rename debug_16_ "debug<16>") + (joined + (portRef (member debug 15)) + (portRef O (instanceRef debug_16_OBUF)) + ) + ) + (net (rename debug_15_ "debug<15>") + (joined + (portRef (member debug 16)) + (portRef O (instanceRef debug_15_OBUF)) + ) + ) + (net (rename debug_14_ "debug<14>") + (joined + (portRef (member debug 17)) + (portRef O (instanceRef debug_14_OBUF)) + ) + ) + (net (rename debug_13_ "debug<13>") + (joined + (portRef (member debug 18)) + (portRef O (instanceRef debug_13_OBUF)) + ) + ) + (net (rename debug_12_ "debug<12>") + (joined + (portRef (member debug 19)) + (portRef O (instanceRef debug_12_OBUF)) + ) + ) + (net (rename debug_11_ "debug<11>") + (joined + (portRef (member debug 20)) + (portRef O (instanceRef debug_11_OBUF)) + ) + ) + (net (rename debug_10_ "debug<10>") + (joined + (portRef (member debug 21)) + (portRef O (instanceRef debug_10_OBUF)) + ) + ) + (net (rename debug_9_ "debug<9>") + (joined + (portRef (member debug 22)) + (portRef O (instanceRef debug_9_OBUF)) + ) + ) + (net (rename debug_8_ "debug<8>") + (joined + (portRef (member debug 23)) + (portRef O (instanceRef debug_8_OBUF)) + ) + ) + (net (rename debug_7_ "debug<7>") + (joined + (portRef (member debug 24)) + (portRef O (instanceRef debug_7_OBUF)) + ) + ) + (net (rename debug_6_ "debug<6>") + (joined + (portRef (member debug 25)) + (portRef O (instanceRef debug_6_OBUF)) + ) + ) + (net (rename debug_5_ "debug<5>") + (joined + (portRef (member debug 26)) + (portRef O (instanceRef debug_5_OBUF)) + ) + ) + (net (rename debug_4_ "debug<4>") + (joined + (portRef (member debug 27)) + (portRef O (instanceRef debug_4_OBUF)) + ) + ) + (net (rename debug_3_ "debug<3>") + (joined + (portRef (member debug 28)) + (portRef O (instanceRef debug_3_OBUF)) + ) + ) + (net (rename debug_2_ "debug<2>") + (joined + (portRef (member debug 29)) + (portRef O (instanceRef debug_2_OBUF)) + ) + ) + (net (rename debug_1_ "debug<1>") + (joined + (portRef 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slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<7>_rt") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__rt_renamed_180)) + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_7__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<6>_rt") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__rt_renamed_181)) + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_6__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<5>_rt") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5__rt_renamed_182)) + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_5__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<4>_rt") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__rt_renamed_183)) + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_4__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<3>_rt") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3__rt_renamed_184)) + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_3__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<2>_rt") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__rt_renamed_185)) + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_2__)) + ) + ) + (net (rename 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slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<5>_rt") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__rt_renamed_190)) + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_5__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<4>_rt") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__rt_renamed_191)) + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_4__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<3>_rt") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3__rt_renamed_192)) + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_3__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<2>_rt") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2__rt_renamed_193)) + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_2__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<1>_rt") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__rt_renamed_194)) + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_1__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<0>_rt") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__rt_renamed_195)) + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_0__)) + ) + ) + (net (rename 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(portRef LI (instanceRef f1_Mcount_rd_addr_xor_8__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_7__rt "f1/Mcount_rd_addr_cy<7>_rt") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_7__rt_renamed_200)) + (portRef S (instanceRef f1_Mcount_rd_addr_cy_7__)) + (portRef LI (instanceRef f1_Mcount_rd_addr_xor_7__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_6__rt "f1/Mcount_rd_addr_cy<6>_rt") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_6__rt_renamed_201)) + (portRef S (instanceRef f1_Mcount_rd_addr_cy_6__)) + (portRef LI (instanceRef f1_Mcount_rd_addr_xor_6__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_5__rt "f1/Mcount_rd_addr_cy<5>_rt") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_5__rt_renamed_202)) + (portRef S (instanceRef f1_Mcount_rd_addr_cy_5__)) + (portRef LI (instanceRef f1_Mcount_rd_addr_xor_5__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_4__rt "f1/Mcount_rd_addr_cy<4>_rt") + (joined + (portRef O (instanceRef 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slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd2_BRB1") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB1_renamed_477)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o1)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB0") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0_renamed_478)) + (portRef I0 (instanceRef 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slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB2") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2_renamed_480)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB3") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3_renamed_481)) + (portRef I3 (instanceRef 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"slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB2") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2_renamed_486)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB3") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3_renamed_487)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB4") + 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"slave_fifo32/gpif_data_out<17>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_17)) + (portRef I (instanceRef GPIF_D_17_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_18 "slave_fifo32/sloe_18") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_18_renamed_569)) + (portRef T (instanceRef GPIF_D_16_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_16_ "slave_fifo32/gpif_data_out<16>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_16)) + (portRef I (instanceRef GPIF_D_16_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_17 "slave_fifo32/sloe_17") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_17_renamed_570)) + (portRef T (instanceRef GPIF_D_15_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_15_ "slave_fifo32/gpif_data_out<15>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_15)) + (portRef I (instanceRef GPIF_D_15_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_16 "slave_fifo32/sloe_16") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_16_renamed_571)) + (portRef T (instanceRef GPIF_D_14_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_14_ "slave_fifo32/gpif_data_out<14>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_14)) + (portRef I (instanceRef GPIF_D_14_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_15 "slave_fifo32/sloe_15") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_15_renamed_572)) + (portRef T (instanceRef GPIF_D_13_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_13_ "slave_fifo32/gpif_data_out<13>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_13)) + (portRef I (instanceRef GPIF_D_13_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_14 "slave_fifo32/sloe_14") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_14_renamed_573)) + (portRef T (instanceRef GPIF_D_12_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_12_ "slave_fifo32/gpif_data_out<12>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_12)) + (portRef I (instanceRef GPIF_D_12_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_13 "slave_fifo32/sloe_13") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_13_renamed_574)) + (portRef T (instanceRef GPIF_D_11_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_11_ "slave_fifo32/gpif_data_out<11>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_11)) + (portRef I (instanceRef GPIF_D_11_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_12 "slave_fifo32/sloe_12") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_12_renamed_575)) + (portRef T (instanceRef GPIF_D_10_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_10_ "slave_fifo32/gpif_data_out<10>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_10)) + (portRef I (instanceRef GPIF_D_10_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_11 "slave_fifo32/sloe_11") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_11_renamed_576)) + (portRef T (instanceRef GPIF_D_9_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_9_ "slave_fifo32/gpif_data_out<9>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_9)) + (portRef I (instanceRef GPIF_D_9_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_10 "slave_fifo32/sloe_10") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_10_renamed_577)) + (portRef T (instanceRef GPIF_D_8_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_8_ "slave_fifo32/gpif_data_out<8>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_8)) + (portRef I (instanceRef GPIF_D_8_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_9 "slave_fifo32/sloe_9") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_9_renamed_578)) + (portRef T (instanceRef GPIF_D_7_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_7_ "slave_fifo32/gpif_data_out<7>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_7)) + (portRef I (instanceRef GPIF_D_7_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_8 "slave_fifo32/sloe_8") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_8_renamed_579)) + (portRef T (instanceRef GPIF_D_6_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_6_ "slave_fifo32/gpif_data_out<6>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_6)) + (portRef I (instanceRef GPIF_D_6_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_7 "slave_fifo32/sloe_7") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_7_renamed_580)) + (portRef T (instanceRef GPIF_D_5_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_5_ "slave_fifo32/gpif_data_out<5>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_5)) + (portRef I (instanceRef GPIF_D_5_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_6 "slave_fifo32/sloe_6") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_6_renamed_581)) + (portRef T (instanceRef GPIF_D_4_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_4_ "slave_fifo32/gpif_data_out<4>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_4)) + (portRef I (instanceRef GPIF_D_4_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_5 "slave_fifo32/sloe_5") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_5_renamed_582)) + (portRef T (instanceRef GPIF_D_3_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_3_ "slave_fifo32/gpif_data_out<3>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_3)) + (portRef I (instanceRef GPIF_D_3_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_4 "slave_fifo32/sloe_4") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_4_renamed_583)) + (portRef T (instanceRef GPIF_D_2_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_2_ "slave_fifo32/gpif_data_out<2>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_2)) + (portRef I (instanceRef GPIF_D_2_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_3 "slave_fifo32/sloe_3") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_3_renamed_584)) + (portRef T (instanceRef GPIF_D_1_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_1_ "slave_fifo32/gpif_data_out<1>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_1)) + (portRef I (instanceRef GPIF_D_1_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_2 "slave_fifo32/sloe_2") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_2_renamed_585)) + (portRef T (instanceRef GPIF_D_0_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_0_ "slave_fifo32/gpif_data_out<0>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_0)) + (portRef I (instanceRef GPIF_D_0_IOBUF)) + ) + ) + ) + ) + ) + ) + + (design b200 + (cellRef b200 + (libraryRef b200_lib) + ) + (property PART (string "xc6slx75-3-fgg484") (owner "Xilinx")) + ) +) + diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/constrs_1/fileset.xml b/fpga/usrp3/top/b200/planahead/planahead.data/constrs_1/fileset.xml new file mode 100644 index 000000000..6234dfdc5 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/constrs_1/fileset.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1.psg b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1.psg new file mode 100644 index 000000000..147f3a950 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1.psg @@ -0,0 +1,20 @@ + + + + ISE Defaults, including packing registers in IOs off + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/constrs_in.xml b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/constrs_in.xml new file mode 100644 index 000000000..d7d32c943 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/constrs_in.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/constrs_out.xml b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/constrs_out.xml new file mode 100644 index 000000000..4d152cf5b --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/constrs_out.xml @@ -0,0 +1,20 @@ + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/impl_1.psg b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/impl_1.psg new file mode 100644 index 000000000..147f3a950 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/impl_1.psg @@ -0,0 +1,20 @@ + + + + ISE Defaults, including packing registers in IOs off + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/sources.xml b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/sources.xml new file mode 100644 index 000000000..1ebdc052b --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/sources.xml @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/runs/runs.xml b/fpga/usrp3/top/b200/planahead/planahead.data/runs/runs.xml new file mode 100644 index 000000000..b8f171cc0 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/runs/runs.xml @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/sim_1/fileset.xml b/fpga/usrp3/top/b200/planahead/planahead.data/sim_1/fileset.xml new file mode 100644 index 000000000..65babe32f --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/sim_1/fileset.xml @@ -0,0 +1,10 @@ + + + + + + + diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/sources_1/fileset.xml b/fpga/usrp3/top/b200/planahead/planahead.data/sources_1/fileset.xml new file mode 100644 index 000000000..b0421e4c2 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/sources_1/fileset.xml @@ -0,0 +1,26 @@ + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/wt/java_command_handlers.wdf b/fpga/usrp3/top/b200/planahead/planahead.data/wt/java_command_handlers.wdf new file mode 100644 index 000000000..d32729c6c --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/wt/java_command_handlers.wdf @@ -0,0 +1,12 @@ +version:1 +70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464737263:31:00:00 +70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697466696e64:32:00:00 +70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697470726f70657274696573:31:00:00 +70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:66696c6565786974:31:00:00 +70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 +70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f67676c657a6f6f6d617265616d6f6465:32:00:00 +70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:31:00:00 +70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7a6f6f6d666974:31:00:00 +70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7a6f6f6d696e:3133:00:00 +70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7a6f6f6d6f7574:3137:00:00 +eof:1108508211 diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/wt/project.wpc b/fpga/usrp3/top/b200/planahead/planahead.data/wt/project.wpc new file mode 100644 index 000000000..9b3420931 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/wt/project.wpc @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:1 +eof: diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/wt/webtalk_pa.xml b/fpga/usrp3/top/b200/planahead/planahead.data/wt/webtalk_pa.xml new file mode 100644 index 000000000..4c889614e --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/wt/webtalk_pa.xml @@ -0,0 +1,38 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/fpga/usrp3/top/b200/planahead/planahead.ppr b/fpga/usrp3/top/b200/planahead/planahead.ppr new file mode 100644 index 000000000..706cfae4b --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.ppr @@ -0,0 +1,28 @@ + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/.jobs/job1.bat b/fpga/usrp3/top/b200/planahead/planahead.runs/.jobs/job1.bat new file mode 100644 index 000000000..f95ac9bd2 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/.jobs/job1.bat @@ -0,0 +1,21 @@ +@echo off + +rem PlanAhead(TM) +rem launch.bat: a PlanAhead-generated ExploreAhead Script +rem Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved. + + +setlocal + +set HD_LDIR=%~dp0 + +rem *** Create Queue Clues +set HD_RUNDIR=%HD_LDIR%\../impl_1 +if exist "%HD_RUNDIR%" echo. > "%HD_RUNDIR%/.ISE.queue.rst" + + +rem *** Launch Runs (one at a time) +set HD_RUNBAT=%HD_LDIR%\../impl_1\runme.bat +if exist "%HD_RUNBAT%" call "%HD_RUNBAT%" %* + + diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/.jobs/job1.sh b/fpga/usrp3/top/b200/planahead/planahead.runs/.jobs/job1.sh new file mode 100755 index 000000000..48861c686 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/.jobs/job1.sh @@ -0,0 +1,26 @@ +#!/bin/sh + +# +# PlanAhead(TM) +# launch.sh: a PlanAhead-generated ExploreAhead Script for UNIX +# Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved. +# + +HD_LDIR=`dirname "$0"` + +# *** Create Queue Clues +HD_RUNDIR="$HD_LDIR/../impl_1" +if [ -d "$HD_RUNDIR" ] +then +/bin/touch "$HD_RUNDIR/.ISE.queue.rst" +fi + + +# *** Launch Runs (one at a time) +HD_RUNSH="$HD_LDIR/../impl_1/runme.sh" +if [ -f "$HD_RUNSH" ] +then +"$HD_RUNSH" +fi + + diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.constrs/b200.ucf b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.constrs/b200.ucf new file mode 100644 index 000000000..665f5d76c --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.constrs/b200.ucf @@ -0,0 +1,317 @@ +## SPI Nets + +NET "cat_ce" LOC = Y1; +NET "cat_ce" IOSTANDARD = LVCMOS18; +NET "cat_miso" LOC = V1; +NET "cat_miso" IOSTANDARD = LVCMOS18; +NET "cat_mosi" LOC = T4; +NET "cat_mosi" IOSTANDARD = LVCMOS18; +NET "cat_sclk" LOC = P7; +NET "cat_sclk" IOSTANDARD = LVCMOS18; + +NET "fx3_ce" LOC = H20; +NET "fx3_miso" LOC = G20; +NET "fx3_mosi" LOC = AA20; +NET "fx3_sclk" LOC = Y21; + +NET "pll_ce" LOC = W11; +NET "pll_mosi" LOC = AB11; +NET "pll_sclk" LOC = Y12; + +NET "FPGA_RXD0" LOC = AB8; +NET "FPGA_TXD0" LOC = AB7; + +NET "SCL_FPGA" LOC = P21; +NET "SDA_FPGA" LOC = W22; + +## Catalina Controls + +NET "codec_enable" LOC = J6; +NET "codec_enable" IOSTANDARD = LVCMOS18; +NET "codec_en_agc" LOC = P6; +NET "codec_en_agc" IOSTANDARD = LVCMOS18; +NET "codec_reset" LOC = Y2; +NET "codec_reset" IOSTANDARD = LVCMOS18; +NET "codec_sync" LOC = M3; +NET "codec_sync" IOSTANDARD = LVCMOS18; +NET "codec_txrx" LOC = M7; +NET "codec_txrx" IOSTANDARD = LVCMOS18; + +NET "codec_ctrl_in[0]" LOC = E3; +NET "codec_ctrl_in[0]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in[1]" LOC = F2; +NET "codec_ctrl_in[1]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in[2]" LOC = F1; +NET "codec_ctrl_in[2]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in[3]" LOC = E1; +NET "codec_ctrl_in[3]" IOSTANDARD = LVCMOS18; + +NET "codec_ctrl_out[0]" LOC = D1; +NET "codec_ctrl_out[0]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[1]" LOC = C1; +NET "codec_ctrl_out[1]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[2]" LOC = H3; +NET "codec_ctrl_out[2]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[3]" LOC = F3; +NET "codec_ctrl_out[3]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[4]" LOC = P1; +NET "codec_ctrl_out[4]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[5]" LOC = J1; +NET "codec_ctrl_out[5]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[6]" LOC = B1; +NET "codec_ctrl_out[6]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[7]" LOC = H2; +NET "codec_ctrl_out[7]" IOSTANDARD = LVCMOS18; + +## Catalina Data RX + +NET "rx_codec_d[0]" LOC = T2; +NET "rx_codec_d[0]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[0]" DRIVE = 4; +NET "rx_codec_d[1]" LOC = R1; +NET "rx_codec_d[1]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[1]" DRIVE = 4; +NET "rx_codec_d[2]" LOC = V2; +NET "rx_codec_d[2]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[2]" DRIVE = 4; +NET "rx_codec_d[3]" LOC = N1; +NET "rx_codec_d[3]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[3]" DRIVE = 4; +NET "rx_codec_d[4]" LOC = V3; +NET "rx_codec_d[4]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[4]" DRIVE = 4; +NET "rx_codec_d[5]" LOC = T1; +NET "rx_codec_d[5]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[5]" DRIVE = 4; +NET "rx_codec_d[6]" LOC = W1; +NET "rx_codec_d[6]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[6]" DRIVE = 4; +NET "rx_codec_d[7]" LOC = U1; +NET "rx_codec_d[7]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[7]" DRIVE = 4; +NET "rx_codec_d[8]" LOC = W3; +NET "rx_codec_d[8]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[8]" DRIVE = 4; +NET "rx_codec_d[9]" LOC = U3; +NET "rx_codec_d[9]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[9]" DRIVE = 4; +NET "rx_codec_d[10]" LOC = P2; +NET "rx_codec_d[10]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[10]" DRIVE = 4; +NET "rx_codec_d[11]" LOC = R3; +NET "rx_codec_d[11]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[11]" DRIVE = 4; + +## Catalina Data TX + +NET "tx_codec_d[0]" LOC = M1; +NET "tx_codec_d[0]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[0]" DRIVE = 4; +NET "tx_codec_d[1]" LOC = K1; +NET "tx_codec_d[1]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[1]" DRIVE = 4; +NET "tx_codec_d[2]" LOC = L3; +NET "tx_codec_d[2]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[2]" DRIVE = 4; +NET "tx_codec_d[3]" LOC = K2; +NET "tx_codec_d[3]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[3]" DRIVE = 4; +NET "tx_codec_d[4]" LOC = M4; +NET "tx_codec_d[4]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[4]" DRIVE = 4; +NET "tx_codec_d[5]" LOC = J4; +NET "tx_codec_d[5]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[5]" DRIVE = 4; +NET "tx_codec_d[6]" LOC = L4; +NET "tx_codec_d[6]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[6]" DRIVE = 4; +NET "tx_codec_d[7]" LOC = H1; +NET "tx_codec_d[7]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[7]" DRIVE = 4; +NET "tx_codec_d[8]" LOC = M2; +NET "tx_codec_d[8]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[8]" DRIVE = 4; +NET "tx_codec_d[9]" LOC = G1; +NET "tx_codec_d[9]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[9]" DRIVE = 4; +NET "tx_codec_d[10]" LOC = N3; +NET "tx_codec_d[10]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[10]" DRIVE = 4; +NET "tx_codec_d[11]" LOC = G3; +NET "tx_codec_d[11]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[11]" DRIVE = 4; + +## Catalina Clocks + +NET "cat_clkout_fpga" LOC = J3; +NET "cat_clkout_fpga" IOSTANDARD = LVCMOS18; +NET "codec_data_clk_p" LOC = K3; +NET "codec_data_clk_p" IOSTANDARD = LVCMOS18; +NET "codec_fb_clk_p" LOC = P3; +NET "codec_fb_clk_p" IOSTANDARD = LVCMOS18; +# | IOSTANDARD = LVCMOS18; +NET "codec_main_clk_p" LOC = K5; +# | IOSTANDARD = LVCMOS18; +NET "codec_main_clk_n" LOC = K4; + +NET "rx_frame_p" LOC = U4; +NET "rx_frame_p" IOSTANDARD = LVCMOS18; +NET "tx_frame_p" LOC = T3; +NET "tx_frame_p" IOSTANDARD = LVCMOS18; + +## Debug Bus + +NET "debug[0]" LOC = C14; +NET "debug[1]" LOC = F15; +NET "debug[2]" LOC = A18; +NET "debug[3]" LOC = A17; +NET "debug[4]" LOC = E14; +NET "debug[5]" LOC = G13; +NET "debug[6]" LOC = D13; +NET "debug[7]" LOC = F13; +NET "debug[8]" LOC = D8; +NET "debug[9]" LOC = A6; +NET "debug[10]" LOC = D7; +NET "debug[11]" LOC = A5; +NET "debug[12]" LOC = B6; +NET "debug[13]" LOC = A3; +NET "debug[14]" LOC = A7; +NET "debug[15]" LOC = A8; +NET "debug[16]" LOC = B18; +NET "debug[17]" LOC = C17; +NET "debug[18]" LOC = H13; +NET "debug[19]" LOC = D12; +NET "debug[20]" LOC = H14; +NET "debug[21]" LOC = C10; +NET "debug[22]" LOC = D10; +NET "debug[23]" LOC = C8; +NET "debug[24]" LOC = D9; +NET "debug[25]" LOC = C5; +NET "debug[26]" LOC = A9; +NET "debug[27]" LOC = B8; +NET "debug[28]" LOC = A4; +NET "debug[29]" LOC = C7; +NET "debug[30]" LOC = C6; +NET "debug[31]" LOC = D6; + +NET "debug_clk[0]" LOC = A12; +NET "debug_clk[1]" LOC = C12; + +## GPIF + +NET "IFCLK" LOC = H21; +NET "FX3_EXTINT" LOC = U20; + +NET "GPIF_CTL0" LOC = V20; +NET "GPIF_CTL1" LOC = T22; +NET "GPIF_CTL2" LOC = R22; +NET "GPIF_CTL3" LOC = U22; +NET "GPIF_CTL4" LOC = P19; +NET "GPIF_CTL5" LOC = N22; +NET "GPIF_CTL6" LOC = T21; +NET "GPIF_CTL7" LOC = V21; +NET "GPIF_CTL8" LOC = K18; +NET "GPIF_CTL9" LOC = R20; +##GPIF_CTL10 is "FPGA_CFG_DONE", defined later. +NET "GPIF_CTL11" LOC = P22; +NET "GPIF_CTL12" LOC = M20; + +NET "GPIF_D[0]" LOC = T17; +NET "GPIF_D[1]" LOC = U14; +NET "GPIF_D[2]" LOC = U13; +NET "GPIF_D[3]" LOC = AA6; +NET "GPIF_D[4]" LOC = AB6; +NET "GPIF_D[5]" LOC = Y3; +NET "GPIF_D[6]" LOC = AB3; +NET "GPIF_D[7]" LOC = AA4; +NET "GPIF_D[8]" LOC = AA2; +NET "GPIF_D[9]" LOC = AB2; +NET "GPIF_D[10]" LOC = AB19; +NET "GPIF_D[11]" LOC = AA18; +NET "GPIF_D[12]" LOC = AB18; +NET "GPIF_D[13]" LOC = Y13; +NET "GPIF_D[14]" LOC = AA12; +NET "GPIF_D[15]" LOC = AB12; +NET "GPIF_D[16]" LOC = N20; +NET "GPIF_D[17]" LOC = L20; +NET "GPIF_D[18]" LOC = N19; +NET "GPIF_D[19]" LOC = M22; +NET "GPIF_D[20]" LOC = L19; +NET "GPIF_D[21]" LOC = M21; +NET "GPIF_D[22]" LOC = M19; +NET "GPIF_D[23]" LOC = K22; +NET "GPIF_D[24]" LOC = J20; +NET "GPIF_D[25]" LOC = L22; +NET "GPIF_D[26]" LOC = K19; +NET "GPIF_D[27]" LOC = H22; +NET "GPIF_D[28]" LOC = J22; +NET "GPIF_D[29]" LOC = K20; +NET "GPIF_D[30]" LOC = G22; +NET "GPIF_D[31]" LOC = F22; + +## GPS + +NET "gps_lock" LOC = Y17; +NET "gps_out_enable" LOC = V22; +NET "gps_ref_enable" LOC = AB13; +NET "gps_rxd" LOC = AB14; +NET "gps_txd" LOC = W12; +NET "gps_txd_nmea" LOC = AA14; + +## LEDS + +NET "LED_RX1" LOC = C22; +NET "LED_RX2" LOC = L15; +NET "LED_TXRX1_TX" LOC = C20; +NET "LED_TXRX2_RX" LOC = D21; +NET "LED_TXRX1_RX" LOC = K16; +NET "LED_TXRX2_TX" LOC = D22; + +## Misc Hardware Control + +NET "ext_ref_enable" LOC = Y15; +NET "pll_lock" LOC = AB10; +NET "AUX_PWR_ON" LOC = AA21; +#NET "RFUSE" LOC = "P15" ; + +## PPS + +NET "pps_fpga_out_enable" LOC = AB15; +NET "PPS_IN_EXT" LOC = AB16; +NET "PPS_IN_INT" LOC = AB21; +NET "pps_out" LOC = AB17; + +## RF Hardware Control + +NET "SFDX1_RX" LOC = W4; +NET "SFDX1_TX" LOC = T18; +NET "SFDX2_RX" LOC = F18; +NET "SFDX2_TX" LOC = H17; +NET "SRX1_RX" LOC = Y7; +NET "SRX1_TX" LOC = AA8; +NET "SRX2_RX" LOC = J17; +NET "SRX2_TX" LOC = F19; +NET "tx_bandsel_a" LOC = N16; +NET "tx_bandsel_b" LOC = M16; +NET "tx_enable1" LOC = Y4; +NET "tx_enable2" LOC = R19; +NET "rx_bandsel_a" LOC = T20; +NET "rx_bandsel_b" LOC = U19; +NET "rx_bandsel_c" LOC = P20; + +## FPGA Config Pins + +#NET "FPGA_CFG_INIT_B" LOC = "T6" ; +#NET "FPGA_CFG_DONE" LOC = "Y22" ; +#NET "FPGA_CFG_M0" LOC = "AA22" ; +#NET "FPGA_CFG_M1" LOC = "U15" ; +#NET "FPGA_CFG_PROG_B" LOC = "AA1" ; + +## Special Pins + +#NET "VFS" LOC = "P16" ; +#NET "TMS" LOC = "C18" ; +#NET "TDO" LOC = "A19" ; +#NET "TDI" LOC = "E18" ; +#NET "TCK" LOC = "G15" ; +#NET "GND" LOC = "N15" ; diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.constrs/timing.ucf b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.constrs/timing.ucf new file mode 100644 index 000000000..907b97539 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.constrs/timing.ucf @@ -0,0 +1,85 @@ + +# codec_main_clk is 40 MHz main tcxo clock +NET "codec_main_clk*" TNM_NET = "codec_main_clk"; +TIMESPEC TS_codec_main_clk = PERIOD "codec_main_clk" 25000 ps HIGH 50 %; + + +# IFCLK is 100 MHz GPIF clock +NET "IFCLK" TNM_NET = "IFCLK"; +TIMESPEC TS_IFCLK = PERIOD "IFCLK" 10000 ps HIGH 50 %; + + +# codec_data_clk is the data clock from catalina, sample rate dependent +# this clock equals sample rate in CMOS DDR 1R1T mode +# this clock is double the sample rate in CMOS DDR 2R2T mode +# Max clock rate is 61.44 MHz +NET "codec_data_clk_p" TNM_NET = "codec_data_clk_p"; +TIMESPEC TS_codec_data_clk_p = PERIOD "codec_data_clk_p" 16276 ps HIGH 50 %; + + +#always use IOB for GPIF pins for awesome timing +INST "GPIF_D_9_IOBUF" IOB =TRUE; +INST "GPIF_D_8_IOBUF" IOB =TRUE; +INST "GPIF_D_7_IOBUF" IOB =TRUE; +INST "GPIF_D_6_IOBUF" IOB =TRUE; +INST "GPIF_D_5_IOBUF" IOB =TRUE; +INST "GPIF_D_4_IOBUF" IOB =TRUE; +INST "GPIF_D_3_IOBUF" IOB =TRUE; +INST "GPIF_D_31_IOBUF" IOB =TRUE; +INST "GPIF_D_30_IOBUF" IOB =TRUE; +INST "GPIF_D_2_IOBUF" IOB =TRUE; +INST "GPIF_D_29_IOBUF" IOB =TRUE; +INST "GPIF_D_28_IOBUF" IOB =TRUE; +INST "GPIF_D_27_IOBUF" IOB =TRUE; +INST "GPIF_D_26_IOBUF" IOB =TRUE; +INST "GPIF_D_25_IOBUF" IOB =TRUE; +INST "GPIF_D_24_IOBUF" IOB =TRUE; +INST "GPIF_D_23_IOBUF" IOB =TRUE; +INST "GPIF_D_22_IOBUF" IOB =TRUE; +INST "GPIF_D_21_IOBUF" IOB =TRUE; +INST "GPIF_D_20_IOBUF" IOB =TRUE; +INST "GPIF_D_1_IOBUF" IOB =TRUE; +INST "GPIF_CTL0_OBUF" IOB =TRUE; +INST "GPIF_CTL11_OBUF" IOB =TRUE; +INST "GPIF_CTL12_OBUF" IOB =TRUE; +INST "GPIF_CTL1_OBUF" IOB =TRUE; +INST "GPIF_CTL2_OBUF" IOB =TRUE; +INST "GPIF_CTL3_OBUF" IOB =TRUE; +INST "GPIF_CTL4_IBUF" IOB =TRUE; +INST "GPIF_CTL5_IBUF" IOB =TRUE; +INST "GPIF_CTL7_OBUF" IOB =TRUE; +INST "GPIF_CTL9_IBUF" IOB =TRUE; +INST "GPIF_D_0_IOBUF" IOB =TRUE; +INST "GPIF_D_10_IOBUF" IOB =TRUE; +INST "GPIF_D_11_IOBUF" IOB =TRUE; +INST "GPIF_D_12_IOBUF" IOB =TRUE; +INST "GPIF_D_13_IOBUF" IOB =TRUE; +INST "GPIF_D_14_IOBUF" IOB =TRUE; +INST "GPIF_D_15_IOBUF" IOB =TRUE; +INST "GPIF_D_16_IOBUF" IOB =TRUE; +INST "GPIF_D_17_IOBUF" IOB =TRUE; +INST "GPIF_D_18_IOBUF" IOB =TRUE; +INST "GPIF_D_19_IOBUF" IOB =TRUE; + +# TODO not working... constraints ignored + +#constrain FX3 IO +INST "GPIF_D[*]" TNM = "gpif_net_out"; +INST "GPIF_D[*]" TNM = "gpif_net_in"; +INST "GPIF_CTL0" TNM = "gpif_net_out"; +INST "GPIF_CTL1" TNM = "gpif_net_out"; +INST "GPIF_CTL2" TNM = "gpif_net_out"; +INST "GPIF_CTL3" TNM = "gpif_net_out"; +INST "GPIF_CTL4" TNM = "gpif_net_in"; +INST "GPIF_CTL5" TNM = "gpif_net_in"; +INST "GPIF_CTL6" TNM = gpif_net_in; +INST "GPIF_CTL7" TNM = "gpif_net_out"; +INST "GPIF_CTL8" TNM = gpif_net_in; +INST "GPIF_CTL11" TNM = "gpif_net_out"; +INST "GPIF_CTL12" TNM = "gpif_net_out"; + +#NET "gpif_clk" TNM_NET = "TNM_gpif_clk"; +#OFFSET = OUT 5 ns AFTER "gpif_clk"; +#TIMESPEC "TS_gpif_clk" = PERIOD "TNM_gpif_clk" 10000 ps HIGH 50 %; +#TIMEGRP "gpif_net_in" OFFSET = IN 6 ns VALID 6 ns BEFORE "gpif_clk" RISING; +#TIMEGRP "gpif_net_out" OFFSET = OUT 6 ns AFTER "gpif_clk" RISING; diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.map.begin.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.map.begin.rst new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.map.end.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.map.end.rst new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.ngdbuild.begin.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.ngdbuild.begin.rst new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.ngdbuild.end.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.ngdbuild.end.rst new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.par.begin.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.par.begin.rst new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.par.end.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.par.end.rst new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.trce.begin.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.trce.begin.rst new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.trce.end.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.trce.end.rst new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.xdl.begin.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.xdl.begin.rst new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.xdl.end.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.xdl.end.rst new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/ISEWrap.js b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/ISEWrap.js new file mode 100644 index 000000000..72d04e50d --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/ISEWrap.js @@ -0,0 +1,196 @@ +// +// PlanAhead(TM) +// ISEWrap.js: ExploreAhead Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2010 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.close(); +} + +function ISEOpenFile( ISEFilename ) { + + var ISEFullPath = ISERunDir + "/" + ISEFilename; + return ISEFileSys.OpenTextFile( ISEFullPath, 8, true ); +} diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/ISEWrap.sh b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/ISEWrap.sh new file mode 100755 index 000000000..4ebc95977 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/ISEWrap.sh @@ -0,0 +1,62 @@ +#!/bin/sh + +# +# PlanAhead(TM) +# ISEWrap.sh: ExploreAhead Script for UNIX +# Copyright 1986-1999, 2001-2010 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.edf b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.edf new file mode 100644 index 000000000..6fe23b7b5 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.edf @@ -0,0 +1,51815 @@ +(edif b200 + (edifversion 2 0 0) + (edifLevel 0) + (keywordmap (keywordlevel 0)) +(status + (written + (timeStamp 2013 01 29 17 25 56) + (program "PlanAhead" (version "14.4")) + (comment "Built on 'Tue Dec 18 05:17:28 MST 2012'") + (comment "Built by 'xbuild'") + ) +) + (Library hdi_primitives + (edifLevel 0) + (technology (numberDefinition )) + (cell FDRE (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port CE (direction INPUT)) + (port D (direction INPUT)) + (port R (direction INPUT)) + ) + ) + ) + (cell MUXCY (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port CI (direction INPUT)) + (port DI (direction INPUT)) + (port S (direction INPUT)) + ) + ) + ) + (cell LUT2 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + ) + ) + ) + (cell LUT3 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + ) + ) + ) + (cell SRLC32E (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port Q31 (direction OUTPUT)) + (port CE (direction INPUT)) + (port CLK (direction INPUT)) + (port D (direction INPUT)) + (port (array (rename A "A[4:0]") 5) (direction INPUT)) + ) + ) + ) + (cell XORCY (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port CI (direction INPUT)) + (port LI (direction INPUT)) + ) + ) + ) + (cell OBUF (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I (direction INPUT)) + ) + ) + ) + (cell FD (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port D (direction INPUT)) + ) + ) + ) + (cell ODDR2 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C0 (direction INPUT)) + (port C1 (direction INPUT)) + (port CE (direction INPUT)) + (port D0 (direction INPUT)) + (port D1 (direction INPUT)) + (port R (direction INPUT)) + (port S (direction INPUT)) + ) + ) + ) + (cell IOBUF (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I (direction INPUT)) + (port T (direction INPUT)) + (port IO (direction INOUT)) + ) + ) + ) + (cell LUT6 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + (port I3 (direction INPUT)) + (port I4 (direction INPUT)) + (port I5 (direction INPUT)) + ) + ) + ) + (cell RAMB16BWER (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port CLKA (direction INPUT)) + (port CLKB (direction INPUT)) + (port ENA (direction INPUT)) + (port ENB (direction INPUT)) + (port REGCEA (direction INPUT)) + (port REGCEB (direction INPUT)) + (port RSTA (direction INPUT)) + (port RSTB (direction INPUT)) + (port (array (rename DOA "DOA[31:0]") 32) (direction OUTPUT)) + (port (array (rename DOB "DOB[31:0]") 32) (direction OUTPUT)) + (port (array (rename DOPA "DOPA[3:0]") 4) (direction OUTPUT)) + (port (array (rename DOPB "DOPB[3:0]") 4) (direction OUTPUT)) + (port (array (rename ADDRA "ADDRA[13:0]") 14) (direction INPUT)) + (port (array (rename ADDRB "ADDRB[13:0]") 14) (direction INPUT)) + (port (array (rename DIA "DIA[31:0]") 32) (direction INPUT)) + (port (array (rename DIB "DIB[31:0]") 32) (direction INPUT)) + (port (array (rename DIPA "DIPA[3:0]") 4) (direction INPUT)) + (port (array (rename DIPB "DIPB[3:0]") 4) (direction INPUT)) + (port (array (rename WEA "WEA[3:0]") 4) (direction INPUT)) + (port (array (rename WEB "WEB[3:0]") 4) (direction INPUT)) + ) + ) + ) + (cell LUT1 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + ) + ) + ) + (cell FDSE (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port CE (direction INPUT)) + (port D (direction INPUT)) + (port S (direction INPUT)) + ) + ) + ) + (cell LUT4 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + (port I3 (direction INPUT)) + ) + ) + ) + (cell LUT5 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + (port I3 (direction INPUT)) + (port I4 (direction INPUT)) + ) + ) + ) + (cell FDR (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port D (direction INPUT)) + (port R (direction INPUT)) + ) + ) + ) + (cell FDE (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port CE (direction INPUT)) + (port D (direction INPUT)) + ) + ) + ) + (cell IBUFG (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I (direction INPUT)) + ) + ) + ) + (cell MUXF7 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port S (direction INPUT)) + ) + ) + ) + (cell RAMB8BWER (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port CLKAWRCLK (direction INPUT)) + (port CLKBRDCLK (direction INPUT)) + (port ENAWREN (direction INPUT)) + (port ENBRDEN (direction INPUT)) + (port REGCEA (direction INPUT)) + (port REGCEBREGCE (direction INPUT)) + (port RSTA (direction INPUT)) + (port RSTBRST (direction INPUT)) + (port (array (rename DOADO "DOADO[15:0]") 16) (direction OUTPUT)) + (port (array (rename DOBDO "DOBDO[15:0]") 16) (direction OUTPUT)) + (port (array (rename DOPADOP "DOPADOP[1:0]") 2) (direction OUTPUT)) + (port (array (rename DOPBDOP "DOPBDOP[1:0]") 2) (direction OUTPUT)) + (port (array (rename ADDRAWRADDR "ADDRAWRADDR[12:0]") 13) (direction INPUT)) + (port (array (rename ADDRBRDADDR "ADDRBRDADDR[12:0]") 13) (direction INPUT)) + (port (array (rename DIADI "DIADI[15:0]") 16) (direction INPUT)) + (port (array (rename DIBDI "DIBDI[15:0]") 16) (direction INPUT)) + (port (array (rename DIPADIP "DIPADIP[1:0]") 2) (direction INPUT)) + (port (array (rename DIPBDIP "DIPBDIP[1:0]") 2) (direction INPUT)) + (port (array (rename WEAWEL "WEAWEL[1:0]") 2) (direction INPUT)) + (port (array (rename WEBWEU "WEBWEU[1:0]") 2) (direction INPUT)) + ) + ) + ) + (cell BUFG (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I (direction INPUT)) + ) + ) + ) + (cell IBUFGDS (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I (direction INPUT)) + (port IB (direction INPUT)) + ) + ) + ) + (cell FDS (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port D (direction INPUT)) + (port S (direction INPUT)) + ) + ) + ) + (cell FDP (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port D (direction INPUT)) + (port PRE (direction INPUT)) + ) + ) + ) + (cell GND (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port G (direction OUTPUT)) + ) + ) + ) + (cell IBUF (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I (direction INPUT)) + ) + ) + ) + (cell VCC (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port P (direction OUTPUT)) + ) + ) + ) + (cell DCM_SP (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port CLK0 (direction OUTPUT)) + (port CLK180 (direction OUTPUT)) + (port CLK270 (direction OUTPUT)) + (port CLK2X (direction OUTPUT)) + (port CLK2X180 (direction OUTPUT)) + (port CLK90 (direction OUTPUT)) + (port CLKDV (direction OUTPUT)) + (port CLKFX (direction OUTPUT)) + (port CLKFX180 (direction OUTPUT)) + (port LOCKED (direction OUTPUT)) + (port PSDONE (direction OUTPUT)) + (port CLKFB (direction INPUT)) + (port CLKIN (direction INPUT)) + (port DSSEN (direction INPUT)) + (port PSCLK (direction INPUT)) + (port PSEN (direction INPUT)) + (port PSINCDEC (direction INPUT)) + (port RST (direction INPUT)) + (port (array (rename STATUS "STATUS[7:0]") 8) (direction OUTPUT)) + ) + ) + ) + (cell INV (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port I (direction INPUT)) + (port O (direction OUTPUT)) + ) + ) + ) + ) + (Library b200_lib + (edifLevel 0) + (technology (numberDefinition )) + (cell fifo_4k_2clk (celltype GENERIC) + (view view_1 (viewtype NETLIST) + (interface + (port rst (direction INPUT)) + (port wr_clk (direction INPUT)) + (port rd_clk (direction INPUT)) + (port wr_en (direction INPUT)) + (port rd_en (direction INPUT)) + (port full (direction OUTPUT)) + (port empty (direction OUTPUT)) + (port (array (rename din "din[71:0]") 72) (direction INPUT)) + (port (array (rename dout "dout[71:0]") 72) (direction OUTPUT)) + (port (array (rename rd_data_count "rd_data_count[9:0]") 10) (direction OUTPUT)) + (port (array (rename wr_data_count "wr_data_count[9:0]") 10) (direction OUTPUT)) + ) + ) + ) + (cell b200 (celltype GENERIC) + (view view_1 (viewtype NETLIST) + (interface + (port cat_miso (direction INPUT)) + (port fx3_ce (direction INPUT)) + (port fx3_mosi (direction INPUT)) + (port fx3_sclk (direction INPUT)) + (port FPGA_RXD0 (direction INPUT)) + (port FPGA_TXD0 (direction INPUT)) + (port SCL_FPGA (direction INPUT)) + (port SDA_FPGA (direction INPUT)) + (port codec_data_clk_p (direction INPUT)) + (port rx_frame_p (direction INPUT)) + (port cat_clkout_fpga (direction INPUT)) + (port codec_main_clk_p (direction INPUT)) + (port codec_main_clk_n (direction INPUT)) + (port GPIF_CTL4 (direction INPUT)) + (port GPIF_CTL5 (direction INPUT)) + (port GPIF_CTL6 (direction INPUT)) + (port GPIF_CTL8 (direction INPUT)) + (port GPIF_CTL9 (direction INPUT)) + (port gps_lock (direction INPUT)) + (port gps_rxd (direction INPUT)) + (port gps_txd (direction INPUT)) + (port gps_txd_nmea (direction INPUT)) + (port pll_lock (direction INPUT)) + (port FPGA_CFG_CS (direction INPUT)) + (port AUX_PWR_ON (direction INPUT)) + (port PPS_IN_EXT (direction INPUT)) + (port PPS_IN_INT (direction INPUT)) + (port pps_out (direction INPUT)) + (port cat_ce (direction OUTPUT)) + (port cat_mosi (direction OUTPUT)) + (port cat_sclk (direction OUTPUT)) + (port fx3_miso (direction OUTPUT)) + (port pll_ce (direction OUTPUT)) + (port pll_mosi (direction OUTPUT)) + (port pll_sclk (direction OUTPUT)) + (port codec_enable (direction OUTPUT)) + (port codec_en_agc (direction OUTPUT)) + (port codec_reset (direction OUTPUT)) + (port codec_sync (direction OUTPUT)) + (port codec_txrx (direction OUTPUT)) + (port codec_fb_clk_p (direction OUTPUT)) + (port tx_frame_p (direction OUTPUT)) + (port IFCLK (direction OUTPUT)) + (port FX3_EXTINT (direction OUTPUT)) + (port GPIF_CTL0 (direction OUTPUT)) + (port GPIF_CTL1 (direction OUTPUT)) + (port GPIF_CTL2 (direction OUTPUT)) + (port GPIF_CTL3 (direction OUTPUT)) + (port GPIF_CTL7 (direction OUTPUT)) + (port GPIF_CTL11 (direction OUTPUT)) + (port GPIF_CTL12 (direction OUTPUT)) + (port gps_out_enable (direction OUTPUT)) + (port gps_ref_enable (direction OUTPUT)) + (port LED_RX1 (direction OUTPUT)) + (port LED_RX2 (direction OUTPUT)) + (port LED_TXRX1_RX (direction OUTPUT)) + (port LED_TXRX1_TX (direction OUTPUT)) + (port LED_TXRX2_RX (direction OUTPUT)) + (port LED_TXRX2_TX (direction OUTPUT)) + (port ext_ref_enable (direction OUTPUT)) + (port pps_fpga_out_enable (direction OUTPUT)) + (port SFDX1_RX (direction OUTPUT)) + (port SFDX1_TX (direction OUTPUT)) + (port SFDX2_RX (direction OUTPUT)) + (port SFDX2_TX (direction OUTPUT)) + (port SRX1_RX (direction OUTPUT)) + (port SRX1_TX (direction OUTPUT)) + (port SRX2_RX (direction OUTPUT)) + (port SRX2_TX (direction OUTPUT)) + (port tx_bandsel_a (direction OUTPUT)) + (port tx_bandsel_b (direction OUTPUT)) + (port tx_enable1 (direction OUTPUT)) + (port tx_enable2 (direction OUTPUT)) + (port rx_bandsel_a (direction OUTPUT)) + (port rx_bandsel_b (direction OUTPUT)) + (port rx_bandsel_c (direction OUTPUT)) + (port (array (rename codec_ctrl_out "codec_ctrl_out[7:0]") 8) (direction INPUT)) + (port (array (rename rx_codec_d "rx_codec_d[11:0]") 12) (direction INPUT)) + (port (array (rename codec_ctrl_in "codec_ctrl_in[3:0]") 4) (direction OUTPUT)) + (port (array (rename tx_codec_d "tx_codec_d[11:0]") 12) (direction OUTPUT)) + (port (array (rename debug "debug[31:0]") 32) (direction OUTPUT)) + (port (array (rename debug_clk "debug_clk[1:0]") 2) (direction OUTPUT)) + (port (array (rename GPIF_D "GPIF_D[31:0]") 32) (direction INOUT)) + ) + (contents + (instance (rename f1_Result_7_2_FRB "f1/Result<7>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Result_11_2_FRB "f1/Result<11>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcompar_becoming_full_cy_2_ "f1/Mcompar_becoming_full_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_tx/cross_clock_fifo/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___120___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg_glue_set")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata341 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata341") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___111___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata291")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata291 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata291") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___111___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata291")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_20__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[20].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_15__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[15].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_43__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[43].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_38__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[38].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Mcompar_becoming_full_cy_3_ "f1/Mcompar_becoming_full_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata401 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata401") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___108___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata510")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata351 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata351") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___85___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata351")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance debug_23_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance debug_18_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata410 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata410") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___109___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata410")) + (property INIT (string "4'h8")) + ) + (instance (rename f1_Mcompar_becoming_full_cy_4_ "f1/Mcompar_becoming_full_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata411 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata411") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___107___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata65")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata361 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata361") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___84___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata361")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_GND_14_o_read_OR_37_o1 "f1/GND_14_o_read_OR_37_o1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___31___f1/GND_14_o_read_OR_37_o1")) + (property INIT (string "8'h72")) + ) + (instance (rename slave_fifo32_debug1_0 "slave_fifo32/debug1_0") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_wr_addr_xor_10_ "f0/Mcount_wr_addr_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_debug1_1 "slave_fifo32/debug1_1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata421 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata421") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___106___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata71")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata371 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata371") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___110___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata210")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_debug1_2 "slave_fifo32/debug1_2") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_debug1_3 "slave_fifo32/debug1_3") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_4 "slave_fifo32/debug1_4") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_5 "slave_fifo32/debug1_5") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_wr_addr_xor_11_ "f0/Mcount_wr_addr_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_debug1_6 "slave_fifo32/debug1_6") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata431 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata431") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___105___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata81")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata381 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata381") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___82___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata310")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_debug1_7 "slave_fifo32/debug1_7") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_debug1_8 "slave_fifo32/debug1_8") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_9 "slave_fifo32/debug1_9") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_17__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[17].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_22__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[22].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f0_Mcount_wr_addr_xor_12_ "f0/Mcount_wr_addr_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata391 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata391") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___109___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata410")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata441 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata441") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___104___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata91")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename catgen_gen_pins_4__oddr2 "catgen/gen_pins[4].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata501 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata501") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___98___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata151")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata451 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata451") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___103___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata301")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___134___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata510 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata510") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___108___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata510")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata461 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata461") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___102___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata101")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_o_tvalid11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___169___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_o_tvalid11")) + (property INIT (string "8'hC8")) + ) + (instance (rename f1_dont_write_past_me_1__FRB "f1/dont_write_past_me<1>_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata511 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata511") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___97___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata161")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_1_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_sloe_rstpot "slave_fifo32/sloe_rstpot") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_debug2_0 "slave_fifo32/debug2_0") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT111") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___134___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_debug2_1 "slave_fifo32/debug2_1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In12_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In12_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___47___slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/read1")) + (property INIT (string "4'hD")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata521 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata521") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___96___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata171")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata471 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata471") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___101___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata111")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_18__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[18].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_23__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[23].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_debug2_2 "slave_fifo32/debug2_2") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_46__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[46].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_51__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[51].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_debug2_3 "slave_fifo32/debug2_3") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_4 "slave_fifo32/debug2_4") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug2_5 "slave_fifo32/debug2_5") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___133___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug2_6 "slave_fifo32/debug2_6") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata531 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata531") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___95___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata181")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata481 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata481") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___100___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata131")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug2_7 "slave_fifo32/debug2_7") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_8_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_Mcount_fifoadr_xor_1_11 "slave_fifo32/Mcount_fifoadr_xor<1>11") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___42___slave_fifo32/Mcount_fifoadr_xor<1>11")) + (property INIT (string "4'h6")) + ) + (instance (rename slave_fifo32_debug2_8 "slave_fifo32/debug2_8") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug2_9 "slave_fifo32/debug2_9") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT131") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___133___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata541 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata541") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___94___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata191")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata491 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata491") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___99___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata141")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_9_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_read_ready_go "slave_fifo32/read_ready_go") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_sloe_1_rstpot "slave_fifo32/sloe_1_rstpot") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAA2AAAAAAAFFAA")) + ) + (instance debug_19_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance debug_24_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tready1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0111111111111111")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT141 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___132___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_10 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata601 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata601") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___88___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata251")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata551 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata551") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___93___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata201")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_12 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_13 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_13") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_14 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_14") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_1_11 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<1>11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___117___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<1>11")) + (property INIT (string "8'h69")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_15 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_15") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT151 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT151") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___132___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata561 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata561") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___92___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata311")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata611 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata611") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___87___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata321")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_25__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[25].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_30__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[30].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT161") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram1") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + 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(property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + 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(property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string 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"256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string 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(property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string 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(property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string 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(property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string 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(property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_5__INV_0 "f1/Msub_dont_write_past_me_lut<5>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram7") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string 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(property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string 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(property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string 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(property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string 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slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata581 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata581") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___90___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata221")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_1 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram8") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string 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(property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string 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(property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string 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(property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string 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(true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string 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"256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_3 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_4 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata591 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata591") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___89___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata241")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata641 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata641") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___84___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata361")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___38___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>1")) + (property INIT (string "4'h6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_26__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[26].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_31__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[31].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_54__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[54].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_49__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[49].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_dont_write_past_me_2__FRB "f1/dont_write_past_me<2>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/empty_glue_rst") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFBFBFBFFFB00FB00")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<0>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<1>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_33__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[33].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_28__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[28].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<2>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance debug_30_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance debug_25_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<3>1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<3>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<4>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<5>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_34__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[34].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_29__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[29].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_57__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[57].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_62__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[62].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<6>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_EP_READY1 "slave_fifo32/EP_READY1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_5__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<5>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<7>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_9 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_dont_write_past_me_3__FRB "f1/dont_write_past_me<3>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<8>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_EP_READY "slave_fifo32/EP_READY") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_0__rt "f1/Msub_dont_write_past_me_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<9>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_36__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[36].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9CCC9CC6CCCCCCC6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_41__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[41].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_i_tready1 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/i_tready1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___170___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/i_tready1")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg_glue_set") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___119___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg_glue_set")) + (property INIT (string "16'hFFA2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_1__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[1].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance debug_26_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance debug_31_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_i_tvalid_int1_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'h8000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<5>1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h999A999999959999")) + ) + (instance (rename f0_Result_8_2_FRB "f0/Result<8>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv1_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_37__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[37].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o10_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_42__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[42].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<10>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<11>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename f1_dont_write_past_me_4__FRB "f1/dont_write_past_me<4>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_write1 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/write1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___16___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/write1")) + (property INIT (string "16'h5400")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<12>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_39__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[39].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata65 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata65") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___75___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata65")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_44__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[44].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata71 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata71") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___74___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata71")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_6_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<6>1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8211") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0001FFFF00007FFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_4__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[4].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata81 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata81") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___73___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata81")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_2_11 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<2>11") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___11___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<3>11")) + (property INIT (string "16'h6AA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata91 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata91") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___72___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata91")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker__n0131_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/_n0131_inv1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___46___slave_fifo32/fifo64_to_gpmc32_tx/checker/_n0131_inv1")) + (property INIT (string "16'h0455")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_45__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[45].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance debug_27_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_50__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[50].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_20_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_15_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv6_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___124___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8212_SW0")) + (property INIT (string "16'hEEEF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_rd_addr_0 "f1/rd_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_rd_addr_1 "f1/rd_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_rd_addr_2 "f1/rd_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_rd_addr_3 "f1/rd_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_rd_addr_4 "f1/rd_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_8__INV_0 "f0/Msub_dont_write_past_me_lut<8>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_rd_addr_5 "f1/rd_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_rd_addr_6 "f1/rd_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_rd_addr_7 "f1/rd_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker__n0227_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/_n0227_inv1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___4___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/_n0227_inv1")) + (property INIT (string "16'h0455")) + ) + (instance (rename f1_rd_addr_8 "f1/rd_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_rd_addr_9 "f1/rd_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr10_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr10_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_wr_addr_cy_10__rt "f0/Mcount_wr_addr_cy<10>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_52__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[52].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance SRX1_RX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_47__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[47].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_7__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[7].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_dont_write_past_me_5__FRB "f1/dont_write_past_me<5>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcount_rd_addr_cy_1__rt "f1/Mcount_rd_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAAAAAAAAAAAAA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h01FE00FF00FF807F")) + ) + (instance (rename f1_Mcount_wr_addr_xor_12__rt "f1/Mcount_wr_addr_xor<12>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_GND_56_o_read_OR_123_o1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/GND_56_o_read_OR_123_o1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___171___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tvalid11")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Result_8_2_FRB "f1/Result<8>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance cat_sclk_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/fifo_4k_2clk") (viewref view_1 (cellref fifo_4k_2clk (libraryref b200_lib))) + (property BUS_INFO (string "10:OUTPUT:wr_data_count<9:0>")) + ) + (instance (rename f1_Result_12_2_FRB "f1/Result<12>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_53__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[53].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_48__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[48].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance debug_28_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_2__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[2].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8211") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFF7FFFFFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_rd_addr_cy_5__rt "f0/Mcount_rd_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance ODDR2_ifclk_dbg (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "NONE")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_55__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[55].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_60__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[60].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_Mcount_idle_cycles_xor_0_11 "slave_fifo32/Mcount_idle_cycles_xor<0>11") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___177___slave_fifo32/Mcount_idle_cycles_xor<0>11")) + (property INIT (string "4'h1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/clear_dump_OR_154_o") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000000000000001")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<10>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___130___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101")) + (property INIT (string "4'hE")) + ) + (instance (rename f1_Mcount_wr_addr_xor_10_ "f1/Mcount_wr_addr_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_dont_write_past_me_6__FRB "f1/dont_write_past_me<6>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance SRX2_TX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<11>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename f1_Mcount_rd_addr_cy_6__rt "f1/Mcount_rd_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance GPIF_D_2_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_56__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[56].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_61__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[61].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT111") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___130___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101")) + (property INIT (string "4'hE")) + ) + (instance (rename f1_Mcount_wr_addr_xor_11_ "f1/Mcount_wr_addr_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_10_ "f1/Msub_dont_write_past_me_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<12>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram1") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram2") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram3") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___129___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram4") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string 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(property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string 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(property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string 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(property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string 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(libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<13>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram6") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string 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"slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram8") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string 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(property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string 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"256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram9") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT131") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___129___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121")) + (property INIT (string "4'hE")) + ) + (instance (rename f0_Mcount_rd_addr_cy_0_ "f0/Mcount_rd_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_5__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[5].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<14>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename f1_Mcount_wr_addr_cy_11__rt "f1/Mcount_wr_addr_cy<11>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance debug_29_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT141 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___128___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141")) + (property INIT (string "4'hE")) + ) + (instance (rename f0_Mcount_rd_addr_cy_1_ "f0/Mcount_rd_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<15>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata101 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata101") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___146___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata101")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_58__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[58].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT151 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT151") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___128___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_63__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[63].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32__n0223_inv1 "slave_fifo32/_n0223_inv1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___21___slave_fifo32/_n0223_inv1")) + (property INIT (string "8'h82")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f0_Mcount_rd_addr_cy_2_ "f0/Mcount_rd_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata110 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata110") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___151___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata110")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata111 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata111") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___146___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata101")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr3_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT161") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename f0_Mcount_rd_addr_cy_3_ "f0/Mcount_rd_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata121 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata121") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___145___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata121")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<0>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hAC")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename f0_Mcount_rd_addr_cy_4_ "f0/Mcount_rd_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9CCC9CC6CCCCCCC6")) + ) + (instance (rename slave_fifo32__n0279_inv_SW0 "slave_fifo32/_n0279_inv_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___121___slave_fifo32/_n0258_inv_SW0")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_3__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<3>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/dump_glue_set") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h00400000AAEAAAAA")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata131 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata131") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___145___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata121")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<1>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hAC")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f0_Mcount_rd_addr_cy_5_ "f0/Mcount_rd_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_59__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[59].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_64__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[64].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata141 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata141") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___144___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata141")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<2>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<3>11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___11___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<3>11")) + (property INIT (string "32'h6AAAAAA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_0_11_INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<0>11_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename f0_Mcount_rd_addr_cy_6_ "f0/Mcount_rd_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_dont_write_past_me_7__FRB "f1/dont_write_past_me<7>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata151 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata151") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___144___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata141")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata201 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata201") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___141___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata201")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<3>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_slrd1 "slave_fifo32/slrd1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_slrd2 "slave_fifo32/slrd2") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_slrd3 "slave_fifo32/slrd3") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_rd_addr_cy_7_ "f0/Mcount_rd_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata210 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata210") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___151___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata110")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata161 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata161") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___143___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata161")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata211 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata211") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___141___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata201")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<4>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_o_tlast1 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/o_tlast1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___170___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/i_tready1")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_8__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[8].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f0_Mcount_rd_addr_cy_8_ "f0/Mcount_rd_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata171 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata171") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___143___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata161")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_gpif_data_out_0 "slave_fifo32/gpif_data_out_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata221 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata221") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___140___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata221")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<5>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_gpif_data_out_1 "slave_fifo32/gpif_data_out_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr7_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_gpif_data_out_2 "slave_fifo32/gpif_data_out_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename f0_Mcount_rd_addr_cy_9_ "f0/Mcount_rd_addr_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_gpif_data_out_3 "slave_fifo32/gpif_data_out_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_4 "slave_fifo32/gpif_data_out_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata231 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata231") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___140___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata221")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_gpif_data_out_5 "slave_fifo32/gpif_data_out_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename f0__n0161_inv1_cy1 "f0/_n0161_inv1_cy1") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata181 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata181") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___142___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata181")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<6>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_gpif_data_out_6 "slave_fifo32/gpif_data_out_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_7 "slave_fifo32/gpif_data_out_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT33 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT33") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_gpif_data_out_8 "slave_fifo32/gpif_data_out_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___7___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv_SW0")) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename slave_fifo32__n0279_inv "slave_fifo32/_n0279_inv") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0020202008282828")) + ) + (instance (rename slave_fifo32_gpif_data_out_9 "slave_fifo32/gpif_data_out_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata191 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata191") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___142___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata181")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata241 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata241") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___139___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata241")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<7>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT41 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT41") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata251 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata251") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___139___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata241")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata301 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata301") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___147___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata91")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<8>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT51 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT51") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr8_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___32___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111_SW0")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata261 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata261") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___138___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata261")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111_SW1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___32___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111_SW0")) + (property INIT (string "16'hF110")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata311 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata311") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___136___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata311")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<9>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT61 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT61") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata321 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata321") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___136___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata311")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata271 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata271") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___138___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata261")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT71 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT71") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata281 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata281") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___137___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata281")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT81 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT81") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_1_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<1>11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h69")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata291 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata291") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___137___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata281")) + (property INIT (string "8'hE4")) + ) + (instance (rename f1_dont_write_past_me_8__FRB "f1/dont_write_past_me<8>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT91 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT91") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___42___slave_fifo32/Mcount_fifoadr_xor<1>11")) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<10>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_cy "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_cy") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcount_rd_addr_cy_10__rt "f1/Mcount_rd_addr_cy<10>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_dont_write_past_me_10__FRB "f1/dont_write_past_me<10>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_0 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_1 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_2 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_10__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[10].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_3 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_4 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/state") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32__n0230_inv1 "slave_fifo32/_n0230_inv1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___48___slave_fifo32/_n0230_inv1")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int16_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'hEFFF")) + ) + (instance (rename f0_Result_9_2_FRB "f0/Result<9>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_GND_14_o_read_OR_37_o1 "f0/GND_14_o_read_OR_37_o1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___30___f0/GND_14_o_read_OR_37_o1")) + (property INIT (string "8'h72")) + ) + (instance (rename slave_fifo32_Mcount_idle_cycles_xor_1_11 "slave_fifo32/Mcount_idle_cycles_xor<1>11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___23___slave_fifo32/Mcount_idle_cycles_xor<2>11")) + (property INIT (string "8'h14")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr4_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_3 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_4 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_5 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_full_reg "f1/full_reg") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_6 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_rd_addr_xor_12__rt "f0/Mcount_rd_addr_xor<12>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___2___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0")) + (property INIT (string "16'hFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr5_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_GND_66_o_read_OR_144_o1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/GND_66_o_read_OR_144_o1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___169___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_o_tvalid11")) + (property INIT (string "8'hE4")) + ) + (instance (rename catgen_gen_pins_7__oddr2 "catgen/gen_pins[7].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename f1_dont_write_past_me_9__FRB "f1/dont_write_past_me<9>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0004FFFF00040004")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_12__INV_0 "f0/Msub_dont_write_past_me_lut<12>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_13__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[13].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr6_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_dont_write_past_me_11__FRB "f1/dont_write_past_me<11>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/clear_dump_OR_154_o_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'hD")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_0") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd2_BRB0") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance GPIF_D_21_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_16_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd2_BRB1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr7_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_2") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_3") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_4") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_5") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_6") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_4_11 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<4>11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h6AAAAAAAAAAAAAA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_7") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_8") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o10") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h8000000000000000")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_8__INV_0 "f1/Msub_dont_write_past_me_lut<8>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename f0__n0161_inv1_lut1 "f0/_n0161_inv1_lut1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'hD")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_F "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In14_F") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAA2A22FFAA7F22")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_16__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[16].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_G "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In14_G") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hA2AAA6A6F7FFA6A6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_21__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[21].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/empty_glue_rst_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename f1_Result_9_2_FRB "f1/Result<9>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_wr_addr_cy_3__rt "f0/Mcount_wr_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_dont_write_past_me_12__FRB "f1/dont_write_past_me<12>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tready_int1_SW0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h2F")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o61 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o61") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename f1_Mcount_rd_addr_cy_0_ "f1/Mcount_rd_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o71 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o71") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename f1_Mcount_wr_addr_cy_3__rt "f1/Mcount_wr_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Mcount_rd_addr_cy_1_ "f1/Mcount_rd_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o81 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o81") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename f1_rd_addr_10 "f1/rd_addr_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_rd_addr_11 "f1/rd_addr_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_rd_addr_cy_2_ "f1/Mcount_rd_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_rd_addr_12 "f1/rd_addr_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_2_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<2>11") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___20___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<2>11")) + (property INIT (string "16'h6AA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance LED_TXRX2_RX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f1_Mcount_rd_addr_cy_3_ "f1/Mcount_rd_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/clear_inv1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename f1_Mcount_rd_addr_cy_4_ "f1/Mcount_rd_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_19__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[19].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_24__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[24].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance gps_out_enable_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr4_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_rd_addr_cy_5_ "f1/Mcount_rd_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_8__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<8>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename f1_Mcount_rd_addr_cy_6_ "f1/Mcount_rd_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance GPIF_D_3_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT11_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename f1_Mcount_wr_addr_cy_0_ "f1/Mcount_wr_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr4_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_rd_addr_cy_7_ "f1/Mcount_rd_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_wr_addr_cy_8__rt "f0/Mcount_wr_addr_cy<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tlast1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0C0C0C0C0C0D0C0C")) + ) + (instance (rename f1_Mcount_wr_addr_cy_1_ "f1/Mcount_wr_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcount_rd_addr_cy_8_ "f1/Mcount_rd_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_Mcount_idle_cycles_xor_2_11 "slave_fifo32/Mcount_idle_cycles_xor<2>11") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___23___slave_fifo32/Mcount_idle_cycles_xor<2>11")) + (property INIT (string "16'h1444")) + ) + (instance (rename f1_Mcount_wr_addr_cy_2_ "f1/Mcount_wr_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcount_rd_addr_cy_9_ "f1/Mcount_rd_addr_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcount_wr_addr_cy_3_ "f1/Mcount_wr_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcount_wr_addr_cy_8__rt "f1/Mcount_wr_addr_cy<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Mcount_wr_addr_cy_4_ "f1/Mcount_wr_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01212") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0010001000000010")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01213 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01213") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9090900000900000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01214 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01214") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h99900000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01215 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01215") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0220000000000220")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[32].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01216 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01216") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_27__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[27].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Mcount_wr_addr_cy_5_ "f1/Mcount_wr_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01217 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01217") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0080000000000080")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01218 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01218") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___116___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full921")) + (property INIT (string "16'h0440")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01219 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01219") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFAF8AA0000000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror5_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror5_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFEFFFF")) + ) + (instance (rename f1_Mcount_wr_addr_cy_6_ "f1/Mcount_wr_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr9_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr9_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_wr_addr_cy_7_ "f1/Mcount_wr_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance FX3_EXTINT_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_0_ "f1/Msub_dont_write_past_me_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcount_wr_addr_cy_8_ "f1/Mcount_wr_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_gpif_data_out_31_1 "slave_fifo32/gpif_data_out_31_1") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_9__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<9>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance codec_data_clk_bufg (viewref netlist (cellref IBUFG (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + (property IBUF_DELAY_VALUE (string "0")) + (property IBUF_LOW_PWR (boolean (true))) + (property IOSTANDARD (string "DEFAULT")) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_1_ "f1/Msub_dont_write_past_me_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcount_wr_addr_cy_9_ "f1/Mcount_wr_addr_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212111 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01212111") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr9_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr9_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_2_ "f1/Msub_dont_write_past_me_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tvalid11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___127___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tvalid11")) + (property INIT (string "8'hE0")) + ) + (instance (rename f0_read_state_FSM_FFd2_In1 "f0/read_state_FSM_FFd2-In1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFDFDFDFFA8A8A8FF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_3_ "f1/Msub_dont_write_past_me_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_4_ "f1/Msub_dont_write_past_me_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT11_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0021FFFF00FFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_i_tready "slave_fifo32/fifo64_to_gpmc32_ctrl/i_tready") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13_SW1") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_40__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[40].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[35].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_5_ "f1/Msub_dont_write_past_me_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_read_state_FSM_FFd2_In1 "f1/read_state_FSM_FFd2-In1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFDFDFDFFA8A8A8FF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h1")) + ) + (instance (rename f0__n0161_inv1_lut "f0/_n0161_inv1_lut") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11_SW1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h01")) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_6_ "f1/Msub_dont_write_past_me_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_7_ "f1/Msub_dont_write_past_me_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_8_ "f1/Msub_dont_write_past_me_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_slrd2_1 "slave_fifo32/slrd2_1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1-In111") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___10___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n0146_inv1")) + (property INIT (string "16'h7F2A")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_9_ "f1/Msub_dont_write_past_me_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o1 "slave_fifo32/ctrl_tx_tready_data_tx_tready_OR_55_o1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'h5410")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_1__rt "f0/Msub_dont_write_past_me_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1 "slave_fifo32/Mmux_state[1]_wr_fifo_eof_Mux_22_o1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h2A7F7F7FFFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01216_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01216_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFF6FFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_43__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[43].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_38__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[38].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<3>11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___20___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<2>11")) + (property INIT (string "32'h6AAAAAA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_12__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<12>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012111") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h2002000000002002")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012112") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h8822228C80202084")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012113 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012113") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename f0_ram_Mram_ram10 "f0/ram/Mram_ram10") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_111 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_space_xor<3>111") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___29___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_space_xor<3>111")) + (property INIT (string "32'hFFAEFFFF")) + ) + (instance (rename f0_Mcount_wr_addr_xor_0_ "f0/Mcount_wr_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_3__INV_0 "f0/Msub_dont_write_past_me_lut<3>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename f0_ram_Mram_ram11 "f0/ram/Mram_ram11") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + 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(property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string 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LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000000023003300")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_ram_Mram_ram13 "f0/ram/Mram_ram13") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string 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(property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string 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(property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string 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(property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + 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(viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_ram_Mram_ram16 "f0/ram/Mram_ram16") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string 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(property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string 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(property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string 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(property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string 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(property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string 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(property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property 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(property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string 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(property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string 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INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_ram_Mram_ram18 "f0/ram/Mram_ram18") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string 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(property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string 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(property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string 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(property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string 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(property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string 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(property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string 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(property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string 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(property INIT (string "1'b0")) + ) + (instance (rename f0_ram_Mram_ram24 "f0/ram/Mram_ram24") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string 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(property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string 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(property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string 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(property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string 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(property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string 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(property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string 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(property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f0_ram_Mram_ram30 "f0/ram/Mram_ram30") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string 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(property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f0_ram_Mram_ram25 "f0/ram/Mram_ram25") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_10 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_ram_Mram_ram26 "f0/ram/Mram_ram26") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f0_ram_Mram_ram31 "f0/ram/Mram_ram31") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f0_Mcount_wr_addr_xor_2_ "f0/Mcount_wr_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_ram_Mram_ram27 "f0/ram/Mram_ram27") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f0_ram_Mram_ram32 "f0/ram/Mram_ram32") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_12 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_ram_Mram_ram28 "f0/ram/Mram_ram28") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f0_ram_Mram_ram33 "f0/ram/Mram_ram33") (viewref netlist (cellref RAMB8BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "16:OUTPUT:DOBDO<15:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 1)) + (property DATA_WIDTH_B (integer 1)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "18'h00000")) + (property INIT_B (string "18'h00000")) + (property RAM_MODE (string "TDP")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "18'h00000")) + (property SRVAL_B (string "18'h00000")) + (property INIT_FILE (string "NONE")) + (property SIM_COLLISION_CHECK (string "ALL")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_ram_Mram_ram29 "f0/ram/Mram_ram29") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f0_Mcount_wr_addr_xor_3_ "f0/Mcount_wr_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_wr_addr_xor_4_ "f0/Mcount_wr_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_wr_addr_xor_5_ "f0/Mcount_wr_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_51__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[51].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_46__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[46].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_wr_addr_xor_6_ "f0/Mcount_wr_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance rx_bandsel_a_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_read1 "slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/read1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___47___slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/read1")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___37___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0154_inv1")) + (property INIT (string "4'h4")) + ) + (instance (rename f0_Mcount_wr_addr_xor_7_ "f0/Mcount_wr_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_wr_addr_xor_8_ "f0/Mcount_wr_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0121111 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0121111") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___173___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0121111")) + (property INIT (string "4'hE")) + ) + (instance (rename f0_Mcount_wr_addr_xor_9_ "f0/Mcount_wr_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_22_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_17_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/read") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0111111111111111")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_6__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<6>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance SRX1_TX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_54__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[54].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_49__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[49].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0076_inv") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h00000001FFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename f1_ram_Mram_ram10 "f1/ram/Mram_ram10") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance rx_bandsel_b_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f1_ram_Mram_ram11 "f1/ram/Mram_ram11") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_11_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_ram_Mram_ram12 "f1/ram/Mram_ram12") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_i_tready "slave_fifo32/fifo64_to_gpmc32_tx/i_tready") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_ram_Mram_ram13 "f1/ram/Mram_ram13") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) 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(property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string 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(property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string 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(property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f1_ram_Mram_ram14 "f1/ram/Mram_ram14") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string 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(property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string 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(property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string 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(property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string 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slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h5140514055555140")) + ) + (instance (rename f1_ram_Mram_ram15 "f1/ram/Mram_ram15") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string 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(property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string 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(property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string 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(property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f1_ram_Mram_ram20 "f1/ram/Mram_ram20") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string 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(property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string 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(property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string 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(property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string 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(property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string 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(property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string 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INIT_FILE (string "NONE")) + ) + (instance (rename f1_ram_Mram_ram16 "f1/ram/Mram_ram16") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string 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(property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string 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(property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string 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(property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string 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BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string 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(property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string 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(property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string 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(property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f1_ram_Mram_ram22 "f1/ram/Mram_ram22") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string 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(property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string 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(property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string 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(property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string 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"f1/Mcount_rd_addr_xor<12>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_ram_Mram_ram23 "f1/ram/Mram_ram23") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 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INIT_FILE (string "NONE")) + ) + (instance (rename f1_ram_Mram_ram18 "f1/ram/Mram_ram18") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string 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(property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string 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(property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f1_ram_Mram_ram26 "f1/ram/Mram_ram26") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string 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(property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string 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(property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string 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(property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_ram_Mram_ram27 "f1/ram/Mram_ram27") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string 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(property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string 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(property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string 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(property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f1_ram_Mram_ram32 "f1/ram/Mram_ram32") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string 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(property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string 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(property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string 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(property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_ram_Mram_ram28 "f1/ram/Mram_ram28") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string 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(property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string 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(property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string 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(property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string 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"256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f1_ram_Mram_ram33 "f1/ram/Mram_ram33") (viewref netlist (cellref RAMB8BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "16:OUTPUT:DOBDO<15:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string 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(property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 1)) + (property DATA_WIDTH_B (integer 1)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "18'h00000")) + (property INIT_B (string "18'h00000")) + (property RAM_MODE (string "TDP")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "18'h00000")) + (property SRVAL_B (string "18'h00000")) + (property INIT_FILE (string "NONE")) + (property SIM_COLLISION_CHECK (string "ALL")) + ) + (instance (rename f1_ram_Mram_ram29 "f1/ram/Mram_ram29") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32__n0237_inv1 "slave_fifo32/_n0237_inv1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000000100000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1__n0161_inv1_cy1 "f1/_n0161_inv1_cy1") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_pktend "slave_fifo32/pktend") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + (property IOB (string "TRUE")) + ) + (instance fx3_miso1 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___180___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/write1")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_57__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[57].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[62].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/ram/Mram_ram1") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 18)) + (property DATA_WIDTH_B (integer 18)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/ram/Mram_ram2") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 18)) + (property DATA_WIDTH_B (integer 18)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f1_Mcount_rd_addr_xor_0_ "f1/Mcount_rd_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT21") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___22___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511")) + (property INIT (string "32'hBF4040BF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_4_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_4_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<4>11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h6AAAAAAAAAAAAAA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___14___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv31")) + (property INIT (string "32'hFFFF4B44")) + ) + (instance (rename f1_Mcount_rd_addr_xor_1_ "f1/Mcount_rd_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT31") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hE178E1E1E1E1E1E1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance rx_bandsel_c_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_rd_one_rstpot "slave_fifo32/rd_one_rstpot") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename f1_Mcount_rd_addr_xor_2_ "f1/Mcount_rd_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT41") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___36___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111")) + (property INIT (string "32'h9AAAAAA6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_9_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_9_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_rd_addr_xor_3_ "f1/Mcount_rd_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT51") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAA9AAAA6A696A6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_o_tvalid11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000FFFF0000FEFF")) + ) + (instance (rename slave_fifo32_slrd_rstpot "slave_fifo32/slrd_rstpot") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAA2AAAFAAA2AFAFA")) + ) + (instance (rename f1_Mcount_rd_addr_xor_4_ "f1/Mcount_rd_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT61") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h99AA99A6AAAAAAA6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_0__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[0].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Mcount_rd_addr_xor_5_ "f1/Mcount_rd_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcount_rd_addr_xor_6_ "f1/Mcount_rd_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFF0040BFBF4000FF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_1__rt "f1/Msub_dont_write_past_me_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Mcount_rd_addr_xor_7_ "f1/Mcount_rd_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___4___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/_n0227_inv1")) + (property INIT (string "32'hDFDDFFFF")) + ) + (instance LED_RX1_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In12") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFBEEEA55514440")) + ) + (instance (rename f1_Mcount_rd_addr_xor_8_ "f1/Mcount_rd_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Result_0_1_FRB "f0/Result<0>1_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In14") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAAAAAA2A080808")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/empty_glue_rst") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFC55FC54FF55FF55")) + ) + (instance (rename f1_Mcount_rd_addr_xor_9_ "f1/Mcount_rd_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT4_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___126___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/clear_dump_OR_131_o_SW0")) + (property INIT (string "16'hCCC9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In31") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In32") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In33 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In33") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'hFDFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In34") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFB")) + ) + (instance (rename catgen_gen_pins_10__oddr2 "catgen/gen_pins[10].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_11__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<11>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_debug1_16_BRB0 "slave_fifo32/debug1_16_BRB0") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_3__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[3].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_9_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_9_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8212_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___124___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8212_SW0")) + (property INIT (string "4'h6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8212_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAAAAAAAAAAAAA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata101 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata101") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___70___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata101")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata110 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata110") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___81___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata110")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata111 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata111") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___69___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata111")) + (property INIT (string "4'h8")) + ) + (instance pll_ce_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata121 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata121") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___80___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata121")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full411") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___19___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full421")) + (property INIT (string "16'hFEEE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/state") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata131 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata131") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___68___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata131")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full421") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___19___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full421")) + (property INIT (string "16'h0111")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In11") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___118___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In11")) + (property INIT (string "16'hFFF9")) + ) + (instance LED_RX2_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename catgen_gen_pins_2__oddr2 "catgen/gen_pins[2].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata141 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata141") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___67___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata141")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In13") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAA3B8819AA2A8808")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1 "slave_fifo32/Mmux_state[1]_wr_fifo_xfer_Mux_21_o1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h777FF7FFFFFFFFFF")) + ) + (instance (rename slave_fifo32_state_FSM_FFd1 "slave_fifo32/state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_state_FSM_FFd2 "slave_fifo32/state_FSM_FFd2") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01212211") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h8020401008020401")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata201 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata201") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___61___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata201")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata151 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata151") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___66___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata151")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_11__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[11].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_space_xor<3>111_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata210 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata210") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___78___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata210")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata161 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata161") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___65___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata161")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata211 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata211") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___59___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata211")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_Mcount_fifoadr_xor_0_11_INV_0 "slave_fifo32/Mcount_fifoadr_xor<0>11_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename gen_clks_clkout1_buf "gen_clks/clkout1_buf") (viewref netlist (cellref BUFG (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_6__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[6].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata171 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata171") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___64___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata171")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata221 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata221") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___58___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata221")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_debug1_17_BRB0 "slave_fifo32/debug1_17_BRB0") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_rd_addr_cy_1__rt "f0/Mcount_rd_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata181 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata181") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___63___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata181")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata231 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata231") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___51___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata231")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT11_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<12>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr11_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr11_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata191 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata191") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___62___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata191")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata241 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata241") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___57___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata241")) + (property INIT (string "4'h8")) + ) + (instance (rename f0_Mcount_wr_addr_cy_11__rt "f0/Mcount_wr_addr_cy<11>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f0_Mcount_rd_addr_cy_10_ "f0/Mcount_rd_addr_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<13>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata251 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata251") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___56___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata251")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata301 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata301") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___71___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata301")) + (property INIT (string "8'hE4")) + ) + (instance (rename f1_Result_0_1_FRB "f1/Result<0>1_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename f0_Mcount_rd_addr_cy_11_ "f0/Mcount_rd_addr_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<14>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata310 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata310") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___50___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata310")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata261 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata261") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___81___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata110")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata311 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata311") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___60___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata311")) + (property INIT (string "8'hE4")) + ) + (instance (rename f1_Mcount_rd_addr_cy_2__rt "f1/Mcount_rd_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_3__INV_0 "f1/Msub_dont_write_past_me_lut<3>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata271 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata271") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___80___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata121")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata321 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata321") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___55___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata321")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_14__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[14].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata281 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata281") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___51___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata231")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata331 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata331") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___54___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata331")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full621") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFEFEFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_2__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[2].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata291 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata291") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___79___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata291")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata341 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata341") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___79___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata291")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_9__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[9].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance tx_enable1_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr10_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr10_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata351 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata351") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___53___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata351")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata401 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata401") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___76___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata510")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata410 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata410") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___77___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata410")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata361 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata361") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___52___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata361")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata411 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata411") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___75___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata65")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_rd_addr_cy_6__rt "f0/Mcount_rd_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata421 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata421") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___74___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata71")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata371 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata371") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___78___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata210")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_wr_one "slave_fifo32/wr_one") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata431 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata431") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___73___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata81")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata381 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata381") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___50___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata310")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename gen_clks_clkin1_buf "gen_clks/clkin1_buf") (viewref netlist (cellref IBUFGDS (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + (property IOSTANDARD (string "DEFAULT")) + (property IBUF_DELAY_VALUE (string "0")) + (property IBUF_LOW_PWR (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_11_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata441 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata441") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___72___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata91")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata391 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata391") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___77___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata410")) + (property INIT (string "8'hE4")) + ) + (instance LED_TXRX1_RX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___45___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/write1")) + (property INIT (string "4'h4")) + ) + (instance GPIF_D_23_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_18_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_12_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata501 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata501") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___66___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata151")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata451 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata451") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___71___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata301")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_22__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[22].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_write11 "f1/write11") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___123___f1/write11")) + (property INIT (string "4'h1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_17__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[17].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Mcount_rd_addr_cy_7__rt "f1/Mcount_rd_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata510 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata510") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___76___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata510")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata461 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata461") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___70___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata101")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata511 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata511") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___65___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata161")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_5__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[5].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT21") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'h9996")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata471 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata471") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___69___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata111")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata521 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata521") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___64___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata171")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_3__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<3>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr3_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT31") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hA9A9A9A9FF0000FF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata481 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata481") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___68___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata131")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata531 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata531") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___63___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata181")) + (property INIT (string "8'hE4")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_10_ "f0/Msub_dont_write_past_me_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance tx_enable2_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata491 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata491") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___67___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata141")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata541 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata541") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___62___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata191")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_11_ "f0/Msub_dont_write_past_me_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_write1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/write1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0001000000000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT52") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hC9C9C9C900FFFF00")) + ) + (instance (rename slave_fifo32_sloe_1 "slave_fifo32/sloe_1") (viewref netlist (cellref FDS (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata601 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata601") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___56___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata251")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata551 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata551") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___61___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata201")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_sloe_2 "slave_fifo32/sloe_2") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_12_ "f0/Msub_dont_write_past_me_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_sloe_3 "slave_fifo32/sloe_3") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_4 "slave_fifo32/sloe_4") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr4_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_sloe_5 "slave_fifo32/sloe_5") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata561 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata561") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___60___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata311")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_sloe_6 "slave_fifo32/sloe_6") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata611 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata611") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___55___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata321")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_sloe_7 "slave_fifo32/sloe_7") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename f0_Mcount_rd_addr_cy_10__rt "f0/Mcount_rd_addr_cy<10>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_sloe_8 "slave_fifo32/sloe_8") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_9 "slave_fifo32/sloe_9") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT71") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0EE00FF00FF00FF0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata571 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata571") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___59___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata211")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata621 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata621") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___54___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata331")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT73") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFF0000FFFF1000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<0>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_30__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[30].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hF0F0F0F08877EE11")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_25__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[25].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata581 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata581") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___58___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata221")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata631 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata631") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___53___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata351")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full921 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full921") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___116___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full921")) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<1>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_8__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[8].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata641 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata641") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___52___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata361")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata591 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata591") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___57___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata241")) + (property INIT (string "8'hE4")) + ) + (instance (rename f0_Mcount_wr_addr_cy_0_ "f0/Mcount_wr_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0076_inv_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___41___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<2>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_lut1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFF1110FFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance LED_TXRX2_TX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f0_Mcount_wr_addr_cy_1_ "f0/Mcount_wr_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<3>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_wr_addr_cy_2_ "f0/Mcount_wr_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<4>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename f1__n0161_inv1_lut "f1/_n0161_inv1_lut") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr8_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_wr_addr_cy_3_ "f0/Mcount_wr_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/GND_56_o_read_OR_123_o1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h11101110FFFF1110")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<5>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1_SW0 "slave_fifo32/Mmux_state[1]_wr_fifo_xfer_Mux_21_o1_SW0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___24___slave_fifo32/Mmux_state[1]_wr_fifo_xfer_Mux_21_o1_SW0")) + (property INIT (string "8'hD0")) + ) + (instance (rename f0_Mcount_wr_addr_cy_4_ "f0/Mcount_wr_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_5_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<6>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0144_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0144_inv1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___8___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd1-In11")) + (property INIT (string "32'h00440F44")) + ) + (instance (rename f0_Mcount_wr_addr_cy_5_ "f0/Mcount_wr_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<7>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_12__INV_0 "f1/Msub_dont_write_past_me_lut<12>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_10__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[10].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr9_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr9_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_wr_addr_cy_6_ "f0/Mcount_wr_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_33__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[33].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<8>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_28__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[28].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_wr_addr_cy_7_ "f0/Mcount_wr_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<9>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_wr_addr_cy_8_ "f0/Mcount_wr_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/dump") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_wr_addr_cy_9_ "f0/Mcount_wr_addr_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT21") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_6__INV_0 "f0/Msub_dont_write_past_me_lut<6>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT17 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT17") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h56555656")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAAAAAAAAAAAAA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<11>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_12__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[12].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW2") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT31") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_rd_addr_cy_11__rt "f1/Mcount_rd_addr_cy<11>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tready_int11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_o_tready_int11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___33___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_o_tready_int11")) + (property INIT (string "8'h54")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01212111") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT41") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename f0_Result_1_1_FRB "f0/Result<1>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT51") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_glue_set "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/state_glue_set") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___28___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_space_xor<3>111")) + (property INIT (string "8'hA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<13>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_13__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[13].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT61") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0121211") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h8282414141418228")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_41__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[41].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_36__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[36].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<14>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr3_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr5_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<15>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_9_11 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<9>11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAAAAB9AAAAAAA8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___135___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT91") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___135___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___35___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511_SW0")) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01218_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h7")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_20__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[20].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr6_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_15__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[15].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty") (viewref netlist (cellref FDS (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1 "slave_fifo32/ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hA8A8A88820202000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr7_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_16__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[16].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_21__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[21].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/full_reg_glue_set") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFF008C008C008C")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_44__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[44].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_9__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<9>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_39__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[39].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___44___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0")) + (property INIT (string "8'hBF")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr8_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_23__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[23].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set_SW1 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/full_glue_set_SW1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___5___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv_SW0")) + (property INIT (string "32'hFFFF7FFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_18__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[18].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<10>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Result_1_1_FRB "f1/Result<1>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk "slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/fifo_4k_2clk") (viewref view_1 (cellref fifo_4k_2clk (libraryref b200_lib))) + (property BUS_INFO (string "10:OUTPUT:wr_data_count<9:0>")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o9") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11_SW1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_24__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[24].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_19__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[19].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_47__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[47].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_52__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[52].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f0_Mcount_wr_addr_cy_4__rt "f0/Mcount_wr_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_0_ "f1/Msub_dont_write_past_me_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1 "slave_fifo32/fifo64_to_gpmc32_ctrl/GND_63_o_space[15]_LessThan_2_o1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFF55555554")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_1_ "f1/Msub_dont_write_past_me_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcount_wr_addr_cy_4__rt "f1/Mcount_wr_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full411_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_2_ "f1/Msub_dont_write_past_me_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_31__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[31].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_26__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[26].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_gpif_data_in_0 "slave_fifo32/gpif_data_in_0") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_1 "slave_fifo32/gpif_data_in_1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_2 "slave_fifo32/gpif_data_in_2") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000FFFB0004FFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_gpif_data_in_3 "slave_fifo32/gpif_data_in_3") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212211 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212211") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_3_ "f1/Msub_dont_write_past_me_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_gpif_data_in_4 "slave_fifo32/gpif_data_in_4") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance ODDR2_ifclk (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "NONE")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_gpif_data_in_5 "slave_fifo32/gpif_data_in_5") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_full_reg_glue_set "f1/full_reg_glue_set") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___123___f1/write11")) + (property INIT (string "32'hF0FF4044")) + ) + (instance (rename slave_fifo32_gpif_data_in_6 "slave_fifo32/gpif_data_in_6") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_gpif_data_in_7 "slave_fifo32/gpif_data_in_7") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01216") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h350035F0")) + ) + (instance (rename slave_fifo32_gpif_data_in_8 "slave_fifo32/gpif_data_in_8") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/full_glue_set") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAA8AAA8AFFCFAA8A")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01217") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h999F999699999990")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_4_ "f1/Msub_dont_write_past_me_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_slrd_rstpot_SW0 "slave_fifo32/slrd_rstpot_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01218") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h4141414141411441")) + ) + (instance (rename slave_fifo32_gpif_data_in_9 "slave_fifo32/gpif_data_in_9") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01219 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01219") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAA08880800008008")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr5_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_5_ "f1/Msub_dont_write_past_me_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_27__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[27].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_32__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[32].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_24_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_19_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_55__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[55].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_60__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[60].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_6_ "f1/Msub_dont_write_past_me_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_7_ "f1/Msub_dont_write_past_me_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr5_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1__n0161_inv1_lut1 "f1/_n0161_inv1_lut1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'hD")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance IFCLK_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f0_Mcount_wr_addr_cy_9__rt "f0/Mcount_wr_addr_cy<9>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_8_ "f1/Msub_dont_write_past_me_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename catgen_oddr2_frame "catgen/oddr2_frame") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_9_ "f1/Msub_dont_write_past_me_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_34__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[34].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_29__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[29].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_10 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_o_tlast1 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/o_tlast1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___172___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/o_tlast1")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_12 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_wr_addr_cy_9__rt "f1/Mcount_wr_addr_cy<9>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full411_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_40__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[40].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty_glue_rst_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h1111000111111111")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_35__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[35].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_58__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[58].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_63__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[63].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_rd_addr_0 "f0/rd_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___34___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111")) + (property INIT (string "4'h7")) + ) + (instance (rename f0_rd_addr_1 "f0/rd_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_cy "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0_cy") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_i_tready1 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/i_tready1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___172___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/o_tlast1")) + (property INIT (string "4'h4")) + ) + (instance (rename f0_rd_addr_2 "f0/rd_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_rd_addr_3 "f0/rd_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_rd_addr_4 "f0/rd_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_rd_addr_5 "f0/rd_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_rd_addr_6 "f0/rd_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_rd_addr_7 "f0/rd_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_rd_addr_8 "f0/rd_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_rd_addr_9 "f0/rd_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_10 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_37__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[37].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFF66FF69FFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_42__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[42].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/state_glue_set") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___16___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/write1")) + (property INIT (string "16'hA2A6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename catgen_gen_pins_5__oddr2 "catgen/gen_pins[5].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000000000000001")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___3___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0")) + (property INIT (string "16'hFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_2__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[2].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_10__INV_0 "f0/Msub_dont_write_past_me_lut<10>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0004FFFF00040004")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_6_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_10_ "f1/Msub_dont_write_past_me_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_11_ "f1/Msub_dont_write_past_me_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_0__inv1_INV_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state<0>_inv1_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_38__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[38].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_43__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[43].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<13>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full421_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_12_ "f1/Msub_dont_write_past_me_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<14>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1-In111") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___13___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/_n0146_inv1")) + (property INIT (string "16'h7F2A")) + ) + (instance (rename f1_Mcount_rd_addr_xor_10_ "f1/Mcount_rd_addr_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___5___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv_SW0")) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<15>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_rd_addr_xor_11_ "f1/Mcount_rd_addr_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_9 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_rd_addr_xor_12_ "f1/Mcount_rd_addr_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/full_reg") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_45__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[45].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_50__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[50].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg") (viewref netlist (cellref FDS (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_pktend_1 "slave_fifo32/pktend_1") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_6__INV_0 "f1/Msub_dont_write_past_me_lut<6>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_5__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[5].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename gpif_sync_reset_int "gpif_sync/reset_int") (viewref netlist (cellref FDP (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01217_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01217_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'hA521")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Result_10_1_FRB "f0/Result<10>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Result_2_1_FRB "f0/Result<2>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_9 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/full_reg") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_46__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[46].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_51__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[51].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_EP_WMARK "slave_fifo32/EP_WMARK") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance ext_ref_enable_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance codec_reset_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_0__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[0].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_48__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[48].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_53__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[53].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_8__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[8].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv31 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv31") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___14___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv31")) + (property INIT (string "16'h4500")) + ) + (instance (rename slave_fifo32_slrd_1 "slave_fifo32/slrd_1") (viewref netlist (cellref FDS (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_space_xor<3>111_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_49__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[49].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<10>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_54__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[54].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_6__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<6>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___1___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531_SW0")) + (property INIT (string "16'hFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/empty") (viewref netlist (cellref FDS (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<11>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531_SW1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___1___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531_SW0")) + (property INIT (string "16'h8000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance cat_sclk1 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___178___cat_mosi1")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<12>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_3__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[3].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT411 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT411") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<12>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_13_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<13>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename f1_Mcount_wr_addr_lut_0__INV_0 "f1/Mcount_wr_addr_lut<0>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_cy1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_cy1") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<0>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f1_Mcount_rd_addr_lut_0__INV_0 "f1/Mcount_rd_addr_lut<0>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_13_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<13>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_14_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<14>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_56__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[56].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_61__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[61].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<1>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_14_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<14>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_15_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<15>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<2>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f0_write11 "f0/write11") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___122___f0/write11")) + (property INIT (string "4'h1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<3>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f1_Result_2_1_FRB "f1/Result<2>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/state") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_10__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<10>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<4>") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_57__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[57].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT511 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___22___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511")) + (property INIT (string "8'hBF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_62__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[62].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f0_read_state_FSM_FFd1 "f0/read_state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_read_state_FSM_FFd2 "f0/read_state_FSM_FFd2") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv31 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv31") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___12___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv31")) + (property INIT (string "16'h4500")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full1021 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full1021") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___43___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full1021")) + (property INIT (string "4'h9")) + ) + (instance (rename f1_Mcount_wr_addr_cy_10_ "f1/Mcount_wr_addr_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___3___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0")) + (property INIT (string "16'h8000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_6__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[6].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Mcount_wr_addr_cy_11_ "f1/Mcount_wr_addr_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0102_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___117___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<1>11")) + (property INIT (string "16'hFF57")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0102_SW1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___27___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv_SW0")) + (property INIT (string "8'h80")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_59__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[59].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hCCCCCCCCF0550FAA")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_64__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[64].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_dont_write_past_me_10__FRB "f0/dont_write_past_me<10>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_0_11_INV_0 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<0>11_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAA8AAAAAAABAAA")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/dump_glue_set") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h00400000AAEAAAAA")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2_1") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance LED_TXRX1_TX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance GPIF_D_30_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_25_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_11__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<11>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_9__INV_0 "f0/Msub_dont_write_past_me_lut<9>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_9__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[9].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance XST_GND (viewref netlist (cellref GND (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_dont_write_past_me_11__FRB "f0/dont_write_past_me<11>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_state_FSM_FFd1_In2 "slave_fifo32/state_FSM_FFd1-In2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h2700050022000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_state_FSM_FFd1_In3 "slave_fifo32/state_FSM_FFd1-In3") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_state_FSM_FFd1_In4 "slave_fifo32/state_FSM_FFd1-In4") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___176___slave_fifo32/state_FSM_FFd1-In4")) + (property INIT (string "4'hE")) + ) + (instance cat_miso_IBUF (viewref netlist (cellref IBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + (property IBUF_DELAY_VALUE (string "0")) + (property IFD_DELAY_VALUE (string "AUTO")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_full_reg_glue_set "f0/full_reg_glue_set") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___122___f0/write11")) + (property INIT (string "32'hF0FF4044")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_10__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<10>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_wr_one_rstpot "slave_fifo32/wr_one_rstpot") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___48___slave_fifo32/_n0230_inv1")) + (property INIT (string "32'hEEAAA2AA")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Result_0_2_FRB "f0/Result<0>2_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_12__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<12>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0__n0161_inv1_cy "f0/_n0161_inv1_cy") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename gpif_sync_reset_out "gpif_sync/reset_out") (viewref netlist (cellref FDP (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata33 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata33") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___150___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata33")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_9_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid31 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tvalid31") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tvalid11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___125___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tvalid11")) + (property INIT (string "8'hE0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_11__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[11].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata41 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata41") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___150___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata33")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/full_glue_set") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hA8A8FDA8A8A8A8A8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata51 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata51") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___149___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata51")) + (property INIT (string "8'hE4")) + ) + (instance GPIF_D_7_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata61 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata61") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___149___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata51")) + (property INIT (string "8'hE4")) + ) + (instance (rename f0_dont_write_past_me_12__FRB "f0/dont_write_past_me<12>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tvalid61") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFF0001FFFE0000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata71 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata71") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___148___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata71")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata81 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata81") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___148___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata71")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_rd_one_BRB0 "slave_fifo32/rd_one_BRB0") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_rd_one_BRB1 "slave_fifo32/rd_one_BRB1") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata91 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata91") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___147___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata91")) + (property INIT (string "8'hE4")) + ) + (instance SFDX2_RX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename gen_clks_clkout2_buf "gen_clks/clkout2_buf") (viewref netlist (cellref BUFG (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_14__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[14].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_4__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<4>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename f0_Result_11_1_FRB "f0/Result<11>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance codec_enable_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f0_Mcount_rd_addr_cy_2__rt "f0/Mcount_rd_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f0_Result_3_1_FRB "f0/Result<3>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB0") (viewref netlist (cellref FDS (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo__n0146_inv1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/_n0146_inv1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___13___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/_n0146_inv1")) + (property INIT (string "16'h2E22")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr12_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr12_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB2") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB3") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB4") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB5") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_ctrl_tx_tvalid1 "slave_fifo32/ctrl_tx_tvalid1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h01000000")) + ) + (instance (rename f1_Result_0_2_FRB "f1/Result<0>2_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_rstpot") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFF0FFFFFF80FF80")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In12_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2-In12_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___46___slave_fifo32/fifo64_to_gpmc32_tx/checker/_n0131_inv1")) + (property INIT (string "4'hD")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_0") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_rd_addr_cy_3__rt "f1/Mcount_rd_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1__n0161_inv1_cy "f1/_n0161_inv1_cy") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Msub_dont_write_past_me_xor<8>1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hA8A8A8A8A8A8B9A8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_22__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[22].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_17__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[17].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr11_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr11_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h55555504FFFFFF5D")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1 "slave_fifo32/fifo64_to_gpmc32_tx/GND_49_o_space[15]_LessThan_2_o1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFF55555554")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_rd_addr_cy_7__rt "f0/Mcount_rd_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<0>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<1>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o9_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h8421000000000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<13>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<2>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<14>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<3>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename f1_Mcount_rd_addr_cy_8__rt "f1/Mcount_rd_addr_cy<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tready1_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h80000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<15>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<4>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tready1_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h80000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_lut") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000FAFB00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_30__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[30].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_25__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[25].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<5>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr4_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<6>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename f1_Result_3_1_FRB "f1/Result<3>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<7>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<8>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr5_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<9>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename f0_Mcount_rd_addr_cy_11__rt "f0/Mcount_rd_addr_cy<11>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename catgen_gen_pins_8__oddr2 "catgen/gen_pins[8].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror1_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance fx3_ce_IBUF (viewref netlist (cellref IBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + (property IBUF_DELAY_VALUE (string "0")) + (property IFD_DELAY_VALUE (string "AUTO")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror1_SW1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___118___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In11")) + (property INIT (string "8'h04")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW1_F") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFAAAAFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_G "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW1_G") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hFB")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_33__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[33].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_28__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[28].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_9_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg_glue_set") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___120___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg_glue_set")) + (property INIT (string "16'hFFA2")) + ) + (instance (rename f0_Mcount_rd_addr_xor_10_ "f0/Mcount_rd_addr_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr9_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr9_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_rd_addr_xor_11_ "f0/Mcount_rd_addr_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_31_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_26_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_rd_addr_xor_12_ "f0/Mcount_rd_addr_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_idle_cycles_0 "slave_fifo32/idle_cycles_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_idle_cycles_1 "slave_fifo32/idle_cycles_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tvalid11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___171___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tvalid11")) + (property INIT (string "8'hC8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename catgen_gen_pins_0__oddr2 "catgen/gen_pins[0].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_o_tready_int11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h3333333333323333")) + ) + (instance (rename slave_fifo32_idle_cycles_2 "slave_fifo32/idle_cycles_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_9__INV_0 "f1/Msub_dont_write_past_me_lut<9>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_i_tvalid_int1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h1555555555555555")) + ) + (instance gps_ref_enable_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_36__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[36].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_41__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[41].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata65 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata65") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___107___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata65")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full621_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata71 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata71") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___106___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata71")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_write1 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___179___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/write1")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata81 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata81") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___105___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata81")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_0_rstpot") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h6AAA595566AA5555")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata91 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata91") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___104___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata91")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr3_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Result_1_2_FRB "f0/Result<1>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01218_SW0_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/read") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0111111111111111")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr4_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr6_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<12>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/empty_glue_rst") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFC55FC54FF55FF55")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_44__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[44].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_39__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[39].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<13>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_9__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<9>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<14>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance tx_codec_d_0_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance GPIF_D_8_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr7_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT101 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT101") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_0__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<0>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT110 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT110") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT111 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT111") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0146_inv1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___0___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg_rstpot")) + (property INIT (string "32'hFFFF8D88")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full621_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_rd_addr_xor_0_ "f0/Mcount_rd_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT121 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT121") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<0>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr8_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_rd_addr_xor_1_ "f0/Mcount_rd_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT131 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT131") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<1>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f0_Mcount_rd_addr_xor_2_ "f0/Mcount_rd_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifoadr_0_1 "slave_fifo32/fifoadr_0_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT141 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT141") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0121111 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0121111") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___174___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0121111")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<2>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f0_Mcount_rd_addr_xor_3_ "f0/Mcount_rd_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT201 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT201") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT151 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT151") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_47__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[47].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_52__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[52].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<3>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_rd_addr_xor_4_ "f0/Mcount_rd_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT210 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT210") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_0 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_tlast1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0C0C0C0C0C0C0D0C")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT161 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT161") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT211 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT211") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_1 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_2 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Result_12_1_FRB "f0/Result<12>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<4>") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_3 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_rd_addr_xor_5_ "f0/Mcount_rd_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_4 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT171 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT171") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename f0_Result_4_1_FRB "f0/Result<4>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT221 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT221") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB0") (viewref netlist (cellref FDS (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_rd_addr_xor_6_ "f0/Mcount_rd_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB2") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_10 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB3") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT231 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT231") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance XST_VCC (viewref netlist (cellref VCC (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT181 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT181") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB4") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB5") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_wr_addr_10 "f0/wr_addr_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifoadr_1_1 "slave_fifo32/fifoadr_1_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance tx_codec_d_1_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_rd_addr_xor_7_ "f0/Mcount_rd_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_wr_addr_11 "f0/wr_addr_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_wr_addr_12 "f0/wr_addr_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT241 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT241") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT191 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT191") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h1")) + ) + (instance (rename f1_Result_1_2_FRB "f1/Result<1>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_11__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<11>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_1__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<1>_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_read_state_FSM_FFd1_In111 "f0/read_state_FSM_FFd1-In111") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___30___f0/GND_14_o_read_OR_37_o1")) + (property INIT (string "16'hFDA8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_rd_addr_xor_8_ "f0/Mcount_rd_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT251 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT251") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT301 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT301") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance cat_ce_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_rd_addr_xor_9_ "f0/Mcount_rd_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT261 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT261") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT311 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT311") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename f0_Mcount_wr_addr_cy_5__rt "f0/Mcount_wr_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo_rst_gpif_rst_OR_155_o1 "slave_fifo32/fifo64_to_gpmc32_resp/fifo_rst_gpif_rst_OR_155_o1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___175___slave_fifo32/fifo64_to_gpmc32_resp/fifo_rst_gpif_rst_OR_155_o1")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<0>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT271 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT271") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32__n0258_inv_SW0 "slave_fifo32/_n0258_inv_SW0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___121___slave_fifo32/_n0258_inv_SW0")) + (property INIT (string "8'hBF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_1_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<1>11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___115___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<1>11")) + (property INIT (string "8'h69")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT321 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT321") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_i_tvalid_int1_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'h8000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tready_int1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_o_tready_int1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hC000000080000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<1>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_60__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[60].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT281 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT281") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_55__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[55].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_8_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<2>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<10>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename f1_Mcount_wr_addr_cy_5__rt "f1/Mcount_wr_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT291 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT291") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___12___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv31")) + (property INIT (string "32'hFFFF4B44")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_9_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<3>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_space_xor<3>111") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hEFEFEFEEEEEEEEEE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<11>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename f0_Mcompar_becoming_full_cy_0_ "f0/Mcompar_becoming_full_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<4>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_space_xor<3>111") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hEFEFEFEEEEEEEEEE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<12>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename f0_Mcompar_becoming_full_cy_1_ "f0/Mcompar_becoming_full_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<5>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename f0_Mcompar_becoming_full_cy_2_ "f0/Mcompar_becoming_full_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr6_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<6>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance tx_codec_d_2_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f0_Mcompar_becoming_full_cy_3_ "f0/Mcompar_becoming_full_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_2__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<2>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_10__INV_0 "f1/Msub_dont_write_past_me_lut<10>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<7>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename f0_Mcompar_becoming_full_cy_4_ "f0/Mcompar_becoming_full_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<8>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr6_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o41") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_58__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[58].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_data_tx_tvalid1 "slave_fifo32/data_tx_tvalid1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h00010000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[63].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<9>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In12") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFAAB9")) + ) + (instance (rename slave_fifo32__n0290_inv1 "slave_fifo32/_n0290_inv1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___21___slave_fifo32/_n0223_inv1")) + (property INIT (string "32'h20002222")) + ) + (instance (rename f1_Result_4_1_FRB "f1/Result<4>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o61") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___174___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0121111")) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In14") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_4__INV_0 "f0/Msub_dont_write_past_me_lut<4>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o71") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In31") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/GND_49_o_space[15]_LessThan_2_o1_SW1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0102_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___115___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<1>11")) + (property INIT (string "16'hFF57")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In32") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0102_SW1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___26___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv_SW0")) + (property INIT (string "8'h80")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In33 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In33") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'hFDFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT71_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000000000000001")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In34") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFB")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full611 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full611") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000000100010001")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT21") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAAAAAAA9AAAAAA")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_10 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_10") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h04040000FF04FF00")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_11") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_12 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_12") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT31") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hE1E1E1E10FF0F00F")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full621 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full621") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFEFEFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_13 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_13") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance tx_codec_d_3_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_14 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_14") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_1__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[1].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_15 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_15") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_20 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_20") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_16 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_16") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_21 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_21") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_17 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_17") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_3__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<3>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_22 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_22") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_18 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_18") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_23 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_23") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_19 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_19") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_24 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_24") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_25 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_25") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_30 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_30") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_26 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_26") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0154_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0154_inv1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___37___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0154_inv1")) + (property INIT (string "8'hDC")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_31 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_31") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_27 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_27") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_28 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_28") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT52") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hA9A9A9A9AA5555AA")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_29 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_29") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o10") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h8000000000000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0076_inv_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___39___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01213_SW0") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT71") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h54A855AA55AA55AA")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2-In11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFF9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT73") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFF00FFE8FF17FFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In13 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2-In13") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAA3B8819AA2A8808")) + ) + (instance GPIF_D_27_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hCCCCCCCCF50A05FA")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0404040404040504")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o41 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o41") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8211") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFF7FFFFFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror21") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_10_ "f0/Msub_dont_write_past_me_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_7__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<7>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_11_ "f0/Msub_dont_write_past_me_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o61 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o61") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_4__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[4].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o71 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o71") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_10_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_10_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0_lut") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h1111111011111111")) + ) + (instance tx_codec_d_4_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o81 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o81") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01212") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0010001000000010")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01213") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9090900000900000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_2_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<2>11") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___9___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<3>11")) + (property INIT (string "16'h6AA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_4__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<4>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01214") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h99900000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01215") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0220000000000220")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01216 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01216") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01217") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0080000000000080")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01218 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01218") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___114___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full921")) + (property INIT (string "16'h0440")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01219") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFAF8AA0000000000")) + ) + (instance SFDX1_RX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f0_Result_10_2_FRB "f0/Result<10>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Result_2_2_FRB "f0/Result<2>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0076_inv") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h00000001FFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_12__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[12].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f0_Mcompar_becoming_full_lut_0_ "f0/Mcompar_becoming_full_lut<0>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_0__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[0].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f0_Mcompar_becoming_full_lut_1_ "f0/Mcompar_becoming_full_lut<1>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_7__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[7].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set_SW1 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/full_glue_set_SW1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___7___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv_SW0")) + (property INIT (string "32'hFFFF7FFF")) + ) + (instance debug_0_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance codec_fb_clk_p_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f0_Mcompar_becoming_full_lut_2_ "f0/Mcompar_becoming_full_lut<2>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f0_Mcompar_becoming_full_lut_3_ "f0/Mcompar_becoming_full_lut<3>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_11_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_11_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcompar_becoming_full_lut_4_ "f0/Mcompar_becoming_full_lut<4>") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance GPIF_D_9_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance tx_codec_d_5_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_i_tvalid_o_tready_AND_73_o1 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/i_tvalid_o_tready_AND_73_o1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___127___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tvalid11")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_5__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<5>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_write1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/write1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000000100000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hCCCCCCCCF05A0F5A")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_15__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[15].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_20__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[20].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_state_FSM_FFd1_In3_F "slave_fifo32/state_FSM_FFd1-In3_F") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h80808000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_state_FSM_FFd1_In3_G "slave_fifo32/state_FSM_FFd1-In3_G") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h04155555FFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hCCCCCCCC0F5AF05A")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance SFDX2_TX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_3__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[3].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o9_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h8421000000000000")) + ) + (instance (rename slave_fifo32_gpif_data_in_10 "slave_fifo32/gpif_data_in_10") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_11 "slave_fifo32/gpif_data_in_11") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_gpif_data_in_12 "slave_fifo32/gpif_data_in_12") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_13 "slave_fifo32/gpif_data_in_13") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_14 "slave_fifo32/gpif_data_in_14") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_15 "slave_fifo32/gpif_data_in_15") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_20 "slave_fifo32/gpif_data_in_20") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_16 "slave_fifo32/gpif_data_in_16") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror21_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'h0001")) + ) + (instance (rename slave_fifo32_gpif_data_in_21 "slave_fifo32/gpif_data_in_21") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror21_SW1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h01")) + ) + (instance (rename slave_fifo32_gpif_data_in_17 "slave_fifo32/gpif_data_in_17") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_22 "slave_fifo32/gpif_data_in_22") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_18 "slave_fifo32/gpif_data_in_18") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_23 "slave_fifo32/gpif_data_in_23") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_19 "slave_fifo32/gpif_data_in_19") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_24 "slave_fifo32/gpif_data_in_24") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_25 "slave_fifo32/gpif_data_in_25") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_30 "slave_fifo32/gpif_data_in_30") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_26 "slave_fifo32/gpif_data_in_26") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_31 "slave_fifo32/gpif_data_in_31") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance debug_1_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_gpif_data_in_27 "slave_fifo32/gpif_data_in_27") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_28 "slave_fifo32/gpif_data_in_28") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_29 "slave_fifo32/gpif_data_in_29") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename f0_Result_5_1_FRB "f0/Result<5>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/full_glue_set") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAA8AAA8AFFCFAA8A")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_12_BRB0") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_12_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance tx_codec_d_6_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f1_Result_2_2_FRB "f1/Result<2>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212_SW1_SW0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___168___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1021")) + (property INIT (string "8'hEA")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_6__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<6>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename catgen_gen_pins_11__oddr2 "catgen/gen_pins[11].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_12__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<12>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_23__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[23].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_18__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[18].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f0_i_tready1_INV_0 "f0/i_tready1_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_6__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[6].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_wr_addr_0 "f1/wr_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_wr_addr_1 "f1/wr_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_wr_addr_2 "f1/wr_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_wr_addr_3 "f1/wr_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_wr_addr_4 "f1/wr_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance GPIF_CTL4_IBUF (viewref netlist (cellref IBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + (property IBUF_DELAY_VALUE (string "0")) + (property IFD_DELAY_VALUE (string "AUTO")) + ) + (instance (rename f1_wr_addr_5 "f1/wr_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_wr_addr_6 "f1/wr_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_wr_addr_7 "f1/wr_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_wr_addr_8 "f1/wr_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0144_inv1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___6___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1-In11")) + (property INIT (string "32'h00440F44")) + ) + (instance (rename f1_wr_addr_9 "f1/wr_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance debug_clk_0_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance debug_2_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename catgen_gen_pins_3__oddr2 "catgen/gen_pins[3].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o41") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<3>11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___9___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<3>11")) + (property INIT (string "32'h6AAAAAA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_o_tvalid11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h5555555555545555")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_F "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01213_SW0_F") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h00FBFB0005FBFB05")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_13_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_13_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_G "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01213_SW0_G") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFF5455FFFF5657")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_31__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[31].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_26__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[26].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o61") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___173___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0121111")) + (property INIT (string "4'h9")) + ) + (instance tx_codec_d_7_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_7__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<7>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_9__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[9].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o71") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_10__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[10].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f1_Result_5_1_FRB "f1/Result<5>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance GPIF_CTL5_IBUF (viewref netlist (cellref IBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + (property IBUF_DELAY_VALUE (string "0")) + (property IFD_DELAY_VALUE (string "AUTO")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_4__INV_0 "f1/Msub_dont_write_past_me_lut<4>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance debug_clk_1_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_state_FSM_FFd2_In1 "slave_fifo32/state_FSM_FFd2-In1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___177___slave_fifo32/Mcount_idle_cycles_xor<0>11")) + (property INIT (string "16'h8000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/dump") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_11__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[11].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance debug_3_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_state_FSM_FFd2_In2 "slave_fifo32/state_FSM_FFd2-In2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h1054101010101010")) + ) + (instance (rename slave_fifo32_state_FSM_FFd2_In3 "slave_fifo32/state_FSM_FFd2-In3") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___176___slave_fifo32/state_FSM_FFd1-In4")) + (property INIT (string "16'hFFF4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/fifo_4k_2clk") (viewref view_1 (cellref fifo_4k_2clk (libraryref b200_lib))) + (property BUS_INFO (string "10:OUTPUT:wr_data_count<9:0>")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_34__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[34].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_29__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[29].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/empty_glue_rst_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<0>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA6AAA6A6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_14_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_14_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance tx_codec_d_8_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/empty_glue_rst_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h1111000111111111")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<1>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_8__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<8>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAAAAAAAAAAAAA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<2>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance tx_bandsel_a_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_13__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[13].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance reset_global_locked_OR_1_o1 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___179___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/write1")) + (property INIT (string "4'hD")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<3>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<4>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<5>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance GPIF_D_28_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram10") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + 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INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt__n0074_inv1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/_n0074_inv1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hC60ACC000A0A0000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_37__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[37].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram15") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string 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(property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string 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(property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string 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(property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram16") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_space_xor_3_111 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_space_xor<3>111") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___28___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_space_xor<3>111")) + (property INIT (string "32'hFFAEFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram17") (viewref netlist (cellref RAMB8BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "16:OUTPUT:DOBDO<15:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 1)) + (property DATA_WIDTH_B (integer 1)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "18'h00000")) + (property INIT_B (string "18'h00000")) + (property RAM_MODE (string "TDP")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "18'h00000")) + (property SRVAL_B (string "18'h00000")) + (property INIT_FILE (string "NONE")) + (property SIM_COLLISION_CHECK (string "ALL")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<7>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_write_AND_42_o_inv2 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_write_AND_42_o_inv2") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'hDFCF")) + ) + (instance debug_4_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT4_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___35___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511_SW0")) + (property INIT (string "16'hCCC9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_4__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<4>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<8>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv6_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFBF8FFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<9>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv6_SW1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hAABAAAAA")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv6_SW2") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_15_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance tx_codec_d_9_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___119___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg_glue_set")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_16__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[16].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_21__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[21].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_9__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<9>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance tx_bandsel_b_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename gen_clks_clkout3_buf "gen_clks/clkout3_buf") (viewref netlist (cellref BUFG (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename f0_Result_11_2_FRB "f0/Result<11>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB3") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB4") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_rd_addr_cy_3__rt "f0/Mcount_rd_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_17__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[17].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f0_Result_3_2_FRB "f0/Result<3>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_22__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[22].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_50__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[50].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_45__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[45].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_4_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<4>11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h6AAAAAAAAAAAAAA9")) + ) + (instance (rename f1_ram_Mram_ram1 "f1/ram/Mram_ram1") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW0_F") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFEFFFFFFFFFFF")) + ) + (instance (rename f1_ram_Mram_ram2 "f1/ram/Mram_ram2") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_ram_Mram_ram3 "f1/ram/Mram_ram3") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/GND_50_o_read_OR_57_o1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'h2272")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW0_G") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hEEFFFEFFFFFFFFFF")) + ) + (instance (rename f1_ram_Mram_ram4 "f1/ram/Mram_ram4") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string 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(property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property 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(property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string 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(property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string 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(property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string 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(property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string 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(property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string 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(property INIT (string "2'h2")) + ) + (instance (rename f1_ram_Mram_ram7 "f1/ram/Mram_ram7") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string 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(property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string 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(property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string 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(property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string 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(property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string 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(property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string 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(true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string 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(property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_19__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[19].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_24__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[24].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr12_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr12_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW1_F") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hEEFFEFFFFFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW1_G") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFEFFFFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_25__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[25].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_30__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[30].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_48__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[48].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_53__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[53].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_rd_addr_cy_8__rt "f0/Mcount_rd_addr_cy<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance GPIF_D_10_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_7__INV_0 "f0/Msub_dont_write_past_me_lut<7>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Mcount_wr_addr_xor_0_ "f1/Mcount_wr_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_27__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[27].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_32__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[32].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_0 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_0") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__inv_INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>_inv_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_1 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_rd_addr_cy_9__rt "f1/Mcount_rd_addr_cy<9>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance debug_6_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f1_Mcount_wr_addr_xor_1_ "f1/Mcount_wr_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_2 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_2") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_3 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_3") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_4 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_4") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Result_6_1_FRB "f0/Result<6>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_5 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_5") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_6 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_6") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_wr_addr_xor_2_ "f1/Mcount_wr_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_7 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_7") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_dont_write_past_me_0__FRB "f0/dont_write_past_me<0>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_8 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_8") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance pll_mosi_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_9 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_9") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv4") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___33___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_o_tready_int11")) + (property INIT (string "8'hA8")) + ) + (instance fx3_mosi_IBUF (viewref netlist (cellref IBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + (property IBUF_DELAY_VALUE (string "0")) + (property IFD_DELAY_VALUE (string "AUTO")) + ) + (instance (rename f1_Mcount_wr_addr_xor_3_ "f1/Mcount_wr_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h4000FBFF4400FFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr5_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_28__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[28].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Result_3_2_FRB "f1/Result<3>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_33__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[33].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Mcount_wr_addr_xor_4_ "f1/Mcount_wr_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_61__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[61].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_56__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[56].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Mcount_wr_addr_xor_5_ "f1/Mcount_wr_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<9>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Mcount_wr_addr_xor_6_ "f1/Mcount_wr_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr6_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_wr_addr_xor_7_ "f1/Mcount_wr_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___27___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv_SW0")) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/read_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h80000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_35__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[35].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_40__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[40].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Mcount_wr_addr_xor_8_ "f1/Mcount_wr_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_CTL9_IBUF (viewref netlist (cellref IBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + (property IBUF_DELAY_VALUE (string "0")) + (property IFD_DELAY_VALUE (string "AUTO")) + ) + (instance (rename f1_Mcount_wr_addr_xor_9_ "f1/Mcount_wr_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_0__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[0].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance debug_7_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT73_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h5599665556955695")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_0") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_0__inv1_INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state<0>_inv1_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_2") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_3") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_0") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_4") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_dont_write_past_me_1__FRB "f0/dont_write_past_me<1>_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_41__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[41].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_36__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[36].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_5") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_2 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_2") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_6") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_64__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[64].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_59__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[59].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_3 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_3") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_7") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_4 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_4") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_8") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_0_11_INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<0>11_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_5 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_5") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_9 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_9") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_6 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_6") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_7 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_7") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_8 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_8") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_rd_addr_10 "f0/rd_addr_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int14_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFF55FF01FF55FF55")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_rd_addr_11 "f0/rd_addr_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int14_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFF55FF00FF55FF54")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_rd_addr_12 "f0/rd_addr_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_43__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[43].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_38__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[38].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance codec_en_agc_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h5140514055555140")) + ) + (instance tx_codec_d_10_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_3__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[3].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Result_6_1_FRB "f1/Result<6>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Result_10_1_FRB "f1/Result<10>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW2") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW3") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr3_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h04040000FF04FF00")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_2__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<2>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o10_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_39__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[39].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_44__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[44].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance debug_8_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f0_dont_write_past_me_2__FRB "f0/dont_write_past_me<2>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_slwr_1 "slave_fifo32/slwr_1") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Msub_dont_write_past_me_xor<8>1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hA8A8A8A8A8A8B9A8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr4_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___39___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11")) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/ram/Mram_ram1") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 18)) + (property DATA_WIDTH_B (integer 18)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/ram/Mram_ram2") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 18)) + (property DATA_WIDTH_B (integer 18)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_46__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[46].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_51__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[51].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hF2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/full") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int12") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000000000010005")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT411") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr5_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int14 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int14") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'h010F")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int15") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h7FFFFFFFFFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr7_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_6__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[6].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int16") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h00F7000000F7F7F7")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_10 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_13 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_13") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_14 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_14") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance tx_codec_d_11_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_15 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_15") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance GPIF_D_29_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_47__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[47].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_52__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[52].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_11_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance cat_mosi1 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___178___cat_mosi1")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tready1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0111111111111111")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr8_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance debug_9_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFF0D2F087F")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_1__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[1].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_write1 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/write1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___15___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/write1")) + (property INIT (string "16'h5400")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_wr_addr_cy_1__rt "f0/Mcount_wr_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f0_dont_write_past_me_3__FRB "f0/dont_write_past_me<3>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_49__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[49].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_54__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[54].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___38___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>1")) + (property INIT (string "16'hA8EA")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_i_tvalid_int1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h1555555555555555")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___41___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11")) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_9__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[9].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Mcount_wr_addr_cy_1__rt "f1/Mcount_wr_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_gpif_data_out_10 "slave_fifo32/gpif_data_out_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_11 "slave_fifo32/gpif_data_out_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_12 "slave_fifo32/gpif_data_out_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_13 "slave_fifo32/gpif_data_out_13") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_14 "slave_fifo32/gpif_data_out_14") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_gpif_data_out_15 "slave_fifo32/gpif_data_out_15") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_20 "slave_fifo32/gpif_data_out_20") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance SFDX1_TX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance GPIF_CTL11_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_gpif_data_out_21 "slave_fifo32/gpif_data_out_21") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_16 "slave_fifo32/gpif_data_out_16") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename f0_Result_12_2_FRB "f0/Result<12>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_gpif_data_out_17 "slave_fifo32/gpif_data_out_17") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_22 "slave_fifo32/gpif_data_out_22") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_55__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[55].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_gpif_data_out_18 "slave_fifo32/gpif_data_out_18") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_23 "slave_fifo32/gpif_data_out_23") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_60__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[60].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_gpif_data_out_24 "slave_fifo32/gpif_data_out_24") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_19 "slave_fifo32/gpif_data_out_19") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_gpif_data_out_25 "slave_fifo32/gpif_data_out_25") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_30 "slave_fifo32/gpif_data_out_30") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename f0_Result_4_2_FRB "f0/Result<4>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_gpif_data_out_31 "slave_fifo32/gpif_data_out_31") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_26 "slave_fifo32/gpif_data_out_26") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_27 "slave_fifo32/gpif_data_out_27") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_28 "slave_fifo32/gpif_data_out_28") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_29 "slave_fifo32/gpif_data_out_29") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename catgen_oddr2_clk "catgen/oddr2_clk") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_9__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<9>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_4__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[4].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n012110_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n012110_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h00008400")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_57__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[57].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/GND_66_o_read_OR_144_o1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___44___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_62__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[62].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename catgen_gen_pins_6__oddr2 "catgen/gen_pins[6].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_wr_addr_cy_6__rt "f0/Mcount_wr_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f0_dont_write_past_me_4__FRB "f0/dont_write_past_me<4>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_11__INV_0 "f0/Msub_dont_write_past_me_lut<11>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Mcount_wr_addr_cy_6__rt "f1/Mcount_wr_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_58__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[58].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_63__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[63].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance GPIF_CTL12_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance GPIF_D_11_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_7__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[7].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full411") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___17___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421")) + (property INIT (string "16'hFEEE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr7_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___17___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421")) + (property INIT (string "16'h0111")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_7__INV_0 "f1/Msub_dont_write_past_me_lut<7>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_11_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/GND_63_o_space[15]_LessThan_2_o1_SW1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr7_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/_n0146_inv1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hFFB8FF88")) + ) + (instance (rename f0_Result_7_1_FRB "f0/Result<7>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_dont_write_past_me_5__FRB "f0/dont_write_past_me<5>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_gpif_data_out_31_rstpot "slave_fifo32/gpif_data_out_31_rstpot") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename f1_Result_4_2_FRB "f1/Result<4>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW0") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW1") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance pps_fpga_out_enable_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/full_glue_set") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hA8A8FDA8A8A8A8A8")) + ) + (instance (rename f1_Mcompar_becoming_full_lut_0_ "f1/Mcompar_becoming_full_lut<0>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full621") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFEFEFE")) + ) + (instance (rename f1_Mcompar_becoming_full_lut_1_ "f1/Mcompar_becoming_full_lut<1>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/clear_dump_OR_131_o") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000000000000001")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_7__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<7>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state_glue_set "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/state_glue_set") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___29___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_space_xor<3>111")) + (property INIT (string "8'hA9")) + ) + (instance (rename f1_Mcompar_becoming_full_lut_2_ "f1/Mcompar_becoming_full_lut<2>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f0_dont_write_past_me_6__FRB "f0/dont_write_past_me<6>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/state") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcompar_becoming_full_lut_3_ "f1/Mcompar_becoming_full_lut<3>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f0_full_reg "f0/full_reg") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcompar_becoming_full_lut_4_ "f1/Mcompar_becoming_full_lut<4>") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg_rstpot") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___0___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg_rstpot")) + (property INIT (string "32'hFFFF7222")) + ) + (instance fx3_miso_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int16_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hEEEEFEEE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_11_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_12_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_12__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[12].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Result_7_1_FRB "f1/Result<7>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Result_11_1_FRB "f1/Result<11>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/full") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance tx_frame_p_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata101 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata101") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___162___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata101")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<0>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata110 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata110") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___167___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata110")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata111 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata111") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___162___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata101")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<1>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full611") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000000100010001")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata121 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata121") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___161___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata121")) + (property INIT (string "8'hE4")) + ) + (instance (rename f0_dont_write_past_me_7__FRB "f0/dont_write_past_me<7>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<2>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full621 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full621") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFEFEFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata131 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata131") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___161___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata121")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<3>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_F "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13_SW1_F") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFF5554")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0146_inv1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n0146_inv1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___10___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n0146_inv1")) + (property INIT (string "16'h2E22")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata141 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata141") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___160___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata141")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_G "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13_SW1_G") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<4>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata201 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata201") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___157___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata201")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata151 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata151") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___160___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata141")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<5>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_20__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[20].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_15__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[15].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata210 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata210") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___167___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata110")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata161 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata161") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___159___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata161")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata211 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata211") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___157___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata201")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<6>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full921 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full921") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___114___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full921")) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata171 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata171") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___159___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata161")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata221 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata221") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___156___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata221")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<7>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata231 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata231") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___156___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata221")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata181 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata181") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___158___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata181")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifoadr_0 "slave_fifo32/fifoadr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<8>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___40___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/write1")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifoadr_1 "slave_fifo32/fifoadr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata241 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata241") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___155___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata241")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata191 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata191") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___158___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata181")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_12__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<12>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<9>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/full_reg_glue_set") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h4C4CFF4C4C4C4C4C")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT21") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata251 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata251") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___155___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata241")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<9>11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAAAAB9AAAAAAA8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT17 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT17") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___175___slave_fifo32/fifo64_to_gpmc32_resp/fifo_rst_gpif_rst_OR_155_o1")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata301 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata301") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___163___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata91")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0154_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/_n0154_inv1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hDC")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT31") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance GPIF_CTL0_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata261 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata261") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___154___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata261")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata311 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata311") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___152___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata311")) + (property INIT (string "8'hE4")) + ) + (instance (rename f0_dont_write_past_me_8__FRB "f0/dont_write_past_me<8>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_13_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<13>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_2 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT41") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_3 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata321 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata321") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___152___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata311")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata271 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata271") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___154___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata261")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_4 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_5 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_6 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_14_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<14>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT51") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata281 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata281") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___153___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata281")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_23__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[23].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_18__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[18].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_15_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<15>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT61") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata291 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata291") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___153___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata281")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_8 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_11__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<11>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___131___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Result_5_2_FRB "f0/Result<5>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_2__INV_0 "f0/Msub_dont_write_past_me_lut<2>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT91") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___131___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_EP_WMARK1 "slave_fifo32/EP_WMARK1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h00000000DD09C000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance GPIF_CTL1_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_9 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01215") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0020000002200200")) + ) + (instance (rename f0_dont_write_past_me_9__FRB "f0/dont_write_past_me<9>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance codec_sync_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/clear_dump_OR_131_o_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___126___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/clear_dump_OR_131_o_SW0")) + (property INIT (string "4'hD")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_31__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[31].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_26__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[26].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/full_reg") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance GPIF_D_12_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance cat_mosi_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_5__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<5>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_34__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[34].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_29__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[29].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Result_8_1_FRB "f0/Result<8>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance GPIF_CTL2_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0303CFCF0203DFCF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk "slave_fifo32/fifo64_to_gpmc32_tx/cross_clock_fifo/fifo_4k_2clk") (viewref view_1 (cellref fifo_4k_2clk (libraryref b200_lib))) + (property BUS_INFO (string "10:OUTPUT:wr_data_count<9:0>")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty_glue_rst") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFBFBFBFFFB00FB00")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Result_5_2_FRB "f1/Result<5>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_read_state_FSM_FFd1_In111 "f1/read_state_FSM_FFd1-In111") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___31___f1/GND_14_o_read_OR_37_o1")) + (property INIT (string "16'hFDA8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_debug1_10 "slave_fifo32/debug1_10") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_debug1_11 "slave_fifo32/debug1_11") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_12 "slave_fifo32/debug1_12") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_13 "slave_fifo32/debug1_13") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_14 "slave_fifo32/debug1_14") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_15 "slave_fifo32/debug1_15") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_debug1_21 "slave_fifo32/debug1_21") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_22 "slave_fifo32/debug1_22") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_o_tvalid1_INV_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/o_tvalid1_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_1_11 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<1>11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h69")) + ) + (instance (rename slave_fifo32_debug1_18 "slave_fifo32/debug1_18") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_23 "slave_fifo32/debug1_23") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_19 "slave_fifo32/debug1_19") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_debug1_26 "slave_fifo32/debug1_26") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_31 "slave_fifo32/debug1_31") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_27 "slave_fifo32/debug1_27") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_28 "slave_fifo32/debug1_28") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_29 "slave_fifo32/debug1_29") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_0_ "f0/Msub_dont_write_past_me_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_42__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[42].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[37].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_1_ "f0/Msub_dont_write_past_me_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_2_ "f0/Msub_dont_write_past_me_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/full_reg_glue_set") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___45___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/write1")) + (property INIT (string "32'h5540FFC0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_F "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW2_F") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hEFEEEFEEEFEEFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW2_G") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h54555454FCFFFCFC")) + ) + (instance GPIF_CTL3_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_3_ "f0/Msub_dont_write_past_me_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/ram/Mram_ram") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 36)) + (property DATA_WIDTH_B (integer 36)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_4_ "f0/Msub_dont_write_past_me_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012111 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012111") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h2002000000002002")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_write1 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___180___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/write1")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012112 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012112") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h8822228C80202084")) + ) + (instance (rename bus_sync_reset_int "bus_sync/reset_int") (viewref netlist (cellref FDP (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012113 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012113") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_5_ "f0/Msub_dont_write_past_me_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012114 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012114") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB33A820A820A820")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_6_ "f0/Msub_dont_write_past_me_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_7_ "f0/Msub_dont_write_past_me_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___36___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111")) + (property INIT (string "4'h7")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_8_ "f0/Msub_dont_write_past_me_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_45__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[45].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_50__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[50].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Result_8_1_FRB "f1/Result<8>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_9_ "f0/Msub_dont_write_past_me_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Result_12_1_FRB "f1/Result<12>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_read1 "slave_fifo32/fifo64_to_gpmc32_tx/cross_clock_fifo/read1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_0_ "f0/Msub_dont_write_past_me_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename catgen_gen_pins_9__oddr2 "catgen/gen_pins[9].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_1_ "f0/Msub_dont_write_past_me_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/ram/Mram_ram") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 36)) + (property DATA_WIDTH_B (integer 36)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f0_Mcount_rd_addr_cy_4__rt "f0/Mcount_rd_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_2_ "f0/Msub_dont_write_past_me_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_10__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<10>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_3_ "f0/Msub_dont_write_past_me_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[53].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_48__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[48].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_4_ "f0/Msub_dont_write_past_me_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance debug_10_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_5_ "f0/Msub_dont_write_past_me_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcount_rd_addr_cy_5__rt "f1/Mcount_rd_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_6_ "f0/Msub_dont_write_past_me_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___26___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv_SW0")) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_7_ "f0/Msub_dont_write_past_me_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_wr_addr_cy_10__rt "f1/Mcount_wr_addr_cy<10>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_8_ "f0/Msub_dont_write_past_me_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename catgen_gen_pins_1__oddr2 "catgen/gen_pins[1].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_9_ "f0/Msub_dont_write_past_me_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_sloe "slave_fifo32/sloe") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_debug2_10 "slave_fifo32/debug2_10") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2-In1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h7FFF7F7F2AFF2A2A")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug2_11 "slave_fifo32/debug2_11") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_12 "slave_fifo32/debug2_12") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename f0_Mcount_rd_addr_cy_9__rt "f0/Mcount_rd_addr_cy<9>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_debug2_13 "slave_fifo32/debug2_13") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_14 "slave_fifo32/debug2_14") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_15 "slave_fifo32/debug2_15") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_61__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[61].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_56__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[56].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_debug2_16 "slave_fifo32/debug2_16") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_21 "slave_fifo32/debug2_21") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_17 "slave_fifo32/debug2_17") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_2_11 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<2>11") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___18___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<2>11")) + (property INIT (string "16'h6AA9")) + ) + (instance (rename slave_fifo32_debug2_22 "slave_fifo32/debug2_22") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_18 "slave_fifo32/debug2_18") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_slrd "slave_fifo32/slrd") (viewref netlist (cellref FDS (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_23 "slave_fifo32/debug2_23") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_19 "slave_fifo32/debug2_19") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_debug2_26 "slave_fifo32/debug2_26") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_31 "slave_fifo32/debug2_31") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_27 "slave_fifo32/debug2_27") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_28 "slave_fifo32/debug2_28") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_29 "slave_fifo32/debug2_29") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance debug_11_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_write_AND_42_o_inv2 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_write_AND_42_o_inv2") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'hDFCF")) + ) + (instance (rename f0_Result_6_2_FRB "f0/Result<6>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full1011 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1011") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___49___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1011")) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT411") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hFE")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_2__INV_0 "f1/Msub_dont_write_past_me_lut<2>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full1021 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1021") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___168___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1021")) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr6_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_10 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_10") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_11 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_11") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_12 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_12") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_13 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_13") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT21") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___25___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511")) + (property INIT (string "32'hBF4040BF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_14 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_14") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_F "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW2_F") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFD")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_20 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_20") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_G "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW2_G") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_15 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_15") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_21 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_21") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0121211 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n0121211") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h8282414141418228")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_16 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_16") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_17 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_17") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd2_BRB0") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_22 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_22") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_18 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_18") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT31") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hE178E1E1E1E1E1E1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd2_BRB1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_23 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_23") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_19 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_19") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_24 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_24") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_25 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_25") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_30 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_30") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_31 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_31") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_26 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_26") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_27 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_27") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_28 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_28") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT41") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___34___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111")) + (property INIT (string "32'h9AAAAAA6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_59__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[59].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[64].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_29 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_29") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr7_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_0_11_INV_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<0>11_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_slwr "slave_fifo32/slwr") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT51") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAA9AAAA6A696A6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___40___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/write1")) + (property INIT (string "16'hEFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT61") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h99AA99A6AAAAAAA6")) + ) + (instance (rename slave_fifo32_sloe_10 "slave_fifo32/sloe_10") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance codec_ctrl_in_0_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA9AAA9A9")) + ) + (instance (rename slave_fifo32_sloe_11 "slave_fifo32/sloe_11") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_sloe_12 "slave_fifo32/sloe_12") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01211_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01211_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFF05FF04FF")) + ) + (instance (rename slave_fifo32_sloe_13 "slave_fifo32/sloe_13") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_14 "slave_fifo32/sloe_14") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_20 "slave_fifo32/sloe_20") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_15 "slave_fifo32/sloe_15") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFB0400FFFA0500")) + ) + (instance (rename slave_fifo32_sloe_16 "slave_fifo32/sloe_16") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_21 "slave_fifo32/sloe_21") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_sloe_17 "slave_fifo32/sloe_17") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_22 "slave_fifo32/sloe_22") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_23 "slave_fifo32/sloe_23") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_18 "slave_fifo32/sloe_18") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance debug_12_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_sloe_19 "slave_fifo32/sloe_19") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_24 "slave_fifo32/sloe_24") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFF0040BFBF4000FF")) + ) + (instance (rename slave_fifo32_sloe_25 "slave_fifo32/sloe_25") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_30 "slave_fifo32/sloe_30") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<0>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA6AAA6A6")) + ) + (instance (rename slave_fifo32_sloe_26 "slave_fifo32/sloe_26") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_31 "slave_fifo32/sloe_31") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_sloe_27 "slave_fifo32/sloe_27") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_32 "slave_fifo32/sloe_32") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_33 "slave_fifo32/sloe_33") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_28 "slave_fifo32/sloe_28") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_34 "slave_fifo32/sloe_34") (viewref netlist (cellref FDS (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_sloe_29 "slave_fifo32/sloe_29") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_13_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<1>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_read_state_FSM_FFd1 "f1/read_state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/full") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_read_state_FSM_FFd2 "f1/read_state_FSM_FFd2") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<2>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_2__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[2].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_10_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_10_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<12>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<3>1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA9AAA9A9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<3>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/state_glue_set") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___15___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/write1")) + (property INIT (string "16'hA2A6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_2__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<2>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata33 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata33") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___166___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata33")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<10>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<13>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<4>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata41 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata41") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___166___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata33")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Result_9_1_FRB "f0/Result<9>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance GPIF_CTL7_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<11>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<14>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr3_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<5>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata51 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata51") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___165___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata51")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<12>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<6>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata61 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata61") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___165___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata51")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Result_6_2_FRB "f1/Result<6>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<13>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename bus_sync_reset_out "bus_sync/reset_out") (viewref netlist (cellref FDP (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o9") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000000000")) + ) + (instance codec_ctrl_in_1_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<7>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename f1_Result_10_2_FRB "f1/Result<10>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata71 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata71") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___164___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata71")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int11") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'h0307")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int12") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h7FFFFFFFFFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<14>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01216_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFDBFDDBFDFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int13 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int13") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'hF700")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01216_SW1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___43___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full1021")) + (property INIT (string "16'hEFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_4_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<4>1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA9AAA9A9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<8>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr4_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01216_SW2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFCBFFBEFFC7FF7DF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata81 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata81") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___164___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata71")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_10__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[10].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int16") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hF0E4D8CC00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<15>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance debug_13_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance pll_sclk_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<9>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata91 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata91") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___163___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata91")) + (property INIT (string "8'hE4")) + ) + (instance fx3_sclk_IBUF (viewref netlist (cellref IBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + (property IBUF_DELAY_VALUE (string "0")) + (property IFD_DELAY_VALUE (string "AUTO")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_5__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[5].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr5_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram10") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram11") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram12") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string 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"slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram13") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string 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(property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string 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(property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string 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(property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_11_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_11_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram14") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string 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(property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string 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(property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string 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(property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string 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(property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string 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(property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string 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(property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram16") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string 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(property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string 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(property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string 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(property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram17") (viewref netlist (cellref RAMB8BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "16:OUTPUT:DOBDO<15:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string 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(property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 1)) + (property DATA_WIDTH_B (integer 1)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "18'h00000")) + (property INIT_B (string "18'h00000")) + (property RAM_MODE (string "TDP")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "18'h00000")) + (property SRVAL_B (string "18'h00000")) + (property INIT_FILE (string "NONE")) + (property SIM_COLLISION_CHECK (string "ALL")) + ) + (instance (rename f0_Mcount_wr_addr_cy_11_ "f0/Mcount_wr_addr_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<5>1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA9AAA9A9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<3>11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___18___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<2>11")) + (property INIT (string "32'h6AAAAAA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr6_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr8_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance SRX2_RX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance GPIF_D_0_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance codec_txrx_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_13__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[13].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_11__INV_0 "f1/Msub_dont_write_past_me_lut<11>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_EP_WMARK1_1 "slave_fifo32/EP_WMARK1_1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance codec_ctrl_in_2_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_1__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[1].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_8__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[8].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance debug_14_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f0_wr_addr_0 "f0/wr_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_wr_addr_1 "f0/wr_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_wr_addr_2 "f0/wr_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_wr_addr_3 "f0/wr_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/empty") (viewref netlist (cellref FDS (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename f0_wr_addr_4 "f0/wr_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Result_9_1_FRB "f1/Result<9>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_wr_addr_cy_2__rt "f0/Mcount_wr_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f0_wr_addr_5 "f0/wr_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_5__INV_0 "f0/Msub_dont_write_past_me_lut<5>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename f0_wr_addr_6 "f0/wr_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_wr_addr_7 "f0/wr_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_wr_addr_8 "f0/wr_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/_n0074_inv1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hC60ACC000A0A0000")) + ) + (instance (rename f0_wr_addr_9 "f0/wr_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_12_BRB0") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_12_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_wr_addr_cy_2__rt "f1/Mcount_wr_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/empty") (viewref netlist (cellref FDS (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_16__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[16].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_21__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[21].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_4__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[4].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance codec_ctrl_in_3_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f0_ram_Mram_ram1 "f0/ram/Mram_ram1") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f0_ram_Mram_ram2 "f0/ram/Mram_ram2") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string 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(true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string 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(property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f0_ram_Mram_ram9 "f0/ram/Mram_ram9") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance debug_20_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance debug_15_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_inv1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0155115501111111")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT411 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT411") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr3_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_wr_addr_cy_7__rt "f0/Mcount_wr_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename gen_clks_dcm_sp_inst "gen_clks/dcm_sp_inst") (viewref netlist (cellref DCM_SP (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "8:OUTPUT:STATUS<7:0>")) + (property CLKIN_DIVIDE_BY_2 (boolean (false))) + (property CLKOUT_PHASE_SHIFT (string "NONE")) + (property CLK_FEEDBACK (string "1X")) + (property DESKEW_ADJUST (string "SYSTEM_SYNCHRONOUS")) + (property DFS_FREQUENCY_MODE (string "LOW")) + (property DLL_FREQUENCY_MODE (string "LOW")) + (property DSS_MODE (string "NONE")) + (property DUTY_CYCLE_CORRECTION (boolean (true))) + (property FACTORY_JF (string "16'hC080")) + (property STARTUP_WAIT (boolean (false))) + (property CLKFX_DIVIDE (integer 2)) + (property CLKFX_MULTIPLY (integer 5)) + (property PHASE_SHIFT (integer 0)) + (property CLKDV_DIVIDE (string "2.000000")) + (property CLKIN_PERIOD (string "25.000000")) + (property VERY_HIGH_FREQUENCY (string "FALSE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_13_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_13_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/clear_inv1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_24__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[24].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_19__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[19].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Mcount_wr_addr_cy_7__rt "f1/Mcount_wr_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1-In11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___6___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1-In11")) + (property INIT (string "32'h8A8ADF8A")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_8__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<8>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_7__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[7].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT511 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___25___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511")) + (property INIT (string "8'hBF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_12__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<12>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_rd_addr_cy_10_ "f1/Mcount_rd_addr_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___2___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0")) + (property INIT (string "16'h8000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr8_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_9 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_rd_addr_cy_11_ "f1/Mcount_rd_addr_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance debug_21_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance debug_16_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/read_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h80000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr8_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Result_7_2_FRB "f0/Result<7>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_wr_addr_xor_12__rt "f0/Mcount_wr_addr_xor<12>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_4_11 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<4>11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h6AAAAAAAAAAAAAA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_32__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[32].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_27__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[27].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_write_ready_go "slave_fifo32/write_ready_go") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata101 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata101") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___102___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata101")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_14_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_14_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1_SW0 "slave_fifo32/Mmux_state[1]_wr_fifo_eof_Mux_22_o1_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___24___slave_fifo32/Mmux_state[1]_wr_fifo_xfer_Mux_21_o1_SW0")) + (property INIT (string "32'h80008080")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata110 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata110") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___113___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata110")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata111 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata111") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___101___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata111")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata121 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata121") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___112___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata121")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_i_tvalid_o_tready_AND_73_o1 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/i_tvalid_o_tready_AND_73_o1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___125___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tvalid11")) + (property INIT (string "4'h4")) + ) + (instance (rename f0_Mcount_wr_addr_lut_0__INV_0 "f0/Mcount_wr_addr_lut<0>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_rd_addr_lut_0__INV_0 "f0/Mcount_rd_addr_lut<0>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata131 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata131") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___100___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata131")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<10>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_11__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[11].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata141 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata141") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___99___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata141")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<11>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tready_int1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h00000C0000000800")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<9>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata151 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata151") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___98___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata151")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<12>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata201 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata201") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___93___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata201")) + (property INIT (string "4'h8")) + ) + (instance (rename f1_wr_addr_10 "f1/wr_addr_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_wr_addr_11 "f1/wr_addr_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hFB")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_wr_addr_12 "f1/wr_addr_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW1") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata210 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata210") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___110___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata210")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata161 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata161") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___97___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata161")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<13>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000000100000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata211 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata211") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___91___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata211")) + (property INIT (string "4'h8")) + ) + (instance debug_22_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance debug_17_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_12__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[12].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<14>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2-In1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h7FFF7F7F2AFF2A2A")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata221 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata221") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___90___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata221")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata171 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata171") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___96___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata171")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_40__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[40].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_35__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[35].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_14_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_0__rt "f0/Msub_dont_write_past_me_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<15>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata231 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata231") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___83___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata231")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata181 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata181") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___95___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata181")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01215_SW0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___49___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1011")) + (property INIT (string "8'h9F")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata241 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata241") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___89___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata241")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata191 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata191") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___94___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata191")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_15_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata301 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata301") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___103___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata301")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata251 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata251") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___88___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata251")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata310 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata310") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___82___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata310")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_14__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[14].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata311 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata311") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___92___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata311")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata261 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata261") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___113___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata110")) + (property INIT (string "8'hE4")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_dont_write_past_me_0__FRB "f1/dont_write_past_me<0>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename f1_Mcompar_becoming_full_cy_0_ "f1/Mcompar_becoming_full_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata321 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata321") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___87___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata321")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata271 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata271") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___112___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata121")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Mcompar_becoming_full_cy_1_ "f1/Mcompar_becoming_full_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata331 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata331") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___86___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata331")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata281 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata281") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___83___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata231")) + (property INIT (string "8'hE4")) + ) + (net codec_main_clk_n (joined + (portref IB (instanceref gen_clks_clkin1_buf)) + (portref codec_main_clk_n) + ) + + (property DIFF_TERM (boolean (false))) + ) + (net codec_main_clk_p (joined + (portref I (instanceref gen_clks_clkin1_buf)) + (portref codec_main_clk_p) + ) + + (property DIFF_TERM (boolean (false))) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[0]") (joined + (portref O (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref S (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[0]") (joined + (portref O (instanceref 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slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + (portref rst (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + (portref rst (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_7_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<2>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<8>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8__rt)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_9_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<1>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_10_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_10_)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_9__rt "f1/Mcount_rd_addr_cy<9>_rt") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_9__rt)) + (portref S (instanceref f1_Mcount_rd_addr_cy_9_)) + (portref LI (instanceref f1_Mcount_rd_addr_xor_9_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<9>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9__rt)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9_)) + ) + ) + (net (rename f0_rd_addr_12__wr_addr_12__equal_11_o_l1 "f0/rd_addr[12]_wr_addr[12]_equal_11_o_l1") (joined + (portref O (instanceref f0__n0161_inv1_cy)) + (portref CI (instanceref f0__n0161_inv1_cy1)) + ) + ) + (net (rename slave_fifo32_Mcount_idle_cycles1 "slave_fifo32/Mcount_idle_cycles1") (joined + (portref D (instanceref slave_fifo32_idle_cycles_1)) + (portref O (instanceref slave_fifo32_Mcount_idle_cycles_xor_1_11)) + ) + ) + (net (rename slave_fifo32_Mcount_idle_cycles2 "slave_fifo32/Mcount_idle_cycles2") (joined + (portref D (instanceref slave_fifo32_idle_cycles_2)) + (portref O (instanceref slave_fifo32_Mcount_idle_cycles_xor_2_11)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_5__rt "f0/Mcount_rd_addr_cy<5>_rt") (joined + (portref O (instanceref f0_Mcount_rd_addr_cy_5__rt)) + (portref S (instanceref f0_Mcount_rd_addr_cy_5_)) + (portref LI (instanceref f0_Mcount_rd_addr_xor_5_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/empty_glue_rst") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst)) + ) + ) + (net (rename f0_wr_addr_0_ "f0/wr_addr[0]") (joined + (portref Q (instanceref f0_wr_addr_0)) + (portref I1 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref I0 (instanceref f0_Mcompar_becoming_full_lut_0_)) + (portref (member ADDRAWRADDR 12) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_1_ "f0/wr_addr[1]") (joined + (portref Q (instanceref f0_wr_addr_1)) + (portref I3 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref I2 (instanceref f0_Mcompar_becoming_full_lut_0_)) + (portref (member ADDRAWRADDR 11) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_10__rt "f0/Mcount_rd_addr_cy<10>_rt") (joined + (portref O (instanceref f0_Mcount_rd_addr_cy_10__rt)) + (portref S (instanceref f0_Mcount_rd_addr_cy_10_)) + (portref LI (instanceref f0_Mcount_rd_addr_xor_10_)) + ) + ) + (net (rename f0_wr_addr_2_ "f0/wr_addr[2]") (joined + (portref Q (instanceref f0_wr_addr_2)) + (portref I5 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref I4 (instanceref f0_Mcompar_becoming_full_lut_0_)) + (portref (member ADDRAWRADDR 10) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_3_ "f0/wr_addr[3]") (joined + (portref Q (instanceref f0_wr_addr_3)) + (portref I1 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref I0 (instanceref f0_Mcompar_becoming_full_lut_1_)) + (portref (member ADDRAWRADDR 9) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_4_ "f0/wr_addr[4]") (joined + (portref Q (instanceref f0_wr_addr_4)) + (portref I3 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref I2 (instanceref f0_Mcompar_becoming_full_lut_1_)) + (portref (member ADDRAWRADDR 8) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_5_ "f0/wr_addr[5]") (joined + (portref Q (instanceref f0_wr_addr_5)) + (portref I5 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref I4 (instanceref f0_Mcompar_becoming_full_lut_1_)) + (portref (member ADDRAWRADDR 7) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_6_ "f0/wr_addr[6]") (joined + (portref Q (instanceref f0_wr_addr_6)) + (portref I1 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref I0 (instanceref f0_Mcompar_becoming_full_lut_2_)) + (portref (member ADDRAWRADDR 6) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_Result_5_2_FRB "f0/Result<5>2_FRB") (joined + (portref D (instanceref f0_wr_addr_5)) + (portref Q (instanceref f0_Result_5_2_FRB)) + (portref I0 (instanceref f0_Mcount_wr_addr_cy_5__rt)) + ) + ) + (net (rename f0_wr_addr_7_ "f0/wr_addr[7]") (joined + (portref Q (instanceref f0_wr_addr_7)) + (portref I3 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref I2 (instanceref f0_Mcompar_becoming_full_lut_2_)) + (portref (member ADDRAWRADDR 5) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_8_ "f0/wr_addr[8]") (joined + (portref Q (instanceref f0_wr_addr_8)) + (portref I5 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref I4 (instanceref f0_Mcompar_becoming_full_lut_2_)) + (portref (member ADDRAWRADDR 4) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_9_ "f0/wr_addr[9]") (joined + (portref Q (instanceref f0_wr_addr_9)) + (portref I1 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref I0 (instanceref f0_Mcompar_becoming_full_lut_3_)) + (portref (member ADDRAWRADDR 3) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<8>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8__rt)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8_)) + ) + ) + (net (rename f0_rd_addr_10_ "f0/rd_addr[10]") (joined + (portref Q (instanceref f0_rd_addr_10)) + (portref I2 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref (member ADDRBRDADDR 2) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f1_Result_11_1_FRB "f1/Result<11>1_FRB") (joined + (portref D (instanceref f1_rd_addr_11)) + (portref Q (instanceref f1_Result_11_1_FRB)) + (portref I0 (instanceref f1_Mcount_rd_addr_cy_11__rt)) + (portref I0 (instanceref f1_Msub_dont_write_past_me_lut_11__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14)) + ) + ) + (net (rename f0_rd_addr_11_ "f0/rd_addr[11]") (joined + (portref Q (instanceref f0_rd_addr_11)) + (portref I4 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref (member ADDRBRDADDR 1) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_12_ "f0/rd_addr[12]") (joined + (portref Q (instanceref f0_rd_addr_12)) + (portref I0 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_)) + (portref (member ADDRBRDADDR 0) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 0) (instanceref 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(instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_13_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[13]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata51)) + (portref (member din 58) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_14_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[14]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata61)) + (portref (member din 57) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f1__n0161_inv "f1/_n0161_inv") (joined + (portref CE (instanceref f1_rd_addr_1)) + (portref CE (instanceref f1_rd_addr_2)) + (portref CE (instanceref f1_rd_addr_3)) + (portref CE (instanceref f1_rd_addr_4)) + (portref CE (instanceref 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(portref (member din 51) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_15_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[15]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata71)) + (portref (member din 56) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_21_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[21]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata141)) + (portref (member din 50) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_16_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[16]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata81)) + (portref (member din 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"slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[17]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata91)) + (portref (member din 54) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_23_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[23]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata161)) + (portref (member din 48) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_18_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[18]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata101)) + (portref (member din 53) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f0_dont_write_past_me_12__FRB "f0/dont_write_past_me<12>_FRB") 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(member din 44) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_28_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[28]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata211)) + (portref (member din 43) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_29_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[29]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata221)) + (portref (member din 42) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_o_tready_int "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/o_tready_int") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tready_int11)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB4)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32[0]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In33)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32[1]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In33)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32[2]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_2)) + (portref I1 (instanceref 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(portref I3 (instanceref slave_fifo32_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_5_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[3]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_3)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_)) + (portref I0 (instanceref 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slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr[5]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_5)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211)) + (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211)) + ) + ) + (net (rename tx_tdata_9_ "tx_tdata[9]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_9__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram5)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/read") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read)) + (portref rd_en (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_30_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[30]") (joined + (portref (member DIA 19) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member dout 41) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_25_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[25]") (joined + (portref (member DIA 24) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member dout 46) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr[6]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_6)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o61)) + (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_31_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[31]") (joined + (portref (member DIA 18) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member dout 40) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_26_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[26]") (joined + (portref (member DIA 23) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member dout 45) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr[7]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_7)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o71)) + (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB0") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_27_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[27]") (joined + (portref (member DIA 22) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member dout 44) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_32_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[32]") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_G)) + (portref (member dout 39) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB2") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr[8]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_8)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o81)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217)) + (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB3") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB4") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_i32_tlast "slave_fifo32/fifo64_to_gpmc32_resp/i32_tlast") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_o_tlast1)) + (portref (member din 39) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB5") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_28_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[28]") (joined + (portref (member DIA 21) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member dout 43) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr[9]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_9)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW1)) + (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n012110_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_29_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[29]") (joined + (portref (member DIA 20) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member dout 42) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_data_rx_tvalid "slave_fifo32/data_rx_tvalid") (joined + (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1)) + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tvalid11)) + (portref I5 (instanceref slave_fifo32_state_FSM_FFd1_In2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0008_10_ "slave_fifo32/fifo64_to_gpmc32_tx/n0008[10]") (joined + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_10_)) + (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member dout 61) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0008_11_ "slave_fifo32/fifo64_to_gpmc32_tx/n0008[11]") (joined + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_11_)) + (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member dout 60) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0008_12_ "slave_fifo32/fifo64_to_gpmc32_tx/n0008[12]") (joined + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_12_)) + (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member dout 59) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_write "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/write") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_write1)) + (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member WEA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member WEA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member WEA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member WEA 2) (instanceref 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(rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_6_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0003_12_ "slave_fifo32/fifo64_to_gpmc32_rx/n0003[12]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_12__srlc32e)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata41)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_10_ 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(portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0154_inv1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0__4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0][4]") (joined + (portref (member DOB 27) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member din 67) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv3 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv3") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv31)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01214)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_full "slave_fifo32/fifo64_to_gpmc32_tx/cross_clock_fifo/full") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg_glue_set)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_GND_50_o_read_OR_57_o1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_write1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1_In11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_)) + (portref I3 (instanceref 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full (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0__5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0][5]") (joined + (portref (member DOB 26) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member din 66) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0__6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0][6]") (joined + (portref (member DOB 25) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member din 65) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0__7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0][7]") (joined + (portref (member DOB 24) (instanceref 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f1_Result_11_2_FRB)) + (portref I0 (instanceref f1_Mcount_wr_addr_cy_11__rt)) + ) + ) + (net fx3_miso (joined + (portref O (instanceref fx3_miso_OBUF)) + (portref fx3_miso) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<0>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state_glue_set "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/state_glue_set") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state_glue_set)) + ) + ) + (net tx_tlast (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_64__srlc32e)) + (portref (member DIADI 15) (instanceref f1_ram_Mram_ram33)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_empty "slave_fifo32/fifo64_to_gpmc32_tx/cross_clock_fifo/empty") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_read1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker__n0131_inv1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In12_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_F)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_G)) + (portref I4 (instanceref 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slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_1_)) + ) + ) + (net (rename gen_clks_clk0 "gen_clks/clk0") (joined + (portref I (instanceref gen_clks_clkout1_buf)) + (portref CLK0 (instanceref gen_clks_dcm_sp_inst)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1_)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_11__rt "f0/Mcount_wr_addr_cy<11>_rt") (joined + (portref O (instanceref f0_Mcount_wr_addr_cy_11__rt)) + (portref S (instanceref f0_Mcount_wr_addr_cy_11_)) + (portref LI (instanceref f0_Mcount_wr_addr_xor_11_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_0_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[0]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata110)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata261)) + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_11_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_11_BRB1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_11_BRB1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3_)) + (portref CI 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slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_9_)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_1__rt "f0/Msub_dont_write_past_me_cy<1>_rt") (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_1__rt)) + (portref S (instanceref f0_Msub_dont_write_past_me_cy_1_)) + (portref LI (instanceref f0_Msub_dont_write_past_me_xor_1_)) + ) + ) + (net fx3_mosi (joined + (portref I (instanceref fx3_mosi_IBUF)) + (portref fx3_mosi) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_10_ "f1/Mcount_wr_addr_cy[10]") (joined + (portref O (instanceref f1_Mcount_wr_addr_cy_10_)) + (portref CI (instanceref f1_Mcount_wr_addr_cy_11_)) + (portref CI (instanceref f1_Mcount_wr_addr_xor_11_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>_inv") (joined + (portref D (instanceref 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f1__n0161_inv1_cy1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0076_inv") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_0)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/state_glue_set") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_glue_set)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/read") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read)) + (portref rd_en (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_0)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_2)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_3)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_4)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv)) + ) + ) + (net (rename bus_sync_reset_int "bus_sync/reset_int") (joined + (portref Q (instanceref bus_sync_reset_int)) + (portref D (instanceref bus_sync_reset_out)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full92 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full92") (joined + (portref O (instanceref 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(rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[1]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_1_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_1_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[2]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_2_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_2_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr1_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1__rt)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr1_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[3]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_3_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_3_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_3_)) + ) + ) + (net (rename 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(instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0154_inv1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[4]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_4_)) + (portref LI (instanceref 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(portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[7]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_7_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_7_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_7_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1-In") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[8]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_8_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_8_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_dont_write_past_me_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/dont_write_past_me[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1-In1") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_0)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_2)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_3)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_4)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[9]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_9_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_9_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_9_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full621_FRB") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0121111)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01213)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621_FRB)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012112)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid_bdd2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tvalid_bdd2") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid31)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid_bdd8 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tvalid_bdd8") (joined + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_o_tready_int "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/o_tready_int") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr2_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_2)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr2_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2__rt)) + ) + ) + (net tx_codec_d_5_OBUF (joined + (portref Q (instanceref catgen_gen_pins_5__oddr2)) + (portref I (instanceref tx_codec_d_5_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[0]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0_)) + (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRA 12) (instanceref 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slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member ADDRAWRADDR 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[1]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0_)) + (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRA 11) (instanceref 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slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member ADDRAWRADDR 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr6_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_6)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr6_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_6__rt)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[2]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_2)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0_)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member ADDRAWRADDR 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + ) + ) + (net (rename f0_Result_9_2_FRB "f0/Result<9>2_FRB") (joined + (portref D (instanceref f0_wr_addr_9)) + (portref Q (instanceref f0_Result_9_2_FRB)) + (portref I0 (instanceref f0_Mcount_wr_addr_cy_9__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[3]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_3)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1_)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member ADDRAWRADDR 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[4]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_4)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1_)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member ADDRAWRADDR 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_4_)) + ) + ) + (net tx_frame_p_OBUF (joined + (portref Q (instanceref catgen_oddr2_frame)) + (portref I (instanceref tx_frame_p_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[5]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_5)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1_)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member ADDRAWRADDR 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_inv") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1)) + ) + ) + (net IFCLK (joined + (portref O (instanceref IFCLK_OBUF)) + (portref IFCLK) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[6]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_6)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2_)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member ADDRAWRADDR 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[7]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_7)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2_)) + (portref (member ADDRA 5) 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slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7)) + (portref R (instanceref f1_wr_addr_9)) + (portref R (instanceref f1_wr_addr_8)) + (portref R (instanceref f1_wr_addr_7)) + (portref R (instanceref f1_wr_addr_6)) + (portref R (instanceref f1_wr_addr_5)) + (portref R (instanceref f1_wr_addr_4)) + (portref R (instanceref f1_wr_addr_3)) + (portref R (instanceref f1_wr_addr_2)) + (portref R (instanceref f1_wr_addr_12)) + (portref R (instanceref f1_wr_addr_11)) + (portref R (instanceref f1_wr_addr_10)) + (portref R (instanceref f1_wr_addr_1)) + (portref R (instanceref f1_wr_addr_0)) + (portref R (instanceref f1_rd_addr_9)) + (portref R (instanceref f1_rd_addr_8)) + (portref R (instanceref f1_rd_addr_7)) + (portref R (instanceref f1_rd_addr_6)) + (portref R (instanceref f1_rd_addr_5)) + (portref R (instanceref f1_rd_addr_4)) + (portref R (instanceref f1_rd_addr_3)) + (portref R (instanceref f1_rd_addr_2)) + (portref R (instanceref f1_rd_addr_12)) + (portref R (instanceref f1_rd_addr_11)) + (portref R (instanceref f1_rd_addr_10)) + (portref R (instanceref f1_rd_addr_1)) + (portref R (instanceref f1_rd_addr_0)) + (portref R (instanceref f1_read_state_FSM_FFd1)) + (portref R (instanceref f0_wr_addr_9)) + (portref R (instanceref f0_wr_addr_8)) + (portref R (instanceref f0_wr_addr_7)) + (portref R (instanceref f0_wr_addr_6)) + (portref R (instanceref f0_wr_addr_5)) + (portref R (instanceref f0_wr_addr_4)) + (portref R (instanceref f0_wr_addr_3)) + (portref R (instanceref f0_wr_addr_2)) + (portref R (instanceref f0_wr_addr_12)) + (portref R (instanceref f0_wr_addr_11)) + (portref R (instanceref f0_wr_addr_10)) + (portref R (instanceref f0_wr_addr_1)) + (portref R (instanceref f0_wr_addr_0)) + (portref R (instanceref f0_rd_addr_9)) + (portref R (instanceref f0_rd_addr_8)) + (portref R (instanceref f0_rd_addr_7)) + (portref R (instanceref f0_rd_addr_6)) + (portref R (instanceref f0_rd_addr_5)) + (portref R (instanceref f0_rd_addr_4)) + (portref R (instanceref f0_rd_addr_3)) + (portref R (instanceref f0_rd_addr_2)) + (portref R (instanceref f0_rd_addr_12)) + (portref R (instanceref f0_rd_addr_11)) + (portref R (instanceref f0_rd_addr_10)) + (portref R (instanceref f0_rd_addr_1)) + (portref R (instanceref f0_rd_addr_0)) + (portref R (instanceref f0_read_state_FSM_FFd1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo_rst_gpif_rst_OR_155_o1)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump)) + (portref R (instanceref f1_full_reg)) + (portref R (instanceref f0_full_reg)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg)) + (portref S (instanceref f1_Result_0_2_FRB)) + (portref R (instanceref f1_Result_1_2_FRB)) + (portref R (instanceref f1_Result_2_2_FRB)) + (portref R (instanceref f1_Result_3_2_FRB)) + (portref R (instanceref f1_Result_4_2_FRB)) + (portref R (instanceref f1_Result_5_2_FRB)) + (portref R (instanceref f1_Result_6_2_FRB)) + (portref R (instanceref f1_Result_7_2_FRB)) + (portref R (instanceref f1_Result_8_2_FRB)) + (portref R (instanceref f1_Result_9_2_FRB)) + (portref R (instanceref f1_Result_10_2_FRB)) + (portref R (instanceref f1_Result_11_2_FRB)) + (portref R (instanceref f1_Result_12_2_FRB)) + (portref S (instanceref f1_Result_0_1_FRB)) + (portref R (instanceref f1_Result_1_1_FRB)) + (portref R (instanceref f1_Result_2_1_FRB)) + (portref R (instanceref f1_Result_3_1_FRB)) + (portref R (instanceref f1_Result_4_1_FRB)) + (portref R (instanceref f1_Result_5_1_FRB)) + (portref R (instanceref f1_Result_6_1_FRB)) + (portref R (instanceref f1_Result_7_1_FRB)) + (portref R (instanceref f1_Result_8_1_FRB)) + (portref R (instanceref f1_Result_9_1_FRB)) + (portref R (instanceref f1_Result_10_1_FRB)) + (portref R (instanceref f1_Result_11_1_FRB)) + (portref R (instanceref f1_Result_12_1_FRB)) + (portref S (instanceref f1_dont_write_past_me_0__FRB)) + (portref R (instanceref f1_dont_write_past_me_1__FRB)) + (portref S (instanceref f1_dont_write_past_me_2__FRB)) + (portref S (instanceref f1_dont_write_past_me_3__FRB)) + (portref S (instanceref f1_dont_write_past_me_4__FRB)) + (portref S (instanceref f1_dont_write_past_me_5__FRB)) + (portref S (instanceref f1_dont_write_past_me_6__FRB)) + (portref S (instanceref f1_dont_write_past_me_7__FRB)) + (portref S (instanceref f1_dont_write_past_me_8__FRB)) + (portref S (instanceref f1_dont_write_past_me_9__FRB)) + (portref S (instanceref f1_dont_write_past_me_10__FRB)) + (portref S (instanceref f1_dont_write_past_me_11__FRB)) + (portref S (instanceref f1_dont_write_past_me_12__FRB)) + (portref S (instanceref f0_Result_0_2_FRB)) + (portref R (instanceref f0_Result_1_2_FRB)) + (portref R (instanceref f0_Result_2_2_FRB)) + (portref R (instanceref f0_Result_3_2_FRB)) + (portref R (instanceref f0_Result_4_2_FRB)) + (portref R (instanceref f0_Result_5_2_FRB)) + (portref R (instanceref f0_Result_6_2_FRB)) + (portref R (instanceref f0_Result_7_2_FRB)) + (portref R (instanceref f0_Result_8_2_FRB)) + (portref R (instanceref f0_Result_9_2_FRB)) + (portref R (instanceref f0_Result_10_2_FRB)) + (portref R (instanceref f0_Result_11_2_FRB)) + (portref R (instanceref f0_Result_12_2_FRB)) + (portref S (instanceref f0_Result_0_1_FRB)) + (portref R (instanceref f0_Result_1_1_FRB)) + (portref R (instanceref f0_Result_2_1_FRB)) + (portref R (instanceref f0_Result_3_1_FRB)) + (portref R (instanceref f0_Result_4_1_FRB)) + (portref R (instanceref f0_Result_5_1_FRB)) + (portref R (instanceref f0_Result_6_1_FRB)) + (portref R (instanceref f0_Result_7_1_FRB)) + (portref R (instanceref f0_Result_8_1_FRB)) + (portref R (instanceref f0_Result_9_1_FRB)) + (portref R (instanceref f0_Result_10_1_FRB)) + (portref R (instanceref f0_Result_11_1_FRB)) + (portref R (instanceref f0_Result_12_1_FRB)) + (portref S (instanceref f0_dont_write_past_me_0__FRB)) + (portref R (instanceref f0_dont_write_past_me_1__FRB)) + (portref S (instanceref f0_dont_write_past_me_2__FRB)) + (portref S (instanceref f0_dont_write_past_me_3__FRB)) + (portref S (instanceref f0_dont_write_past_me_4__FRB)) + (portref S (instanceref f0_dont_write_past_me_5__FRB)) + (portref S (instanceref f0_dont_write_past_me_6__FRB)) + (portref S (instanceref f0_dont_write_past_me_7__FRB)) + (portref S (instanceref f0_dont_write_past_me_8__FRB)) + (portref S (instanceref f0_dont_write_past_me_9__FRB)) + (portref S (instanceref f0_dont_write_past_me_10__FRB)) + (portref S (instanceref f0_dont_write_past_me_11__FRB)) + (portref S (instanceref f0_dont_write_past_me_12__FRB)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0_FRB)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_1)) + ) + ) + (net (rename f0_Result_11_1_FRB "f0/Result<11>1_FRB") (joined + (portref D (instanceref f0_rd_addr_11)) + (portref Q (instanceref f0_Result_11_1_FRB)) + (portref I0 (instanceref f0_Mcount_rd_addr_cy_11__rt)) + (portref I0 (instanceref f0_Msub_dont_write_past_me_lut_11__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_10_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[10]") (joined + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_11_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[11]") (joined + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[12]") (joined + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_13_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[13]") (joined + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_0)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_2)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_3)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_4)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_5)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_6)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_7)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_8)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB0)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_13_BRB1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_14_BRB1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15_BRB1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_11_BRB1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_10_BRB1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_9_BRB1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd2_BRB0") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd2_BRB1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1)) + ) + ) + (net (rename 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slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT110)) + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename ctrl_tdata_8_ "ctrl_tdata[8]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_8__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram5)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_2_)) + ) + ) + (net GPIF_CTL5_IBUF (joined + (portref D (instanceref slave_fifo32_EP_WMARK)) + (portref O (instanceref GPIF_CTL5_IBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/GND_56_o_read_OR_123_o") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref ENB (instanceref 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slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a1 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a1") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_0)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_0_11_INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<4>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a2 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a2") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_1_11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0154_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0154_inv") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_0)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_2)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_3)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_4)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_5)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_6)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_7)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_8)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_FRB)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr1_FRB)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr2_FRB)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr3_FRB)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr4_FRB)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr5_FRB)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr6_FRB)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr7_FRB)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr8_FRB)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_write1)) + (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member WEA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member WEA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member WEA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a3 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a3") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_2)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_2_11)) + ) + ) + (net (rename f1_GND_14_o_read_OR_37_o "f1/GND_14_o_read_OR_37_o") (joined + (portref O (instanceref f1_GND_14_o_read_OR_37_o1)) + (portref ENBRDEN (instanceref f1_ram_Mram_ram33)) + (portref ENB (instanceref f1_ram_Mram_ram31)) + (portref ENB (instanceref f1_ram_Mram_ram30)) + (portref ENB (instanceref f1_ram_Mram_ram32)) + (portref ENB (instanceref f1_ram_Mram_ram28)) + (portref ENB (instanceref f1_ram_Mram_ram27)) + (portref ENB (instanceref f1_ram_Mram_ram29)) + (portref ENB (instanceref f1_ram_Mram_ram25)) + (portref ENB (instanceref f1_ram_Mram_ram24)) + (portref ENB (instanceref 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(instanceref f1_ram_Mram_ram2)) + (portref ENB (instanceref f1_ram_Mram_ram4)) + (portref ENB (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker__n0131_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/_n0131_inv") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_0)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_2)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_3)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_4)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_5)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_6)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_7)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_8)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_9)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_10)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_11)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_12)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_13)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_14)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_15)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker__n0131_inv1)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tdata_3_ "slave_fifo32/ctrl_rx_tdata[3]") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT261)) + (portref (member DOB 28) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a4 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a4") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_3)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_3_11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a5 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a5") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_4)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_4_11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_5_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tready_int11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tdata_4_ "slave_fifo32/ctrl_rx_tdata[4]") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT271)) + (portref (member DOB 27) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_slrd_rstpot "slave_fifo32/slrd_rstpot") (joined + (portref D (instanceref slave_fifo32_slrd)) + (portref O (instanceref slave_fifo32_slrd_rstpot)) + (portref D (instanceref slave_fifo32_slrd_1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_6_)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tdata_5_ "slave_fifo32/ctrl_rx_tdata[5]") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT281)) + (portref (member DOB 26) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<3>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_3_)) + ) + ) + (net tx_codec_d_11_OBUF (joined + (portref Q (instanceref catgen_gen_pins_11__oddr2)) + (portref I (instanceref tx_codec_d_11_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_7_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[10]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11_)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tdata_6_ "slave_fifo32/ctrl_rx_tdata[6]") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT291)) + (portref (member DOB 25) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[11]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12_)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tdata_7_ "slave_fifo32/ctrl_rx_tdata[7]") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT301)) + (portref (member DOB 24) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net tx_codec_d_9_OBUF (joined + (portref Q (instanceref catgen_gen_pins_9__oddr2)) + (portref I (instanceref tx_codec_d_9_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[12]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_empty "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/empty") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1)) + (portref empty (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tdata_8_ "slave_fifo32/ctrl_rx_tdata[8]") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT311)) + (portref (member DOB 23) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[13]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_)) + (portref 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slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_10_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_10)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines3211 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines3211") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_11_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines3212 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines3212") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_12_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_12)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In_bdd1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In_bdd1") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In13)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_F)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_G)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines3213 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines3213") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_13_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_13)) + ) + ) + (net (rename slave_fifo32_read_ready_go "slave_fifo32/read_ready_go") (joined + (portref Q (instanceref slave_fifo32_read_ready_go)) + (portref I2 (instanceref slave_fifo32__n0290_inv1)) + (portref I0 (instanceref slave_fifo32__n0258_inv_SW0)) + (portref I1 (instanceref slave_fifo32__n0279_inv_SW0)) + (portref I3 (instanceref slave_fifo32_state_FSM_FFd2_In2)) + (portref I1 (instanceref slave_fifo32_slrd_rstpot_SW0)) + (portref I2 (instanceref slave_fifo32_sloe_1_rstpot)) + (portref I3 (instanceref slave_fifo32_state_FSM_FFd1_In3_F)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines3214 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines3214") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_14_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_14)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines3215 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines3215") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_15_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_15)) + ) + ) + (net (rename slave_fifo32_state_FSM_FFd1_In2 "slave_fifo32/state_FSM_FFd1-In2") (joined + (portref O (instanceref slave_fifo32_state_FSM_FFd1_In2)) + (portref I1 (instanceref slave_fifo32_state_FSM_FFd1_In4)) + (portref I3 (instanceref slave_fifo32_state_FSM_FFd2_In3)) + ) + ) + (net (rename slave_fifo32_state_FSM_FFd1_In3 "slave_fifo32/state_FSM_FFd1-In3") (joined + (portref O (instanceref slave_fifo32_state_FSM_FFd1_In3)) + (portref I0 (instanceref slave_fifo32_state_FSM_FFd1_In4)) + ) + ) + (net (rename codec_ctrl_in_0_ "codec_ctrl_in[0]") (joined + (portref O (instanceref codec_ctrl_in_0_OBUF)) + (portref (member codec_ctrl_in 3)) + ) + ) + (net (rename codec_ctrl_in_1_ "codec_ctrl_in[1]") (joined + (portref O (instanceref codec_ctrl_in_1_OBUF)) + (portref (member codec_ctrl_in 2)) + ) + ) + (net (rename codec_ctrl_in_2_ "codec_ctrl_in[2]") (joined + (portref O (instanceref codec_ctrl_in_2_OBUF)) + (portref (member codec_ctrl_in 1)) + ) + ) + (net (rename codec_ctrl_in_3_ "codec_ctrl_in[3]") (joined + (portref O (instanceref codec_ctrl_in_3_OBUF)) + (portref (member codec_ctrl_in 0)) + ) + ) + (net codec_sync (joined + (portref O (instanceref codec_sync_OBUF)) + (portref codec_sync) + ) + ) + (net (rename tx_tdata_10_ "tx_tdata[10]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_10__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o1)) + ) + ) + (net (rename tx_tdata_11_ "tx_tdata[11]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_11__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<1>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_1_)) + ) + ) + (net (rename tx_tdata_12_ "tx_tdata[12]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_12__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram7)) + ) + ) + (net ctrl_tlast (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e)) + (portref (member DIADI 15) (instanceref f0_ram_Mram_ram33)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_2__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<2>_FRB") (joined + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_0_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_2__FRB)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_write "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/write") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_write1)) + (portref wr_en (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename tx_tdata_13_ "tx_tdata[13]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_13__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram7)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_0)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_4_)) + ) + ) + (net (rename tx_tdata_14_ "tx_tdata[14]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_14__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram8)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<0>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_0__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_0_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_5_)) + ) + ) + (net (rename tx_tdata_20_ "tx_tdata[20]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_20__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram11)) + ) + ) + (net (rename tx_tdata_15_ "tx_tdata[15]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_15__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram8)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_6_)) + ) + ) + (net (rename slave_fifo32_debug1_0_ "slave_fifo32/debug1[0]") (joined + (portref Q (instanceref slave_fifo32_debug1_0)) + (portref D (instanceref slave_fifo32_debug2_0)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_8__rt "f1/Mcount_wr_addr_cy<8>_rt") (joined + (portref O (instanceref f1_Mcount_wr_addr_cy_8__rt)) + (portref S (instanceref f1_Mcount_wr_addr_cy_8_)) + (portref LI (instanceref f1_Mcount_wr_addr_xor_8_)) + ) + ) + (net (rename tx_tdata_16_ "tx_tdata[16]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_16__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram9)) + ) + ) + (net (rename tx_tdata_21_ "tx_tdata[21]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_21__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_7_)) + ) + ) + (net (rename slave_fifo32_debug1_1_ "slave_fifo32/debug1[1]") (joined + (portref Q (instanceref slave_fifo32_debug1_1)) + (portref D (instanceref slave_fifo32_debug2_1)) + ) + ) + (net (rename tx_tdata_22_ "tx_tdata[22]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_22__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram12)) + ) + ) + (net (rename tx_tdata_17_ "tx_tdata[17]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_17__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram9)) + ) + ) + (net (rename f1_rd_addr_10_ "f1/rd_addr[10]") (joined + (portref Q (instanceref f1_rd_addr_10)) + (portref I2 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref (member ADDRBRDADDR 2) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_8_)) + ) + ) + (net (rename slave_fifo32_debug1_2_ "slave_fifo32/debug1[2]") (joined + (portref Q (instanceref slave_fifo32_debug1_2)) + (portref D (instanceref slave_fifo32_debug2_2)) + ) + ) + (net (rename tx_tdata_23_ "tx_tdata[23]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_23__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram12)) + ) + ) + (net (rename tx_tdata_18_ "tx_tdata[18]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_18__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram10)) + ) + ) + (net (rename f1_rd_addr_11_ "f1/rd_addr[11]") (joined + (portref Q (instanceref f1_rd_addr_11)) + (portref I4 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref (member ADDRBRDADDR 1) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_9_)) + ) + ) + (net (rename slave_fifo32_debug1_3_ "slave_fifo32/debug1[3]") (joined + (portref Q (instanceref slave_fifo32_debug1_3)) + (portref D (instanceref slave_fifo32_debug2_3)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/full_glue_set") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set)) + ) + ) + (net (rename tx_tdata_24_ "tx_tdata[24]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_24__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram13)) + ) + ) + (net (rename tx_tdata_19_ "tx_tdata[19]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_19__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram10)) + ) + ) + (net (rename f1_rd_addr_12_ "f1/rd_addr[12]") (joined + (portref Q (instanceref f1_rd_addr_12)) + (portref I0 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_)) + (portref (member ADDRBRDADDR 0) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_10_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_10_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_2_)) + ) + ) + (net (rename slave_fifo32_debug1_4_ "slave_fifo32/debug1[4]") (joined + (portref Q (instanceref slave_fifo32_debug1_4)) + (portref D (instanceref slave_fifo32_debug2_4)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[10]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_10_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_11_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_11_)) + ) + ) + (net (rename tx_tdata_30_ "tx_tdata[30]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_30__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram16)) + ) + ) + (net (rename tx_tdata_25_ "tx_tdata[25]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_25__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram13)) + ) + ) + (net (rename slave_fifo32_debug1_5_ "slave_fifo32/debug1[5]") (joined + (portref Q (instanceref slave_fifo32_debug1_5)) + (portref D (instanceref slave_fifo32_debug2_5)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[11]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_11_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_12_)) + ) + ) + (net (rename tx_tdata_31_ "tx_tdata[31]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_31__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram16)) + ) + ) + (net (rename tx_tdata_26_ "tx_tdata[26]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_26__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram14)) + ) + ) + (net (rename slave_fifo32_debug1_6_ "slave_fifo32/debug1[6]") (joined + (portref Q (instanceref slave_fifo32_debug1_6)) + (portref D (instanceref slave_fifo32_debug2_6)) + ) + ) + (net (rename tx_tdata_32_ "tx_tdata[32]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_32__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram17)) + ) + ) + (net (rename tx_tdata_27_ "tx_tdata[27]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_27__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram14)) + ) + ) + (net GPIF_CTL9_IBUF (joined + (portref RST (instanceref gen_clks_dcm_sp_inst)) + (portref I1 (instanceref reset_global_locked_OR_1_o1)) + (portref O (instanceref GPIF_CTL9_IBUF)) + ) + ) + (net (rename slave_fifo32_debug1_7_ "slave_fifo32/debug1[7]") (joined + (portref Q (instanceref slave_fifo32_debug1_7)) + (portref D (instanceref slave_fifo32_debug2_7)) + ) + ) + (net (rename tx_tdata_33_ "tx_tdata[33]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_33__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram17)) + ) + ) + (net (rename tx_tdata_28_ "tx_tdata[28]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_28__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram15)) + ) + ) + (net (rename slave_fifo32_debug1_8_ "slave_fifo32/debug1[8]") (joined + (portref Q (instanceref slave_fifo32_debug1_8)) + (portref D (instanceref slave_fifo32_debug2_8)) + ) + ) + (net (rename tx_tdata_34_ "tx_tdata[34]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_34__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram18)) + ) + ) + (net (rename tx_tdata_29_ "tx_tdata[29]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_29__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram15)) + ) + ) + (net (rename slave_fifo32_debug1_9_ "slave_fifo32/debug1[9]") (joined + (portref Q (instanceref slave_fifo32_debug1_9)) + (portref D (instanceref slave_fifo32_debug2_9)) + ) + ) + (net (rename tx_tdata_40_ "tx_tdata[40]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_40__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram21)) + ) + ) + (net (rename tx_tdata_35_ "tx_tdata[35]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_35__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram18)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/empty_glue_rst") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst)) + ) + ) + (net (rename tx_tdata_41_ "tx_tdata[41]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_41__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram21)) + ) + ) + (net (rename tx_tdata_36_ "tx_tdata[36]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_36__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram19)) + ) + ) + (net (rename tx_tdata_42_ "tx_tdata[42]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_42__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram22)) + ) + ) + (net (rename tx_tdata_37_ "tx_tdata[37]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_37__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram19)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg_glue_set") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg_glue_set)) + ) + ) + (net (rename tx_tdata_43_ "tx_tdata[43]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_43__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram22)) + ) + ) + (net (rename tx_tdata_38_ "tx_tdata[38]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_38__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram20)) + ) + ) + (net (rename tx_tdata_39_ "tx_tdata[39]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_39__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram20)) + ) + ) + (net (rename tx_tdata_44_ "tx_tdata[44]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_44__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram23)) + ) + ) + (net (rename tx_tdata_50_ "tx_tdata[50]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_50__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram26)) + ) + ) + (net (rename tx_tdata_45_ "tx_tdata[45]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_45__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram23)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32[10]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_10)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_10_)) + ) + ) + (net fx3_sclk_IBUF (joined + (portref I1 (instanceref cat_sclk1)) + (portref O (instanceref fx3_sclk_IBUF)) + ) + ) + (net (rename tx_tdata_51_ "tx_tdata[51]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_51__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram26)) + ) + ) + (net (rename tx_tdata_46_ "tx_tdata[46]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_46__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram24)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32[11]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_11)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_11_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_4__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<4>_FRB") (joined + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_1_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_4__FRB)) + ) + ) + (net (rename tx_tdata_52_ "tx_tdata[52]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_52__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram27)) + ) + ) + (net (rename tx_tdata_47_ "tx_tdata[47]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_47__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram24)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32[12]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_12)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_12_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_10__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<10>_FRB") (joined + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_3_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_10__FRB)) + ) + ) + (net (rename tx_tdata_53_ "tx_tdata[53]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_53__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram27)) + ) + ) + (net (rename tx_tdata_48_ "tx_tdata[48]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_48__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram25)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_13_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32[13]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_13)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_13_)) + ) + ) + (net (rename tx_tdata_54_ "tx_tdata[54]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_54__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram28)) + ) + ) + (net (rename tx_tdata_49_ "tx_tdata[49]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_49__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram25)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_14_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32[14]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_14)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_14_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr4_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_4)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt)) + ) + ) + (net (rename tx_tdata_60_ "tx_tdata[60]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_60__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram31)) + ) + ) + (net (rename tx_tdata_55_ "tx_tdata[55]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_55__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram28)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_15_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32[15]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_15)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_15_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_9_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_9_BRB1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_9_BRB1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_)) + ) + ) + (net (rename slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o "slave_fifo32/ctrl_tx_tready_data_tx_tready_OR_55_o") (joined + (portref D (instanceref slave_fifo32_read_ready_go)) + (portref O (instanceref slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o1)) + ) + ) + (net (rename tx_tdata_61_ "tx_tdata[61]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_61__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram31)) + ) + ) + (net (rename tx_tdata_56_ "tx_tdata[56]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_56__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram29)) + ) + ) + (net codec_txrx (joined + (portref O (instanceref codec_txrx_OBUF)) + (portref codec_txrx) + ) + ) + (net (rename tx_tdata_62_ "tx_tdata[62]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_62__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram32)) + ) + ) + (net (rename tx_tdata_57_ "tx_tdata[57]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_57__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram29)) + ) + ) + (net (rename tx_tdata_63_ "tx_tdata[63]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_63__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram32)) + ) + ) + (net (rename tx_tdata_58_ "tx_tdata[58]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_58__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram30)) + ) + ) + (net (rename tx_tdata_59_ "tx_tdata[59]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_59__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram30)) + ) + ) + (net (rename slave_fifo32_debug2_0_ "slave_fifo32/debug2[0]") (joined + (portref Q (instanceref slave_fifo32_debug2_0)) + (portref I (instanceref debug_0_OBUF)) + ) + ) + (net (rename slave_fifo32_debug2_1_ "slave_fifo32/debug2[1]") (joined + (portref Q (instanceref slave_fifo32_debug2_1)) + (portref I (instanceref debug_1_OBUF)) + ) + ) + (net (rename slave_fifo32_debug2_2_ "slave_fifo32/debug2[2]") (joined + (portref Q (instanceref slave_fifo32_debug2_2)) + (portref I (instanceref debug_2_OBUF)) + ) + ) + (net (rename f0_full_reg "f0/full_reg") (joined + (portref I1 (instanceref f0_write11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW0)) + (portref Q (instanceref f0_full_reg)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111_SW0)) + (portref D (instanceref slave_fifo32_debug1_16_BRB0)) + (portref I4 (instanceref f0_read_state_FSM_FFd2_In1)) + (portref I4 (instanceref f0_full_reg_glue_set)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111)) + ) + ) + (net (rename slave_fifo32_debug2_3_ "slave_fifo32/debug2[3]") (joined + (portref Q (instanceref slave_fifo32_debug2_3)) + (portref I (instanceref debug_3_OBUF)) + ) + ) + (net (rename slave_fifo32_debug2_4_ "slave_fifo32/debug2[4]") (joined + (portref Q (instanceref slave_fifo32_debug2_4)) + (portref I (instanceref debug_4_OBUF)) + ) + ) + (net (rename slave_fifo32_debug2_5_ "slave_fifo32/debug2[5]") (joined + (portref Q (instanceref slave_fifo32_debug2_5)) + (portref I (instanceref debug_5_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT311 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT311") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1)) + ) + ) + (net (rename f1_wr_addr_0_ "f1/wr_addr[0]") (joined + (portref Q (instanceref f1_wr_addr_0)) + (portref I1 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref I0 (instanceref f1_Mcompar_becoming_full_lut_0_)) + (portref (member ADDRAWRADDR 12) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_debug2_6_ "slave_fifo32/debug2[6]") (joined + (portref Q (instanceref slave_fifo32_debug2_6)) + (portref I (instanceref debug_6_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_write "slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/write") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_write1)) + (portref wr_en (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f1_wr_addr_1_ "f1/wr_addr[1]") (joined + (portref Q (instanceref f1_wr_addr_1)) + (portref I3 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref I2 (instanceref f1_Mcompar_becoming_full_lut_0_)) + (portref (member ADDRAWRADDR 11) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_debug2_7_ "slave_fifo32/debug2[7]") (joined + (portref Q (instanceref slave_fifo32_debug2_7)) + (portref I (instanceref debug_7_OBUF)) + ) + ) + (net (rename f1_wr_addr_2_ "f1/wr_addr[2]") (joined + (portref Q (instanceref f1_wr_addr_2)) + (portref I5 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref I4 (instanceref f1_Mcompar_becoming_full_lut_0_)) + (portref (member ADDRAWRADDR 10) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_debug2_8_ "slave_fifo32/debug2[8]") (joined + (portref Q (instanceref slave_fifo32_debug2_8)) + (portref I (instanceref debug_8_OBUF)) + ) + ) + (net (rename f1_wr_addr_3_ "f1/wr_addr[3]") (joined + (portref Q (instanceref f1_wr_addr_3)) + (portref I1 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref I0 (instanceref f1_Mcompar_becoming_full_lut_1_)) + (portref (member ADDRAWRADDR 9) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_debug2_9_ "slave_fifo32/debug2[9]") (joined + (portref Q (instanceref slave_fifo32_debug2_9)) + (portref I (instanceref debug_9_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT311 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT311") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0146_inv1)) + ) + ) + (net (rename f1_wr_addr_4_ "f1/wr_addr[4]") (joined + (portref Q (instanceref f1_wr_addr_4)) + (portref I3 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref I2 (instanceref f1_Mcompar_becoming_full_lut_1_)) + (portref (member ADDRAWRADDR 8) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_i32_tdata_10_ "slave_fifo32/fifo64_to_gpmc32_resp/i32_tdata[10]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata210)) + (portref (member din 61) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f1_wr_addr_5_ "f1/wr_addr[5]") (joined + (portref Q (instanceref f1_wr_addr_5)) + (portref I5 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref I4 (instanceref f1_Mcompar_becoming_full_lut_1_)) + (portref (member ADDRAWRADDR 7) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_6__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<6>_FRB") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_2_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_6__FRB)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_i32_tdata_11_ "slave_fifo32/fifo64_to_gpmc32_resp/i32_tdata[11]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata33)) + (portref (member din 60) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[10]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_10)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata210)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata371)) + (portref (member DOB 21) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_6_ "f1/wr_addr[6]") (joined + (portref Q (instanceref f1_wr_addr_6)) + (portref I1 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref I0 (instanceref f1_Mcompar_becoming_full_lut_2_)) + (portref (member ADDRAWRADDR 6) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_12__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<12>_FRB") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_4_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_12__FRB)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_i32_tdata_12_ "slave_fifo32/fifo64_to_gpmc32_resp/i32_tdata[12]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata41)) + (portref (member din 59) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[11]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata310)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata381)) + (portref (member DOB 20) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_7_ "f1/wr_addr[7]") (joined + (portref Q (instanceref f1_wr_addr_7)) + (portref I3 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref I2 (instanceref f1_Mcompar_becoming_full_lut_2_)) + (portref (member ADDRAWRADDR 5) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram1)) + ) + ) + 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) + ) + (net (rename slave_fifo32_data_rx_tdata_11_ "slave_fifo32/data_rx_tdata[11]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT33)) + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_i32_tdata_31_ "slave_fifo32/fifo64_to_gpmc32_resp/i32_tdata[31]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata251)) + (portref (member din 40) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_i32_tdata_26_ "slave_fifo32/fifo64_to_gpmc32_resp/i32_tdata[26]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata191)) + (portref (member din 45) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename 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slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01211_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_i32_tdata_29_ "slave_fifo32/fifo64_to_gpmc32_resp/i32_tdata[29]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata221)) + (portref (member din 42) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_28_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[28]") 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slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tlast "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tlast") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_glue_set)) + (portref (member DOB 17) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tvalid11)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_write1)) + ) + ) + (net (rename f1_Result_9_1_FRB "f1/Result<9>1_FRB") (joined + (portref D (instanceref f1_rd_addr_9)) + (portref Q (instanceref f1_Result_9_1_FRB)) + (portref I0 (instanceref f1_Mcount_rd_addr_cy_9__rt)) + (portref I0 (instanceref f1_Msub_dont_write_past_me_lut_9__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_29_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[29]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_29)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata221)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata581)) + (portref (member DOB 20) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_16_ "slave_fifo32/data_rx_tdata[16]") (joined + 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(portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_18_ "slave_fifo32/data_rx_tdata[18]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT101)) + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_23_ "slave_fifo32/data_rx_tdata[23]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT161)) + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[10]") (joined + (portref S (instanceref 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slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[11]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_25_ "slave_fifo32/data_rx_tdata[25]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT181)) + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_30_ "slave_fifo32/data_rx_tdata[30]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT241)) + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[12]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_26_ "slave_fifo32/data_rx_tdata[26]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT191)) + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_31_ "slave_fifo32/data_rx_tdata[31]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT251)) + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_8__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<8>_FRB") (joined + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_2_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_8__FRB)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[13]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8211") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_27_ "slave_fifo32/data_rx_tdata[27]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT201)) + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr3_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_3)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr3_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[14]") (joined + (portref S (instanceref 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+ (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_29_ "slave_fifo32/data_rx_tdata[29]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT221)) + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n012121 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n012121") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0121211)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01216_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215_SW0)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_0_ "f1/Mcount_rd_addr_cy[0]") (joined + (portref O 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slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_1_ "f1/Mcount_rd_addr_cy[1]") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_1_)) + (portref CI (instanceref f1_Mcount_rd_addr_cy_2_)) + (portref CI (instanceref f1_Mcount_rd_addr_xor_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_lut1") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_cy1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1)) + ) + ) + (net (rename slave_fifo32_fifoadr_0_ "slave_fifo32/fifoadr[0]") (joined + (portref Q (instanceref slave_fifo32_fifoadr_0)) + (portref I (instanceref GPIF_CTL12_OBUF)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_2_ "f1/Mcount_rd_addr_cy[2]") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_2_)) + (portref CI (instanceref f1_Mcount_rd_addr_cy_3_)) + (portref CI (instanceref f1_Mcount_rd_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr7_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_7)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr7_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_7__rt)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_GND_50_o_read_OR_57_o "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/GND_50_o_read_OR_57_o") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_GND_50_o_read_OR_57_o1)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifoadr_1_ "slave_fifo32/fifoadr[1]") (joined + (portref Q (instanceref slave_fifo32_fifoadr_1)) + (portref I (instanceref GPIF_CTL11_OBUF)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_3_ "f1/Mcount_rd_addr_cy[3]") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_3_)) + (portref CI (instanceref f1_Mcount_rd_addr_cy_4_)) + (portref CI (instanceref f1_Mcount_rd_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[10]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_10__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata210)) + ) + ) + (net (rename f0_rd_addr_0_ "f0/rd_addr[0]") (joined + (portref Q (instanceref f0_rd_addr_0)) + (portref I0 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref (member ADDRBRDADDR 12) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB0") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_4_ "f1/Mcount_rd_addr_cy[4]") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_4_)) + (portref CI (instanceref f1_Mcount_rd_addr_cy_5_)) + (portref CI (instanceref f1_Mcount_rd_addr_xor_5_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB2") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[11]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_11__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata310)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB3") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB4") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename f0_rd_addr_1_ "f0/rd_addr[1]") (joined + (portref Q (instanceref f0_rd_addr_1)) + (portref I2 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref (member ADDRBRDADDR 11) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB5") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_5_ "f1/Mcount_rd_addr_cy[5]") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_5_)) + (portref CI (instanceref f1_Mcount_rd_addr_cy_6_)) + (portref CI (instanceref f1_Mcount_rd_addr_xor_6_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[12]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_12__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata410)) + ) + ) + (net (rename f0_rd_addr_2_ "f0/rd_addr[2]") (joined + (portref Q (instanceref f0_rd_addr_2)) + (portref I4 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref (member ADDRBRDADDR 10) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_6_ "f1/Mcount_rd_addr_cy[6]") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_6_)) + (portref CI (instanceref f1_Mcount_rd_addr_cy_7_)) + (portref CI (instanceref f1_Mcount_rd_addr_xor_7_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[13]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_13__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata510)) + ) + ) + (net (rename f0_rd_addr_3_ "f0/rd_addr[3]") (joined + (portref Q (instanceref f0_rd_addr_3)) + (portref I0 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref (member ADDRBRDADDR 9) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_7_ "f1/Mcount_rd_addr_cy[7]") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_7_)) + (portref CI (instanceref f1_Mcount_rd_addr_cy_8_)) + (portref CI (instanceref f1_Mcount_rd_addr_xor_8_)) + ) + ) + (net codec_enable (joined + (portref O (instanceref codec_enable_OBUF)) + (portref codec_enable) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[14]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_14__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata65)) + ) + ) + (net (rename f0_rd_addr_4_ "f0/rd_addr[4]") (joined + (portref Q (instanceref f0_rd_addr_4)) + (portref I2 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref (member ADDRBRDADDR 8) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tlast "slave_fifo32/fifo64_to_gpmc32_tx/o32_tlast") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_64__srlc32e)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW2)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state_glue_set)) + (portref (member DOBDO 15) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tvalid11)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_write1)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_8_ "f1/Mcount_rd_addr_cy[8]") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_8_)) + (portref CI (instanceref f1_Mcount_rd_addr_cy_9_)) + (portref CI (instanceref f1_Mcount_rd_addr_xor_9_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_20_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[20]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_20__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata131)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[15]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_15__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata71)) + ) + ) + (net (rename f1_dont_write_past_me_1__FRB "f1/dont_write_past_me<1>_FRB") (joined + (portref I3 (instanceref f1_Mcompar_becoming_full_lut_0_)) + (portref Q (instanceref f1_dont_write_past_me_1__FRB)) + ) + ) + (net (rename f0_rd_addr_5_ "f0/rd_addr[5]") (joined + (portref Q (instanceref f0_rd_addr_5)) + (portref I4 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref (member ADDRBRDADDR 7) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_9_ "f1/Mcount_rd_addr_cy[9]") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_9_)) + (portref CI (instanceref f1_Mcount_rd_addr_cy_10_)) + (portref CI (instanceref f1_Mcount_rd_addr_xor_10_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_21_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[21]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_21__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata141)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_16_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[16]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_16__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata81)) + ) + ) + (net (rename f0_rd_addr_6_ "f0/rd_addr[6]") (joined + (portref Q (instanceref f0_rd_addr_6)) + (portref I0 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref (member ADDRBRDADDR 6) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_0)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_2)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_3)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_4)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_22_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[22]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_22__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata151)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_17_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[17]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_17__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata91)) + ) + ) + (net (rename f0_Result_11_2_FRB "f0/Result<11>2_FRB") (joined + (portref D (instanceref f0_wr_addr_11)) + (portref Q (instanceref f0_Result_11_2_FRB)) + (portref I0 (instanceref f0_Mcount_wr_addr_cy_11__rt)) + ) + ) + (net (rename f0_rd_addr_7_ "f0/rd_addr[7]") (joined + (portref Q (instanceref f0_rd_addr_7)) + (portref I2 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref (member ADDRBRDADDR 5) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/full") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_111)) + (portref I0 (instanceref f1__n0161_inv1_lut)) + (portref I1 (instanceref f1_GND_14_o_read_OR_37_o1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_write1)) + (portref I1 (instanceref f1_read_state_FSM_FFd1_In111)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst)) + (portref I2 (instanceref f1_read_state_FSM_FFd2_In1)) + (portref I2 (instanceref f1_full_reg_glue_set)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_23_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[23]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_23__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata161)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_18_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[18]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_18__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata101)) + ) + ) + (net (rename f0_rd_addr_8_ "f0/rd_addr[8]") (joined + (portref Q (instanceref f0_rd_addr_8)) + (portref I4 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref (member ADDRBRDADDR 4) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[0]") (joined + (portref O (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref S (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_24_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[24]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_24__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata171)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_19_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[19]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_19__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata111)) + ) + ) + (net (rename f0_rd_addr_9_ "f0/rd_addr[9]") (joined + (portref Q (instanceref f0_rd_addr_9)) + (portref I0 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref (member ADDRBRDADDR 3) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[1]") (joined + (portref O (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref S (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_30_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[30]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_30__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata241)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_25_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[25]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_25__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata181)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[2]") (joined + (portref O (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref S (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_31_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[31]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_31__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata251)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_26_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[26]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_26__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata191)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[3]") (joined + (portref O (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref S (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_27_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[27]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_27__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata201)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_32_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[32]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata261)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr6_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_6)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr6_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__rt)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[4]") (joined + (portref O (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_)) + (portref S (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_)) + ) + ) + (net (rename f1_Result_7_2_FRB "f1/Result<7>2_FRB") (joined + (portref D (instanceref f1_wr_addr_7)) + (portref Q (instanceref f1_Result_7_2_FRB)) + (portref I0 (instanceref f1_Mcount_wr_addr_cy_7__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_33_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[33]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_33__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata271)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_28_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[28]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_28__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata211)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_i_tvalid_int "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/i_tvalid_int") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_write1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0154_inv1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[0]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_0)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_29_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[29]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_29__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata221)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_34_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[34]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_34__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata281)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[1]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_1)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_40_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[40]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_40__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata351)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_35_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[35]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata291)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_2__rt "f1/Mcount_rd_addr_cy<2>_rt") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_2__rt)) + (portref S (instanceref f1_Mcount_rd_addr_cy_2_)) + (portref LI (instanceref f1_Mcount_rd_addr_xor_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[2]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_2)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_1__rt "f1/Msub_dont_write_past_me_cy<1>_rt") (joined + (portref O (instanceref f1_Msub_dont_write_past_me_cy_1__rt)) + (portref S (instanceref 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(portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_37_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[37]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata311)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_42_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[42]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_42__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata371)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr6_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_6)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr6_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__rt)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/dump_glue_set") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[4]") (joined + (portref Q (instanceref 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"slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[43]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_43__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata381)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_10_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[10]") (joined + (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6)) + (portref (member dout 61) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f0_full_reg_glue_set "f0/full_reg_glue_set") (joined + (portref D (instanceref f0_full_reg)) + (portref O (instanceref f0_full_reg_glue_set)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_11_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_11_BRB1") (joined + (portref Q (instanceref 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"slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[39]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_39__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata331)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_44_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[44]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_44__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata391)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_11_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[11]") (joined + (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6)) + (portref (member dout 60) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename 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"slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[53]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata491)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_20_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[20]") (joined + (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11)) + (portref (member dout 51) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_15_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[15]") (joined + (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8)) + (portref (member dout 56) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename 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slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_5)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata311)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_29_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[29]") (joined + (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15)) + (portref (member dout 42) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[6]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_6)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata321)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_becoming_full "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/becoming_full") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_4_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg_glue_set)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<4>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[7]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_7)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata331)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[8]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_8)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata351)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[9]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_9)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata361)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_3_)) + ) + ) + (net (rename f1_write "f1/write") (joined + (portref CE (instanceref f1_wr_addr_1)) + (portref CE (instanceref f1_wr_addr_2)) + (portref CE (instanceref f1_wr_addr_3)) + (portref CE (instanceref f1_wr_addr_4)) + (portref CE (instanceref f1_wr_addr_5)) + (portref CE (instanceref f1_wr_addr_6)) + (portref CE (instanceref f1_wr_addr_7)) + (portref CE (instanceref f1_wr_addr_8)) + (portref CE (instanceref f1_wr_addr_9)) + (portref CE (instanceref f1_wr_addr_10)) + (portref CE (instanceref f1_wr_addr_11)) + (portref CE (instanceref f1_wr_addr_12)) + (portref CE (instanceref f1_wr_addr_0)) + (portref O (instanceref f1_write11)) + (portref CE (instanceref f1_Result_0_2_FRB)) + (portref CE (instanceref f1_Result_1_2_FRB)) + (portref CE (instanceref f1_Result_2_2_FRB)) + (portref CE (instanceref f1_Result_3_2_FRB)) + (portref CE (instanceref f1_Result_4_2_FRB)) + (portref CE (instanceref f1_Result_5_2_FRB)) + (portref CE (instanceref f1_Result_6_2_FRB)) + (portref CE (instanceref f1_Result_7_2_FRB)) + (portref CE (instanceref f1_Result_8_2_FRB)) + (portref CE (instanceref f1_Result_9_2_FRB)) + (portref CE (instanceref f1_Result_10_2_FRB)) + (portref CE (instanceref f1_Result_11_2_FRB)) + (portref CE (instanceref f1_Result_12_2_FRB)) + (portref (member WEAWEL 1) (instanceref f1_ram_Mram_ram33)) + (portref (member WEAWEL 0) (instanceref f1_ram_Mram_ram33)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram31)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram31)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram31)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram31)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram30)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram30)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram30)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram30)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram32)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram32)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram32)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram32)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram28)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram28)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram28)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram28)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram27)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram27)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram27)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram27)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram29)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram29)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram29)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram29)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram25)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram25)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram25)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram25)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram24)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram24)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram24)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram24)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram26)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram26)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram26)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram26)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram22)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram22)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram22)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram22)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram21)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram21)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram21)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram21)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram23)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram23)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram23)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram23)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram19)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram19)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram19)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram19)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram18)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram18)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram18)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram18)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram20)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram20)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram20)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram20)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram16)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram16)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram16)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram16)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram15)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram15)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram15)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram15)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram17)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram17)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram17)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram17)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram14)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram14)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram14)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram14)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram13)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram13)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram13)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram13)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram12)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram12)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram12)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram12)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram11)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram11)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram11)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram11)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram9)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram9)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram9)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram9)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram8)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram8)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram8)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram8)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram10)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram10)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram10)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram10)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram6)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram6)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram6)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram6)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram5)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram5)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram5)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram5)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram7)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram7)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram7)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram7)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram3)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram3)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram3)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram3)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram2)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram2)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram2)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram2)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram4)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram4)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram4)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram4)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram1)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram1)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram1)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/empty") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_write1)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_space_xor_3_111)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_glue_set)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_13_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_13_BRB1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_13_BRB1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_8__rt "f0/Mcount_rd_addr_cy<8>_rt") (joined + (portref O (instanceref f0_Mcount_rd_addr_cy_8__rt)) + (portref S (instanceref f0_Mcount_rd_addr_cy_8_)) + (portref LI (instanceref f0_Mcount_rd_addr_xor_8_)) + ) + ) + (net (rename f0_Result_0_2_FRB "f0/Result<0>2_FRB") (joined + (portref D (instanceref f0_wr_addr_0)) + (portref Q (instanceref f0_Result_0_2_FRB)) + (portref I0 (instanceref f0_Mcount_wr_addr_lut_0__INV_0)) + ) + ) + (net (rename f0_dont_write_past_me_3__FRB "f0/dont_write_past_me<3>_FRB") (joined + (portref I1 (instanceref f0_Mcompar_becoming_full_lut_1_)) + (portref Q (instanceref f0_dont_write_past_me_3__FRB)) + ) + ) + (net (rename f1_dont_write_past_me_5__FRB "f1/dont_write_past_me<5>_FRB") (joined + (portref I5 (instanceref f1_Mcompar_becoming_full_lut_1_)) + (portref Q (instanceref f1_dont_write_past_me_5__FRB)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_2_)) + ) + ) + (net (rename f0_GND_14_o_read_OR_37_o "f0/GND_14_o_read_OR_37_o") (joined + (portref O (instanceref f0_GND_14_o_read_OR_37_o1)) + (portref ENBRDEN (instanceref f0_ram_Mram_ram33)) + (portref ENB (instanceref f0_ram_Mram_ram31)) + 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+ ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr1") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_28_ "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding[28]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_28)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata571)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr2") (joined + (portref O (instanceref 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(instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_0_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_0)) + ) + ) + (net (rename f1_Mcount_wr_addr_lut_0_ "f1/Mcount_wr_addr_lut[0]") (joined + (portref S (instanceref f1_Mcount_wr_addr_cy_0_)) + (portref LI (instanceref f1_Mcount_wr_addr_xor_0_)) + (portref O (instanceref f1_Mcount_wr_addr_lut_0__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[2]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_2)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611)) + (portref I5 (instanceref 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(joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_3)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full621)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[4]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_4)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full621)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0076_inv") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In_bdd1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In_bdd1") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[5]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_5)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full621)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr5_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_5)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[6]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_6)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o61)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01219)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[7]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_7)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o71)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + ) + ) + (net rx_bandsel_c_OBUF (joined + (portref G (instanceref XST_GND)) + (portref D (instanceref bus_sync_reset_int)) + (portref D (instanceref gpif_sync_reset_int)) + (portref D1 (instanceref ODDR2_ifclk)) + (portref R (instanceref ODDR2_ifclk)) + (portref S (instanceref ODDR2_ifclk)) + (portref D1 (instanceref ODDR2_ifclk_dbg)) + (portref R (instanceref ODDR2_ifclk_dbg)) + (portref S (instanceref ODDR2_ifclk_dbg)) + (portref DSSEN (instanceref gen_clks_dcm_sp_inst)) + (portref PSCLK (instanceref gen_clks_dcm_sp_inst)) + (portref PSEN (instanceref gen_clks_dcm_sp_inst)) + (portref PSINCDEC (instanceref gen_clks_dcm_sp_inst)) + (portref D0 (instanceref catgen_gen_pins_0__oddr2)) + (portref D1 (instanceref catgen_gen_pins_0__oddr2)) + (portref R (instanceref catgen_gen_pins_0__oddr2)) + (portref S (instanceref catgen_gen_pins_0__oddr2)) + (portref D0 (instanceref catgen_gen_pins_1__oddr2)) + (portref D1 (instanceref catgen_gen_pins_1__oddr2)) + (portref R (instanceref catgen_gen_pins_1__oddr2)) + (portref S (instanceref catgen_gen_pins_1__oddr2)) + (portref D0 (instanceref catgen_gen_pins_2__oddr2)) + (portref D1 (instanceref catgen_gen_pins_2__oddr2)) + (portref R (instanceref catgen_gen_pins_2__oddr2)) + (portref S (instanceref catgen_gen_pins_2__oddr2)) + (portref D0 (instanceref catgen_gen_pins_3__oddr2)) + (portref D1 (instanceref catgen_gen_pins_3__oddr2)) + (portref R (instanceref catgen_gen_pins_3__oddr2)) + (portref S (instanceref catgen_gen_pins_3__oddr2)) + (portref D0 (instanceref catgen_gen_pins_4__oddr2)) + (portref D1 (instanceref catgen_gen_pins_4__oddr2)) + (portref R (instanceref catgen_gen_pins_4__oddr2)) + (portref S (instanceref catgen_gen_pins_4__oddr2)) + (portref D0 (instanceref catgen_gen_pins_5__oddr2)) + (portref D1 (instanceref catgen_gen_pins_5__oddr2)) + (portref R (instanceref catgen_gen_pins_5__oddr2)) + (portref S (instanceref catgen_gen_pins_5__oddr2)) + (portref D0 (instanceref catgen_gen_pins_6__oddr2)) + (portref D1 (instanceref catgen_gen_pins_6__oddr2)) + (portref R (instanceref catgen_gen_pins_6__oddr2)) + (portref S (instanceref catgen_gen_pins_6__oddr2)) + (portref D0 (instanceref catgen_gen_pins_7__oddr2)) + (portref D1 (instanceref catgen_gen_pins_7__oddr2)) + (portref R (instanceref catgen_gen_pins_7__oddr2)) + (portref S (instanceref catgen_gen_pins_7__oddr2)) + (portref D0 (instanceref catgen_gen_pins_8__oddr2)) + (portref D1 (instanceref catgen_gen_pins_8__oddr2)) + (portref R (instanceref catgen_gen_pins_8__oddr2)) + (portref S (instanceref catgen_gen_pins_8__oddr2)) + (portref D0 (instanceref catgen_gen_pins_9__oddr2)) + (portref D1 (instanceref catgen_gen_pins_9__oddr2)) + (portref R (instanceref catgen_gen_pins_9__oddr2)) + (portref S (instanceref catgen_gen_pins_9__oddr2)) + (portref D0 (instanceref catgen_gen_pins_10__oddr2)) + (portref D1 (instanceref catgen_gen_pins_10__oddr2)) + (portref R (instanceref catgen_gen_pins_10__oddr2)) + (portref S (instanceref catgen_gen_pins_10__oddr2)) + (portref D0 (instanceref catgen_gen_pins_11__oddr2)) + (portref D1 (instanceref catgen_gen_pins_11__oddr2)) + (portref R (instanceref catgen_gen_pins_11__oddr2)) + (portref S (instanceref catgen_gen_pins_11__oddr2)) + (portref D0 (instanceref catgen_oddr2_frame)) + (portref D1 (instanceref catgen_oddr2_frame)) + (portref R (instanceref catgen_oddr2_frame)) + (portref S (instanceref catgen_oddr2_frame)) + (portref D1 (instanceref catgen_oddr2_clk)) + (portref R (instanceref catgen_oddr2_clk)) + (portref S (instanceref catgen_oddr2_clk)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_11_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_9_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_0_)) + (portref DI (instanceref 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slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref REGCEBREGCE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref RSTBRST (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member WEBWEU 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member WEBWEU 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member DIPA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member DIPA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member DIPA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member DIPB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member DIPB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member DIPB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member DIA 16) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member DIB 16) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member DIPA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member DIPA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member DIPB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member DIPB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref REGCEA (instanceref f1_ram_Mram_ram33)) + (portref REGCEBREGCE (instanceref f1_ram_Mram_ram33)) + (portref RSTA (instanceref f1_ram_Mram_ram33)) + (portref RSTBRST (instanceref f1_ram_Mram_ram33)) + (portref (member WEBWEU 1) (instanceref f1_ram_Mram_ram33)) + (portref (member WEBWEU 0) (instanceref f1_ram_Mram_ram33)) + (portref REGCEA (instanceref f1_ram_Mram_ram31)) + (portref REGCEB (instanceref f1_ram_Mram_ram31)) + (portref RSTA (instanceref f1_ram_Mram_ram31)) + (portref RSTB (instanceref f1_ram_Mram_ram31)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram31)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram31)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram31)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram31)) + (portref REGCEA (instanceref f1_ram_Mram_ram30)) + (portref REGCEB (instanceref f1_ram_Mram_ram30)) + (portref RSTA (instanceref f1_ram_Mram_ram30)) + (portref RSTB (instanceref f1_ram_Mram_ram30)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram30)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram30)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram30)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram30)) + (portref REGCEA (instanceref f1_ram_Mram_ram32)) + (portref REGCEB (instanceref f1_ram_Mram_ram32)) + (portref RSTA (instanceref f1_ram_Mram_ram32)) + (portref RSTB (instanceref f1_ram_Mram_ram32)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram32)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram32)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram32)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram32)) + (portref REGCEA (instanceref f1_ram_Mram_ram28)) + (portref REGCEB (instanceref f1_ram_Mram_ram28)) + (portref RSTA (instanceref f1_ram_Mram_ram28)) + (portref RSTB (instanceref f1_ram_Mram_ram28)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram28)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram28)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram28)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram28)) + (portref REGCEA (instanceref f1_ram_Mram_ram27)) + (portref REGCEB (instanceref f1_ram_Mram_ram27)) + (portref RSTA (instanceref f1_ram_Mram_ram27)) + (portref RSTB (instanceref f1_ram_Mram_ram27)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram27)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram27)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram27)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram27)) + (portref REGCEA (instanceref f1_ram_Mram_ram29)) + (portref REGCEB (instanceref f1_ram_Mram_ram29)) + (portref RSTA (instanceref f1_ram_Mram_ram29)) + (portref RSTB (instanceref f1_ram_Mram_ram29)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram29)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram29)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram29)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram29)) + (portref REGCEA (instanceref f1_ram_Mram_ram25)) + (portref REGCEB (instanceref f1_ram_Mram_ram25)) + (portref RSTA (instanceref f1_ram_Mram_ram25)) + (portref RSTB (instanceref f1_ram_Mram_ram25)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram25)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram25)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram25)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram25)) + (portref REGCEA (instanceref f1_ram_Mram_ram24)) + (portref REGCEB (instanceref f1_ram_Mram_ram24)) + (portref RSTA (instanceref f1_ram_Mram_ram24)) + (portref RSTB (instanceref f1_ram_Mram_ram24)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram24)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram24)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram24)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram24)) + (portref REGCEA (instanceref f1_ram_Mram_ram26)) + (portref REGCEB (instanceref f1_ram_Mram_ram26)) + (portref RSTA (instanceref f1_ram_Mram_ram26)) + (portref RSTB (instanceref f1_ram_Mram_ram26)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram26)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram26)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram26)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram26)) + (portref REGCEA (instanceref f1_ram_Mram_ram22)) + (portref REGCEB (instanceref f1_ram_Mram_ram22)) + (portref RSTA (instanceref f1_ram_Mram_ram22)) + (portref RSTB (instanceref f1_ram_Mram_ram22)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram22)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram22)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram22)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram22)) + (portref REGCEA (instanceref f1_ram_Mram_ram21)) + (portref REGCEB (instanceref f1_ram_Mram_ram21)) + (portref RSTA (instanceref f1_ram_Mram_ram21)) + (portref RSTB (instanceref f1_ram_Mram_ram21)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram21)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram21)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram21)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram21)) + (portref REGCEA (instanceref f1_ram_Mram_ram23)) + (portref REGCEB (instanceref f1_ram_Mram_ram23)) + (portref RSTA (instanceref f1_ram_Mram_ram23)) + (portref RSTB (instanceref f1_ram_Mram_ram23)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram23)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram23)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram23)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram23)) + (portref REGCEA (instanceref f1_ram_Mram_ram19)) + (portref REGCEB (instanceref f1_ram_Mram_ram19)) + (portref RSTA (instanceref f1_ram_Mram_ram19)) + (portref RSTB (instanceref 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f1_ram_Mram_ram20)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram20)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram20)) + (portref REGCEA (instanceref f1_ram_Mram_ram16)) + (portref REGCEB (instanceref f1_ram_Mram_ram16)) + (portref RSTA (instanceref f1_ram_Mram_ram16)) + (portref RSTB (instanceref f1_ram_Mram_ram16)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram16)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram16)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram16)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram16)) + (portref REGCEA (instanceref f1_ram_Mram_ram15)) + (portref REGCEB (instanceref f1_ram_Mram_ram15)) + (portref RSTA (instanceref f1_ram_Mram_ram15)) + (portref RSTB (instanceref f1_ram_Mram_ram15)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram15)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram15)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram15)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram15)) + (portref REGCEA (instanceref f1_ram_Mram_ram17)) + (portref REGCEB (instanceref f1_ram_Mram_ram17)) + (portref RSTA (instanceref f1_ram_Mram_ram17)) + (portref RSTB (instanceref f1_ram_Mram_ram17)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram17)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram17)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram17)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram17)) + (portref REGCEA (instanceref f1_ram_Mram_ram14)) + (portref REGCEB (instanceref f1_ram_Mram_ram14)) + (portref RSTA (instanceref f1_ram_Mram_ram14)) + (portref RSTB (instanceref f1_ram_Mram_ram14)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram14)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram14)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram14)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram14)) + (portref REGCEA (instanceref f1_ram_Mram_ram13)) + (portref REGCEB (instanceref f1_ram_Mram_ram13)) + (portref RSTA (instanceref f1_ram_Mram_ram13)) + (portref RSTB (instanceref f1_ram_Mram_ram13)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram13)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram13)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram13)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram13)) + (portref REGCEA (instanceref f1_ram_Mram_ram12)) + (portref REGCEB (instanceref f1_ram_Mram_ram12)) + (portref RSTA (instanceref f1_ram_Mram_ram12)) + (portref RSTB (instanceref f1_ram_Mram_ram12)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram12)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram12)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram12)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram12)) + (portref REGCEA (instanceref f1_ram_Mram_ram11)) + (portref REGCEB (instanceref f1_ram_Mram_ram11)) + (portref RSTA (instanceref f1_ram_Mram_ram11)) + (portref RSTB (instanceref f1_ram_Mram_ram11)) + (portref (member WEB 3) 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(portref REGCEB (instanceref f1_ram_Mram_ram5)) + (portref RSTA (instanceref f1_ram_Mram_ram5)) + (portref RSTB (instanceref f1_ram_Mram_ram5)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram5)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram5)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram5)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram5)) + (portref REGCEA (instanceref f1_ram_Mram_ram7)) + (portref REGCEB (instanceref f1_ram_Mram_ram7)) + (portref RSTA (instanceref f1_ram_Mram_ram7)) + (portref RSTB (instanceref f1_ram_Mram_ram7)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram7)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram7)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram7)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram7)) + (portref REGCEA (instanceref f1_ram_Mram_ram3)) + (portref REGCEB (instanceref f1_ram_Mram_ram3)) + (portref RSTA (instanceref f1_ram_Mram_ram3)) + (portref RSTB (instanceref f1_ram_Mram_ram3)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram3)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram3)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram3)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram3)) + (portref REGCEA (instanceref f1_ram_Mram_ram2)) + (portref REGCEB (instanceref f1_ram_Mram_ram2)) + (portref RSTA (instanceref f1_ram_Mram_ram2)) + (portref RSTB (instanceref f1_ram_Mram_ram2)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram2)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram2)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram2)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram2)) + (portref REGCEA (instanceref f1_ram_Mram_ram4)) + (portref REGCEB (instanceref f1_ram_Mram_ram4)) + (portref RSTA (instanceref f1_ram_Mram_ram4)) + (portref RSTB (instanceref f1_ram_Mram_ram4)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram4)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram4)) + (portref (member WEB 1) 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slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + (portref (member din 36) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + (portref (member din 37) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + (portref (member din 38) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full61 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full61") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01219)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full62 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full62") (joined + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01219)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full621)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[8]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_8)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o81)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + ) + ) + (net fx3_miso_OBUF (joined + (portref O (instanceref fx3_miso1)) + (portref I (instanceref fx3_miso_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW1)) + (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + ) + ) + (net (rename f0_dont_write_past_me_7__FRB "f0/dont_write_past_me<7>_FRB") (joined + (portref I3 (instanceref f0_Mcompar_becoming_full_lut_2_)) + (portref Q (instanceref f0_dont_write_past_me_7__FRB)) + ) + ) + (net (rename f1_dont_write_past_me_9__FRB "f1/dont_write_past_me<9>_FRB") (joined + (portref I1 (instanceref f1_Mcompar_becoming_full_lut_3_)) + (portref Q (instanceref f1_dont_write_past_me_9__FRB)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0146_inv") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_0)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_2)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_3)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_4)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_5)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_6)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_7)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_8)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0_FRB)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines3210 "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines3210") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_10_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_10)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines3211 "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines3211") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_11_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines3212 "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines3212") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_12_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_12)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines3213 "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines3213") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_13_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_13)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines3214 "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines3214") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_14_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_14)) + ) + ) + (net (rename slave_fifo32_wr_one "slave_fifo32/wr_one") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1_SW0)) + (portref Q (instanceref slave_fifo32_wr_one)) + (portref I0 (instanceref slave_fifo32_wr_one_rstpot)) + (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines3215 "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines3215") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_15_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_15)) + ) + ) + (net (rename slave_fifo32_sloe_1 "slave_fifo32/sloe_1") (joined + (portref I (instanceref GPIF_CTL2_OBUF)) + (portref Q (instanceref slave_fifo32_sloe_1)) + ) + ) + (net (rename slave_fifo32_sloe_2 "slave_fifo32/sloe_2") (joined + (portref Q (instanceref slave_fifo32_sloe_2)) + (portref T (instanceref GPIF_D_0_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_3 "slave_fifo32/sloe_3") (joined + (portref Q (instanceref slave_fifo32_sloe_3)) + (portref T (instanceref GPIF_D_1_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_4 "slave_fifo32/sloe_4") (joined + (portref Q (instanceref slave_fifo32_sloe_4)) + (portref T (instanceref GPIF_D_2_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_5 "slave_fifo32/sloe_5") (joined + (portref Q (instanceref slave_fifo32_sloe_5)) + (portref T (instanceref GPIF_D_3_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_6 "slave_fifo32/sloe_6") (joined + (portref Q (instanceref slave_fifo32_sloe_6)) + (portref T (instanceref GPIF_D_4_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_7 "slave_fifo32/sloe_7") (joined + (portref Q (instanceref slave_fifo32_sloe_7)) + (portref T (instanceref GPIF_D_5_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_8 "slave_fifo32/sloe_8") (joined + (portref Q (instanceref slave_fifo32_sloe_8)) + (portref T (instanceref GPIF_D_6_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_9 "slave_fifo32/sloe_9") (joined + (portref Q (instanceref slave_fifo32_sloe_9)) + (portref T (instanceref GPIF_D_7_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_empty "slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/empty") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_read1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker__n0227_inv1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In12_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int11)) + (portref empty (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename GPIF_D_10_ "GPIF_D[10]") (joined + (portref IO (instanceref GPIF_D_10_IOBUF)) + (portref (member GPIF_D 21)) + ) + ) + (net (rename GPIF_D_11_ "GPIF_D[11]") (joined + (portref IO (instanceref GPIF_D_11_IOBUF)) + (portref (member GPIF_D 20)) + ) + ) + (net pll_ce (joined + (portref O (instanceref pll_ce_OBUF)) + (portref pll_ce) + ) + ) + (net (rename GPIF_D_12_ "GPIF_D[12]") (joined + (portref IO (instanceref GPIF_D_12_IOBUF)) + (portref (member GPIF_D 19)) + ) + ) + (net (rename GPIF_D_13_ "GPIF_D[13]") (joined + (portref IO (instanceref GPIF_D_13_IOBUF)) + (portref (member GPIF_D 18)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full102 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full102") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full1021)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10)) + ) + ) + (net (rename GPIF_D_14_ "GPIF_D[14]") (joined + (portref IO (instanceref GPIF_D_14_IOBUF)) + (portref (member GPIF_D 17)) + ) + ) + (net N10 (joined + (portref O (instanceref slave_fifo32__n0279_inv_SW0)) + (portref I3 (instanceref slave_fifo32__n0279_inv)) + ) + ) + (net (rename GPIF_D_20_ "GPIF_D[20]") (joined + (portref IO (instanceref GPIF_D_20_IOBUF)) + (portref (member GPIF_D 11)) + ) + ) + (net (rename GPIF_D_15_ "GPIF_D[15]") (joined + (portref IO (instanceref GPIF_D_15_IOBUF)) + (portref (member GPIF_D 16)) + ) + ) + (net N14 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv)) + ) + ) + (net cat_miso (joined + (portref I (instanceref cat_miso_IBUF)) + (portref cat_miso) + ) + ) + (net N22 (joined + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0)) + ) + ) + (net N18 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv)) + ) + ) + (net (rename GPIF_D_21_ "GPIF_D[21]") (joined + (portref IO (instanceref GPIF_D_21_IOBUF)) + (portref (member GPIF_D 10)) + ) + ) + (net (rename GPIF_D_16_ "GPIF_D[16]") (joined + (portref IO (instanceref GPIF_D_16_IOBUF)) + (portref (member GPIF_D 15)) + ) + ) + (net N24 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1)) + ) + ) + (net LED_RX1 (joined + (portref O (instanceref LED_RX1_OBUF)) + (portref LED_RX1) + ) + ) + (net N30 (joined + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0)) + ) + ) + (net LED_RX2 (joined + (portref O (instanceref LED_RX2_OBUF)) + (portref LED_RX2) + ) + ) + (net N26 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1)) + ) + ) + (net (rename GPIF_D_22_ "GPIF_D[22]") (joined + (portref IO (instanceref GPIF_D_22_IOBUF)) + (portref (member GPIF_D 9)) + ) + ) + (net (rename GPIF_D_17_ "GPIF_D[17]") (joined + (portref IO (instanceref GPIF_D_17_IOBUF)) + (portref (member GPIF_D 14)) + ) + ) + (net N34 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr5_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_5)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr5_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_5__rt)) + ) + ) + (net N40 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set)) + ) + ) + (net N42 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv)) + ) + ) + (net N38 (joined + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW0)) + ) + ) + (net (rename GPIF_D_23_ "GPIF_D[23]") (joined + (portref IO (instanceref GPIF_D_23_IOBUF)) + (portref (member GPIF_D 8)) + ) + ) + (net (rename GPIF_D_18_ "GPIF_D[18]") (joined + (portref IO (instanceref GPIF_D_18_IOBUF)) + (portref (member GPIF_D 13)) + ) + ) + (net N50 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_cy)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3)) + ) + ) + (net N52 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1)) + ) + ) + (net (rename GPIF_D_24_ "GPIF_D[24]") (joined + (portref IO (instanceref GPIF_D_24_IOBUF)) + (portref (member GPIF_D 7)) + ) + ) + (net (rename GPIF_D_19_ "GPIF_D[19]") (joined + (portref IO (instanceref GPIF_D_19_IOBUF)) + (portref (member GPIF_D 12)) + ) + ) + (net N54 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o)) + ) + ) + (net N60 (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0)) + ) + ) + (net N56 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv)) + ) + ) + (net N62 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror11)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast1)) + ) + ) + (net N58 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_4__rt "f0/Mcount_wr_addr_cy<4>_rt") (joined + (portref O (instanceref f0_Mcount_wr_addr_cy_4__rt)) + (portref S (instanceref f0_Mcount_wr_addr_cy_4_)) + (portref LI (instanceref f0_Mcount_wr_addr_xor_4_)) + ) + ) + (net (rename GPIF_D_30_ "GPIF_D[30]") (joined + (portref IO (instanceref GPIF_D_30_IOBUF)) + (portref (member GPIF_D 1)) + ) + ) + (net (rename GPIF_D_25_ "GPIF_D[25]") (joined + (portref IO (instanceref GPIF_D_25_IOBUF)) + (portref (member GPIF_D 6)) + ) + ) + (net N64 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set)) + ) + ) + (net N66 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv)) + ) + ) + (net (rename f0_dont_write_past_me_9__FRB "f0/dont_write_past_me<9>_FRB") (joined + (portref I1 (instanceref f0_Mcompar_becoming_full_lut_3_)) + (portref Q (instanceref f0_dont_write_past_me_9__FRB)) + ) + ) + (net (rename GPIF_D_31_ "GPIF_D[31]") (joined + (portref IO (instanceref GPIF_D_31_IOBUF)) + (portref (member GPIF_D 0)) + ) + ) + (net (rename GPIF_D_26_ "GPIF_D[26]") (joined + (portref IO (instanceref GPIF_D_26_IOBUF)) + (portref (member GPIF_D 5)) + ) + ) + (net (rename f1_read_state_FSM_FFd1 "f1/read_state_FSM_FFd1") (joined + (portref Q (instanceref f1_read_state_FSM_FFd1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_111)) + (portref I1 (instanceref f1__n0161_inv1_lut)) + (portref I1 (instanceref f1__n0161_inv1_lut1)) + (portref I0 (instanceref f1_GND_14_o_read_OR_37_o1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_write1)) + (portref I0 (instanceref f1_read_state_FSM_FFd1_In111)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst)) + (portref I0 (instanceref f1_read_state_FSM_FFd2_In1)) + (portref I3 (instanceref f1_full_reg_glue_set)) + ) + ) + (net N80 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o)) + ) + ) + (net (rename f1_read_state_FSM_FFd2 "f1/read_state_FSM_FFd2") (joined + (portref Q (instanceref f1_read_state_FSM_FFd2)) + (portref I0 (instanceref f1__n0161_inv1_lut1)) + (portref I2 (instanceref f1_GND_14_o_read_OR_37_o1)) + (portref I3 (instanceref f1_read_state_FSM_FFd1_In111)) + (portref I5 (instanceref f1_read_state_FSM_FFd2_In1)) + ) + ) + (net N76 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3)) + ) + ) + (net N82 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv)) + ) + ) + (net N78 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1)) + ) + ) + (net (rename GPIF_D_27_ "GPIF_D[27]") (joined + (portref IO (instanceref GPIF_D_27_IOBUF)) + (portref (member GPIF_D 4)) + ) + ) + (net N84 (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + ) + ) + (net N90 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + ) + ) + (net N86 (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0)) + ) + ) + (net debug_clk_1_OBUF (joined + (portref Q (instanceref ODDR2_ifclk_dbg)) + (portref I (instanceref debug_clk_1_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_1_)) + ) + ) + (net N88 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61)) + ) + ) + (net (rename GPIF_D_28_ "GPIF_D[28]") (joined + (portref IO (instanceref GPIF_D_28_IOBUF)) + (portref (member GPIF_D 3)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012111 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012111") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0121111)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012114)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01217)) + ) + ) + (net N96 (joined + (portref D (instanceref slave_fifo32_gpif_data_in_31)) + (portref O (instanceref GPIF_D_31_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr3_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_3)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr3_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__rt)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_3__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012112 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012112") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012114)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012111)) + ) + ) + (net N97 (joined + (portref D (instanceref slave_fifo32_gpif_data_in_30)) + (portref O (instanceref GPIF_D_30_IOBUF)) + ) + ) + (net locked (joined + (portref LOCKED (instanceref gen_clks_dcm_sp_inst)) + (portref D (instanceref slave_fifo32_debug1_21)) + (portref I0 (instanceref reset_global_locked_OR_1_o1)) + (portref I1 (instanceref slave_fifo32__n0230_inv1)) + (portref I0 (instanceref slave_fifo32__n0223_inv1)) + (portref I5 (instanceref slave_fifo32__n0237_inv1)) + (portref I0 (instanceref slave_fifo32__n0290_inv1)) + (portref I0 (instanceref slave_fifo32__n0279_inv)) + (portref I1 (instanceref slave_fifo32_state_FSM_FFd2_In1)) + (portref I1 (instanceref slave_fifo32_wr_one_rstpot)) + (portref I2 (instanceref slave_fifo32_slrd_rstpot)) + (portref I3 (instanceref slave_fifo32_sloe_1_rstpot)) + (portref I1 (instanceref slave_fifo32_state_FSM_FFd1_In3_F)) + (portref I5 (instanceref slave_fifo32_state_FSM_FFd1_In3_G)) + (portref I0 (instanceref slave_fifo32_state_FSM_FFd2_In3)) + ) + ) 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"GPIF_D[29]") (joined + (portref IO (instanceref GPIF_D_29_IOBUF)) + (portref (member GPIF_D 2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012114 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012114") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012113)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012114)) + ) + ) + (net N99 (joined + (portref D (instanceref slave_fifo32_gpif_data_in_28)) + (portref O (instanceref GPIF_D_28_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3_)) + (portref CI (instanceref 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f0_Mcount_rd_addr_cy_4__rt)) + (portref I0 (instanceref f0_Msub_dont_write_past_me_lut_4__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr4_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_4)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr4_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr10 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr10") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_10_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_10)) + ) + ) + (net (rename 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"slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[1]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[2]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_2)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr8_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr8_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_8__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[3]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_3)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_0__inv "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state<0>_inv") (joined + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_0_)) + (portref CI (instanceref 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slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv4") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot)) + ) + ) + (net (rename slave_fifo32_EP_WMARK1_1 "slave_fifo32/EP_WMARK1_1") (joined + (portref Q (instanceref slave_fifo32_EP_WMARK1_1)) + (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1_SW0)) + (portref I5 (instanceref slave_fifo32_slrd_rstpot)) + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[5]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_5)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[6]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_6)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + ) + ) + (net cat_mosi (joined + (portref O (instanceref cat_mosi_OBUF)) + (portref cat_mosi) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[7]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + ) + ) + (net fx3_mosi_IBUF (joined + (portref I1 (instanceref cat_mosi1)) + (portref O (instanceref fx3_mosi_IBUF)) + ) + ) + (net (rename slave_fifo32_rd_one "slave_fifo32/rd_one") (joined + (portref D (instanceref slave_fifo32_rd_one_BRB1)) + (portref O (instanceref slave_fifo32_rd_one_rstpot)) + ) + ) + (net (rename slave_fifo32_sloe_rstpot "slave_fifo32/sloe_rstpot") (joined + (portref O (instanceref slave_fifo32_sloe_rstpot)) + (portref D (instanceref slave_fifo32_sloe)) + (portref D (instanceref slave_fifo32_sloe_33)) + (portref D (instanceref slave_fifo32_sloe_32)) + (portref D (instanceref slave_fifo32_sloe_31)) + (portref D (instanceref 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slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<8>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_8__rt)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/full_glue_set") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_3__rt "f1/Mcount_rd_addr_cy<3>_rt") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_3__rt)) + (portref S (instanceref f1_Mcount_rd_addr_cy_3_)) + (portref LI (instanceref f1_Mcount_rd_addr_xor_3_)) + ) + ) + (net (rename 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(instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_16)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_17)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_18)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_19)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_20)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_21)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_22)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_23)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_24)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_25)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_26)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_27)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_28)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_29)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_30)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_31)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_i_tvalid_o_tready_AND_73_o1)) + ) + ) + (net (rename slave_fifo32_debug1_17_BRB0 "slave_fifo32/debug1_17_BRB0") (joined + (portref Q (instanceref slave_fifo32_debug1_17_BRB0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_o_tvalid1_INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_chk_tready "slave_fifo32/fifo64_to_gpmc32_ctrl/chk_tready") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_read1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker__n0227_inv1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In12_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[0]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[1]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[2]") (joined + (portref S (instanceref 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slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB3") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB3)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB4") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB4)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_3_ "f0/Mcount_rd_addr_cy[3]") (joined + (portref O (instanceref f0_Mcount_rd_addr_cy_3_)) + (portref CI (instanceref f0_Mcount_rd_addr_cy_4_)) + (portref CI (instanceref f0_Mcount_rd_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[6]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_10_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[10]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_10__srlc32e)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata210)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_4_ "f0/Mcount_rd_addr_cy[4]") (joined + (portref O (instanceref f0_Mcount_rd_addr_cy_4_)) + (portref CI (instanceref f0_Mcount_rd_addr_cy_5_)) + (portref CI (instanceref f0_Mcount_rd_addr_xor_5_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[7]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7_)) + (portref O (instanceref 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(portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_F)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_G)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_F)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_0__inv1_INV_0)) + ) + ) + (net (rename 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(rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_13_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut[13]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_13_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_13_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_13_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut[4]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_4_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_4_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_4__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_64_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[64]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_64__srlc32e)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_o_tlast1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_59_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[59]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_59__srlc32e)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata201)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_write1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0154_inv1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_9_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_14_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut[14]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_14_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_14_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_14_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut[5]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_5_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_5_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_5__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<2>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_2__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_2_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_10_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_10_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_15_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut[15]") (joined + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_15_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_15_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut[6]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_6_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_6_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_6__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut[7]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_7_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_7_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_7__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut[8]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_8_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_8_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_8__INV_0)) + ) + ) + (net tx_bandsel_a (joined + (portref O (instanceref tx_bandsel_a_OBUF)) + (portref tx_bandsel_a) + ) + ) + (net tx_bandsel_b (joined + (portref O (instanceref tx_bandsel_b_OBUF)) + (portref tx_bandsel_b) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut[9]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_9_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_9__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_4_)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_10__rt "f1/Mcount_rd_addr_cy<10>_rt") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_10__rt)) + (portref S (instanceref f1_Mcount_rd_addr_cy_10_)) + (portref LI (instanceref f1_Mcount_rd_addr_xor_10_)) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[0]") (joined + (portref O (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_)) + (portref CI (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_)) + ) + ) + (net GPIF_CTL0 (joined + (portref O (instanceref GPIF_CTL0_OBUF)) + (portref GPIF_CTL0) + ) + ) + (net GPIF_CTL1 (joined + (portref O (instanceref GPIF_CTL1_OBUF)) + (portref GPIF_CTL1) + ) + ) + (net GPIF_CTL2 (joined + (portref O (instanceref GPIF_CTL2_OBUF)) + (portref GPIF_CTL2) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[1]") (joined + (portref O (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_)) + (portref CI (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_)) + ) + ) + (net GPIF_CTL3 (joined + (portref O (instanceref GPIF_CTL3_OBUF)) + (portref GPIF_CTL3) + ) + ) + (net GPIF_CTL4 (joined + (portref I (instanceref GPIF_CTL4_IBUF)) + (portref GPIF_CTL4) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/clear_inv") (joined + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1)) + ) + ) + (net GPIF_CTL5 (joined + (portref I (instanceref GPIF_CTL5_IBUF)) + (portref GPIF_CTL5) + ) + ) + (net GPIF_CTL7 (joined + (portref O (instanceref GPIF_CTL7_OBUF)) + (portref GPIF_CTL7) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[2]") (joined + (portref O (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_)) + (portref CI (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_0_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[0]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT110)) + (portref D (instanceref slave_fifo32_gpif_data_out_0)) + ) + ) + (net GPIF_CTL9 (joined + (portref I (instanceref GPIF_CTL9_IBUF)) + (portref GPIF_CTL9) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[3]") (joined + (portref O (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_)) + (portref CI (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_1_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[1]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT121)) + (portref D (instanceref slave_fifo32_gpif_data_out_1)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_2_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[2]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT231)) + (portref D (instanceref slave_fifo32_gpif_data_out_2)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_3_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[3]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT261)) + (portref D (instanceref slave_fifo32_gpif_data_out_3)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_4_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[4]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT271)) + (portref D (instanceref slave_fifo32_gpif_data_out_4)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_GND_66_o_read_OR_144_o "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/GND_66_o_read_OR_144_o") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_GND_66_o_read_OR_144_o1)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_5_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[5]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT281)) + (portref D (instanceref slave_fifo32_gpif_data_out_5)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_6_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[6]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT291)) + (portref D (instanceref slave_fifo32_gpif_data_out_6)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_7_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[7]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT301)) + (portref D (instanceref slave_fifo32_gpif_data_out_7)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[10]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_10_)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3_)) + ) + ) + (net (rename n0035_10_ "n0035[10]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_10__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/_n0074_inv") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_0)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_2)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_3)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_4)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_5)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_6)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[0]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0__rt)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member ADDRBRDADDR 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_8_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[8]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT311)) + (portref D (instanceref slave_fifo32_gpif_data_out_8)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[11]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_11_)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3_)) + ) + ) + (net (rename n0035_11_ "n0035[11]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_11__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram6)) + ) + ) + (net pll_sclk (joined + (portref O (instanceref pll_sclk_OBUF)) + (portref pll_sclk) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[1]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1__rt)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member ADDRBRDADDR 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_9_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[9]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT321)) + (portref D (instanceref slave_fifo32_gpif_data_out_9)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[12]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_12_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_4_)) + ) + ) + (net (rename n0035_12_ "n0035[12]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_12__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram7)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[2]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_2)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref (member ADDRBRDADDR 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_2__INV_0)) + ) + ) + (net (rename n0035_13_ "n0035[13]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_13__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram7)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr6_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_6)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[3]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_3)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref (member ADDRBRDADDR 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_3__INV_0)) + ) + ) + (net (rename n0035_14_ "n0035[14]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_14__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram8)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2-In") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In13)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[4]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_4)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref (member ADDRBRDADDR 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_4__INV_0)) + ) + ) + (net (rename n0035_20_ "n0035[20]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_20__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram11)) + ) + ) + (net (rename n0035_15_ "n0035[15]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_15__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram8)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_5_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[5]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_5)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref (member ADDRBRDADDR 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_5__INV_0)) + ) + ) + (net (rename n0035_21_ "n0035[21]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_21__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram11)) + ) + ) + (net (rename n0035_16_ "n0035[16]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_16__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram9)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr1_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_1)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr1_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[10]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_10_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_11_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_11_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_6_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[6]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_6)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref (member ADDRBRDADDR 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_6__INV_0)) + ) + ) + (net (rename n0035_22_ "n0035[22]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_22__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram12)) + ) + ) + (net (rename n0035_17_ "n0035[17]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_17__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram9)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_7_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[7]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_7)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref (member ADDRBRDADDR 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_7__INV_0)) + ) + ) + (net (rename n0035_23_ "n0035[23]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_23__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram12)) + ) + ) + (net (rename n0035_18_ "n0035[18]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_18__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram10)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[8]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_8)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref (member ADDRBRDADDR 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_8__INV_0)) + ) + ) + (net (rename n0035_19_ "n0035[19]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_19__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram10)) + ) + ) + (net (rename n0035_24_ "n0035[24]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_24__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram13)) + ) + ) + (net cat_sclk (joined + (portref O (instanceref cat_sclk_OBUF)) + (portref cat_sclk) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[9]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_9)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref (member ADDRBRDADDR 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_9__INV_0)) + ) + ) + (net (rename n0035_25_ "n0035[25]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_25__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram13)) + ) + ) + (net (rename n0035_30_ "n0035[30]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_30__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram16)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_10_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_10_)) + ) + ) + (net (rename n0035_26_ "n0035[26]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_26__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram14)) + ) + ) + (net (rename n0035_31_ "n0035[31]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_31__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram16)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/_n0146_inv") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_0)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_2)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_3)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_4)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_5)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_6)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_7)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_8)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_9)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_10)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_11)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_12)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_10__rt "f1/Mcount_wr_addr_cy<10>_rt") (joined + (portref O (instanceref f1_Mcount_wr_addr_cy_10__rt)) + (portref S (instanceref f1_Mcount_wr_addr_cy_10_)) + (portref LI (instanceref f1_Mcount_wr_addr_xor_10_)) + ) + ) + (net (rename n0035_27_ "n0035[27]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_27__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram14)) + ) + ) + (net (rename n0035_32_ "n0035[32]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_32__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram17)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_GND_66_o_read_OR_144_o1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_G)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tvalid11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0146_inv1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_GND_66_o_read_OR_144_o1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0146_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<0>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_0_)) + ) + ) + (net (rename n0035_28_ "n0035[28]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_28__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram15)) + ) + ) + (net (rename n0035_33_ "n0035[33]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_33__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram17)) + ) + ) + (net (rename n0035_29_ "n0035[29]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_29__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram15)) + ) + ) + (net (rename n0035_34_ "n0035[34]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_34__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram18)) + ) + ) + (net (rename f0_Result_6_1_FRB "f0/Result<6>1_FRB") (joined + (portref D (instanceref f0_rd_addr_6)) + (portref Q (instanceref f0_Result_6_1_FRB)) + (portref I0 (instanceref f0_Mcount_rd_addr_cy_6__rt)) + (portref I0 (instanceref f0_Msub_dont_write_past_me_lut_6__INV_0)) + ) + ) + (net (rename n0035_35_ "n0035[35]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_35__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram18)) + ) + ) + (net (rename n0035_40_ "n0035[40]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_40__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram21)) + ) + ) + (net (rename f0_Mcount_wr_addr_lut_0_ "f0/Mcount_wr_addr_lut[0]") (joined + (portref S (instanceref f0_Mcount_wr_addr_cy_0_)) + (portref LI (instanceref f0_Mcount_wr_addr_xor_0_)) + (portref O (instanceref f0_Mcount_wr_addr_lut_0__INV_0)) + ) + ) + (net (rename n0035_36_ "n0035[36]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_36__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram19)) + ) + ) + (net (rename n0035_41_ "n0035[41]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_41__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram21)) + ) + ) + (net (rename n0035_37_ "n0035[37]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_37__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram19)) + ) + ) + (net (rename n0035_42_ "n0035[42]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_42__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram22)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_tlast") (joined + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set)) + (portref (member DIADI 15) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW0)) + ) + ) + (net ext_ref_enable (joined + (portref O (instanceref ext_ref_enable_OBUF)) + (portref ext_ref_enable) + ) + ) + (net (rename f1_Mcount_rd_addr_lut_0_ "f1/Mcount_rd_addr_lut[0]") (joined + (portref S (instanceref f1_Mcount_rd_addr_cy_0_)) + (portref LI (instanceref f1_Mcount_rd_addr_xor_0_)) + (portref O (instanceref f1_Mcount_rd_addr_lut_0__INV_0)) + ) + ) + (net (rename n0035_38_ "n0035[38]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_38__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram20)) + ) + ) + (net (rename n0035_43_ "n0035[43]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_43__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram22)) + ) + ) + (net (rename n0035_44_ "n0035[44]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_44__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram23)) + ) + ) + (net (rename n0035_39_ "n0035[39]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_39__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram20)) + ) + ) + (net (rename n0035_50_ "n0035[50]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_50__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram26)) + ) + ) + (net (rename n0035_45_ "n0035[45]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_45__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram23)) + ) + ) + (net (rename f1_dont_write_past_me_10__FRB "f1/dont_write_past_me<10>_FRB") (joined + (portref I3 (instanceref f1_Mcompar_becoming_full_lut_3_)) + (portref Q (instanceref f1_dont_write_past_me_10__FRB)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror_bdd0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror_bdd0") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW0)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_4_1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_F)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + ) + ) + (net (rename n0035_51_ "n0035[51]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_51__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram26)) + ) + ) + (net (rename n0035_46_ "n0035[46]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_46__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram24)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror_bdd6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror_bdd6") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In11)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In12)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW0)) + ) + ) + (net (rename n0035_52_ "n0035[52]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_52__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram27)) + ) + ) + (net (rename n0035_47_ "n0035[47]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_47__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram24)) + ) + ) + (net (rename n0035_53_ "n0035[53]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_53__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram27)) + ) + ) + (net (rename n0035_48_ "n0035[48]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_48__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram25)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr6_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_6)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr6_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_0_ "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding[0]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata261)) + ) + ) + (net (rename n0035_54_ "n0035[54]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_54__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram28)) + ) + ) + (net (rename n0035_49_ "n0035[49]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_49__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram25)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_1_ "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding[1]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata271)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines321 "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines321") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_1_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines322 "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines322") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_2_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_2)) + ) + ) + (net (rename n0035_60_ "n0035[60]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_60__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram31)) + ) + ) + (net (rename n0035_55_ "n0035[55]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_55__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram28)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines323 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slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + (portref I (instanceref gpif_clk_inverter)) + ) + ) + (net gpif_clk_inv (joined + (portref O (instanceref gpif_clk_inverter)) + (portref C1 (instanceref ODDR2_ifclk_dbg)) + (portref C1 (instanceref ODDR2_ifclk)) + ) + ) + (net (rename GPIF_D_6_ "GPIF_D[6]") (joined + (portref IO (instanceref GPIF_D_6_IOBUF)) + (portref (member GPIF_D 25)) + ) + ) + (net (rename ctrl_tdata_30_ "ctrl_tdata[30]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_30__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram16)) + ) + ) + (net (rename ctrl_tdata_25_ "ctrl_tdata[25]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_25__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram13)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_i_tvalid_o_tready_AND_73_o "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/i_tvalid_o_tready_AND_73_o") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_0)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_2)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_3)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_4)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_5)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_6)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_7)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_8)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_9)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_10)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_11)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_12)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_13)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_14)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_15)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_16)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_17)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_18)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_19)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_20)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_21)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_22)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_23)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_24)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_25)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_26)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_27)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_28)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_29)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_30)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_31)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_i_tvalid_o_tready_AND_73_o1)) + ) + ) + (net (rename GPIF_D_7_ "GPIF_D[7]") (joined + (portref IO (instanceref GPIF_D_7_IOBUF)) + (portref (member GPIF_D 24)) + ) + ) + (net (rename ctrl_tdata_31_ "ctrl_tdata[31]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_31__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram16)) + ) + ) + (net (rename ctrl_tdata_26_ "ctrl_tdata[26]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_26__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram14)) + ) + ) + (net (rename f1_dont_write_past_me_12__FRB "f1/dont_write_past_me<12>_FRB") (joined + (portref I1 (instanceref f1_Mcompar_becoming_full_lut_4_)) + (portref Q (instanceref f1_dont_write_past_me_12__FRB)) + ) + ) + (net (rename GPIF_D_8_ "GPIF_D[8]") (joined + (portref IO (instanceref GPIF_D_8_IOBUF)) + (portref (member GPIF_D 23)) + ) + ) + (net (rename f0_Result_4_2_FRB "f0/Result<4>2_FRB") (joined + (portref D (instanceref f0_wr_addr_4)) + (portref Q (instanceref f0_Result_4_2_FRB)) + (portref I0 (instanceref f0_Mcount_wr_addr_cy_4__rt)) + ) + ) + (net reset_global_locked_OR_1_o (joined + (portref PRE (instanceref bus_sync_reset_int)) + (portref PRE (instanceref bus_sync_reset_out)) + (portref PRE (instanceref gpif_sync_reset_int)) + (portref PRE (instanceref gpif_sync_reset_out)) + (portref O (instanceref reset_global_locked_OR_1_o1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11)) + (portref I3 (instanceref slave_fifo32_ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tvalid11)) + ) + ) + (net (rename ctrl_tdata_32_ "ctrl_tdata[32]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram17)) + ) + ) + (net (rename ctrl_tdata_27_ "ctrl_tdata[27]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_27__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram14)) + ) + ) + (net (rename GPIF_D_9_ "GPIF_D[9]") (joined + (portref IO (instanceref GPIF_D_9_IOBUF)) + (portref (member GPIF_D 22)) + ) + ) + (net (rename ctrl_tdata_28_ "ctrl_tdata[28]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_28__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram15)) + ) + ) + (net (rename ctrl_tdata_33_ "ctrl_tdata[33]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_33__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram17)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr5_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_5)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr5_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__rt)) + ) + ) + (net (rename ctrl_tdata_29_ "ctrl_tdata[29]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_29__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram15)) + ) + ) + (net (rename ctrl_tdata_34_ "ctrl_tdata[34]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_34__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram18)) + ) + ) + (net (rename ctrl_tdata_35_ "ctrl_tdata[35]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram18)) + ) + ) + (net (rename ctrl_tdata_40_ "ctrl_tdata[40]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_40__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram21)) + ) + ) + (net (rename ctrl_tdata_36_ "ctrl_tdata[36]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_36__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram19)) + ) + ) + (net (rename ctrl_tdata_41_ "ctrl_tdata[41]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_41__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram21)) + ) + ) + (net (rename f1_Result_10_1_FRB "f1/Result<10>1_FRB") (joined + (portref D (instanceref f1_rd_addr_10)) + (portref Q (instanceref f1_Result_10_1_FRB)) + (portref I0 (instanceref f1_Mcount_rd_addr_cy_10__rt)) + (portref I0 (instanceref f1_Msub_dont_write_past_me_lut_10__INV_0)) + ) + ) + (net (rename ctrl_tdata_37_ "ctrl_tdata[37]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram19)) + ) + ) + (net (rename ctrl_tdata_42_ "ctrl_tdata[42]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_42__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram22)) + ) + ) + (net (rename ctrl_tdata_38_ "ctrl_tdata[38]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_38__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram20)) + ) + ) + (net (rename ctrl_tdata_43_ "ctrl_tdata[43]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_43__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram22)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tready_int1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tvalid11)) + ) + ) + (net (rename ctrl_tdata_39_ "ctrl_tdata[39]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_39__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram20)) + ) + ) + (net (rename ctrl_tdata_44_ "ctrl_tdata[44]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_44__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram23)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_0_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_0_)) + ) + ) + (net (rename ctrl_tdata_45_ "ctrl_tdata[45]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_45__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram23)) + ) + ) + (net (rename ctrl_tdata_50_ "ctrl_tdata[50]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_50__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram26)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_1_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW2)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tvalid11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1)) + ) + ) + (net (rename ctrl_tdata_46_ "ctrl_tdata[46]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_46__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram24)) + ) + ) + (net (rename ctrl_tdata_51_ "ctrl_tdata[51]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_51__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram26)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_2_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_2_)) + ) + ) + (net (rename ctrl_tdata_47_ "ctrl_tdata[47]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_47__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram24)) + ) + ) + (net (rename ctrl_tdata_52_ "ctrl_tdata[52]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_52__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram27)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_10_ "slave_fifo32/gpif_data_out[10]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_10)) + (portref I (instanceref GPIF_D_10_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_3_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_3_)) + ) + ) + (net (rename ctrl_tdata_53_ "ctrl_tdata[53]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram27)) + ) + ) + (net (rename ctrl_tdata_48_ "ctrl_tdata[48]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_48__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram25)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_11_ "slave_fifo32/gpif_data_out[11]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_11)) + (portref I (instanceref GPIF_D_11_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_4_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_4_)) + ) + ) + (net (rename ctrl_tdata_54_ "ctrl_tdata[54]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_54__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram28)) + ) + ) + (net (rename ctrl_tdata_49_ "ctrl_tdata[49]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_49__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram25)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_0__inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/state<0>_inv") (joined + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_0_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_0__inv1_INV_0)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_12_ "slave_fifo32/gpif_data_out[12]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_12)) + (portref I (instanceref GPIF_D_12_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o "slave_fifo32/fifo64_to_gpmc32_tx/GND_49_o_space[15]_LessThan_2_o") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_i_tready)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1)) + ) + ) + (net (rename ctrl_tdata_60_ "ctrl_tdata[60]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_60__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram31)) + ) + ) + (net (rename ctrl_tdata_55_ "ctrl_tdata[55]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_55__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram28)) + ) + ) + (net (rename f1_Result_2_1_FRB "f1/Result<2>1_FRB") (joined + (portref D (instanceref f1_rd_addr_2)) + (portref Q (instanceref f1_Result_2_1_FRB)) + (portref I0 (instanceref f1_Mcount_rd_addr_cy_2__rt)) + (portref I0 (instanceref f1_Msub_dont_write_past_me_lut_2__INV_0)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_13_ "slave_fifo32/gpif_data_out[13]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_13)) + (portref I (instanceref GPIF_D_13_IOBUF)) + ) + ) + (net (rename ctrl_tdata_56_ "ctrl_tdata[56]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_56__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram29)) + ) + ) + (net (rename ctrl_tdata_61_ "ctrl_tdata[61]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_61__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram31)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_14_ "slave_fifo32/gpif_data_out[14]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_14)) + (portref I (instanceref GPIF_D_14_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_1_)) + ) + ) + (net (rename ctrl_tdata_62_ "ctrl_tdata[62]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram32)) + ) + ) + (net (rename ctrl_tdata_57_ "ctrl_tdata[57]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_57__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram29)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_20_ "slave_fifo32/gpif_data_out[20]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_20)) + (portref I (instanceref GPIF_D_20_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_15_ "slave_fifo32/gpif_data_out[15]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_15)) + (portref I (instanceref GPIF_D_15_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_2_)) + ) + ) + (net (rename ctrl_tdata_63_ "ctrl_tdata[63]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram32)) + ) + ) + (net (rename ctrl_tdata_58_ "ctrl_tdata[58]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_58__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram30)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_16_ "slave_fifo32/gpif_data_out[16]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_16)) + (portref I (instanceref GPIF_D_16_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_21_ "slave_fifo32/gpif_data_out[21]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_21)) + (portref I (instanceref GPIF_D_21_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_3_)) + ) + ) + (net (rename ctrl_tdata_59_ "ctrl_tdata[59]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_59__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram30)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_22_ "slave_fifo32/gpif_data_out[22]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_22)) + (portref I (instanceref GPIF_D_22_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_17_ "slave_fifo32/gpif_data_out[17]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_17)) + (portref I (instanceref GPIF_D_17_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_4_)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_23_ "slave_fifo32/gpif_data_out[23]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_23)) + (portref I (instanceref GPIF_D_23_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_18_ "slave_fifo32/gpif_data_out[18]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_18)) + (portref I (instanceref GPIF_D_18_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_5_)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_24_ "slave_fifo32/gpif_data_out[24]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_24)) + (portref I (instanceref GPIF_D_24_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_19_ "slave_fifo32/gpif_data_out[19]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_19)) + (portref I (instanceref GPIF_D_19_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_6_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr8_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_8)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr8_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__rt)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_30_ "slave_fifo32/gpif_data_out[30]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_30)) + (portref I (instanceref GPIF_D_30_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_25_ "slave_fifo32/gpif_data_out[25]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_25)) + (portref I (instanceref GPIF_D_25_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_7_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_i_tready "slave_fifo32/fifo64_to_gpmc32_ctrl/i_tready") (joined + (portref D (instanceref slave_fifo32_debug1_18)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_i_tready)) + (portref I3 (instanceref slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_0)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0__rt)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_31_ "slave_fifo32/gpif_data_out[31]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_31)) + (portref I (instanceref GPIF_D_31_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_26_ "slave_fifo32/gpif_data_out[26]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_26)) + (portref I (instanceref GPIF_D_26_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_space_xor<3>11") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_4_11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_3_11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_1_11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_2_11)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_27_ "slave_fifo32/gpif_data_out[27]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_27)) + (portref I (instanceref GPIF_D_27_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_8_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_9_)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_4__rt "f1/Mcount_rd_addr_cy<4>_rt") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_4__rt)) + (portref S (instanceref f1_Mcount_rd_addr_cy_4_)) + (portref LI (instanceref f1_Mcount_rd_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_28_ "slave_fifo32/gpif_data_out[28]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_28)) + (portref I (instanceref GPIF_D_28_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_9_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_10_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_10_)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_29_ "slave_fifo32/gpif_data_out[29]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_29)) + (portref I (instanceref GPIF_D_29_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr8_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr8_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8__rt)) + ) + ) + (net (rename f1_Mcompar_becoming_full_lut_0_ "f1/Mcompar_becoming_full_lut[0]") (joined + (portref O (instanceref f1_Mcompar_becoming_full_lut_0_)) + (portref S (instanceref f1_Mcompar_becoming_full_cy_0_)) + ) + ) + (net (rename f1_Mcompar_becoming_full_lut_1_ "f1/Mcompar_becoming_full_lut[1]") (joined + (portref O (instanceref f1_Mcompar_becoming_full_lut_1_)) + (portref S (instanceref f1_Mcompar_becoming_full_cy_1_)) + ) + ) + (net (rename f1_Mcompar_becoming_full_lut_2_ "f1/Mcompar_becoming_full_lut[2]") (joined + (portref O (instanceref f1_Mcompar_becoming_full_lut_2_)) + (portref S (instanceref f1_Mcompar_becoming_full_cy_2_)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_0_ "slave_fifo32/data_rx_tdata[0]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT110)) + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename f1_Mcompar_becoming_full_lut_3_ "f1/Mcompar_becoming_full_lut[3]") (joined + (portref O (instanceref f1_Mcompar_becoming_full_lut_3_)) + (portref S (instanceref f1_Mcompar_becoming_full_cy_3_)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_1_ "slave_fifo32/data_rx_tdata[1]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT121)) + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename f1_Mcompar_becoming_full_lut_4_ "f1/Mcompar_becoming_full_lut[4]") (joined + (portref O (instanceref f1_Mcompar_becoming_full_lut_4_)) + (portref S (instanceref f1_Mcompar_becoming_full_cy_4_)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_2_ "slave_fifo32/data_rx_tdata[2]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT231)) + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2)) + ) + ) + (net (rename slave_fifo32_EP_WMARK "slave_fifo32/EP_WMARK") (joined + (portref Q (instanceref slave_fifo32_EP_WMARK)) + (portref D (instanceref slave_fifo32_EP_WMARK1)) + (portref D (instanceref slave_fifo32_EP_WMARK1_1)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_3_ "slave_fifo32/data_rx_tdata[3]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT261)) + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_4_ "slave_fifo32/data_rx_tdata[4]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT271)) + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_4_)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_10_ "f0/Mcount_rd_addr_cy[10]") (joined + (portref O (instanceref f0_Mcount_rd_addr_cy_10_)) + (portref CI (instanceref f0_Mcount_rd_addr_cy_11_)) + (portref CI (instanceref f0_Mcount_rd_addr_xor_11_)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_5_ "slave_fifo32/data_rx_tdata[5]") (joined + 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(rename slave_fifo32_fifoadr_0_1 "slave_fifo32/fifoadr_0_1") (joined + (portref Q (instanceref slave_fifo32_fifoadr_0_1)) + (portref D (instanceref slave_fifo32_debug1_26)) + (portref I1 (instanceref slave_fifo32_Mcount_fifoadr_xor_1_11)) + (portref I0 (instanceref slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o1)) + (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT110)) + (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT101)) + (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT111)) + (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT121)) + (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT131)) + (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT141)) + (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT151)) + (portref I3 (instanceref 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slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata431)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_21_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[21]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_21)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata491)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2_1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int12)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int14)) + ) + ) + (net (rename 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f1_ram_Mram_ram13)) + (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_30_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[30]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_30)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata591)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_25_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[25]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_25)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata531)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_1_ "slave_fifo32/gpif_data_out[1]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_1)) + (portref I (instanceref GPIF_D_1_IOBUF)) + ) + ) + (net (rename f1_rd_addr_1_ "f1/rd_addr[1]") (joined + (portref Q (instanceref f1_rd_addr_1)) + (portref I2 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref (member ADDRBRDADDR 11) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_31_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[31]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_31)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata601)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_26_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[26]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_26)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata541)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_2_ "slave_fifo32/gpif_data_out[2]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_2)) + (portref I (instanceref GPIF_D_2_IOBUF)) + ) + ) + (net (rename f1_rd_addr_2_ "f1/rd_addr[2]") (joined + (portref Q (instanceref f1_rd_addr_2)) + (portref I4 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref (member ADDRBRDADDR 10) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_27_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[27]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_27)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata551)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_3_ "slave_fifo32/gpif_data_out[3]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_3)) + (portref I (instanceref GPIF_D_3_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_0)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt)) + ) + ) + (net (rename f1_rd_addr_3_ "f1/rd_addr[3]") (joined + (portref Q (instanceref f1_rd_addr_3)) + (portref I0 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref (member ADDRBRDADDR 9) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_28_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[28]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_28)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata571)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tvalid "slave_fifo32/ctrl_rx_tvalid") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1)) + (portref I2 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tvalid11)) + (portref I5 (instanceref slave_fifo32_ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1)) + (portref I4 (instanceref slave_fifo32_state_FSM_FFd1_In2)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_4_ "slave_fifo32/gpif_data_out[4]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_4)) + (portref I (instanceref GPIF_D_4_IOBUF)) + ) + ) + (net (rename f1_rd_addr_4_ "f1/rd_addr[4]") (joined + (portref Q (instanceref f1_rd_addr_4)) + (portref I2 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref (member ADDRBRDADDR 8) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_29_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[29]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_29)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata581)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_5_ "slave_fifo32/gpif_data_out[5]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_5)) + (portref I (instanceref GPIF_D_5_IOBUF)) + ) + ) + (net (rename f1_rd_addr_5_ "f1/rd_addr[5]") (joined + (portref Q (instanceref f1_rd_addr_5)) + (portref I4 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref (member ADDRBRDADDR 7) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_6_ "slave_fifo32/gpif_data_out[6]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_6)) + (portref I (instanceref GPIF_D_6_IOBUF)) + ) + ) + (net (rename f1_rd_addr_6_ "f1/rd_addr[6]") (joined + (portref Q (instanceref f1_rd_addr_6)) + (portref I0 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref (member ADDRBRDADDR 6) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_7_ "slave_fifo32/gpif_data_out[7]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_7)) + (portref I (instanceref GPIF_D_7_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/full_glue_set") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set)) + ) + ) + (net (rename f1_rd_addr_7_ "f1/rd_addr[7]") (joined + (portref Q (instanceref f1_rd_addr_7)) + (portref I2 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref (member ADDRBRDADDR 5) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_8_ "slave_fifo32/gpif_data_out[8]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_8)) + (portref I (instanceref GPIF_D_8_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_9_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_9_BRB1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_9_BRB1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_)) + ) + ) + (net (rename f1_rd_addr_8_ "f1/rd_addr[8]") (joined + (portref Q (instanceref f1_rd_addr_8)) + (portref I4 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref (member ADDRBRDADDR 4) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_9_ "slave_fifo32/gpif_data_out[9]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_9)) + (portref I (instanceref GPIF_D_9_IOBUF)) + ) + ) + (net (rename f1_rd_addr_9_ "f1/rd_addr[9]") (joined + (portref Q (instanceref f1_rd_addr_9)) + (portref I0 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref (member ADDRBRDADDR 3) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<4>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_0_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[0]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT411)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0)) + ) + ) + (net (rename f1_rd_addr_12__wr_addr_12__equal_11_o "f1/rd_addr[12]_wr_addr[12]_equal_11_o") (joined + (portref O (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_)) + (portref CI (instanceref f1__n0161_inv1_cy)) + (portref I2 (instanceref f1_read_state_FSM_FFd1_In111)) + (portref I1 (instanceref f1_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_1_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[1]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT411)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<3>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_3__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_3_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_2_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[2]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_2)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT411)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_3_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[3]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_3)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_SW0)) + ) + ) + (net (rename f0_dont_write_past_me_11__FRB "f0/dont_write_past_me<11>_FRB") (joined + (portref I5 (instanceref f0_Mcompar_becoming_full_lut_3_)) + (portref Q (instanceref f0_dont_write_past_me_11__FRB)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[0]") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_4_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[4]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_4)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[1]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_5_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[5]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_5)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[2]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_2)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15)) + ) + ) + (net (rename f0_Result_8_1_FRB "f0/Result<8>1_FRB") (joined + (portref D (instanceref f0_rd_addr_8)) + (portref Q (instanceref f0_Result_8_1_FRB)) + (portref I0 (instanceref f0_Mcount_rd_addr_cy_8__rt)) + (portref I0 (instanceref f0_Msub_dont_write_past_me_lut_8__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_6_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[6]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_6)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11)) + ) + ) + (net (rename tx_codec_d_0_ "tx_codec_d[0]") (joined + (portref O (instanceref tx_codec_d_0_OBUF)) + (portref (member tx_codec_d 11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[3]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_3)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_5_)) + ) + ) + (net (rename slave_fifo32_ctrl_tx_tvalid "slave_fifo32/ctrl_tx_tvalid") (joined + (portref D (instanceref slave_fifo32_debug1_19)) + (portref O (instanceref slave_fifo32_ctrl_tx_tvalid1)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4_)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6_)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv31)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_write_AND_42_o_inv2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[7]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tready_int1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tvalid11)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_11__rt "f1/Mcount_rd_addr_cy<11>_rt") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_11__rt)) + (portref S (instanceref f1_Mcount_rd_addr_cy_11_)) + (portref LI (instanceref f1_Mcount_rd_addr_xor_11_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1_)) + ) + ) + (net (rename tx_codec_d_1_ "tx_codec_d[1]") (joined + (portref O (instanceref tx_codec_d_1_OBUF)) + (portref (member tx_codec_d 10)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[4]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_4)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_4_1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_F)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tvalid11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2_)) + ) + ) + (net (rename tx_codec_d_2_ "tx_codec_d[2]") (joined + (portref O (instanceref tx_codec_d_2_OBUF)) + (portref (member tx_codec_d 9)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[5]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_5)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tvalid11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3_)) + ) + ) + (net (rename tx_codec_d_3_ "tx_codec_d[3]") (joined + (portref O (instanceref tx_codec_d_3_OBUF)) + (portref (member tx_codec_d 8)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01211 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01211") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[6]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_6)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tvalid11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01212") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01213") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01214") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01215") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4_)) + ) + ) + (net (rename tx_codec_d_4_ "tx_codec_d[4]") (joined + (portref O (instanceref tx_codec_d_4_OBUF)) + (portref (member tx_codec_d 7)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01216 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01216") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01216)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tready_int11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01217") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219)) + ) + ) + (net (rename slave_fifo32_sloe_10 "slave_fifo32/sloe_10") (joined + (portref Q (instanceref slave_fifo32_sloe_10)) + (portref T (instanceref GPIF_D_8_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01218 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01218") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01218)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219)) + ) + ) + (net (rename slave_fifo32_sloe_11 "slave_fifo32/sloe_11") (joined + (portref Q (instanceref slave_fifo32_sloe_11)) + (portref T (instanceref GPIF_D_9_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_12 "slave_fifo32/sloe_12") (joined + (portref Q (instanceref slave_fifo32_sloe_12)) + (portref T (instanceref GPIF_D_10_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5_)) + ) + ) + (net (rename slave_fifo32_sloe_13 "slave_fifo32/sloe_13") (joined + (portref Q (instanceref slave_fifo32_sloe_13)) + (portref T (instanceref GPIF_D_11_IOBUF)) + ) + ) + (net (rename tx_codec_d_5_ "tx_codec_d[5]") (joined + (portref O (instanceref tx_codec_d_5_OBUF)) + (portref (member tx_codec_d 6)) + ) + ) + (net (rename slave_fifo32_sloe_14 "slave_fifo32/sloe_14") (joined + (portref Q (instanceref slave_fifo32_sloe_14)) + (portref T (instanceref GPIF_D_12_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_20 "slave_fifo32/sloe_20") (joined + (portref Q (instanceref slave_fifo32_sloe_20)) + (portref T (instanceref GPIF_D_18_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_15 "slave_fifo32/sloe_15") (joined + (portref Q (instanceref slave_fifo32_sloe_15)) + (portref T (instanceref GPIF_D_13_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_21 "slave_fifo32/sloe_21") (joined + (portref Q (instanceref slave_fifo32_sloe_21)) + (portref T (instanceref GPIF_D_19_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_16 "slave_fifo32/sloe_16") (joined + (portref Q (instanceref slave_fifo32_sloe_16)) + (portref T (instanceref GPIF_D_14_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_22 "slave_fifo32/sloe_22") (joined + (portref Q (instanceref slave_fifo32_sloe_22)) + (portref T (instanceref GPIF_D_20_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_17 "slave_fifo32/sloe_17") (joined + (portref Q (instanceref slave_fifo32_sloe_17)) + (portref T (instanceref GPIF_D_15_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6_)) + ) + ) + (net (rename slave_fifo32_sloe_18 "slave_fifo32/sloe_18") (joined + (portref Q (instanceref slave_fifo32_sloe_18)) + (portref T (instanceref GPIF_D_16_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_23 "slave_fifo32/sloe_23") (joined + (portref Q (instanceref slave_fifo32_sloe_23)) + (portref T (instanceref GPIF_D_21_IOBUF)) + ) + ) + (net (rename tx_codec_d_6_ "tx_codec_d[6]") (joined + (portref O (instanceref tx_codec_d_6_OBUF)) + (portref (member tx_codec_d 5)) + ) + ) + (net (rename slave_fifo32_sloe_19 "slave_fifo32/sloe_19") (joined + (portref Q (instanceref slave_fifo32_sloe_19)) + (portref T (instanceref GPIF_D_17_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_24 "slave_fifo32/sloe_24") (joined + (portref Q (instanceref slave_fifo32_sloe_24)) + (portref T (instanceref GPIF_D_22_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_30 "slave_fifo32/sloe_30") (joined + (portref Q (instanceref slave_fifo32_sloe_30)) + (portref T (instanceref GPIF_D_28_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_25 "slave_fifo32/sloe_25") (joined + (portref Q (instanceref slave_fifo32_sloe_25)) + (portref T (instanceref GPIF_D_23_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_31 "slave_fifo32/sloe_31") (joined + (portref Q (instanceref slave_fifo32_sloe_31)) + (portref T (instanceref GPIF_D_29_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_26 "slave_fifo32/sloe_26") (joined + (portref Q (instanceref slave_fifo32_sloe_26)) + (portref T (instanceref GPIF_D_24_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_32 "slave_fifo32/sloe_32") (joined + (portref Q (instanceref slave_fifo32_sloe_32)) + (portref T (instanceref GPIF_D_30_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_27 "slave_fifo32/sloe_27") (joined + (portref Q (instanceref slave_fifo32_sloe_27)) + (portref T (instanceref GPIF_D_25_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7_)) + ) + ) + (net (rename slave_fifo32_sloe_28 "slave_fifo32/sloe_28") (joined + (portref Q (instanceref slave_fifo32_sloe_28)) + (portref T (instanceref GPIF_D_26_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_33 "slave_fifo32/sloe_33") (joined + (portref Q (instanceref slave_fifo32_sloe_33)) + (portref T (instanceref GPIF_D_31_IOBUF)) + ) + ) + (net (rename tx_codec_d_7_ "tx_codec_d[7]") (joined + (portref O (instanceref tx_codec_d_7_OBUF)) + (portref (member tx_codec_d 4)) + ) + ) + (net (rename slave_fifo32_sloe_29 "slave_fifo32/sloe_29") (joined + (portref Q (instanceref slave_fifo32_sloe_29)) + (portref T (instanceref GPIF_D_27_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_34 "slave_fifo32/sloe_34") (joined + (portref Q (instanceref slave_fifo32_sloe_34)) + (portref D (instanceref slave_fifo32_debug1_31)) + (portref I0 (instanceref slave_fifo32_sloe_1_rstpot)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8_)) + ) + ) + (net (rename tx_codec_d_8_ "tx_codec_d[8]") (joined + (portref O (instanceref tx_codec_d_8_OBUF)) + (portref (member tx_codec_d 3)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9_)) + ) + ) + (net (rename tx_codec_d_9_ "tx_codec_d[9]") (joined + (portref O (instanceref tx_codec_d_9_OBUF)) + (portref (member tx_codec_d 2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10_)) + ) + ) + (net bus_clk (joined + (portref C (instanceref bus_sync_reset_int)) + (portref C (instanceref bus_sync_reset_out)) + (portref O (instanceref gen_clks_clkout3_buf)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_0)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_1)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_2)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_3)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_4)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_0__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_1__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_2__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_3__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_4__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_5__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_6__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_7__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_8__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_9__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_10__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_11__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_12__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_13__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_14__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_15__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_16__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_17__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_18__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_19__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_20__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_21__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_22__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_23__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_24__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_25__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_26__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_27__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_28__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_29__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_30__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_31__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_32__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_33__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_34__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_35__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_36__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_37__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_38__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_39__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_40__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_41__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_42__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_43__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_44__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_45__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_46__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_47__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_48__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_49__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_50__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_51__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_52__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_53__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_54__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_55__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_56__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_57__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_58__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_59__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_60__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_61__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_62__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_63__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_64__srlc32e)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_0)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_1)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_2)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_3)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_4)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_0__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_1__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_2__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_3__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_4__srlc32e)) + (portref CLK (instanceref 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slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_58__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_59__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_60__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_61__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_0)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_1)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_2)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_3)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_4)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_5)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_6)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_7)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_8)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_9)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_10)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_11)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_12)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_13)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_14)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_15)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_0)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_1)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_2)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_3)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_4)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_5)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_6)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_7)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_8)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_0)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_1)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_2)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_3)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_4)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_5)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_6)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_7)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_8)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_9)) + (portref C (instanceref f1_rd_addr_1)) + (portref C (instanceref f1_rd_addr_2)) + (portref C (instanceref f1_rd_addr_3)) + (portref C (instanceref f1_rd_addr_4)) + (portref C (instanceref f1_rd_addr_5)) + (portref C (instanceref f1_rd_addr_6)) + (portref C (instanceref f1_rd_addr_7)) + (portref C (instanceref f1_rd_addr_8)) + (portref C (instanceref f1_rd_addr_9)) + (portref C (instanceref f1_rd_addr_10)) + (portref C (instanceref f1_rd_addr_11)) + (portref C (instanceref f1_rd_addr_12)) + (portref C (instanceref f1_wr_addr_1)) + (portref C (instanceref f1_wr_addr_2)) + (portref C (instanceref f1_wr_addr_3)) + (portref C (instanceref f1_wr_addr_4)) + (portref C (instanceref f1_wr_addr_5)) + (portref C (instanceref f1_wr_addr_6)) + (portref C (instanceref f1_wr_addr_7)) + (portref C (instanceref f1_wr_addr_8)) + (portref C (instanceref f1_wr_addr_9)) + (portref C (instanceref f1_wr_addr_10)) + (portref C (instanceref f1_wr_addr_11)) + (portref C (instanceref f1_wr_addr_12)) + (portref C (instanceref f1_read_state_FSM_FFd2)) + (portref C (instanceref f1_read_state_FSM_FFd1)) + (portref C (instanceref f1_rd_addr_0)) + (portref C (instanceref f1_wr_addr_0)) + (portref C (instanceref f0_rd_addr_1)) + (portref C (instanceref f0_rd_addr_2)) + (portref C (instanceref f0_rd_addr_3)) + (portref C (instanceref f0_rd_addr_4)) + (portref C (instanceref f0_rd_addr_5)) + (portref C (instanceref f0_rd_addr_6)) + (portref C (instanceref f0_rd_addr_7)) + (portref C (instanceref f0_rd_addr_8)) + (portref C (instanceref f0_rd_addr_9)) + (portref C (instanceref f0_rd_addr_10)) + (portref C (instanceref f0_rd_addr_11)) + (portref C (instanceref f0_rd_addr_12)) + (portref C (instanceref f0_wr_addr_1)) + (portref C (instanceref f0_wr_addr_2)) + (portref C (instanceref f0_wr_addr_3)) + (portref C (instanceref f0_wr_addr_4)) + (portref C (instanceref f0_wr_addr_5)) + (portref C (instanceref f0_wr_addr_6)) + (portref C (instanceref f0_wr_addr_7)) + (portref C (instanceref f0_wr_addr_8)) + (portref C (instanceref f0_wr_addr_9)) + (portref C (instanceref f0_wr_addr_10)) + (portref C (instanceref f0_wr_addr_11)) + (portref C (instanceref f0_wr_addr_12)) + (portref C (instanceref f0_read_state_FSM_FFd2)) + (portref C (instanceref f0_read_state_FSM_FFd1)) + (portref C (instanceref f0_rd_addr_0)) + (portref C (instanceref f0_wr_addr_0)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump)) + (portref C (instanceref f1_full_reg)) + (portref C (instanceref f0_full_reg)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg)) + (portref C (instanceref f1_Result_0_2_FRB)) + (portref C (instanceref f1_Result_1_2_FRB)) + (portref C (instanceref f1_Result_2_2_FRB)) + (portref C (instanceref f1_Result_3_2_FRB)) + (portref C (instanceref f1_Result_4_2_FRB)) + (portref C (instanceref f1_Result_5_2_FRB)) + (portref C (instanceref f1_Result_6_2_FRB)) + (portref C (instanceref f1_Result_7_2_FRB)) + (portref C (instanceref f1_Result_8_2_FRB)) + (portref C (instanceref f1_Result_9_2_FRB)) + (portref C (instanceref f1_Result_10_2_FRB)) + (portref C (instanceref f1_Result_11_2_FRB)) + (portref C (instanceref f1_Result_12_2_FRB)) + (portref C (instanceref f1_Result_0_1_FRB)) + (portref C (instanceref f1_Result_1_1_FRB)) + (portref C (instanceref f1_Result_2_1_FRB)) + (portref C (instanceref f1_Result_3_1_FRB)) + (portref C (instanceref f1_Result_4_1_FRB)) + (portref C (instanceref f1_Result_5_1_FRB)) + (portref C (instanceref f1_Result_6_1_FRB)) + (portref C (instanceref f1_Result_7_1_FRB)) + (portref C (instanceref f1_Result_8_1_FRB)) + (portref C (instanceref f1_Result_9_1_FRB)) + (portref C (instanceref f1_Result_10_1_FRB)) + (portref C (instanceref f1_Result_11_1_FRB)) + (portref C (instanceref f1_Result_12_1_FRB)) + (portref C (instanceref f1_dont_write_past_me_0__FRB)) + (portref C (instanceref f1_dont_write_past_me_1__FRB)) + (portref C (instanceref f1_dont_write_past_me_2__FRB)) + (portref C (instanceref f1_dont_write_past_me_3__FRB)) + (portref C (instanceref f1_dont_write_past_me_4__FRB)) + (portref C (instanceref f1_dont_write_past_me_5__FRB)) + (portref C (instanceref f1_dont_write_past_me_6__FRB)) + (portref C (instanceref f1_dont_write_past_me_7__FRB)) + (portref C (instanceref f1_dont_write_past_me_8__FRB)) + (portref C (instanceref f1_dont_write_past_me_9__FRB)) + (portref C (instanceref f1_dont_write_past_me_10__FRB)) + (portref C (instanceref f1_dont_write_past_me_11__FRB)) + (portref C (instanceref f1_dont_write_past_me_12__FRB)) + (portref C (instanceref f0_Result_0_2_FRB)) + (portref C (instanceref f0_Result_1_2_FRB)) + (portref C (instanceref f0_Result_2_2_FRB)) + (portref C (instanceref f0_Result_3_2_FRB)) + (portref C (instanceref f0_Result_4_2_FRB)) + (portref C (instanceref f0_Result_5_2_FRB)) + (portref C (instanceref f0_Result_6_2_FRB)) + (portref C (instanceref f0_Result_7_2_FRB)) + (portref C (instanceref f0_Result_8_2_FRB)) + (portref C (instanceref f0_Result_9_2_FRB)) + (portref C (instanceref f0_Result_10_2_FRB)) + (portref C (instanceref f0_Result_11_2_FRB)) + (portref C (instanceref f0_Result_12_2_FRB)) + (portref C (instanceref f0_Result_0_1_FRB)) + (portref C (instanceref f0_Result_1_1_FRB)) + (portref C (instanceref f0_Result_2_1_FRB)) + (portref C (instanceref f0_Result_3_1_FRB)) + (portref C (instanceref f0_Result_4_1_FRB)) + (portref C (instanceref f0_Result_5_1_FRB)) + (portref C (instanceref f0_Result_6_1_FRB)) + (portref C (instanceref f0_Result_7_1_FRB)) + (portref C (instanceref f0_Result_8_1_FRB)) + (portref C (instanceref f0_Result_9_1_FRB)) + (portref C (instanceref f0_Result_10_1_FRB)) + (portref C (instanceref f0_Result_11_1_FRB)) + (portref C (instanceref f0_Result_12_1_FRB)) + (portref C (instanceref f0_dont_write_past_me_0__FRB)) + (portref C (instanceref f0_dont_write_past_me_1__FRB)) + (portref C (instanceref f0_dont_write_past_me_2__FRB)) + (portref C (instanceref f0_dont_write_past_me_3__FRB)) + (portref C (instanceref f0_dont_write_past_me_4__FRB)) + (portref C (instanceref f0_dont_write_past_me_5__FRB)) + (portref C (instanceref f0_dont_write_past_me_6__FRB)) + (portref C (instanceref f0_dont_write_past_me_7__FRB)) + (portref C (instanceref f0_dont_write_past_me_8__FRB)) + (portref C (instanceref f0_dont_write_past_me_9__FRB)) + (portref C (instanceref f0_dont_write_past_me_10__FRB)) + (portref C (instanceref f0_dont_write_past_me_11__FRB)) + (portref C (instanceref f0_dont_write_past_me_12__FRB)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0_FRB)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB1)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB3)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB4)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_1)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref CLKAWRCLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref CLKBRDCLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref CLKAWRCLK (instanceref f1_ram_Mram_ram33)) + (portref CLKBRDCLK (instanceref f1_ram_Mram_ram33)) + (portref CLKA (instanceref f1_ram_Mram_ram31)) + (portref CLKB (instanceref f1_ram_Mram_ram31)) + (portref CLKA (instanceref f1_ram_Mram_ram30)) + (portref CLKB (instanceref f1_ram_Mram_ram30)) + (portref CLKA (instanceref f1_ram_Mram_ram32)) + (portref CLKB (instanceref f1_ram_Mram_ram32)) + (portref CLKA (instanceref f1_ram_Mram_ram28)) + (portref CLKB (instanceref f1_ram_Mram_ram28)) + (portref CLKA (instanceref f1_ram_Mram_ram27)) + (portref CLKB (instanceref f1_ram_Mram_ram27)) + (portref CLKA (instanceref f1_ram_Mram_ram29)) + (portref CLKB (instanceref f1_ram_Mram_ram29)) + (portref CLKA (instanceref f1_ram_Mram_ram25)) + (portref CLKB (instanceref f1_ram_Mram_ram25)) + (portref CLKA (instanceref f1_ram_Mram_ram24)) + (portref CLKB (instanceref f1_ram_Mram_ram24)) + (portref CLKA (instanceref f1_ram_Mram_ram26)) + (portref CLKB (instanceref f1_ram_Mram_ram26)) + (portref CLKA (instanceref f1_ram_Mram_ram22)) + (portref CLKB (instanceref f1_ram_Mram_ram22)) + (portref CLKA (instanceref f1_ram_Mram_ram21)) + (portref CLKB (instanceref f1_ram_Mram_ram21)) + (portref CLKA (instanceref f1_ram_Mram_ram23)) + (portref CLKB (instanceref f1_ram_Mram_ram23)) + (portref CLKA (instanceref f1_ram_Mram_ram19)) + (portref CLKB (instanceref f1_ram_Mram_ram19)) + (portref CLKA (instanceref f1_ram_Mram_ram18)) + (portref CLKB (instanceref f1_ram_Mram_ram18)) + (portref CLKA (instanceref f1_ram_Mram_ram20)) + (portref CLKB (instanceref f1_ram_Mram_ram20)) + (portref CLKA (instanceref f1_ram_Mram_ram16)) + (portref CLKB (instanceref f1_ram_Mram_ram16)) + (portref CLKA (instanceref f1_ram_Mram_ram15)) + (portref CLKB (instanceref f1_ram_Mram_ram15)) + (portref CLKA (instanceref f1_ram_Mram_ram17)) + (portref CLKB (instanceref f1_ram_Mram_ram17)) + (portref CLKA (instanceref f1_ram_Mram_ram14)) + (portref CLKB (instanceref f1_ram_Mram_ram14)) + (portref CLKA (instanceref f1_ram_Mram_ram13)) + (portref CLKB (instanceref f1_ram_Mram_ram13)) + (portref CLKA (instanceref f1_ram_Mram_ram12)) + (portref CLKB (instanceref f1_ram_Mram_ram12)) + (portref CLKA (instanceref f1_ram_Mram_ram11)) + (portref CLKB (instanceref f1_ram_Mram_ram11)) + (portref CLKA (instanceref f1_ram_Mram_ram9)) + (portref CLKB (instanceref f1_ram_Mram_ram9)) + (portref CLKA (instanceref f1_ram_Mram_ram8)) + (portref CLKB (instanceref f1_ram_Mram_ram8)) + (portref CLKA (instanceref f1_ram_Mram_ram10)) + (portref CLKB (instanceref f1_ram_Mram_ram10)) + (portref CLKA (instanceref f1_ram_Mram_ram6)) + (portref CLKB (instanceref f1_ram_Mram_ram6)) + (portref CLKA (instanceref f1_ram_Mram_ram5)) + (portref CLKB (instanceref f1_ram_Mram_ram5)) + (portref CLKA (instanceref f1_ram_Mram_ram7)) + (portref CLKB (instanceref f1_ram_Mram_ram7)) + (portref CLKA (instanceref f1_ram_Mram_ram3)) + (portref CLKB (instanceref f1_ram_Mram_ram3)) + (portref CLKA (instanceref f1_ram_Mram_ram2)) + (portref CLKB (instanceref f1_ram_Mram_ram2)) + (portref CLKA (instanceref f1_ram_Mram_ram4)) + (portref CLKB (instanceref f1_ram_Mram_ram4)) + (portref CLKA (instanceref f1_ram_Mram_ram1)) + (portref CLKB (instanceref f1_ram_Mram_ram1)) + (portref CLKAWRCLK (instanceref f0_ram_Mram_ram33)) + (portref CLKBRDCLK (instanceref f0_ram_Mram_ram33)) + (portref CLKA (instanceref f0_ram_Mram_ram31)) + (portref CLKB (instanceref f0_ram_Mram_ram31)) + (portref CLKA (instanceref f0_ram_Mram_ram30)) + (portref CLKB (instanceref f0_ram_Mram_ram30)) + (portref CLKA (instanceref f0_ram_Mram_ram32)) + (portref CLKB (instanceref f0_ram_Mram_ram32)) + (portref CLKA (instanceref f0_ram_Mram_ram28)) + (portref CLKB (instanceref f0_ram_Mram_ram28)) + (portref CLKA (instanceref f0_ram_Mram_ram27)) + (portref CLKB (instanceref f0_ram_Mram_ram27)) + (portref CLKA (instanceref f0_ram_Mram_ram29)) + (portref CLKB (instanceref f0_ram_Mram_ram29)) + (portref CLKA (instanceref f0_ram_Mram_ram25)) + (portref CLKB (instanceref f0_ram_Mram_ram25)) + (portref CLKA (instanceref f0_ram_Mram_ram24)) + (portref CLKB (instanceref f0_ram_Mram_ram24)) + (portref CLKA (instanceref f0_ram_Mram_ram26)) + (portref CLKB (instanceref f0_ram_Mram_ram26)) + (portref CLKA (instanceref f0_ram_Mram_ram22)) + (portref CLKB (instanceref f0_ram_Mram_ram22)) + (portref CLKA (instanceref f0_ram_Mram_ram21)) + (portref CLKB (instanceref f0_ram_Mram_ram21)) + (portref CLKA (instanceref f0_ram_Mram_ram23)) + (portref CLKB (instanceref f0_ram_Mram_ram23)) + (portref CLKA (instanceref f0_ram_Mram_ram19)) + (portref CLKB (instanceref f0_ram_Mram_ram19)) + (portref CLKA (instanceref f0_ram_Mram_ram18)) + (portref CLKB (instanceref f0_ram_Mram_ram18)) + (portref CLKA (instanceref f0_ram_Mram_ram20)) + (portref CLKB (instanceref f0_ram_Mram_ram20)) + (portref CLKA (instanceref f0_ram_Mram_ram16)) + (portref CLKB (instanceref f0_ram_Mram_ram16)) + (portref CLKA (instanceref f0_ram_Mram_ram15)) + (portref CLKB (instanceref f0_ram_Mram_ram15)) + (portref CLKA (instanceref f0_ram_Mram_ram17)) + (portref CLKB (instanceref f0_ram_Mram_ram17)) + (portref CLKA (instanceref f0_ram_Mram_ram14)) + (portref CLKB (instanceref f0_ram_Mram_ram14)) + (portref CLKA (instanceref f0_ram_Mram_ram13)) + (portref CLKB (instanceref f0_ram_Mram_ram13)) + (portref CLKA (instanceref f0_ram_Mram_ram12)) + (portref CLKB (instanceref f0_ram_Mram_ram12)) + (portref CLKA (instanceref f0_ram_Mram_ram11)) + (portref CLKB (instanceref f0_ram_Mram_ram11)) + (portref CLKA (instanceref f0_ram_Mram_ram9)) + (portref CLKB (instanceref f0_ram_Mram_ram9)) + (portref CLKA (instanceref f0_ram_Mram_ram8)) + (portref CLKB (instanceref f0_ram_Mram_ram8)) + (portref CLKA (instanceref f0_ram_Mram_ram10)) + (portref CLKB (instanceref f0_ram_Mram_ram10)) + (portref CLKA (instanceref f0_ram_Mram_ram6)) + (portref CLKB (instanceref f0_ram_Mram_ram6)) + (portref CLKA (instanceref f0_ram_Mram_ram5)) + (portref CLKB (instanceref f0_ram_Mram_ram5)) + (portref CLKA (instanceref f0_ram_Mram_ram7)) + (portref CLKB (instanceref f0_ram_Mram_ram7)) + (portref CLKA (instanceref f0_ram_Mram_ram3)) + (portref CLKB (instanceref f0_ram_Mram_ram3)) + (portref CLKA (instanceref f0_ram_Mram_ram2)) + (portref CLKB (instanceref f0_ram_Mram_ram2)) + (portref CLKA (instanceref f0_ram_Mram_ram4)) + (portref CLKB (instanceref f0_ram_Mram_ram4)) + (portref CLKA (instanceref f0_ram_Mram_ram1)) + (portref CLKB (instanceref f0_ram_Mram_ram1)) + (portref rd_clk (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + (portref rd_clk (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + (portref wr_clk (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + (portref wr_clk (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename gen_clks_CLK_OUT1_40_int "gen_clks/CLK_OUT1_40_int") (joined + (portref O (instanceref gen_clks_clkout1_buf)) + (portref CLKFB (instanceref gen_clks_dcm_sp_inst)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_10_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[10]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_10)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata210)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata371)) + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n012121 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n012121") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216)) + ) + ) + (net (rename n0036_10_ "n0036[10]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_10__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_11_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[11]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata310)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata381)) + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + ) + ) + (net (rename n0036_11_ "n0036[11]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_11__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_12_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[12]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_12)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata410)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata391)) + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + ) + ) + (net (rename n0036_12_ "n0036[12]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_12__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram7)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_13_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[13]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_13)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata510)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata401)) + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + ) + ) + (net (rename n0036_13_ "n0036[13]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_13__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram7)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_14_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[14]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_14)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata65)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata411)) + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT41 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT41") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr7_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_7)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr7_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__rt)) + ) + ) + (net (rename n0036_14_ "n0036[14]") (joined + (portref D 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"slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[22]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_22)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata151)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata501)) + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_17_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[17]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_17)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata91)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata441)) + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + ) + ) + (net (rename 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(rename n0036_26_ "n0036[26]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_26__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram14)) + ) + ) + (net (rename n0036_31_ "n0036[31]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_31__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram16)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[11]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_11_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_11_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_11_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_27_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[27]") (joined + (portref D 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(portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_13_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_13_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_29_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[29]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_29)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata221)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata581)) + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[4]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_4)) + (portref I1 (instanceref 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(rename n0036_35_ "n0036[35]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_35__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram18)) + ) + ) + (net (rename n0036_40_ "n0036[40]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_40__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram21)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[0]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_0__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata110)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[15]") (joined + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_15_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_15_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[6]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_6)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata321)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata611)) + (portref (member DOB 25) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91)) + ) + ) + (net (rename n0036_36_ "n0036[36]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_36__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram19)) + ) + ) + (net (rename n0036_41_ "n0036[41]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_41__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram21)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[1]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_1__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata121)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full101 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full101") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full1011)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01216_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[7]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_7)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata331)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata621)) + (portref (member DOB 24) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full102 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full102") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full1021)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101)) + ) + ) + (net (rename n0036_37_ "n0036[37]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_37__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram19)) + ) + ) + (net (rename n0036_42_ "n0036[42]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_42__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram22)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[2]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_2__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata231)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[8]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_8)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata351)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata631)) + (portref (member DOB 23) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111)) + ) + ) + (net (rename n0036_38_ "n0036[38]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_38__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram20)) + ) + ) + (net (rename n0036_43_ "n0036[43]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_43__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram22)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[3]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_3__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata341)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[9]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_9)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata361)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata641)) + (portref (member DOB 22) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121)) + ) + ) + (net (rename n0036_39_ "n0036[39]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_39__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram20)) + ) + ) + (net (rename n0036_44_ "n0036[44]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_44__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram23)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[4]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_4__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata451)) + ) + ) + (net LED_TXRX1_RX (joined + (portref O (instanceref LED_TXRX1_RX_OBUF)) + (portref LED_TXRX1_RX) + ) + ) + (net (rename f1_Result_12_1_FRB "f1/Result<12>1_FRB") (joined + (portref D (instanceref f1_rd_addr_12)) + (portref Q (instanceref f1_Result_12_1_FRB)) + (portref I0 (instanceref f1_Mcount_rd_addr_xor_12__rt)) + (portref I0 (instanceref f1_Msub_dont_write_past_me_lut_12__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[10]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11_)) + ) + ) + (net (rename n0036_45_ "n0036[45]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_45__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram23)) + ) + ) + (net (rename n0036_50_ "n0036[50]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_50__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram26)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[5]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_5__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata561)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT141)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[11]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12_)) + ) + ) + (net (rename n0036_46_ "n0036[46]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_46__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram24)) + ) + ) + (net (rename n0036_51_ "n0036[51]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_51__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram26)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[6]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_6__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata611)) + ) + ) + (net LED_TXRX1_TX (joined + (portref O (instanceref LED_TXRX1_TX_OBUF)) + (portref LED_TXRX1_TX) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT151)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[12]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13_)) + ) + ) + (net (rename n0036_47_ "n0036[47]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_47__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram24)) + ) + ) + (net (rename n0036_52_ "n0036[52]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_52__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram27)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[7]") (joined + (portref D (instanceref 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(instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0144_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_34_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[34]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_34__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata281)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_29_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[29]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_29__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata221)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0__18_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0][18]") (joined + (portref (member DOB 13) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member din 53) (instanceref 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(instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full411_FRB") (joined + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01213)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411_FRB)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int11") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int13)) + ) + ) + (net (rename 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(instanceref slave_fifo32_sloe)) + ) + ) + (net LED_TXRX2_TX (joined + (portref O (instanceref LED_TXRX2_TX_OBUF)) + (portref LED_TXRX2_TX) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_7__num_packets_7__mux_17_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets[7]_num_packets[7]_mux_17_OUT[4]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_4)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_50_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[50]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_50__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata461)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_45_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[45]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_45__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata401)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0__29_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0][29]") (joined + (portref (member DOB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member din 42) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_7__num_packets_7__mux_17_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets[7]_num_packets[7]_mux_17_OUT[5]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_5)) + (portref O (instanceref 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"slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_1_)) + ) + ) + (net (rename slave_fifo32_slrd "slave_fifo32/slrd") (joined + (portref I (instanceref GPIF_CTL3_OBUF)) + (portref Q (instanceref slave_fifo32_slrd)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_7__num_packets_7__mux_17_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets[7]_num_packets[7]_mux_17_OUT[7]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_7)) + (portref O (instanceref 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slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_54_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[54]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_54__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata501)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_49_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[49]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_49__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata441)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv31)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_glue_set)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_write1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_)) + (portref I1 (instanceref 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"slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[60]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_60__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata571)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_55_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[55]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_55__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata511)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_61_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[61]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_61__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata581)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_56_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[56]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_56__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata521)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_62_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[62]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_62__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata591)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_57_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[57]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_57__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata531)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_full "slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/full") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_glue_set)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_write1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4_)) + (portref I2 (instanceref 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f1_Result_2_2_FRB "f1/Result<2>2_FRB") (joined + (portref D (instanceref f1_wr_addr_2)) + (portref Q (instanceref f1_Result_2_2_FRB)) + (portref I0 (instanceref f1_Mcount_wr_addr_cy_2__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_63_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[63]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_63__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata601)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_58_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[58]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_58__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata541)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_59_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[59]") (joined + (portref D (instanceref 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"slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012112") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012113 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012113") (joined + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012114") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012113)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_5__rt "f1/Mcount_rd_addr_cy<5>_rt") (joined + (portref O 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"slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv2") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv5") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv5)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT51") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT511)) + (portref I1 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(instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_11_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[11]") (joined + (portref (member DIA 20) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + (portref (member dout 60) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_12_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[12]") (joined + (portref (member DIA 19) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + (portref (member dout 59) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_13_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[13]") (joined + (portref (member DIA 18) (instanceref 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"f0/Mcompar_becoming_full_lut[0]") (joined + (portref O (instanceref f0_Mcompar_becoming_full_lut_0_)) + (portref S (instanceref f0_Mcompar_becoming_full_cy_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_2_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata231)) + (portref (member din 69) (instanceref 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slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_4_)) + ) + ) + (net (rename f0_Mcompar_becoming_full_lut_1_ "f0/Mcompar_becoming_full_lut[1]") (joined + (portref O (instanceref f0_Mcompar_becoming_full_lut_1_)) + (portref S (instanceref f0_Mcompar_becoming_full_cy_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_3_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[3]") (joined + (portref O (instanceref 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"slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata271)) + (portref (member din 67) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net tx_codec_d_0_OBUF (joined + (portref Q (instanceref catgen_gen_pins_0__oddr2)) + (portref I (instanceref tx_codec_d_0_OBUF)) + ) + ) + (net (rename f0_Mcompar_becoming_full_lut_3_ "f0/Mcompar_becoming_full_lut[3]") (joined + (portref O (instanceref f0_Mcompar_becoming_full_lut_3_)) + (portref S (instanceref f0_Mcompar_becoming_full_cy_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_5_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata281)) + (portref (member din 66) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f0_Mcompar_becoming_full_lut_4_ "f0/Mcompar_becoming_full_lut[4]") (joined + (portref O (instanceref f0_Mcompar_becoming_full_lut_4_)) + (portref S (instanceref f0_Mcompar_becoming_full_cy_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_6_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata291)) + (portref (member din 65) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f1_full_reg_glue_set "f1/full_reg_glue_set") (joined + (portref D (instanceref f1_full_reg)) + (portref O (instanceref f1_full_reg_glue_set)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT311 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT311") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_7_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata301)) + (portref (member din 64) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f0_Result_8_2_FRB "f0/Result<8>2_FRB") (joined + (portref D (instanceref f0_wr_addr_8)) + (portref Q (instanceref f0_Result_8_2_FRB)) + (portref I0 (instanceref f0_Mcount_wr_addr_cy_8__rt)) + ) + ) + (net tx_frame_p (joined + (portref O (instanceref tx_frame_p_OBUF)) + (portref tx_frame_p) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_6_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_8_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata311)) + (portref (member din 63) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In11") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In12") (joined + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_read1)) + (portref rd_en (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_9_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata321)) + (portref (member din 62) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In31") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In32") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In33)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_12_BRB0") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_12_BRB1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_)) + ) + ) + (net (rename f0_Result_10_1_FRB "f0/Result<10>1_FRB") (joined + (portref D (instanceref f0_rd_addr_10)) + (portref Q (instanceref f0_Result_10_1_FRB)) + (portref I0 (instanceref f0_Mcount_rd_addr_cy_10__rt)) + (portref I0 (instanceref f0_Msub_dont_write_past_me_lut_10__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<10>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_10_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut[2]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_2_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_2_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_2__INV_0)) + ) + ) + (net (rename slave_fifo32_EP_READY1 "slave_fifo32/EP_READY1") (joined + (portref Q (instanceref slave_fifo32_EP_READY1)) + (portref I (instanceref debug_24_OBUF)) + ) + ) + (net (rename f1_read_state_FSM_FFd2_In "f1/read_state_FSM_FFd2-In") (joined + (portref D (instanceref f1_read_state_FSM_FFd2)) + (portref O (instanceref f1_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut[3]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_3_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_3_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_3__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut[4]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_4_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_4_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_4__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut[5]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_5_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_5_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_5__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut[6]") (joined + (portref S (instanceref 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(instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_3_11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_1_11)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_2_11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1)) + (portref I4 (instanceref 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"slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_4_1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__0_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][0]") (joined + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 71) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__1_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][1]") (joined + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 70) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/dump") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_F)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_G)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int14)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0)) + ) + ) + (net (rename f0_wr_addr_10_ "f0/wr_addr[10]") (joined + (portref Q (instanceref f0_wr_addr_10)) + (portref I3 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref I2 (instanceref f0_Mcompar_becoming_full_lut_3_)) + (portref (member ADDRAWRADDR 2) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__2_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][2]") (joined + (portref (member DOB 29) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 69) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f0_wr_addr_11_ "f0/wr_addr[11]") (joined + (portref Q (instanceref f0_wr_addr_11)) + (portref I5 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref I4 (instanceref f0_Mcompar_becoming_full_lut_3_)) + (portref (member ADDRAWRADDR 1) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_slrd2_1 "slave_fifo32/slrd2_1") (joined + (portref Q (instanceref slave_fifo32_slrd2_1)) + (portref D (instanceref slave_fifo32_slrd3)) + (portref (member DIPA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member DIPA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__3_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][3]") (joined + (portref (member DOB 28) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 68) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f0_wr_addr_12_ "f0/wr_addr[12]") (joined + (portref Q (instanceref f0_wr_addr_12)) + (portref I1 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_)) + (portref I0 (instanceref f0_Mcompar_becoming_full_lut_4_)) + (portref (member ADDRAWRADDR 0) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__4_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][4]") (joined + (portref (member DOB 27) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 67) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__5_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][5]") (joined + (portref (member DOB 26) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 66) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr7_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_7)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr7_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__6_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][6]") (joined + (portref (member DOB 25) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 65) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__7_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][7]") (joined + (portref (member DOB 24) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 64) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__8_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][8]") (joined + (portref (member DOB 23) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 63) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net tx_codec_d_6_OBUF (joined + (portref Q (instanceref catgen_gen_pins_6__oddr2)) + (portref I (instanceref tx_codec_d_6_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__9_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][9]") (joined + (portref (member DOB 22) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 62) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_10_ "f1/Msub_dont_write_past_me_lut[10]") (joined + (portref S (instanceref f1_Msub_dont_write_past_me_cy_10_)) + (portref LI (instanceref f1_Msub_dont_write_past_me_xor_10_)) + (portref O (instanceref f1_Msub_dont_write_past_me_lut_10__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int11") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int12)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int14)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int14 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int14") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_11_ "f1/Msub_dont_write_past_me_lut[11]") (joined + (portref S (instanceref f1_Msub_dont_write_past_me_cy_11_)) + (portref LI (instanceref f1_Msub_dont_write_past_me_xor_11_)) + (portref O (instanceref f1_Msub_dont_write_past_me_lut_11__INV_0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_12_ "f1/Msub_dont_write_past_me_lut[12]") (joined + (portref LI (instanceref f1_Msub_dont_write_past_me_xor_12_)) + (portref O (instanceref f1_Msub_dont_write_past_me_lut_12__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_2_)) + ) + ) + (net (rename tx_codec_d_10_ "tx_codec_d[10]") (joined + (portref O (instanceref tx_codec_d_10_OBUF)) + (portref (member tx_codec_d 1)) + ) + ) + (net (rename f0_Mcount_rd_addr_xor_12__rt "f0/Mcount_rd_addr_xor<12>_rt") (joined + (portref O (instanceref f0_Mcount_rd_addr_xor_12__rt)) + (portref LI (instanceref f0_Mcount_rd_addr_xor_12_)) + ) + ) + (net (rename n0035_0_ "n0035[0]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_0__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_o_tready_int "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/o_tready_int") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tready_int1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_GND_66_o_read_OR_144_o1)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0146_inv1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv1)) + ) + ) + (net (rename tx_codec_d_11_ "tx_codec_d[11]") (joined + (portref O (instanceref tx_codec_d_11_OBUF)) + (portref (member tx_codec_d 0)) + ) + ) + (net (rename n0035_1_ "n0035[1]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_1__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty_glue_rst") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst)) + ) + ) + (net (rename n0035_2_ "n0035[2]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_2__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[0]") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_0_)) + (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW0)) + (portref (member dout 71) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename n0035_3_ "n0035[3]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_3__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[1]") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In11)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_1_)) + (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1)) + (portref (member dout 70) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename n0035_4_ "n0035[4]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_4__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram3)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[2]") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_2_)) + (portref (member DIA 29) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member dout 69) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename n0035_5_ "n0035[5]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_5__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram3)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[3]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_3_)) + (portref (member DIA 28) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member dout 68) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename n0035_6_ "n0035[6]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_6__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram4)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o5 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o5") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[4]") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_4_)) + (portref (member DIA 27) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member dout 67) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o7 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o7") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1)) + ) + ) + (net (rename n0035_7_ "n0035[7]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_7__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram4)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o8 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o8") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[5]") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_5_)) + (portref (member DIA 26) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_F)) + (portref (member dout 66) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net GPIF_CTL4_IBUF (joined + (portref D (instanceref slave_fifo32_EP_READY)) + (portref O (instanceref GPIF_CTL4_IBUF)) + ) + ) + (net (rename n0035_8_ "n0035[8]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_8__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram5)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[6]") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_6_)) + (portref (member DIA 25) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F)) + (portref (member dout 65) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename n0035_9_ "n0035[9]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_9__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram5)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[7]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_7_)) + (portref (member DIA 24) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F)) + (portref (member dout 64) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f0_becoming_full "f0/becoming_full") (joined + (portref O (instanceref f0_Mcompar_becoming_full_cy_4_)) + (portref I1 (instanceref f0_full_reg_glue_set)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0144_inv") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_0)) + (portref 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O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[8]") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_8_)) + (portref (member DIA 23) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61)) + (portref (member dout 63) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[9]") (joined + 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"f1/Msub_dont_write_past_me_cy[3]") (joined + (portref O (instanceref f1_Msub_dont_write_past_me_cy_3_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_cy_4_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_2_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[2]") (joined + (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2)) + (portref (member dout 69) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename n0036_4_ "n0036[4]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_4__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram3)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_7_ "f1/Mcount_wr_addr_cy[7]") (joined + (portref O (instanceref f1_Mcount_wr_addr_cy_7_)) + (portref CI (instanceref f1_Mcount_wr_addr_cy_8_)) + (portref CI (instanceref f1_Mcount_wr_addr_xor_8_)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_4_ "f1/Msub_dont_write_past_me_cy[4]") (joined + (portref O (instanceref f1_Msub_dont_write_past_me_cy_4_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_cy_5_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_xor_5_)) + ) + ) + (net (rename gen_clks_clkfx "gen_clks/clkfx") (joined + (portref I (instanceref gen_clks_clkout3_buf)) + (portref I (instanceref gen_clks_clkout2_buf)) + (portref CLKFX (instanceref gen_clks_dcm_sp_inst)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_3_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[3]") (joined + (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2)) + (portref (member dout 68) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv3 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv3") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv31)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214)) + ) + ) + (net (rename n0036_5_ "n0036[5]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_5__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram3)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_8_ "f1/Mcount_wr_addr_cy[8]") (joined + (portref O (instanceref f1_Mcount_wr_addr_cy_8_)) + (portref CI (instanceref f1_Mcount_wr_addr_cy_9_)) + (portref CI (instanceref f1_Mcount_wr_addr_xor_9_)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_5_ "f1/Msub_dont_write_past_me_cy[5]") (joined + (portref O (instanceref f1_Msub_dont_write_past_me_cy_5_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_cy_6_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_xor_6_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_4_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[4]") (joined + (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3)) + (portref (member dout 67) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename n0036_6_ "n0036[6]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_6__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram4)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_9_ "f1/Mcount_wr_addr_cy[9]") (joined + (portref O (instanceref f1_Mcount_wr_addr_cy_9_)) + (portref CI (instanceref f1_Mcount_wr_addr_cy_10_)) + (portref CI (instanceref f1_Mcount_wr_addr_xor_10_)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_6_ "f1/Msub_dont_write_past_me_cy[6]") (joined + (portref O (instanceref f1_Msub_dont_write_past_me_cy_6_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_cy_7_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_xor_7_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[10]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_10_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_10)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref (member ADDRBRDADDR 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_10__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_5_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[5]") (joined + (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3)) + (portref (member dout 66) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename n0036_7_ "n0036[7]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_7__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram4)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_7_ "f1/Msub_dont_write_past_me_cy[7]") (joined + (portref O (instanceref f1_Msub_dont_write_past_me_cy_7_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_cy_8_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_xor_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[11]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_11_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_11)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref (member ADDRBRDADDR 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_11__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_6_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[6]") (joined + (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4)) + (portref (member dout 65) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename n0036_8_ "n0036[8]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_8__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram5)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_8_ "f1/Msub_dont_write_past_me_cy[8]") (joined + (portref O (instanceref f1_Msub_dont_write_past_me_cy_8_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_cy_9_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_xor_9_)) + ) + ) + (net (rename slave_fifo32_Result_0_ "slave_fifo32/Result[0]") (joined + (portref D (instanceref slave_fifo32_fifoadr_0)) + (portref D (instanceref slave_fifo32_fifoadr_0_1)) + (portref O (instanceref slave_fifo32_Mcount_fifoadr_xor_0_11_INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[12]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_12_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_12)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_)) + (portref (member ADDRBRDADDR 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 0) (instanceref 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) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[11]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/full") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_i_tvalid_o_tready_AND_73_o1)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full)) + (portref I0 (instanceref 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slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7__num_packets_7__mux_17_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[7]_num_packets[7]_mux_17_OUT[3]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_3)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[12]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr4_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_4)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7__num_packets_7__mux_17_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[7]_num_packets[7]_mux_17_OUT[4]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_4)) + (portref O (instanceref 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(instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[13]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/full") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_space_xor_3_111)) + (portref I0 (instanceref f0__n0161_inv1_lut)) + (portref I1 (instanceref f0_GND_14_o_read_OR_37_o1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_write1)) + (portref I1 (instanceref f0_read_state_FSM_FFd1_In111)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst)) + (portref I2 (instanceref f0_read_state_FSM_FFd2_In1)) + (portref I2 (instanceref f0_full_reg_glue_set)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7__num_packets_7__mux_17_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[7]_num_packets[7]_mux_17_OUT[5]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_5)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr[1]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full921)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01217)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01215)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01218)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[14]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tdata_10_ "slave_fifo32/ctrl_rx_tdata[10]") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT210)) + (portref (member DOB 21) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7__num_packets_7__mux_17_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[7]_num_packets[7]_mux_17_OUT[6]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_6)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr[2]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_2)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01217)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01215)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01218)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[15]") (joined + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[0]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tdata_11_ "slave_fifo32/ctrl_rx_tdata[11]") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT33)) + (portref (member DOB 20) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7__num_packets_7__mux_17_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[7]_num_packets[7]_mux_17_OUT[7]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr[3]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_3)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012113)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212111)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012111)) + (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[1]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tdata_12_ "slave_fifo32/ctrl_rx_tdata[12]") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT41)) + (portref (member DOB 19) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr[4]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_4)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41)) + (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[2]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0154_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/_n0154_inv") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_0)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_1)) + (portref CE (instanceref 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(instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[3]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tdata_14_ "slave_fifo32/ctrl_rx_tdata[14]") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT61)) + (portref (member DOB 17) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename 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slave_fifo32_debug2_15)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tdata_29_ "slave_fifo32/ctrl_rx_tdata[29]") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT221)) + (portref (member DOB 20) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2)) + ) + ) + (net (rename slave_fifo32_debug1_21_ "slave_fifo32/debug1[21]") (joined + (portref Q (instanceref slave_fifo32_debug1_21)) + (portref D (instanceref slave_fifo32_debug2_21)) + ) + ) + (net (rename slave_fifo32_debug1_16_ "slave_fifo32/debug1[16]") (joined + (portref D (instanceref slave_fifo32_debug2_16)) + (portref O (instanceref f0_i_tready1_INV_0)) + ) + ) + (net (rename slave_fifo32_debug1_22_ "slave_fifo32/debug1[22]") (joined + (portref Q (instanceref slave_fifo32_debug1_22)) + (portref D (instanceref slave_fifo32_debug2_22)) + ) + ) + (net (rename slave_fifo32_debug1_17_ "slave_fifo32/debug1[17]") (joined + (portref D (instanceref slave_fifo32_debug2_17)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_o_tvalid1_INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/full_reg") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT511)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_write1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt__n0074_inv1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg_glue_set)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_debug1_23_ "slave_fifo32/debug1[23]") (joined + (portref Q (instanceref slave_fifo32_debug1_23)) + (portref D (instanceref slave_fifo32_debug2_23)) + (portref I2 (instanceref slave_fifo32_rd_one_rstpot)) + (portref I2 (instanceref slave_fifo32_state_FSM_FFd1_In3_G)) + ) + ) + (net (rename slave_fifo32_debug1_18_ "slave_fifo32/debug1[18]") (joined + (portref Q (instanceref slave_fifo32_debug1_18)) + (portref D (instanceref slave_fifo32_debug2_18)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_)) + ) + ) + (net (rename f0_write "f0/write") (joined + (portref CE (instanceref f0_wr_addr_1)) + (portref CE (instanceref f0_wr_addr_2)) + (portref CE (instanceref f0_wr_addr_3)) + (portref CE (instanceref f0_wr_addr_4)) + (portref CE (instanceref f0_wr_addr_5)) + (portref CE (instanceref f0_wr_addr_6)) + (portref CE (instanceref f0_wr_addr_7)) + (portref CE (instanceref f0_wr_addr_8)) + (portref CE (instanceref f0_wr_addr_9)) + (portref CE (instanceref f0_wr_addr_10)) + (portref CE (instanceref f0_wr_addr_11)) + (portref CE (instanceref f0_wr_addr_12)) + (portref CE (instanceref f0_wr_addr_0)) + (portref O (instanceref f0_write11)) + (portref CE (instanceref f0_Result_0_2_FRB)) + (portref CE (instanceref f0_Result_1_2_FRB)) + (portref CE (instanceref f0_Result_2_2_FRB)) + (portref CE (instanceref f0_Result_3_2_FRB)) + (portref CE (instanceref f0_Result_4_2_FRB)) + (portref CE (instanceref f0_Result_5_2_FRB)) + (portref CE (instanceref f0_Result_6_2_FRB)) + (portref CE (instanceref f0_Result_7_2_FRB)) + (portref CE (instanceref f0_Result_8_2_FRB)) + (portref CE (instanceref f0_Result_9_2_FRB)) + (portref CE (instanceref f0_Result_10_2_FRB)) + (portref CE (instanceref f0_Result_11_2_FRB)) + (portref CE (instanceref f0_Result_12_2_FRB)) + (portref (member WEAWEL 1) (instanceref f0_ram_Mram_ram33)) + (portref (member WEAWEL 0) (instanceref f0_ram_Mram_ram33)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram31)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram31)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram31)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram31)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram30)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram30)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram30)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram30)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram32)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram32)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram32)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram32)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram28)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram28)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram28)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram28)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram27)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram27)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram27)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram27)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram29)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram29)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram29)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram29)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram25)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram25)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram25)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram25)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram24)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram24)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram24)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram24)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram26)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram26)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram26)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram26)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram22)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram22)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram22)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram22)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram21)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram21)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram21)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram21)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram23)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram23)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram23)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram23)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram19)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram19)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram19)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram19)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram18)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram18)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram18)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram18)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram20)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram20)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram20)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram20)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram16)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram16)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram16)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram16)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram15)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram15)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram15)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram15)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram17)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram17)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram17)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram17)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram14)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram14)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram14)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram14)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram13)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram13)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram13)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram13)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram12)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram12)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram12)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram12)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram11)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram11)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram11)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram11)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram9)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram9)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram9)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram9)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram8)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram8)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram8)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram8)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram10)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram10)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram10)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram10)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram6)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram6)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram6)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram6)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram5)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram5)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram5)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram5)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram7)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram7)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram7)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram7)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram3)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram3)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram3)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram3)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram2)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram2)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram2)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram2)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram4)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram4)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram4)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram4)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram1)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram1)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram1)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_debug1_19_ "slave_fifo32/debug1[19]") (joined + (portref Q (instanceref slave_fifo32_debug1_19)) + (portref D (instanceref slave_fifo32_debug2_19)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_8__rt "f0/Mcount_wr_addr_cy<8>_rt") (joined + (portref O (instanceref f0_Mcount_wr_addr_cy_8__rt)) + (portref S (instanceref f0_Mcount_wr_addr_cy_8_)) + (portref LI (instanceref f0_Mcount_wr_addr_xor_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr2_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_2)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr2_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_2__rt)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_)) + ) + ) + (net (rename slave_fifo32_debug1_31_ "slave_fifo32/debug1[31]") (joined + (portref Q (instanceref slave_fifo32_debug1_31)) + (portref D (instanceref slave_fifo32_debug2_31)) + ) + ) + (net (rename slave_fifo32_debug1_26_ "slave_fifo32/debug1[26]") (joined + (portref Q (instanceref slave_fifo32_debug1_26)) + (portref D (instanceref slave_fifo32_debug2_26)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_)) + ) + ) + (net (rename slave_fifo32_debug1_27_ "slave_fifo32/debug1[27]") (joined + (portref Q (instanceref slave_fifo32_debug1_27)) + (portref D (instanceref slave_fifo32_debug2_27)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_0_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[0]") (joined + (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + (portref (member dout 71) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr7_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_7)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr7_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__rt)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_7__INV_0)) + ) + ) + (net (rename slave_fifo32_debug1_28_ "slave_fifo32/debug1[28]") (joined + (portref Q (instanceref slave_fifo32_debug1_28)) + (portref D (instanceref slave_fifo32_debug2_28)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_1_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[1]") (joined + (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + (portref (member dout 70) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_debug1_29_ "slave_fifo32/debug1[29]") (joined + (portref Q (instanceref slave_fifo32_debug1_29)) + (portref D (instanceref slave_fifo32_debug2_29)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_2_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[2]") (joined + (portref (member DIA 29) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + (portref (member dout 69) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_3_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[3]") (joined + (portref (member DIA 28) (instanceref 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dout 66) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_6_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[6]") (joined + (portref (member DIA 25) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + (portref (member dout 65) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f0_Mcount_wr_addr_xor_12__rt "f0/Mcount_wr_addr_xor<12>_rt") (joined + (portref O (instanceref f0_Mcount_wr_addr_xor_12__rt)) + (portref LI (instanceref f0_Mcount_wr_addr_xor_12_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_7_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[7]") (joined + (portref (member DIA 24) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + (portref (member dout 64) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_8_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[8]") (joined + (portref (member DIA 23) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + (portref (member dout 63) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_9_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[9]") (joined + (portref (member DIA 22) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + (portref (member dout 62) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In3") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34)) + ) + ) + (net (rename f1_full_reg "f1/full_reg") (joined + (portref I1 (instanceref f1_write11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW0)) + (portref Q (instanceref f1_full_reg)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111_SW0)) + (portref I4 (instanceref f1_read_state_FSM_FFd2_In1)) + (portref I4 (instanceref f1_full_reg_glue_set)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_31_1 "slave_fifo32/gpif_data_out_31_1") (joined + (portref Q (instanceref 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"f0/Msub_dont_write_past_me_cy[10]") (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_10_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_cy_11_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_xor_11_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr1_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_1)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr1_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1__rt)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_10_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_10_BRB1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_10_BRB1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[10]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_10_BRB1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[11]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_11_BRB1)) + ) + ) + (net (rename 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"f0/dont_write_past_me<0>_FRB") (joined + (portref I1 (instanceref f0_Mcompar_becoming_full_lut_0_)) + (portref Q (instanceref f0_dont_write_past_me_0__FRB)) + ) + ) + (net (rename f1_dont_write_past_me_2__FRB "f1/dont_write_past_me<2>_FRB") (joined + (portref I5 (instanceref f1_Mcompar_becoming_full_lut_0_)) + (portref Q (instanceref f1_dont_write_past_me_2__FRB)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[15]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15_BRB1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[10]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_11_)) + ) + ) + (net (rename f0__n0161_inv "f0/_n0161_inv") (joined + (portref CE (instanceref f0_rd_addr_1)) + (portref CE (instanceref f0_rd_addr_2)) + (portref CE (instanceref f0_rd_addr_3)) + (portref CE (instanceref f0_rd_addr_4)) + (portref CE (instanceref f0_rd_addr_5)) + (portref CE (instanceref f0_rd_addr_6)) + (portref CE (instanceref f0_rd_addr_7)) + (portref CE (instanceref f0_rd_addr_8)) + (portref CE (instanceref f0_rd_addr_9)) + (portref CE (instanceref f0_rd_addr_10)) + (portref CE (instanceref f0_rd_addr_11)) + (portref CE (instanceref f0_rd_addr_12)) + (portref CE (instanceref f0_rd_addr_0)) + (portref CE (instanceref f0_Result_0_1_FRB)) + (portref CE (instanceref f0_Result_1_1_FRB)) + (portref CE (instanceref f0_Result_2_1_FRB)) + (portref CE (instanceref f0_Result_3_1_FRB)) + (portref CE (instanceref f0_Result_4_1_FRB)) + (portref CE (instanceref f0_Result_5_1_FRB)) + (portref CE (instanceref f0_Result_6_1_FRB)) + (portref CE (instanceref f0_Result_7_1_FRB)) + (portref CE (instanceref f0_Result_8_1_FRB)) + (portref CE (instanceref f0_Result_9_1_FRB)) + (portref CE (instanceref f0_Result_10_1_FRB)) + (portref CE (instanceref f0_Result_11_1_FRB)) + (portref CE (instanceref f0_Result_12_1_FRB)) + (portref CE (instanceref f0_dont_write_past_me_0__FRB)) + (portref CE (instanceref f0_dont_write_past_me_1__FRB)) + (portref CE (instanceref f0_dont_write_past_me_2__FRB)) + (portref CE (instanceref f0_dont_write_past_me_3__FRB)) + (portref CE (instanceref f0_dont_write_past_me_4__FRB)) + (portref CE (instanceref f0_dont_write_past_me_5__FRB)) + (portref CE (instanceref f0_dont_write_past_me_6__FRB)) + (portref CE (instanceref f0_dont_write_past_me_7__FRB)) + (portref CE (instanceref f0_dont_write_past_me_8__FRB)) + (portref CE (instanceref f0_dont_write_past_me_9__FRB)) + (portref CE (instanceref f0_dont_write_past_me_10__FRB)) + (portref CE (instanceref f0_dont_write_past_me_11__FRB)) + (portref CE (instanceref f0_dont_write_past_me_12__FRB)) + (portref O (instanceref f0__n0161_inv1_cy1)) + ) + ) + (net cat_ce (joined + (portref O (instanceref cat_ce_OBUF)) + (portref cat_ce) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<0>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a1 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a1") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_0)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_0_11_INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a2 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a2") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_1_11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a3 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a3") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_2)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_2_11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In11") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In12)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14)) + ) + ) + (net (rename f1_Mcount_rd_addr_xor_12__rt "f1/Mcount_rd_addr_xor<12>_rt") (joined + (portref O (instanceref f1_Mcount_rd_addr_xor_12__rt)) + (portref LI (instanceref f1_Mcount_rd_addr_xor_12_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a4 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a4") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_3)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_3_11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In12") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_read1)) + (portref rd_en (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a5 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a5") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_4)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_4_11)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_7__rt "f1/Mcount_rd_addr_cy<7>_rt") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_7__rt)) + (portref S (instanceref f1_Mcount_rd_addr_cy_7_)) + (portref LI (instanceref f1_Mcount_rd_addr_xor_7_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In31") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In32") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In33)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_12_BRB0") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_12_BRB1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT311 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT311") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_i_tvalid_int "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/i_tvalid_int") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT511)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_write1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_4_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_)) + (portref S (instanceref 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"slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[22]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT151)) + (portref D (instanceref slave_fifo32_gpif_data_out_22)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_18_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[18]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT101)) + (portref D (instanceref slave_fifo32_gpif_data_out_18)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_23_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[23]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT161)) + (portref D (instanceref slave_fifo32_gpif_data_out_23)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tvalid_data_rx_tvalid_OR_56_o "slave_fifo32/ctrl_rx_tvalid_data_rx_tvalid_OR_56_o") (joined + (portref D (instanceref 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"slave_fifo32/pktend") (joined + (portref Q (instanceref slave_fifo32_pktend)) + (portref I (instanceref GPIF_CTL7_OBUF)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_26_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[26]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT191)) + (portref D (instanceref slave_fifo32_gpif_data_out_26)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_31_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[31]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT251)) + (portref I2 (instanceref slave_fifo32_gpif_data_out_31_rstpot)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr11_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr11_FRB") (joined + (portref D (instanceref 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(instanceref f0_Result_2_1_FRB)) + (portref O (instanceref f0_Mcount_rd_addr_xor_2_)) + ) + ) + (net N252 (joined + (portref D (instanceref f1_Result_8_2_FRB)) + (portref O (instanceref f1_Mcount_wr_addr_xor_8_)) + ) + ) + (net N247 (joined + (portref D (instanceref f1_Result_3_2_FRB)) + (portref O (instanceref f1_Mcount_wr_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_3_)) + ) + ) + (net N198 (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr10_FRB)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_10_)) + ) + ) + (net N303 (joined + (portref D (instanceref f0_Result_3_1_FRB)) + (portref O (instanceref f0_Mcount_rd_addr_xor_3_)) + ) + ) + (net N253 (joined + (portref D (instanceref f1_Result_9_2_FRB)) + (portref O (instanceref f1_Mcount_wr_addr_xor_9_)) + ) + ) + (net N248 (joined + (portref D (instanceref f1_Result_4_2_FRB)) + (portref O (instanceref f1_Mcount_wr_addr_xor_4_)) + ) + ) + (net N199 (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr11_FRB)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_11_)) + ) + ) + (net N304 (joined + (portref D (instanceref f0_Result_4_1_FRB)) + (portref O (instanceref f0_Mcount_rd_addr_xor_4_)) + ) + ) + (net N254 (joined + (portref D (instanceref f1_Result_10_2_FRB)) + (portref O (instanceref f1_Mcount_wr_addr_xor_10_)) + ) + ) + (net N249 (joined + (portref D (instanceref f1_Result_5_2_FRB)) + (portref O (instanceref f1_Mcount_wr_addr_xor_5_)) + ) + ) + (net N255 (joined + (portref D (instanceref f1_Result_11_2_FRB)) + (portref O (instanceref f1_Mcount_wr_addr_xor_11_)) + ) + ) + (net N310 (joined + (portref D (instanceref f0_Result_10_1_FRB)) + (portref O (instanceref f0_Mcount_rd_addr_xor_10_)) + ) + ) + (net N305 (joined + (portref D (instanceref f0_Result_5_1_FRB)) + (portref O (instanceref f0_Mcount_rd_addr_xor_5_)) + ) + ) + (net N260 (joined + (portref D (instanceref f1_Result_2_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_2_)) + ) + ) + (net N256 (joined + (portref O (instanceref f1_Mcount_wr_addr_cy_11_)) + (portref CI (instanceref f1_Mcount_wr_addr_xor_12_)) + ) + ) + (net N311 (joined + (portref D (instanceref f0_Result_11_1_FRB)) + (portref O (instanceref f0_Mcount_rd_addr_xor_11_)) + ) + ) + (net N306 (joined + (portref D (instanceref f0_Result_6_1_FRB)) + (portref O (instanceref f0_Mcount_rd_addr_xor_6_)) + ) + ) + (net N261 (joined + (portref D (instanceref f1_Result_3_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_4_)) + ) + ) + (net N312 (joined + (portref O (instanceref f0_Mcount_rd_addr_cy_11_)) + (portref CI (instanceref f0_Mcount_rd_addr_xor_12_)) + ) + ) + (net N307 (joined + (portref D (instanceref f0_Result_7_1_FRB)) + (portref O (instanceref f0_Mcount_rd_addr_xor_7_)) + ) + ) + (net N262 (joined + (portref D (instanceref f1_Result_4_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_4_)) + ) + ) + (net N257 (joined + (portref D (instanceref f1_Result_12_2_FRB)) + (portref O (instanceref f1_Mcount_wr_addr_xor_12_)) + ) + ) + (net (rename f0_Result_3_1_FRB "f0/Result<3>1_FRB") (joined + (portref D (instanceref f0_rd_addr_3)) + (portref Q (instanceref f0_Result_3_1_FRB)) + (portref I0 (instanceref f0_Mcount_rd_addr_cy_3__rt)) + (portref I0 (instanceref f0_Msub_dont_write_past_me_lut_3__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<7>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_7_)) + ) + ) + (net N313 (joined + (portref D (instanceref f0_Result_12_1_FRB)) + (portref O (instanceref f0_Mcount_rd_addr_xor_12_)) + ) + ) + (net N308 (joined + (portref D (instanceref f0_Result_8_1_FRB)) + (portref O (instanceref f0_Mcount_rd_addr_xor_8_)) + ) + ) + (net N263 (joined + (portref D (instanceref f1_Result_5_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_5_)) + ) + ) + (net N258 (joined + (portref D (instanceref f1_Result_0_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_0_)) + ) + ) + (net N259 (joined + (portref D (instanceref f1_Result_1_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_1_)) + ) + ) + (net N314 (joined + (portref D (instanceref f0_dont_write_past_me_0__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_0_)) + ) + ) + (net N309 (joined + (portref D (instanceref f0_Result_9_1_FRB)) + (portref O (instanceref f0_Mcount_rd_addr_xor_9_)) + ) + ) + (net N264 (joined + (portref D (instanceref f1_Result_6_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_6_)) + ) + ) + (net N265 (joined + (portref D (instanceref f1_Result_7_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_7_)) + ) + ) + (net N320 (joined + (portref D (instanceref f0_dont_write_past_me_6__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_6_)) + ) + ) + (net N315 (joined + (portref D (instanceref f0_dont_write_past_me_1__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_1_)) + ) + ) + (net N270 (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_11_)) + (portref CI (instanceref f1_Mcount_rd_addr_xor_12_)) + ) + ) + (net N266 (joined + (portref D (instanceref f1_Result_8_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_8_)) + ) + ) + (net N321 (joined + (portref D (instanceref f0_dont_write_past_me_7__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_7_)) + ) + ) + (net N316 (joined + (portref D (instanceref f0_dont_write_past_me_2__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_2_)) + ) + ) + (net N271 (joined + (portref D (instanceref f1_Result_12_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_12_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_5_)) + ) + ) + (net N322 (joined + (portref D (instanceref f0_dont_write_past_me_8__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_8_)) + ) + ) + (net N317 (joined + (portref D (instanceref f0_dont_write_past_me_3__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_3_)) + ) + ) + (net N272 (joined + (portref D (instanceref f1_dont_write_past_me_0__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_0_)) + ) + ) + (net N267 (joined + (portref D (instanceref f1_Result_9_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_9_)) + ) + ) + (net N268 (joined + (portref D (instanceref f1_Result_10_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_10_)) + ) + ) + (net N323 (joined + (portref D (instanceref f0_dont_write_past_me_9__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_9_)) + ) + ) + (net N318 (joined + (portref D (instanceref f0_dont_write_past_me_4__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_4_)) + ) + ) + (net N273 (joined + (portref D (instanceref f1_dont_write_past_me_1__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_1_)) + ) + ) + (net N269 (joined + (portref D (instanceref f1_Result_11_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_11_)) + ) + ) + (net N324 (joined + (portref D (instanceref f0_dont_write_past_me_10__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_10_)) + ) + ) + (net N319 (joined + (portref D (instanceref f0_dont_write_past_me_5__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_5_)) + ) + ) + (net N274 (joined + (portref D (instanceref f1_dont_write_past_me_2__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_2_)) + ) + ) + (net N275 (joined + (portref D (instanceref f1_dont_write_past_me_3__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_3_)) + ) + ) + (net N325 (joined + (portref D (instanceref f0_dont_write_past_me_11__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_11_)) + ) + ) + (net N280 (joined + (portref D (instanceref f1_dont_write_past_me_8__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_8_)) + ) + ) + (net N276 (joined + (portref D (instanceref f1_dont_write_past_me_4__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_4_)) + ) + ) + (net N331 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + ) + ) + (net N326 (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_11_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_xor_12_)) + ) + ) + (net N281 (joined + (portref D (instanceref f1_dont_write_past_me_9__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_9_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_6_)) + ) + ) + (net N332 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + ) + ) + (net N327 (joined + (portref D (instanceref f0_dont_write_past_me_12__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_12_)) + ) + ) + (net N282 (joined + (portref D (instanceref f1_dont_write_past_me_10__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_10_)) + ) + ) + (net N277 (joined + (portref D (instanceref f1_dont_write_past_me_5__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_5_)) + ) + ) + (net N278 (joined + (portref D (instanceref f1_dont_write_past_me_6__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_6_)) + ) + ) + (net N328 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + ) + ) + (net N283 (joined + (portref D (instanceref f1_dont_write_past_me_11__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_11_)) + ) + ) + (net N279 (joined + (portref D (instanceref f1_dont_write_past_me_7__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_7_)) + ) + ) + (net N334 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + ) + ) + (net N329 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + ) + ) + (net N284 (joined + (portref O (instanceref f1_Msub_dont_write_past_me_cy_11_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_xor_12_)) + ) + ) + (net N285 (joined + (portref D (instanceref f1_dont_write_past_me_12__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_12_)) + ) + ) + (net N335 (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1)) + ) + ) + (net N290 (joined + (portref D (instanceref f0_Result_4_2_FRB)) + (portref O (instanceref f0_Mcount_wr_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<6>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_6_)) + ) + ) + (net N291 (joined + (portref D (instanceref f0_Result_5_2_FRB)) + (portref O (instanceref f0_Mcount_wr_addr_xor_5_)) + ) + ) + (net N286 (joined + (portref D (instanceref f0_Result_0_2_FRB)) + (portref O (instanceref f0_Mcount_wr_addr_xor_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_7_)) + ) + ) + (net N337 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror11)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast1)) + ) + ) + (net N292 (joined + (portref D (instanceref f0_Result_6_2_FRB)) + (portref O (instanceref f0_Mcount_wr_addr_xor_6_)) + ) + ) + (net N287 (joined + (portref D (instanceref f0_Result_1_2_FRB)) + (portref O (instanceref f0_Mcount_wr_addr_xor_1_)) + ) + ) + (net N288 (joined + (portref D (instanceref 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slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_8_)) + ) + ) + (net N347 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71)) + ) + ) + (net N297 (joined + (portref D (instanceref f0_Result_11_2_FRB)) + (portref O (instanceref f0_Mcount_wr_addr_xor_11_)) + ) + ) + (net N298 (joined + (portref O (instanceref f0_Mcount_wr_addr_cy_11_)) + (portref CI (instanceref f0_Mcount_wr_addr_xor_12_)) + ) + ) + (net N353 (joined + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2)) + ) + ) + (net N299 (joined + (portref D (instanceref f0_Result_12_2_FRB)) + (portref O (instanceref f0_Mcount_wr_addr_xor_12_)) + ) + ) + (net N354 (joined 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slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_9_)) + ) + ) + (net N407 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + ) + ) + (net N357 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1)) + (portref I2 (instanceref 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(portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2)) + ) + ) + (net N415 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_SW0)) + ) + ) + (net N370 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW0)) + ) + ) + (net N421 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + ) + ) + (net N417 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11)) + ) + ) + (net N372 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set)) + ) + ) + (net N367 (joined + (portref O (instanceref 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(instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2_)) + ) + ) + (net N441 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10)) + ) + ) + (net N391 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot)) + ) + ) + (net N386 (joined + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_SW0)) + ) + ) + (net N437 (joined + (portref O (instanceref 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(joined + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_SW0)) + ) + ) + (net N439 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In12_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13)) + ) + ) + (net N445 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[2]") (joined + (portref O (instanceref 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slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + ) + ) + (net N397 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + ) + ) + (net N447 (joined + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW1)) + ) + ) + (net N453 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW2)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/clear_inv") (joined + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__GND_50_o_mux_35_OUT_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_GND_50_o_mux_35_OUT[0]") (joined + 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+ ) + (net N458 (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr1_FRB)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_1_)) + ) + ) + (net N463 (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr6_FRB)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_6_)) + ) + ) + (net N459 (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr2_FRB)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_2_)) + ) + ) + (net N464 (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr7_FRB)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_7_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__GND_50_o_mux_35_OUT_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_GND_50_o_mux_35_OUT[1]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81)) + ) + ) + (net N470 (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr3_FRB)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_3_)) + ) + ) + (net N465 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[4]") (joined + (portref O (instanceref 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slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6_)) + ) + ) + (net N481 (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0)) + ) + ) + (net N476 (joined + (portref D (instanceref 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"slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_GND_50_o_mux_35_OUT[3]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_3)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101)) + ) + ) + (net N485 (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0_FRB)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7_)) + ) + ) + (net N543 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__GND_50_o_mux_35_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_GND_50_o_mux_35_OUT[4]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_4)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111)) + ) + ) + (net N550 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0)) + ) + ) + (net N545 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_F)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8_)) + ) + ) + (net N551 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1)) + ) + ) + (net N546 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_G)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2)) + ) + ) + (net N547 (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_F)) + ) + ) + (net N552 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1)) + ) + ) + (net N548 (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_G)) + ) + ) + (net N553 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1)) + ) + ) + (net N549 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0)) + ) + ) + (net N554 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_G)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__GND_50_o_mux_35_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_GND_50_o_mux_35_OUT[5]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_5)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9_)) + ) + ) + (net N561 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst)) + ) + ) + (net N563 (joined + (portref O (instanceref slave_fifo32_slrd_rstpot_SW0)) + (portref I1 (instanceref slave_fifo32_slrd_rstpot)) + ) + ) + (net N559 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__GND_50_o_mux_35_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_GND_50_o_mux_35_OUT[6]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_6)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131)) + ) + ) + (net N565 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10_)) + ) + ) + (net N571 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9)) + ) + ) + (net N567 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215)) + ) + ) + (net N573 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1)) + ) + ) + (net N569 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT17)) + ) + ) + (net N575 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__GND_50_o_mux_35_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_GND_50_o_mux_35_OUT[7]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_7)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT141)) + ) + ) + (net N581 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1_SW1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1)) + ) + ) + (net N577 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set)) + ) + ) + (net N583 (joined + (portref O (instanceref slave_fifo32_state_FSM_FFd1_In3_F)) + (portref I0 (instanceref slave_fifo32_state_FSM_FFd1_In3)) + ) + ) + (net N579 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1_SW1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1)) + ) + ) + (net N584 (joined + (portref O (instanceref slave_fifo32_state_FSM_FFd1_In3_G)) + (portref I1 (instanceref slave_fifo32_state_FSM_FFd1_In3)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81)) + ) + ) + (net N590 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2)) + ) + ) + (net N585 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_F)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__GND_50_o_mux_35_OUT_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_GND_50_o_mux_35_OUT[8]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_8)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT151)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set)) + ) + ) + (net N586 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_G)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14)) + ) + ) + (net N587 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_F)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1)) + ) + ) + (net N588 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_G)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01215") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01217_SW0)) + ) + ) + (net N589 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_F)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_12__wr_addr_12__equal_11_o "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[12]_wr_addr[12]_equal_11_o") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_cy)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__inv_INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT141)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT151)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr5_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_5)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_9_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_9_BRB1)) + ) + ) + (net (rename f0_Result_1_2_FRB "f0/Result<1>2_FRB") (joined + (portref D (instanceref f0_wr_addr_1)) + (portref Q (instanceref f0_Result_1_2_FRB)) + (portref I0 (instanceref f0_Mcount_wr_addr_cy_1__rt)) + ) + ) + (net (rename f0_dont_write_past_me_8__FRB "f0/dont_write_past_me<8>_FRB") (joined + (portref I5 (instanceref f0_Mcompar_becoming_full_lut_2_)) + (portref Q (instanceref f0_dont_write_past_me_8__FRB)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_2_)) + ) + ) + (net (rename f0__n0161_inv1_lut1 "f0/_n0161_inv1_lut1") (joined + (portref O (instanceref f0__n0161_inv1_lut1)) + (portref S (instanceref f0__n0161_inv1_cy1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_4_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_4_)) + ) + ) + (net pps_fpga_out_enable (joined + (portref O (instanceref pps_fpga_out_enable_OBUF)) + (portref pps_fpga_out_enable) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_5_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_5_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_6_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_6_)) + ) + ) + (net (rename slave_fifo32_debug2_10_ "slave_fifo32/debug2[10]") (joined + (portref Q (instanceref slave_fifo32_debug2_10)) + (portref I (instanceref debug_10_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_7_)) + ) + ) + (net (rename slave_fifo32_debug2_11_ "slave_fifo32/debug2[11]") (joined + (portref Q (instanceref slave_fifo32_debug2_11)) + (portref I (instanceref debug_11_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_8_)) + ) + ) + (net (rename slave_fifo32_debug2_12_ "slave_fifo32/debug2[12]") (joined + (portref Q (instanceref slave_fifo32_debug2_12)) + (portref I (instanceref debug_12_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_9_)) + ) + ) + (net (rename slave_fifo32_debug2_13_ "slave_fifo32/debug2[13]") (joined + (portref Q (instanceref slave_fifo32_debug2_13)) + (portref I (instanceref debug_13_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_0)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0__rt)) + ) + ) + (net (rename slave_fifo32_debug2_14_ "slave_fifo32/debug2[14]") (joined + (portref Q (instanceref slave_fifo32_debug2_14)) + (portref I (instanceref debug_14_OBUF)) + ) + ) + (net (rename slave_fifo32_debug2_15_ "slave_fifo32/debug2[15]") (joined + (portref Q (instanceref slave_fifo32_debug2_15)) + (portref I (instanceref debug_15_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_0_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr[0]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01216_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_debug2_16_ "slave_fifo32/debug2[16]") (joined + (portref Q (instanceref slave_fifo32_debug2_16)) + (portref I (instanceref debug_16_OBUF)) + ) + ) + (net (rename slave_fifo32_debug2_21_ "slave_fifo32/debug2[21]") (joined + (portref Q (instanceref slave_fifo32_debug2_21)) + (portref I (instanceref debug_21_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_1_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr[1]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full1021)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01216_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_debug2_17_ "slave_fifo32/debug2[17]") (joined + (portref Q (instanceref slave_fifo32_debug2_17)) + (portref I (instanceref debug_17_OBUF)) + ) + ) + (net (rename slave_fifo32_debug2_22_ "slave_fifo32/debug2[22]") (joined + (portref Q (instanceref slave_fifo32_debug2_22)) + (portref I (instanceref debug_22_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_2_ 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slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr9") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_9_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_9)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__16_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][16]") (joined + (portref (member DOB 15) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 55) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__21_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][21]") (joined + (portref (member DOB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 50) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__17_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][17]") (joined + (portref (member DOB 14) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 54) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__22_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][22]") (joined + (portref (member DOB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 49) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__18_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][18]") (joined + (portref (member DOB 13) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 53) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__23_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][23]") (joined + (portref (member DOB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 48) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2-In1") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In11)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In13)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__19_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][19]") (joined + (portref (member DOB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 52) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__24_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][24]") (joined + (portref (member DOB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 47) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__30_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][30]") (joined + (portref (member DOB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 41) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__25_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][25]") (joined + (portref (member DOB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 46) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__26_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][26]") (joined + (portref (member DOB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 45) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__31_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][31]") (joined + (portref (member DOB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 40) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr2_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_2)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr2_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__32_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][32]") (joined + (portref (member DOPB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 39) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__27_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][27]") (joined + (portref (member DOB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 44) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net codec_en_agc (joined + (portref O (instanceref codec_en_agc_OBUF)) + (portref codec_en_agc) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__28_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][28]") (joined + (portref (member DOB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 43) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv31)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_glue_set)) + (portref D (instanceref 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(member ADDRA 1) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_0_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0_)) + ) + ) + (net (rename slave_fifo32_wr_one_rstpot "slave_fifo32/wr_one_rstpot") (joined + (portref D (instanceref slave_fifo32_wr_one)) + (portref O (instanceref slave_fifo32_wr_one_rstpot)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_GND_56_o_read_OR_123_o "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/GND_56_o_read_OR_123_o") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_GND_56_o_read_OR_123_o1)) + (portref ENBRDEN (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_12_ "f1/wr_addr[12]") (joined + (portref Q (instanceref f1_wr_addr_12)) + (portref I1 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_)) + (portref I0 (instanceref f1_Mcompar_becoming_full_lut_4_)) + (portref (member ADDRAWRADDR 0) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_1_)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01211_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set)) + ) + ) + (net (rename slave_fifo32_state_FSM_FFd1_In "slave_fifo32/state_FSM_FFd1-In") (joined + (portref D (instanceref slave_fifo32_state_FSM_FFd1)) + (portref O (instanceref slave_fifo32_state_FSM_FFd1_In4)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_2_)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_4_)) + ) + ) + (net (rename f1_Mcount_wr_addr_xor_12__rt "f1/Mcount_wr_addr_xor<12>_rt") (joined + (portref O (instanceref f1_Mcount_wr_addr_xor_12__rt)) + (portref LI (instanceref f1_Mcount_wr_addr_xor_12_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_3_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[0]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01216)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_4_)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[1]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full921)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01218)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_debug1_16_BRB0 "slave_fifo32/debug1_16_BRB0") (joined + (portref Q (instanceref slave_fifo32_debug1_16_BRB0)) + (portref I0 (instanceref f0_i_tready1_INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_5_)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[2]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_2)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01218)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tvalid "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tvalid") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tvalid11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_6_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[3]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_3)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012113)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_7_)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1_In11)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0144_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[4]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_4)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_8_)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[5]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_5)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[6]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_6)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0121111)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[7]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_7)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1)) + (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9)) + ) + ) + (net SRX1_RX (joined + (portref O (instanceref SRX1_RX_OBUF)) + (portref SRX1_RX) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<1>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_1_)) + ) + ) + (net SRX1_TX (joined + (portref O (instanceref SRX1_TX_OBUF)) + (portref SRX1_TX) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<0>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_2_)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_8__rt "f1/Mcount_rd_addr_cy<8>_rt") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_8__rt)) + (portref S (instanceref f1_Mcount_rd_addr_cy_8_)) + (portref LI (instanceref f1_Mcount_rd_addr_xor_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_5_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_6_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_7_)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_10_ "f0/Msub_dont_write_past_me_lut[10]") (joined + (portref S (instanceref f0_Msub_dont_write_past_me_cy_10_)) + (portref LI (instanceref f0_Msub_dont_write_past_me_xor_10_)) + (portref O (instanceref f0_Msub_dont_write_past_me_lut_10__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT[0]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_0)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT17)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_11_ "f0/Msub_dont_write_past_me_lut[11]") (joined + (portref S (instanceref f0_Msub_dont_write_past_me_cy_11_)) + (portref LI (instanceref f0_Msub_dont_write_past_me_xor_11_)) + (portref O (instanceref f0_Msub_dont_write_past_me_lut_11__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/dump") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv1_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6)) + (portref I2 (instanceref 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slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT[1]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_12_ "f0/Msub_dont_write_past_me_lut[12]") (joined + (portref LI (instanceref f0_Msub_dont_write_past_me_xor_12_)) + (portref O (instanceref f0_Msub_dont_write_past_me_lut_12__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_full "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/full") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_write1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_i_tready1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_111)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state_glue_set)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set)) + (portref full (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_4__rt "f0/Mcount_rd_addr_cy<4>_rt") (joined + (portref O (instanceref f0_Mcount_rd_addr_cy_4__rt)) + (portref S (instanceref f0_Mcount_rd_addr_cy_4_)) + (portref LI (instanceref f0_Mcount_rd_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT[2]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_2)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91)) + ) + ) + (net (rename slave_fifo32_state_FSM_FFd2_In "slave_fifo32/state_FSM_FFd2-In") (joined + (portref D (instanceref slave_fifo32_state_FSM_FFd2)) + (portref O (instanceref slave_fifo32_state_FSM_FFd2_In3)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT[3]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_3)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT[4]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_4)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT[5]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_5)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_glue_set "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/state_glue_set") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_glue_set)) + ) + ) + (net (rename f1_Mcompar_becoming_full_cy_0_ "f1/Mcompar_becoming_full_cy[0]") (joined + (portref O (instanceref f1_Mcompar_becoming_full_cy_0_)) + (portref CI (instanceref f1_Mcompar_becoming_full_cy_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT[6]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_6)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131)) + ) + ) + (net (rename f1_Mcompar_becoming_full_cy_1_ "f1/Mcompar_becoming_full_cy[1]") (joined + (portref O (instanceref f1_Mcompar_becoming_full_cy_1_)) + (portref CI (instanceref f1_Mcompar_becoming_full_cy_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy[10]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10_)) + (portref CI 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slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0_)) + ) + ) + (net SRX2_RX (joined + (portref O (instanceref SRX2_RX_OBUF)) + (portref SRX2_RX) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[2]") (joined + (portref O (instanceref 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"debug[18]") (joined + (portref O (instanceref debug_18_OBUF)) + (portref (member debug 13)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<9>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut[9]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_9_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_9_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_9_)) + ) + ) + (net (rename debug_24_ "debug[24]") (joined + (portref O (instanceref debug_24_OBUF)) + (portref (member debug 7)) + ) + ) + (net (rename debug_19_ "debug[19]") (joined + (portref O (instanceref debug_19_OBUF)) + (portref (member debug 12)) + ) + ) + (net (rename debug_30_ "debug[30]") (joined + (portref O (instanceref debug_30_OBUF)) + (portref (member debug 1)) + ) + ) + (net (rename debug_25_ "debug[25]") (joined + (portref O (instanceref debug_25_OBUF)) + (portref (member debug 6)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_xfer_Mux_21_o "slave_fifo32/state[1]_wr_fifo_xfer_Mux_21_o") (joined + (portref D (instanceref slave_fifo32_slwr)) + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1)) + (portref D (instanceref slave_fifo32_slwr_1)) + ) + ) + (net (rename debug_31_ "debug[31]") (joined + (portref O (instanceref debug_31_OBUF)) + (portref (member debug 0)) + ) + ) + (net (rename debug_26_ "debug[26]") (joined + (portref O (instanceref debug_26_OBUF)) + (portref (member debug 5)) + ) + ) + (net (rename debug_27_ "debug[27]") (joined + (portref O (instanceref debug_27_OBUF)) + (portref (member debug 4)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr1") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr2") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_2_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr3") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_3_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_3)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr4") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_4_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_4)) + ) + ) + (net (rename debug_28_ "debug[28]") (joined + (portref O (instanceref debug_28_OBUF)) + (portref (member debug 3)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr5") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_5_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_5)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr6") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_6_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_2)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_3)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_4)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_5)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_6)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr7") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_7_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_7)) + ) + ) + (net (rename f1_Result_1_1_FRB "f1/Result<1>1_FRB") (joined + (portref D (instanceref f1_rd_addr_1)) + (portref Q (instanceref f1_Result_1_1_FRB)) + (portref I0 (instanceref f1_Mcount_rd_addr_cy_1__rt)) + (portref I0 (instanceref f1_Msub_dont_write_past_me_cy_1__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr8 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr8") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_8_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_8)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr9") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_9_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_9)) + ) + ) + (net (rename debug_29_ "debug[29]") (joined + (portref O (instanceref debug_29_OBUF)) + (portref (member debug 2)) + ) + ) + (net (rename debug_clk_0_ "debug_clk[0]") (joined + (portref O (instanceref debug_clk_0_OBUF)) + (portref (member debug_clk 1)) + ) + ) + (net (rename debug_clk_1_ "debug_clk[1]") (joined + (portref O (instanceref debug_clk_1_OBUF)) + (portref (member debug_clk 0)) + ) + ) + (net rx_bandsel_a (joined + (portref O (instanceref rx_bandsel_a_OBUF)) + (portref rx_bandsel_a) + ) + ) + (net rx_bandsel_b (joined + (portref O (instanceref rx_bandsel_b_OBUF)) + (portref rx_bandsel_b) + ) + ) + (net rx_bandsel_c (joined + (portref O (instanceref rx_bandsel_c_OBUF)) + (portref rx_bandsel_c) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror11)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_dont_write_past_me_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/dont_write_past_me[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n012110_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr1_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_1)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr1_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_1__rt)) + ) + ) + (net gps_out_enable (joined + (portref O (instanceref gps_out_enable_OBUF)) + (portref gps_out_enable) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr6_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_6)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[0]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int13)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_space_xor<3>11") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_2_11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_1_11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_3_11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_4_11)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_111)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[1]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int13)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[2]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[3]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[4]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_4_)) + ) + ) + (net SFDX1_RX (joined + (portref O (instanceref SFDX1_RX_OBUF)) + (portref SFDX1_RX) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full61 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full61") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full611)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_9_11)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_G)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_F)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[5]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_5_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full62 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full62") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full621)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_9_11)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_G)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_F)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[6]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_6_1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1)) + (portref I5 (instanceref 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"slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_GND_56_o_read_OR_123_o1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo__n0146_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tvalid "slave_fifo32/fifo64_to_gpmc32_tx/o64_tvalid") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tvalid11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst)) + (portref I3 (instanceref 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(portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_12_)) + ) + ) + (net (rename f1_dont_write_past_me_11__FRB "f1/dont_write_past_me<11>_FRB") (joined + (portref I5 (instanceref f1_Mcompar_becoming_full_lut_3_)) + (portref Q (instanceref f1_dont_write_past_me_11__FRB)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy[12]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_12_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_13_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_13_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy[13]") (joined + (portref O (instanceref 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+ ) + ) + (net (rename slave_fifo32_gpif_data_in_0_ "slave_fifo32/gpif_data_in[0]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_in_0)) + (portref D (instanceref slave_fifo32_debug1_0)) + (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tvalid "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tvalid") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_i_tvalid_o_tready_AND_73_o1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_glue_set)) + (portref I2 (instanceref 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slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32__n0279_inv "slave_fifo32/_n0279_inv") (joined + (portref O (instanceref slave_fifo32__n0279_inv)) + (portref D (instanceref slave_fifo32_rd_one_BRB0)) + ) + ) + (net (rename slave_fifo32_gpif_data_in_3_ "slave_fifo32/gpif_data_in[3]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_in_3)) + (portref D (instanceref slave_fifo32_debug1_3)) + (portref (member DIA 28) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member DIA 28) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/GND_66_o_read_OR_144_o") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o1)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr4_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_4)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr4_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4__rt)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621)) + ) + ) + (net (rename slave_fifo32_gpif_data_in_4_ "slave_fifo32/gpif_data_in[4]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_in_4)) + (portref D (instanceref slave_fifo32_debug1_4)) + (portref (member DIA 27) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member DIA 27) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty") (joined + (portref I0 (instanceref f1_write11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW0)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_SW0)) + (portref I3 (instanceref f1_read_state_FSM_FFd2_In1)) + (portref I0 (instanceref f1_full_reg_glue_set)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0_)) + ) + ) + (net (rename slave_fifo32_gpif_data_in_5_ "slave_fifo32/gpif_data_in[5]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_in_5)) + (portref D (instanceref slave_fifo32_debug1_5)) + (portref (member DIA 26) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member DIA 26) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr9_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr9_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_9)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr9_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9__rt)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_9__INV_0)) + ) + ) + (net (rename slave_fifo32_gpif_data_in_6_ "slave_fifo32/gpif_data_in[6]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_in_6)) + (portref D (instanceref slave_fifo32_debug1_6)) + (portref (member DIA 25) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member DIA 25) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[0]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0)) + ) + ) + (net (rename slave_fifo32_gpif_data_in_7_ "slave_fifo32/gpif_data_in[7]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_in_7)) + (portref D (instanceref slave_fifo32_debug1_7)) + (portref (member DIA 24) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member DIA 24) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[1]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + ) + ) + (net (rename slave_fifo32_gpif_data_in_8_ "slave_fifo32/gpif_data_in[8]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_in_8)) + (portref D (instanceref slave_fifo32_debug1_8)) + (portref (member DIA 23) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member DIA 23) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[2]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + ) + ) + (net (rename slave_fifo32_gpif_data_in_9_ "slave_fifo32/gpif_data_in[9]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_in_9)) + (portref D (instanceref slave_fifo32_debug1_9)) + (portref (member DIA 22) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member DIA 22) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_5_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[3]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_6_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[4]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_7_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[5]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6)) + ) + ) + (net SFDX2_RX (joined + (portref O (instanceref SFDX2_RX_OBUF)) + (portref SFDX2_RX) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[6]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_2_ "f0/Msub_dont_write_past_me_lut[2]") (joined + (portref S (instanceref f0_Msub_dont_write_past_me_cy_2_)) + (portref LI (instanceref f0_Msub_dont_write_past_me_xor_2_)) + (portref O (instanceref f0_Msub_dont_write_past_me_lut_2__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_0_ "f0/Msub_dont_write_past_me_cy[0]") (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_0_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_cy_1_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_xor_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_9_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[7]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_3_ "f0/Msub_dont_write_past_me_lut[3]") (joined + (portref S (instanceref f0_Msub_dont_write_past_me_cy_3_)) + (portref LI (instanceref f0_Msub_dont_write_past_me_xor_3_)) + (portref O (instanceref f0_Msub_dont_write_past_me_lut_3__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_1_ "f0/Msub_dont_write_past_me_cy[1]") (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_1_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_cy_2_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_xor_2_)) + ) + ) + (net SFDX2_TX (joined + (portref O (instanceref SFDX2_TX_OBUF)) + (portref SFDX2_TX) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_full "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/full") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_i_tready1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_write1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_space_xor_3_111)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_glue_set)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set)) + (portref full (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_4_ "f0/Msub_dont_write_past_me_lut[4]") (joined + (portref S (instanceref f0_Msub_dont_write_past_me_cy_4_)) + (portref LI (instanceref f0_Msub_dont_write_past_me_xor_4_)) + (portref O (instanceref f0_Msub_dont_write_past_me_lut_4__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_2_ "f0/Msub_dont_write_past_me_cy[2]") (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_2_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_cy_3_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_xor_3_)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_5_ "f0/Msub_dont_write_past_me_lut[5]") (joined + (portref S (instanceref f0_Msub_dont_write_past_me_cy_5_)) + (portref LI (instanceref f0_Msub_dont_write_past_me_xor_5_)) + (portref O (instanceref f0_Msub_dont_write_past_me_lut_5__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_3_ "f0/Msub_dont_write_past_me_cy[3]") (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_3_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_cy_4_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o5 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o5") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01213)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o7 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o7") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr3_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_3)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr3_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o8 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o8") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012112)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_6_ "f0/Msub_dont_write_past_me_lut[6]") (joined + (portref S (instanceref f0_Msub_dont_write_past_me_cy_6_)) + (portref LI (instanceref f0_Msub_dont_write_past_me_xor_6_)) + (portref O (instanceref f0_Msub_dont_write_past_me_lut_6__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_4_ "f0/Msub_dont_write_past_me_cy[4]") (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_4_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_cy_5_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_xor_5_)) + ) + ) + (net (rename slave_fifo32_write_ready_go "slave_fifo32/write_ready_go") (joined + (portref Q (instanceref slave_fifo32_write_ready_go)) + (portref I1 (instanceref slave_fifo32__n0258_inv_SW0)) + (portref I0 (instanceref slave_fifo32__n0279_inv_SW0)) + (portref I5 (instanceref slave_fifo32_state_FSM_FFd2_In2)) + (portref I4 (instanceref slave_fifo32_state_FSM_FFd1_In3_F)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_7_ "f0/Msub_dont_write_past_me_lut[7]") (joined + (portref S (instanceref f0_Msub_dont_write_past_me_cy_7_)) + (portref LI (instanceref f0_Msub_dont_write_past_me_xor_7_)) + (portref O (instanceref f0_Msub_dont_write_past_me_lut_7__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_5_ "f0/Msub_dont_write_past_me_cy[5]") (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_5_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_cy_6_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_xor_6_)) + ) + ) + (net (rename debug_0_ "debug[0]") (joined + (portref O (instanceref debug_0_OBUF)) + (portref (member debug 31)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_8_ "f0/Msub_dont_write_past_me_lut[8]") (joined + (portref S (instanceref f0_Msub_dont_write_past_me_cy_8_)) + (portref LI (instanceref f0_Msub_dont_write_past_me_xor_8_)) + (portref O (instanceref f0_Msub_dont_write_past_me_lut_8__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_6_ "f0/Msub_dont_write_past_me_cy[6]") (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_6_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_cy_7_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_xor_7_)) + ) + ) + (net (rename debug_1_ "debug[1]") (joined + (portref O (instanceref debug_1_OBUF)) + (portref (member debug 30)) + ) + ) + (net fx3_ce (joined + (portref I (instanceref fx3_ce_IBUF)) + (portref fx3_ce) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_9_ "f0/Msub_dont_write_past_me_lut[9]") (joined + (portref S (instanceref f0_Msub_dont_write_past_me_cy_9_)) + (portref LI (instanceref f0_Msub_dont_write_past_me_xor_9_)) + (portref O (instanceref f0_Msub_dont_write_past_me_lut_9__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_7_ "f0/Msub_dont_write_past_me_cy[7]") (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_7_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_cy_8_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_xor_8_)) + ) + ) + (net (rename debug_2_ "debug[2]") (joined + (portref O (instanceref debug_2_OBUF)) + (portref (member debug 29)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_8_ "f0/Msub_dont_write_past_me_cy[8]") (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_8_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_cy_9_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_xor_9_)) + ) + ) + (net (rename debug_3_ "debug[3]") (joined + (portref O (instanceref debug_3_OBUF)) + (portref (member debug 28)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_9_ "f0/Msub_dont_write_past_me_cy[9]") (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_9_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_cy_10_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_xor_10_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr3_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_3)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr3_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3__rt)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621)) + ) + ) + (net (rename debug_4_ "debug[4]") (joined + (portref O (instanceref debug_4_OBUF)) + (portref (member debug 27)) + ) + ) + (net (rename debug_5_ "debug[5]") (joined + (portref O (instanceref debug_5_OBUF)) + (portref (member debug 26)) + ) + ) + (net (rename debug_6_ "debug[6]") (joined + (portref O (instanceref debug_6_OBUF)) + (portref (member debug 25)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_5_)) + ) + ) + (net (rename debug_7_ "debug[7]") (joined + (portref O (instanceref debug_7_OBUF)) + (portref (member debug 24)) + ) + ) + (net (rename debug_8_ "debug[8]") (joined + (portref O (instanceref debug_8_OBUF)) + (portref (member debug 23)) + ) + ) + (net (rename debug_9_ "debug[9]") (joined + (portref O (instanceref debug_9_OBUF)) + (portref (member debug 22)) + ) + ) + ) + + (property TYPE (string "b200")) + (property BUS_INFO (string "32:INOUT:GPIF_D<31:0>")) + (property SHREG_MIN_SIZE (string "2")) + (property X_CORE_INFO (string "fifo_generator_v9_3, Xilinx CORE Generator 14.4")) + (property CORE_GENERATION_INFO (string "b200_clk_gen,clk_wiz_v3_6,{component_name=b200_clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=3,clkin1_period=25.0,clkin2_period=25.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}")) + (property SHREG_EXTRACT_NGC (string "YES")) + (property NLW_UNIQUE_ID (integer 0)) + (property NLW_MACRO_TAG (integer 0)) + (property NLW_MACRO_ALIAS (string "b200_b200")) + ) + ) + ) +(comment "Reference To The Cell Of Highest Level") + + (design b200 + (cellref b200 (libraryref b200_lib)) + (property PART (string "xc6slx75fgg484-3")) + ) +) diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.ncd b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.ncd new file mode 100644 index 000000000..2ef54e4b7 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.ncd @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6 +###4184:XlxV32DM 3ffc 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f88eNrNm8uy3CgShl/GD8D9Ugrv5xl64QiQUERvuhe9dPjdh2tCUuK4qk6dnnGEpbR+AQkpwacsvP0ppb6R27fd2ZsLbtviBdMv2HzBxgvp7NL5790c6fzLU01ZtGT8S35+2+15C5xtf+1O34RW27dg1Y1KyrdYGblxpmi8dtCb3FmsbT9KrQcp59Pk2gNh+d/BytpKoMlDOrZit//sHurdea3X6+TdXstJLmbvfPHOWnPnHTek1WI2PCoeRqUNRhXMdjUqkqlohbHdfftj9/JmflIpaWyVp4NkyUoHIeKByWSlQyz/K/t5lj9hdDa76EIawDM3LAPPnilC6pnWM6tnXh009WzruTnuy4CTUM9nOVNSz7SFm8h5QI8WbvnGcKsp3EI9Fu7ZO2FauN0z4dZ34b589omam7NtMMSbBuOfM8dS/vweXzV6i5e37/mlq1aMR7NUtn6kw69/qAqpQvazKoRtP5TOShmlpKTHLMY2lk7XYseivO9mUOOTE9UUjzjKqfDuQpNjkTg22w95HqVBjRSTlFxGc4YUnRQflXD6oW9xKGrfqhX71iyVrR/yqD0gg4/xLYhKPGQnFPRall7LGM1URvKxrf1obRUrtVUtla0f6ZDKUT20Fd+Uds9piqyQ7FplVWa8+ZPaihfbjbbIDGSK5Fp6rDy+5ak3qoyAgCEVOXItmiTHsPmcJs4UuRZNVmJ4DIVLDHdbhk8iJcVwNyWGFCkphnseWE3Y0MUy5I5nJwXEPVqDk+TMTipw0iAnaXbyEEPh4qQ9SoMUKclJWx80gpTkpPWlDBkGujhpq5O9NoqcDNlJCU465CQpTvKhcHFSlpE8T6QkJ2UZSWaRkpyUaSSN9FmI/0xPUVFdFvYq2LC1vhXhqMKeS+TIFCFU4Qxbe+2iECctFc44s6bH4sbYz792z+JM6ESaXuOKmGYx7lmdqE6J5sXAKIaDwMSG1sPA+LAexhEuc5v1/YbMF3bvF4584egXMnDYUKpwtYr8RKdzb5znWXrvjXOVL7h6Z51gyxoZJ1pZ18pa09l9ELmms/sgcjfO0C+wbfs7zp/j3JzWKTmtU0w+tk7NCwfTbZ3an1mnzAxrfpv4xG3XK5eeHTBt5eJvXMbFPDznY8Mze8dpG57w3uHRi+ExS6hlbxwe/iLUmhXUOvLQ8Lz20EiRbtkvoFZHqBWpVaYTwKYDM8lKhzjd5aKP8+yKY9/Cr3bJr/RtkZU8tSKuONTdgyEXCkVoiMy+jkz/OkMPrlsSKfkCIo3TSKNPA5YFy2EiPWENTgoi0r4kWiBSW4mU7h4wKF5MC1le1yaytBONnkgBGh2YM3rf+NKAZcFymDk7i0UfMXMG6JddMWdqq/KlAcuC5Sbm9ENbjTldZ06HZNcqa7IFf0yDynxjYU7aPww0kktpDvzPTeOhHJVClh54iDceimojSy+GwpgsD6Rck6VBZKnCPnQEkSXv3xp6dLKSpQMnBXKykKVnQ+GRLFXwSLkky6x0slTBDcOJyJL3x1YhJwtZWnBSIicLWXoyFEZkGSxSLskyKwNZnogss5o5URFElrlvRaCYLE0DSOYMvbFbfMaOG5MAkJl7bAFIYegKIMUMkPQxgNQDSL7OjxUTsxMjSHIAyQt+BG5UEz92qBW5FxkoJ45kwJGX+EhfwUdWvgcu8VEfZZZnJq7NT2S1EDD9jgTiI3Au8DEuZncOvM5H5BV8ZEbxFT7q86HheYkambNkQY2c8/eNSmabp6kxjsoyFWroMw/NHVTrjxLE8WGVy1RodCp+hRoRZxKjeTzIdNAiWekQX5hc/godi7MNHSEFKoP7d1KhMdx6gZKcszeGO7ySCo0ju0yFRgx4KdzTS2AXL4FZECjn9E2j0gk0z0SZNvPb1ywNlhkJNN5dV/6idAKtw5WU9LxlAs3XWk5UDGrNicbAlJwoJ8o3WaGcaF4rRwUolLldIuU+J5r7llk0961ZGiwz8mm8m0Df9Eih8TXaxxoTcZYaq6XBMiOFxvdSDb3OFFruyZgZZYlk1yqrMg/gDymYWW+0RT6anJwa5FJajpUPmc86j5WBq5nPGrPCpy0hl17cTFU1ZqxEig+FBz5lTp9IAT6NkRJIAT6NZcYuDnxal6BSho9OVj5lgH4EOUmzk9IMhQc+jQ0eSAE+jU4ypACfRtdONJLp48lW98kQgoFcWUs4fs/W6H4hVwruU+Q+ye6LYyg8kCtz6kQKkCtz3iKlk6tiA7lWtQAqH8i19roIYiDXGrMiyCEnWl+7hrQ25UQnpFUlJzpyLfs91044S36XD93nfKgHnv0NxqoZY+VHGHuXBv0AZ8k25UfZOj96xbXkeI1r1TItGiefl7j2QXCzS5wlb1zJ9xdxdpkNNU/R/nO/7MdRcSucZecbR8W/iLPLJKg5v3BUTFZWOKtTqzIdtE5WOmiTrHTQ9pbL/x5n//1f9mO4/QpnWXhjuN2LOGuXv+w/9fWi1+H++JPX7iuuZccXcK21wLAOLA/WPnGtAxDZJ67tC6sFrrXzb/1ZbVzrgGsBEFIRzLUWKddcaxdcay0wrAPLg7Ujrh1JEOVdoxMGeu1XxGst0K0Dy4O1T8TrhrYa8e6deC2SXausyd0fB0hrgXiFBtkiuRLvWDkm3s6DBmjM3v/WH6fSRmO2E28YCiPiNRop18RrMPEaNXQRE2+vTY9Ozr/1kx05WYhXHUNhRLxGIuWaeDUmXiOGgUZcq+CLRink5PRbfwSY0cnCtWofCiOuNRwpl1yrcEa2etK4VvWMrMZc2zOyBnOtAcFirrWdazW/4Fp9z7X89R/82f/yB3++fZJ0+Uy6ZHsqg5t/TnyFdN1yAwD/VDLuLle5StMcK+Rl+xtXe/Mi8vrlBgD53uFZfRGEJfv6Nw6Peo195bHc1aq/MMFtxPkR+7pEt+mgfbLSQaXMrgjJSodY/v+UfemSfd0bwy1fY18ZluxrP/Wpox+dLNiSfe1XsO8BnBvAomAxzL66r/YMs68E9IkPXmVfGe7ZN6qNfSWwr+i5qoDZV3OkXLJvVi7Z9wDODWBRsNjEvnbwEbGv7plsumTfAzg3gEXBYhP7kqGtxr6sp3NPJLtWWWPfHfwJDW7zjZV9PcgHkmvpsXLEvrInE49GbDmaM/uqRmw5moV9RRgK42wvRcol+2ZlZN8wdBGzb8//+9HJO/Y1yMnCvloOhTH7Hki5Zl8/se8+DDRmX/i2UQ45ObOvRU4W9tVsKIzZ1yPlmn0dZl+H2dcByXrMvh6EHbFvjkwRDsS++bVr7Osv9rmaYZ+rMGKFveTz+1z37dP7FD6Z4P1wn+u0vZVebm8l4sX9CeeSbv2nkjX+0WQNX9KteeN6zl+kW7Kk288ldB+mW7GkW/3G4WEvZnbpkm6/NLOb57jr7a3RqTMxLUl0mw6SJisdJLvloo+D7ddtb42RlUuQVe+KLCs/yl1vb734en1ke+u0q9Vs+HlVS/6UX8GfHFhTgCXBUhN/9hVXTblXWDTj89Fyr6zyJyeyZ43YuKsV5VDZxJ4eKfe7WrP3jSYFWBIshQmzk5dmE2H2nLJcEiYHmhRgSbDURJhiaKsRpuoIyZHsWmVN7sQrGkLmGythUpA5kktp1Tdi0EY/OSrTrlbCGv1EtXGkZENhzJEWKdc5VDrtGjBDRzBH9nw7GZ2cd7USjpysuwboUBjvGtBIueZIgjlSq2E48d6A/mF0IienXa1EICcLR0oyFEYc2TE4K9d7A07MkQHvDTiBCk/MkaQJmuAcKm24eB5H2tR63NRIi3ZMkhKFaFF2kMucJlWdxj7a7UrWGDmmU2G7q53TqG7eJ/ABcXKyJs6RSV0DSjlnWlW/kJsf4ZTPcCrm5KyE5Gzn2ZaN/VOG2upp5220bs7G+hlgL3cmTESb/FP5Kd5idNMDoS+AVLK6YJ2HbuvHwdF6Jef16i7QFxtp9XP/ceMMZHKwIaFk9AkHDTiIkOcjKPovx0YGeg==###4400:XlxV32DM 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1214eNrNm0uS3DgOhi/TBxBJkRIzo/dzhlk4gi9F9Ka98NLhuw9A8AEolVXpiqqe9iKL1i+SAJ+fKEj//FOnsN2KUndIxeWW9nz/9SMd7rbcdFPdYkAN2YGaQNUphy5DFmv9/Zs9MJ+O8H+u7Ki0PEUoGyqR8iihOFQCWlEOZoUt4f5nOuAOZWqBwQjVQLbiSMlDKdWj7uVSS+1qyFv1qHupyU7DMpNvyVc7QxEK+pZ2yrMJBX1LG+U5hIK+pWZkHEriRi5HNTINI3dhpKqZU2KZyUhPHRCkgkb61gGLUNBITx3A2is1I30gI/1QgjCyVCPjMNILI5ea+TAsMxlpW0sGoaCRlloybUJBI21rySgUNNJiS+5BVwH+G+5dDVUwTfDl3n0jYW1CohxlCLYJR7n34QjCrwhpd1M3ezO37effKeqbMfG4/yfF/f5H8sfNLuv9j5LhlsPe/wJvoCD8i+33BzZj0eqOF9Dz+3frNd2QcHzcI7QgCjgRlp+1wKItFm+g+LDcjE66lR+3+3doa8xW7cKCVp5vu/+NvZA15C3e3cBB3Uox3vVS9ksrQ9mZldDhvZqwn6ox6f7fFO1N/azir1pn8pbXWWsKZbj53Zal1ggjpP6FcVQrkLN5v8H9OFGOqkTHlbLg6KSpyhYOPUbn3kdnVmN0hjE69zE6y8Iyi9EZtVDG6NyDEyOtqnV4KL+Azzdlb+GmSh8gacEe9DRAVq3FAHFzYOja5Nu8YO69c9qF5f58LP0Fc3UKGQUf5wVfL6R5IdYLeV4I9UJp43HaZTYU0rTLVLvStMvYemHaZVy90MZ4cVTmMe1baxHHtG9d64Vp31pdO6Z9a22eo9oX1bbqj8wT6CAs0V3Mk7S2eQL32D5Ptk3MEzfnh5edFUqQnRXKdn9lSoEn6uzJ8Zonx8kTo5onS77wZH/mSTx7sp098a96spw8Mf4lT5Q6exK7J+mLPQmXnvgFr4SLZW79CeKG9uz442/1Xlr1DvpXuMl96YNZYGgWlCCWPtjJ21/d/hq+JMLfg/6qtlTWxgIj03EeN+boDaOhPmV6t5jjdOPqXusWc+qWde/dEn+nW8K5W+K5W/Zzt/iLbvkBFrUVuTZ6hdVq5QlWq1phtfpOsKq8iV2GLAxW1T6LrcqAVchThDJgFfIYoTzCarWiwapqsFr3B64OWIVillGgok2seSlgtU6yuok1LzXZ6VhmBqtg5yKUAauQxwtlwCrkUUIZsApVjvZYDm6khNW6pnEjVc2sD5aZwaraRbEMVsFII5QBq5BHljZgFf6fhpKFkQJW6xbCjVxqZmtYZoYDUGESysABcCwIZcAq5MlCYbC6MYRoKqHnzmC1+UaCZ7DaeoaEwGC1DcdGI8qfYTUpBqtrRUMJq4JF/Bk9rqkVmtJ8bDdW9gm1pqU8LjEX1PpsXd+erOvxKb5WkRbyuC9Xa/j7+Crmd+T4WvuCKRNfQVnHdLNjvMYzvtZG7uM1jvG6LiyzGK+iWIGvUYy9qtKAUUYjvmZY9bUeQ0YzfDX6EEPGnoeMO+PrdqZVNsrc81HWLlQs9FsDXHZnup+I15+I1yzPibeDLiffOr+wj+0jAbszAYczAW9nAl4HAU9GnihcWmWHPwNvOAMvY+TlzMjrmZHNZOS/3OZodiqDI2G7mGVrWdtAV7o/G+psxCyz51n21s6+n3f29HxiThhgM1QZe7K1U+1a9O/YGs62bmdb03M4PJm4n0x0ZxNjN3F5ycT3WvHBsvgcwKftwkT9nF8V7MNwx4I/6lbvveRXpfXX8ut25tfSW0ohv+rhzHZq786hay6/MyT2+3vPcNu7DX/1vPAjmL0ttdiYSJ7fYPLhIky2d4WIFa8RsSpt1ZC3ugrXXRwV7YUyaVXbRSiTVrXehTJpVdsolEGrSg/AIsWi4itNc58ax8IdCvesoLNwWCPGenJYi2wTcNVgVEzRNkeNspCJgcnUFKmZqIUy4VZbL5QJt9oooUy41XYXyoRbbRahYFMkW73VwlsFQmje2qFY7lPlYahrYzL55Fv3HkKZLKytE8pkYa2LUCYLa2uFMllYs46yzSePpruYhE8VRzbyaR3KKnwiyy2XySfb6kpCmSiirRHKRGeto1AmOuv1EMpAZ8izCQV9gp/KL7B5A78stwIQM/hl5fxSz0Yez2c72LZFjmNDnudi321oNzzu/e0QLjW+yJYffsHfxjB8+2YnWt/dRjtD8ZZ2bUDod5jaXDK1cpjHXOz2QeWH5dKE/fIk+EzOKmCplpfaFuG9ny/zRdh12wAeWZssrQ1qLd9L2zKay1CL2eyHzsJUjCefTX3OaY7Pja35/PQ5Il4+NqjoT84b3Z2/ACinPuj8+qHjM5XOHQ488onO10W2XLDEDizhYLopWBIghY0ACx6k8AcKhhT+QP7P5wswcG9/ffvbDY+v8Qf06nHu1dx71X5Wr+ZFvUY5ZjMfOqVT9bHESDr6SO/7696vj0O8kVbfG8l9UiP9OGojWVzRYZmBy7jlwJzrqaOnwBhMfcMf3KrS2CtRQQyBZZSUsUfA8GvclTp35fGUjiqdFGL7t5NC8pmKFYSVF83yVSbC/iUmKvVJrTsBPjcneuroKSgdU99gi6DaBnago8RStAU6z0tMuZfYUkdPYYmQ+oY/v37ELTArYT70W469ql6ooRfV1EFHWBFc6/f5qo5WRYOYWjdzZb1oHsZ+aeBY6oeb1DFLbdbeArgE0hEHdUw9H6F52jNzylMxMGup6YIhZXAFpFiFdFB5HKNCKypUlNmzzBzBVNCsAahCTxW60YtOeEiHOEdHN9zVeYULFatYZnFUk/hRDal06Jf5MSHZSULhx4TUYiQc/JiQRnY79cn5hg+Ct8ypydJBIUen8s+gE52yvYZQ61sIZbaPvSRU1ZITQv3Wmnq9lManCLV9IkV87HWiqvEuX4dQWT1FqP0Tnf/YG0iV/dciVH4LoTxCUkBcwh94VIcU/tiEKfyB/O8jFDueNv8UQtWAp2uE8p/Xq+5jLzBVPj4HjZ4N6fwUjcIXoBEsHw2D8oAkaP+eyhKN8jgsQIWjUR7bKQyrhkb5GGgUmNrQyI2XqOQzFXtwNGL0A3Y20smDg8DOnsqSfhgzZPHCROWBIujlNRdhXcRAeRAS1tVSWXJRYVU1LsJbGvlkoYZeVFPH2Uae5JMHFw3aQIOY2riIFy24KA/va+RcvvdeIS7yA1OWQQ15cFHeWGbBRVkzawUX5XESkw2vsHJRXvZRoRIVEheNV1GYWXBRSqwBBBel4XvKosJSK9xGhVpUSFyUIsvMuaiFl3YuSuP1aQsF61yUzRC04KLaYiQYwUX5mFwE9PXIRe6Ri45/Hxe9ebRkXPkYFxX7FVxUt6trLoqfuImkj3FR+dqjpfL8aCl9ovPxY1xUoxG+kIvcW1yUkXwKMhD+WHxr5QymLKbwzAny/zu5qEaIXnNR/sReDR/jovqM+HVHRvWh9ZqLyhdwEfRqY6Ayjoyg/XsqSS4KYz9ChXNRmHjgOhe17wYkF7nBRWFwURgb4Pgm4MxFYGdjoDJOhcDOnkonLsqsPsFFYR7CuGdchHURA5VxXoR1tVQSXLRrVlXjIryFyGdXQg29qKaOY48yz4vc4KKBmmgQUymv4S5yLAoD/cI+oME9YpGLAxrcwKLgWGaBRSUwYwUWjaAwTLEKz1jkkqiQsKh4lllgUVmZ/wKLyjhiLFZUeMIiV0SFhEXFsMwCi1aBRcUOyLECi8o4LopOYFFtMRI2gUX924h6bq5h0XGwgOwDijYWVWbU8iyqzN0ZEF1jzaQURd48o401jXdYKT1boZIMi6gQeE0ax6cty8qdKYkFmaH4a9r/xm7VdqEZXEZLHh1Lar6o0RrTBbaKsBnmrFhEaKkYWfhisHKBpqyz41EmGm4DH9FxZhyvjZ3tr41V1EyeYxbaK6qML20LBp2ZMaLaYNK7fjnebHn3+4n1/sq3OCPcLJzDzV6LLhMBaUVQP9B+q2SEm731oYU7h5mt5zCzcBlmlg/55cUINwvnYLL4+OiwnYPK1HiWmFFm351dZJRZUsd5ulo2XU1dHghL1oklMkJnvXNOifpZ3JqP/bVrVGMV2MLLcWvbux9vxNc+eYg1fuHqIwwf3aOJurwcI5/ur4e4XkbSxRqOcfVVhY/775gW322sh/D99HZ4Gs74p9wfzYqGwWoZTcQU/piEKfwx+VbzX3J/9ef/+Eo56vzkkwkfw++0+Ryg78VTPkQChjv/ZCKN2HRsNB6aFkdoECrEu3ithaatrhMtXuShaXEcIJIyQ9PCeD9KygxNS8oKZYampRHoRsoMTUsjnI1Mn0FmaeUKEus3WI5I2YSCVueDFCcUtDpUYEzmEMo+IrNpnHaFE2rUs3XaV7utGasZ67YwmQezxcFupMxgtjBeSpMyuTWpXSgzmC2NUChSZjBb0k403oxZiyPkClPMdIpZW11hMo9Zi0UJZcashWUVyiTgpKQyY9aStkKZMWtJJdHqYYSm0YZAeVZheqGMvSMxRdhM3lOnuJ3l5vFpcZxqkzLj08KihDLj05KSyoxPS6o+XjczMDSt39Mj1YCudw7qpBJdR63w0BFwm4fg+05D5tnHow/B9uvrH4/+D8C6TSU=###4064:XlxV32DM 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fc8eNrNm82y5CYShV/GDyCBEKIU3s8zzMIRCFCEN/bCyw6/+2Tym0mJq6quOw73QtLlFMUhQfAV0I9fnDWPIMS+/6mMeEyP/XdldL5buKcPyGnHhKMmCB8TXP6kb4KJQmgJB363zd8NKfHu1vbdGnM43RJkTNjyJ00TlijYLJx4/1P5fA9rSg+5iLPZX2IRZ7O/xCJO1xJiBU+fszb7ywz2VzVFYdWxjGM+BH4C/5h+/OLMCdXU+x/O6oc53P5LMOtjPmaxw3dMDylFgDQ/P9SxwberWncbLBardEs4YsLWEqJ1ZVrCFhNsS4CI/+m2aP1vtHZ21uRcrIV3rLmxtc6RvnEkp97RkR256R1HR+9Ijxy1GPHQzPAUqBG3/9cd6rH9AJcBbeBFnviEl2WCi8DLMj9i/r+j8TP9Y/GMnm0gPTPI1Gum3HumOd9FvstscMt3k+/F+BE/F6aQ72e6z1O+zzXCcxfhZSsRFh+1uR13x67NN9Lmf81OYh3Fj19j0KCm+2/w8qCSvBYF6rD/GtMgL8rL6osMiVDC/hu8jjFjmJhiUIl5bAxkUzZUXLQxr0zRqBzJ4MyUFRWblIlZF6BAj0YHsycKNDMocME8iyMKNBxUV01JOZiC9fE5j2UK1seKpBimYH1MVFIPrg6CRG85rC06UwxmCfCUwnoQOYXV2RTWhSlow5kUVs0UtOG2FFbDFAyr01GJo09TMKxuTUpgYZ2xuimsLQ88EevTmaxTOVk3uUcIpqB1k3uEYkqMYO4Rmilo3aQeITxT0LpJPUI4Zn1CRSfrrVKBWQ/J+kbkZF2lqHvPFLSuctRnpqB1laPOFbSuctQPpqB1uPwNQ4NT8jE/hHxsD2F//OEOAQMAtHwcJsS25JHgVGwkCGLhI0EQ6/VYG9mBjgRBzJcwYXqYsAwROF2YShcMNwhmuB4zbMQM2WGGesaNtccNW3GDAckld+QEFRM8BZHflVcUROCuOyBp37jEoFFCkT2hzD2h6EooDFkIqiyIKlp1qBJH4ktUgVf2k9nXjWZfs38xN6AjbCV9RSjnhaPpYI5Ub2DtC74EBFYJ009wQ68ujpsL9SqyV/k8s4p1yl5h2m0dxE+5A6R5PqT5PwKJ6iNRyOg0L0XiDifdbQDucDKOlyNmWgRSEV4WiU94kQpNo3MZ7et/JzM5Nfct60vLTt/QsmvXspXIzuOdPm72uybe+iZ2+x2fH7yPK9lFYjHZqwgfRgLnpjprQVegJOhUIQ90EBC0YPRK0+pK8mRGhLRnRoTEASNGpTFiqmRTGiMSeowKYcRGj1EhjKg0UxQqJlV3YtVt9Chil12wujCoQMD2X2MnLE8yPgEdqo704HsYaypRwzansMFUE/PEWa2W4HwpIT/J+PQbXiJl0hKQWfNnzkQby8RkW76syIV8YlmQWD6YwrB4lpsgbAMwrBhFWNGgTRWYiu3fIyzIA4SNSkPY9JI3pSEsgduoEIRtcBsVgrCKO8BWdyr9ZlCs1RvcutWROKXWsjIRe/vVIml1n7AX5AH2RqVhryOULxn2EiCOCsHe1h5RIdireB6srkmVkgurLgHi9rsPnmileiAGeQDEUbkE4qhcAnFUCBCT2IoOiFeBQCwehgLxUYBYMSBWjGpvCHniA3FBZoLKskfltO4mX0HljpDdLSEfPSGbISEzql37hTjds/NrqPwVIX9ExtMtGc9fkDHOzbqbmysRw1zxxty87a8vUI3mZvs1fjnlurlZFI6YzTdQyjYk8fPnSPxu/eiJP59+LOguAGEE4LP9hgCYAYDDqPMRpun97UgMFi0lprgLANe4aKnR4IawjReYuuAJL7N9xKyvs/eIub+DtddpxNrz8Q2NaIesrb6Xte/f5+2GtVcxYu3Zfc7aq6ywITqirouN0CkKUdsrorZDoracqFfBlGuitkOitkOith1RL8T6M1GrSMKucnQoT9DpypPgbE2Qx3K2XucawOmCrWtZmahDecKy8pPoKFuRsjJl42cKRi9MtuXLilwbFMtKlB0/mCm7/RRwTN5SozeSNQXGYvM/AbUZArXhQL1OTLkGajMEajMEasOBWkjW6ASo1UlCwoBatNXWjVb3eR15G64jbxyoVWDKJVBH5RKoo0KBemUKAWohWHUbUDvlSROn6ppc3VaOZtV9WnvWw7VnzVA70UZTGmrTVWnNUXvmSkFt9vshKlhduACEi3D4B2B4eKwPISuEuwzhpxxB+NJDuOghXPYQPvUQPpNp9nrPm6N2ZnDXk/VXe95+uOddgPqOo22/5LzuL+51L5WX38ZkebHXLU4XG5giqNr/447MzAJqn2crV3YTQOMz6xonQZcmQRHcMgLwQ6ZJEHpInbC1HU3Yx+0CsH1jO53M02DxGO6iq2eLF6vmdwux5r1VOnDkRrvoh37L0R2Hut6I5UYOP1wRFsEvaEPBxR/4hBfv8AkvMPLE/FdUmtwXKq0rwSrYf2ZFGCLsR7voh3kpwk8/A9+mRRrqv+DVy+NxDBpZO81eixJ5LqYVnjO6yJBIeE6c28yUynPCG8eUynPiPBRTKs+BwYMpledAscx6pTZxBqqQvXJQDFPqXjkoG1PqXjkoM1PqQmPup0UhC435VUquXZo5cxgTFxkqEy6C4K1MqVwkvJ2YUrkIgrcxpXIRhMgwpXIRKBsLXqWfPC6lPAe1nhnHWCITxgHrC1Mq40C7B6ZUxgHrPE9lHDComVIZB/IEFnVbSCaP+inPwqwng640JD7BZLGX2udGobkJtIhTn0yp0AI1O5hSoQVczkyp0AKFY0PKbAN5pXym4Mtf25HaLfJUUW3iGsgzI9fAACgq1/jCNcPd9vUNjHlpt/2LzXXCMx3G2I8xRlaMeaaXnz2x11HMcrsNfkkxwY1P7B3vDO7fdEQKHY0P6vl3HJmXN+a3G8Tww4N6x/kJYgwj0pGFm78ii4Cl4wX6DzzhJcB7GBxeYBqI+e/J4p/faxZY9Oh83vxzne8O4vQNWfg2nM6cLPxMlEwWvp3PM3Vq8nNHFoIplCw8UyhZrEwhZOElUwhZeMGsN7IgM75j5/OAEgJROHN4plDmcEyhzHEwhTCHo8FjzOErIPipzH6unc8zK5E5c2imUOaYmUKZwzCFMIfneQhzNINu7pijTbAntV6Y4yAyZw7FFMocJ1Moc2imUObgeQhzuMCsT4Q5mhKY9dBDBTufx6CCnc9jUMHO5zGoCBw3Gq07fj5PnKe6OJ8XCjGol8/nTaPzeevn5/NcRYhuJcTsryHEF5uOy+2m4/35PLVf4sYH5/PmfhdS9LuQev85MOnO58F7OD6ft/7cr8670/Fu/xpM/Ph83oWjN87n2f0WEF4iFTlNbngs73lCfXNDCV7S8bG87Z0AbLe7gu79/dF+NUZ/wUxBIBXhBVgHnvDicXHmwCr4WA/972Sm85SjPUNxfkMTj8/n2Y+a2LzfxPrrJsYpYnQ+z38YCZybKmgd7HwelFuYBB2Q3cQcvZKnrD6tF4zo1hEjOnY+L1eyKY0RCT26lTNio0e3ckY8LVPqbiJUV7DqXpzPi6NL3DmMnbA8KbqHSEnv0Jw1z6WGTdI9RHGulpaA+4WphPyk6M4hUCZtmLhzmD5zJtoIgsm2fFmWz4xzqSzcGswfzItwJ8tNl800rRhbNmtNpOoCjr5AWKdGCOvY+bz8kjelISyBW6c4wja4dYoj7OmYUrcTAW41a/UKtxAdT+JEthPzNJhQWdLqPmGvlyPs9ex8Xp62mtKwlwCxlxx7W3t4ybH33JhStxOhuiurLgHi9uPJC1apHoi9GAGxFyMg9mIExF5wIPaKKQ2IIUby4nzeWYB4ffl83nQNG/RYXgfGcnga7/UltdFpvCcwdndgvO79YtuIh+UtD+v9J0/jLZWD++W4Iey2k3bwGo5P2rlvAqnhFsvNnOqH5+qWb6CL8bm68FK9P4eK7Q4qzuG5OvUNARifq5veaXi7v7qfqm/BuV/sHJ+rA1GjwQ0hGS8w5cATXg77iFlfZ+b/37k6GCuH/4dlXl9oxP8Bm+SDPA==###4352:XlxV32DM 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1250eNq9W0mS5SgSvUwdgEFI4sty32foRZoBArPaVC1ymRZ3b8edwdEQ/0dkRKdZfin0BLgz+XsIfkg5qUcUaXv7tYv1IR7q9w+pZ/MIa9h+IDoLCaiUIRZY7uJhzLr9NDYQYisSVshMZUQT4hriIMu9ZBlFxAKXVuA8FCgo8coSU4Hw8/ZrDR4B+NNtFXUIhALYuFU7CdgLEDDFPjcgFiBRikDAm5fS2Yd8SPnYH3L//U/w6qH1vm7/CR5/7PZXsOmh5bT9FXf5MMlsf4OBkF++Zse3f6Ee6G+bLfsrQJ5R7Vt+EOkFV15AZ+kFveQXsOrydS/XRNfdUMI4l+tCz1MvYVI5g0QlzAsm+DtavHqobAk3+b/4jS5EZbJDGhxy4qFVUMUjv2z/QrPkZLlCooI7zdMtOd2y/RPc8kj0L5ZctJtrLuu5XqArtFwhv4fhua6U4apXyMHO0AZKVdtmWXIFI3vd7KLUAZbyL3RB7vJb9lkcfU6v+bwefNbyYz5ji7jot2vn54PzWlXn7dc5b9LBecj8FeedOTrvv9J5nYdx5NmH7b/Bm8f6W0qjwPVJw4/JP9OUf1b40S7f2QemfztY0msMLXGxDRwYKDTSYHYpV1muqlx1MXAtV1uu1XBP9SpiudKAjFKUq2z1po+tutdWdV/YqvHQqtP8Wqv6Q6tO66da1V63qrMH5ydbnfdf5PyvhG1ncmiA6QMe57kbxlK5g/qvdxbvfuafHFJci0cZyZEKpkdCfEWgW0FbYmqPMStHKsdQ6CmA5vrPMQsTtwAISShSpYzE5Jmd4Faxs9yBnfXO4t1PmN0xw0mx8qAHAxISFTW1onSJtXFBJAZeVthrWXSXyyp3Fu9+5p+3X95KVhR08vpKWhEVA+pqVoSuqaK5IHhW37OINsKQDWIo5ay5i1FnR2Zy0TQXTSUN2CgCm6LWdZ7WCmnARlGUWLPE1BRhpfpZmLFUc45YSmxEA+5YgSdaJIYCiRbhFF4TD7QoSub/QItia1644wUeaZEcCiRaFAVLPNCiNNAiRJHk7GKgRWgnAXKgRVhjBKiBFmGvrrQowaQzwwSyNlJkiRQVPmROfKjwnnljhOia1nSWIj3adsc2JmfrDBXC3QwVtnFmSrdMI3zZtCwndwyaJarJ3wi+dfvfiVYlCtVoU6c86tiJT2o0x1SAzSJshEGxwyQSA0/CJ4OJAzRkJ1eGLLSJ4DbwHu2bdV42ou9Kjy5VX+HeZ998glEJkX6HHqVU61COE2zlhw5lCpGch44FD5b+YNoOXU/iA9sfqBa8ygONpLxwaWvLlb2AJMb6/iBsI6/XAh/s/Q3XiD5n/q5kHoonoXuiMUXonmh0jWsDdC10T7RpYqGrh6oO/jaxFJZ6igkrI/UUE+qN1F2b0BMUFPlaun6Ko8CYFywDmjDnvYwjFTu5MYk6edqXOqx2PYzWU2viqOWtWekjG9fr2JqcipQHjo/8FN3BQCDxxcD9Ewbao4FuO088o4Hr0UA/GuiPBvpqoP+KGnQfr8GDgTkzdzGpTb9TnB4pGvgPVsJ7V5Qcra9zXGPiJrpXGPlzxh2wMw8CJ9Y6klCeVNWNcKjnaa31bF+p56H23qvwZeOa1zLt2+u7Ve8vpwvFyPWX2SWw0kyFUp2n83PkpPkJUVIpxVRBWrTAYA2A2HcO2AyUFJoDjaVCisCBJQOeUkQOzBlwmKKSKQJMBjLnC4l5Au27/chtAw2QvVQ79xKZq0UvF56mEUEaFficeHipBmJBYu8geR+KZTMHsvfBUorAgU4MRTQcyN4HYtTCcyB7H2ZKMXEgex8Meqi4hzIzTPLQ1eeOeSIoGAsGkieW2jFqDmRPbGlHy4HOOEVUHMie2NKOKweyJ7bUluRA9sRmi2cfuCeZU9gFPWlFW+4JRXmxdJA8MaUUwYHsiSltMnOgUVlo3cSB7IkpbaI4kD0x1Ca750D2BH4yYxVOwtwQYNzLzjA8p6wq3FFWdeQNYuOLe+pucW8/0oR4XuUzx0iuh2W/smqBFQF8eMd+/d6qnb6S+ylmU6bL4Lwcpzxtn4h9e5zhjupfI3P6+DqbQFk7XYRoa8TJTCfeX2myx8h3NHNP05MVMX1jpjma6auZ6mym+sPaFChm7UXY1RB21we8oB741tOgy5bBRLmqd4PvTdBl0zUWzGVFHmgMiXmG3wlpCpsQnE8UpTENqWI/v0PTfEhllscWIymc0SL2RXIsMZ/sRUsoDssAoi2g5DtWIM7GIVVllHsyL1BStgtLzOZkJcM8IG1SpgGI89I+FBexuKrd8vDmxZUgZ3paPm+KPXKgLwHsmi0BEEh6fuIrAGQiAYavAIi6AvDm1QoWnZVZYMrMCHNSZoPe+pBEe2eqvZVogzRzRyXmj0qsCBpbBA1XZvaZMjNHZTY1ZXaYxt2HBZk6CjJxFGR6O3zhwdLTftRwcVR5VaJBY643Gk3LMnHBO+IrqO9Jrb0z2V2pNbDD3sg1+tb2sq32qa3rM5q+HCxzNzpNy/kly54pybNBg+l3+gwH651AA1Bnu6b8Yx747lW8INO/UaXhGtoQdFOtIJVVmm7O+BuZpuX6Rx1geSqMTwTiVPErV26zLRM41iqTbsWJiqB4w2ek3pS1c4M9l2/KVV1XkKbfII0ZkCbgII0akKbglHViQJqEU06uA9I1XPlYTpaTiINH0D7osBgcbiqudMGerOm4MmwIKfqnVIogtxKDmZYDE+cBafEd0sQBafEd0kwD0uQcpNkHpOk5SKMGpAm6eTWDt03RlUmKEMt9QhoBZQUGM1UHZYkB6RTCsr5kOYWA5o0D0oQdpHED0pQdpBkt6NJunQafmrYrQYKQdfApUlmWwUzfQVluQBpRgTTrgDSmAmlGpEk8SDMNSNN4kEYMSBd50M/3vFvDAFuRrrGVnak8I+Y7lSeO1EN2On69GLw3gnHkFael3yOvGOjDe0u/+kQwDryCKMlxW8gy8Iy+6wPXmD686wNqOtwISC3daTJ+R0Eu92uiPJJZ/JJwFf3tdBH9Y3wWY32b829C650d6ibW20mc7Uj+/7RYmC3Lo2C9VIVg0vKAwZAe+NrzMM904ef0IA29gygu2x2WsJxravyu9tqX/jzkczHss1dboUJHWSBq38MwBfsexiJUTsKUK/yteSn9qzr8HXka0LQlX/wAXnoJweVLLr5YQpvTHOahbd3nAWGhze0DwkKbCQPCQlvd11CQHtr2KAeEhbZpqL8e2qzvSST3iUKb05bBQ2hT+4D00FY/NFekhzbrRqSHNmfcgPTQttfFwYK00FYmKwoQYTCdPqw3ca9XUtvF+cJDFpaYRzEn5gFhentmerugJJ9Vpton+RyZfFbO3cnn+Sif9VE+y4/L5+nZF85wCmo3a5pFX8dDuLsKc8sxzM3HMOeOXzj10y+c0zNBrY+CWt1/4bwT1LLvoew6WmF4vdLRUpRvnUrt6bk0Cceo4O6l4Ms6etSE6qT5aySVYn/J1lsT/0g0ZcvsTWyVwn+kFv3TWgzbMxpin9lq7pW1gqAJPzr/TA989zLkojPfqazja8panRYwqrKWwn6k4t32bCVjeaqsr3gXE9S5MrmgVk1FZoQEtSp6EmDtQoPdIKh1UgPSBbV2fkC6oNZJDkgX1NrPA9IFtU6jBReCOlteBHU8CWpyuAtqVb9LlmRdUKsmPlUTn1Qpgkw0DOasQyc/IJ11aD8NSGcdOrkB6axDN9akmvgk1qGTHZALQU3edtahmvhUTXyiT8Q6tFcM5qxDp3VAOuvQXg5IZx26ruMXpLMO7cWAdNah0zwgF4KafOqCWsVezDL4RJbXXVEIc0GtkxmQTkV046OEdEGt0zQgXVBr5wakC2qdxIAwQa3x+ANoisfS2Eticlo5f3nu4dm30lC+Z2onPqVHFa6rTZcReDlNYVd69JVPb1DMfBQ1bRsfgm+lzPlqij9+bWtTfNvON4zueRAj2lmO9I9lxXdCfOtPdYEmVJKNdUv0VpUlHsx2Z4mHPpX0gDB6u3B6q2LfBioW3LeX9+/30zFgKtu359Pdesu0fcsJmT8+GbPH6VPf2JM/H4zB7uGUPX8VXj92TEIYfbdt9fwFX836c4cJcF7+xHf7OXzn+Rgxu7vzMWY9+/7JgxTr9KnjMWLR33g8JuGgvD4dk6BHpwgjT8C0koCqwI2Emzwgwb2c9Mt34X3BuRixyLtzMRfb7z7XmrswL20FhFbXnzo+Ixb7ncdn8rx6c3zGuK+pI3Z6Js8tdFImj7RyB61U75bh9IxY2i6OjLDTM1QpeT9C0uXwTH5UD8/MHSxnZ6Dyy9kZcpgytZyD722nV9JEmnPb0lbCfq4me0BnaLIH5Q48qHfLcK5GLKoVJofTM7R3peWIJ2UwR7rLOZa7ZdgwX6l2NpIOz+AbdDymcmoCXc2ogHV3PhaTt9rTa3h0xjc7jeZgTplquKaK6QdnaEIi73TZnZd0OzdT9+7n+Q7ZAbUH7aRZJEs67JeZPbOTH5uhuZ+QwIorG2lSK87w4mgfzexY0mELo5mY5+yIQaoyJEdbVhhto4ltG83gm6AsdU85sJuVb5ZJvu2JscNmmTk0wA2bZbCmCPD8uAx15MKT1nQ+RRzl6RRxEP9nsvSR48TTu8eJV/Wp48RiSX94nPh96rDst7TJfx11kJ+jTav5Vtq06lvaFLjv/wPO9HBk###4172:XlxV32DM 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10c8eNrVm8uO4zoOhl/mPIAuli0l6P08wywa0M3AbE4valnodx9RlGTSsasSV/XBTAMdu/KHJilR0hfZ+f2mtLM3cVPvP8qZu0Wb7uVs8bcs1vvvtyQzqjKLpaixqbOQRVVaUmNj3P2ncakqwXSlnGWhQNFVcfOwWZjDXB2m7lAq5lCgQ0OM0WF5+f1mV4yk/OnvXfVVcE1w+d7jRME3IVYLa4YQmrBWC9su9Tso7dNN3uabvtn3v2NQN61zuP8rBnv/K7r1puZ8/ysneTOruf+nWJUL/RW9u2Ul7/dfpQXKG0WIqR1XPCZTj9nVY/Fja9Dlv3ivF85quf8d/XLzYi4eShMqldbi1IsSQ+xeSxzUq8+2eC1NDFdt4YuboZe1eNklrw+XVbNul42KxJwEHmuD33+VrqWxgxcHn9TEi473f8dSBvK9ir+rSyk9dVkd+TwapYRt8cIi1wu/SWVj7/ySSHF4/wkvVbFEKSGWskigBB1GvRQhrkWIa62kEgIxiQmUVE2ol5LmHY1LPGiXaBC0sLcg7BhJLrXCVmqNRIaK+tnLSghdOruUtr/JPAorQmE5LCwZF1ZY81ZY0x3eWLY3RH0DG68MDlaCrTrK0ZHaDCC4sL3h6htxe8PXN1oFuNyqd4tCa/hA3KLQc33Dbm+Y+sYWjq6BxxrOL5PnVlVbWFP9QB2McNyimWoia9reqCmvNawgc4SPSlrlBppS97ou5dyGywJlFlvdCgG+54NBtxrZSlWU/m6DbrFs0M3boAu8R3xejnukDs/eI9swLQmEfQLrcwnEXQJa9gTEKwm48wRY4K5l9JiA3yWg3XMJ5H0CoSUwra8ksOwT8PsE3P2Zrije4CL+YC6b3os4QTwGXmpkS5vaVvyXach9fiul3haBjCOxrGztKNtRtaOm81854mKRpWhHiUHG5Pat3efToIo/qUe37D84zU91S/VIu2WyvVvytYFxWk6sA3lvvBUna5tCoa1LA5QZFoKDufb3W0yJqKX57j9qygARZY1YY0cHMEF0WCuriNkzxYLSbGamLKAEtIlMmUHxNYqZRFE6+f4DOqj0AmagmaqLWZ5R2aLPbfXALEW96tSxqIwtxCLMUmGcmhhjbtFhnAtTILdo0WZiCuRWVplq45gCucUWZBhKpEFWWIxJjyADC1KiQ0mMKSyKeWIKBOlaByimQJCudcDMFAjSeQxyC9+zIHMNUo0gIwtSVIdhJcYEMItDwRQI0rSW5AoEaVpLaqZAkGaujBkprqKK8JkormJuKGSKq9gzKKwUV7EcG1eoqQx3U1hsGVSRCK7KaBlV2D0rEHjQZEQapyi/wsySri25Ei40HS656nFmcTObWT6aQPzJdG53/giagojzd47T0dQ90NRkwabugahsfFvGm9AXRMmAqE5VRY5xUb/yYL3aUa9y1Gsa9WpHvcaFGPN6TUwZ9eqEYLVXVSwYY/0BiGYColOYH0D0U/48wc50jp2dNhmgHmCn+RQ7p4Gdn9CmGrTJ8PMj7NQEO9VkzKUxYJw8wU4oTixDY90Hq+untHk0FCYzXYJM/A57BJkAa8+E+zIlu/txAvoSZJr6RfUIMrP2ryTgPoXMDym5OMnnbGlsgDAivKRb/ewhW9ZI/yRb+qfYsvSGusSWxi0nbAnd+ZXeCPcra8RbiaiDBTQ6QqZpO1UUMkGtkFlzR8hUZspdHvtTCJkmr0wZkFlsuLJBplklUw4gE6JokOk7ZMIsTtUNMo2bxgVNW2owSwaZdWzhUoNZKowzEmMKmSZzZUBmsUlM2SDT5MyUDTKRLlDRNEgOmXUGo0FKdOiJMYVMkx1TBmQWm8CUDTJN5soGmcaJoUgWJIPMuirQIAU6tMSYLtomG6aMRbvYOKZskGkyv9qATCckXehR9VVQFDIxNxQ0hUzsGRQmCpnGbXuiUR4wwyoYM4SzzStx/I3wY/7kFOH2FJH2m1fhvsMJ/4ATO4pY9hSh95tX5nTz6mTPSgx4IMzgU77EDFGdMUNSS5s1o3SvbJRcA2qf0iWKiOqMIpKaryVwNu0/udPjU7yEE1Gd4UQqfflMJp8lsNyf4qEoP8CJKAOEEeEl3epnD3GiRvoncSI8hxP+4YPP4URUZziR1PRSb5x2whEzRNXXY2hZZAYIZc8MoCIzQIKNGULqKyGYUGaIVjJlY4aQVqZszBCtZsoBM0AUjRlCZwaYxam6MUMcX1yh1HGlwyw5M8AAwpUOs1QYZyTGlBnikpmyMUPYmktxZohWMGVjhqjUUDQNcscMMF/RICU69MSYMkNcAlM2ZgiJKxszxCUxZWOGqLbwJQuSMwOsCjRIgQ4tMabMEJeFKRszhOSYsjFDXDxTCDMYygyoIgHMlBkwNxQWygzYMyhYygxYjo0ZdNhvTK2SbExNIZ5tTIlXNqZKU64XF1h3sjGVlH2cR843ppbn1tEo1/ONKRBxto7OH03UT2xM0fG9so2pOG6RVoVsTEW1lZwb9bruN6ZqI/d6XUe9ZkGMWb3aiSlkY8rx2nO9YKQts8UjZCoKmerKHdIz2lRP3yqNL98qXcaeVYfMHVvq+6tbVeJ8q4rcGF2m5cpgkNaaE9qMsu3Slg5KX9ryOcPOQ9YpmcxXsLNkspxgZ5TylUy+uPdTEjBXaLMk4E5oM0pxrStONt2Ww4a3Vp1CZnG8Fu9ljS4v8lY/ewSZGOCfhMz43P3QZZquQGZJLJxAZhTrl6ropfvsbyWQNqnXtq7YWYPbYWdV8X4opNzuh9pJDDlQ7JQ2T0zZ7ofaSTJlYGexmZnyiJ01ioadsWFnndepOrCz/G2H0hafliW/HwojqS4+Lct6P9TqTIwJdpY4JVO2+6FWr0wZ2FlsNFMGdpa/t+QWGuTufijMVzRIiQ4jMSbYKW3KTNnuh1qdmDKwswQpmDKws/y9dadhQfL7obA80CAFOvTEmCzjJUiubPdDbSeKpgzsLDaJKQQ7PVn6m4oQGQh2ttxQiAQ7W8+gkAh2tnJEihA+AUWIW77JNChiohQh+B3R46entgf56K6S23aVfhmvybo+lnPyFJ2hy3s5tqmYr9m/5oU/GSi1my6t4aLendJ8DS92/XbrmKFxzvILm7M+fWRJ1Kfpjp4stHP73r2m5WsPFpbc9aVVH++Ear7qX8l9Ock97HLXquduHnOXl3JP9VbAR8Cgj3PXyz73BgxePwSnvXtI/TDj+u0oH1CAfZeizHWyPnkgJg9nC5wFOLNwFm/V/ogMaiRXwaA/MFqOrh173OE5cCg9Gfc9mXpPzt9UxUlNz9FJWsUndHLW427X451OvJ4u9/jDk8OT6y2zfE/LvK21X01ZHGA2gSd7f9Sx1c/iOOMP/4r+RC4q8ERumTarojtDQMUhH0HzIB+lvmlXVeQjaPTGR6Jvq1QTwkdJGWJXiQY6FYkm169lPQl4EhmT6GdxnLHnlFvpYRKxPVacF1Ros8Azyu2K7SyOM/4Yc38krEZZxkD/yGqrqpjq+6WaKkcwAR+Bbp9zVRVDXZhaV3+cHLbm2ZBO6NHgutMSdoyozdoDhrkOQQQ7RmF3SGJMkQ7n3x4tNp2vdDke0qtLAHGIv23oe4Z1YaEOJRp7YkzxTPiFNAB5BLytslUxhjmsv21QcjicmEOBxpoYE9RyIlM4QhVRZ6VwhHFWQQoKR9hiKEgKR1jZDY5C+c52K3qicGRwV44SkvtnCIn/NuJ1Ukr5s62/s/kzPJJSmz/1M/PnJ6CUT0HJfhcopZw/AaWz1A9AqaWuXkj9jJPWU05y35d6ushJ6yknyeuclD7ipAQkBIg0ZTgDRJpWOANEMuJW7T/lJLL5q/8pTgrilJP89/VkvMY/dY/imH/E5Z4M8pR/wh/gnzxYZ+1npc37meT8E8bKCArln7HFA5XU+GeSg3+o2vgnx8E/tu+HgAnhH4o4eeDM2s9KnP1McsQhYMB+i9XqCTMQp/CTB+is/Qx8tTPJ4Wchrhr8wEca3sxM9f1STR1rODhqeJMG/ExDzUxt8JNojgx+8uCXdaBB6vAje2PDBNbRIA34sY4Yc/hZSbQMfsb2EkzrxOHuh52wWFCHCD9WE2MOP5k0AIOfsVUESyh1yH/YCQszdYjwsyRiTOFHKgY/OgyU0Qx+9AY/E4efdQiGwc8kyc6QO4Cf+RF+/P8L/IRr8DPpM/hR69fhJ6hT+Inft264a/AzmTP4Ufnr8BP0Kfyk70vdXoQfeQY/Kl2Hn/kD+DES8Aa4x8COrALumWCnqHy5LmewU1Ts/yfhx9tT+Mnf15PLxc0ffQY/6mGE6f8CJSM8Hg==###4004:XlxV32DM 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f8ceNrNmsmS5DYOQH/GHyBuIqkM3+cbfOgIboqYi33wsaL/fQguEKgUa8lWedwRXYkqiARAcHmE0tnHbymyTXnz+K9Sdls2+HTw+VcwET5/erY40Kj8f3n7Ldh9S9I+/gxOb2bdcw923faoH78Ft2yCr6J1GnjuLMTaaVzq525K52nh5fdkVTHy974wsPH2O1s83/KfHyCJLjmDki3SD/jx8+/mG39rmoU/fqy6agTvGr5uiTFoLcSW48rqyBeiXReRtTHprA2lsUpdnZvkoXn8UDu0S7snfuawmp9Nyn52yRbph4rVGx6JPRX2rMk/SgQGIzA1ApV01dAxyUPZbVUJbDXJFukH/Pj5tw+emArG90d2U7Ru0LreVdPicIKh/Lf+nC1adBUcItraNtAQk4BA1poKHGzBSgJ6UhZIBdubNiZTEtCTwmsqDGlcUxFs0WQXD2fryDlRNFJ2jVTU4LIXgwkN2sEgK42tJ42rQRurQU7irwZtM4gaKQaDqRiMaNAPBpdqUJHG1aCCCC1biyL/WtJUtK4odFPY9Oh+VoVpilBalBGrCtsUe3r0WZ0VZXm7jW3rJjbz9mfIgQmx68d/Qt4UymqXi28reld9e8hrPa82zh6Pv/II1KXdl3rY25JXdIlnO6KESbYRrus24rg/byMipGFvQqMumce4ObnT5sRN25z0cs/mlI1IGD1BjIjw+CN4tbG3ovxZLKqVWix2XMIRyU6b2u+S6KZXl76j21rdZbqC7CNkjUl72kZoX8N2EKmiLlpp26Jt44c+0DktcBEJXETStjnNlpWqYTL96DOK5YHkG1u2tLGIc8rAnLJ1TvFohjllhzmFZxDOLRuPBwI8YFN9wPXJd/QgVnigbHM0x6o2SGv71C3nR8+ymN5rz/kUGaev0JA9RieagohEn1t5SrUZqyHXoc0d5pbT3OFldbW5v9d/qc97p5/O5GPeXxzObOez+S9inY2Mcf6LC0BofQ5+/1Tw3pwXDnspeDcJfj0FL3gPPl0Ez14KPvt8Cl7YMXhxHbzh5+B93/DMk3fC2S8Gr2EBpotNybwxZlnufN3zjxxHfpaDBAa1AElvpf3PUxoOn/rulVdKW2Kprqh8aLVP1j55+xR0l8uftn12xz3d/fJnPScyBLRPhlnV56zGntX9rikduTonde/jz3PUTGD2l9ODcv1c9uUp+9L07OuvZH+27s0MyuVy0yARKodtphI4rLkuaZTMQOXVOf7WNITKmenMBtOvUjmMVKfylWgrlcP4NypnoVMWNCFUXpPZ2+WZ+vgd/pSTOCA7BFHxHILokkbJDMhep2ENQg9gzlKgPRYILz02SaNkhpPYGuJlBfPySEVvqwet6101LY4MGCqneH2ugDkSZHGIaMsZX3eKY3gOMmeG4YjydsbXxBQy5z1ZqXB7ePTEFDJnPpDGlMzrvty9pWTOPEbpDTVYyZz3BMOBQw2y2liRxpTM6ynYB4BSTD1+i8Ytg8FC5pyhQTMYLGTObCKNBzJ3lMyrtnK2p2Re/ayKQMm8jlhVRErmdWZ3jgobbONbpBxlK5tTmLLfAFMXDDWS/fssxd9jqUwPH7DUbE9dn1mq7anrHXuqnbGUZLexVOLpA5aaBX/BUi14dQNO7G7GUpLfGHx8kaXclKXkp4K/RijzHkIZgCSgJ2tBAhPWgQT0ZP1W2n+MUHgB7Cj1TyCUnyGUFDcmM7yIRmGKRuIrM9lOZnKYopH8DjSyiEEOJY9SOKERHpqgGdDI4yltEI3CU8EStA2NeEA0ig7P4nBdsAQ/O+k4lDxKYaQfwgxmqDQwLE6UKCdcZJGBHEoepTByUSCmOhcFJB8/aF3vqmkx7t0h+RjkIotaO2gbFxka48BF2DCvvU4N5qliCdtZpwaDXBQlaTxyEfV24CKDXGQMNXiqWMLhQQ1WLgqJNB65iA7AwEUGWcqsg8GxYglHNTVYuQgLwdB44KI0cFHRVsrZBy4yyEVtXiMXOVSwkYsC4SJ5wUXumYvcjIv4lIteqS3dyEX+RS5KUy7id2yoccpF6sbTxL7GRXaZchF7HQ1Kjq5xaL0xZvMaDukwxaHljtISe4+LApAPIFFeMVkCJLJQX9ILSFBfyu3/pVwkplykb8yqfo2LdJpxEdvvWMZyykXmO7goIgMllARK8sRFeGiChnKRjnhKs85FOl1wEUMuwhe5DN8PQ5MJF0VkoISSQEmeuMgQeyMXYWlrF1MuishACSWBkhy4yNHQOhdJJJ990LreVdMiEoChRj4MuQiHFBwi2tIWXyWVECkW6YPFAkIDu8Cio5jCEIucII1HLKLOjliEQdqFGnzCIjsYrFiUVtJ4xCIa/4hFqDFpMHjGIj8YrFiUFtKYYlGrayEWJYQcMWCRxToSlwMW6YAKNWCRTgSL1NOLXE9e5PJ4z4tcZpbZi1z2/Nbl029ywf0ZZdjb9mZm5fxVLijruSWTevfIeuddLsRx+S4XFPRd7rHMrBx3khRoE7ojcKqo69Yedd5dUR/otNa4jgyuI9uroHlpUjV9l8vdEuBdrsqszRlOq0AwW7rxXa45Y/aH9ciGyeUa2B6Mj1Oh0l0WKg9bQj9OqK6+9Bo4nBGdMLt4971wtK+8F+ZWQgfyYhVx1w57btKCh70cVpE5H/YfFTe5Y7MvSvDEn+y9+q5UlDrEl18U59Gwp9HoEM89/8po+M+Ohp/gPU/ixtHwH+D9bDTceTR8Hw31S6NxSYbcijTlfW4V3/ITNv9QK0gBJA1SBMlspf0V71cn/3+vknOa9wnv8yRvTPNHddBZmv0pzZ33uTe/tAW460lfWPnqAsCTumk0jgtA2XEK7JfV1qW9S9kZckzmg6axVdUcF4A2TKCBeVYuAOVv9QIQkiPaegGAhNQLAHeCdXVuQi4A5WSjGgOaQK8GJYJyDSgRdGnvUvaTnOe5w+5nifK4AHBbShTYI8B+7bFJe5egx+O4zxFxElu5AdRnCuPnP7JB7XpnTc1xRFmtl/YHbVUHVLtB3TpPpHNyC2i7Ux24VhxtmVlKPvqNC3a/wsgtM7zmYyGNyS0gD58bNJCPYKrGkkDI/aAdG7WNpa6U+0FIBl1xgyusdMt30pjcD7JBM2jAFRtqJvkwKkBKVtc2jAwnga920tfe1OBkKk5qdNIOTi7VyUgakztFNrgMGnBSmXJFoF8bbdp6d6BfG22xVQX92mgb/6qgXxttC6WBIStF2BMYxnMRVjr7RIefKsa+B4P+yzAoX6rbEiiUjy99WTDGF6EwzKDQ+0+dCJ86712prV+z4HrjsZheZME4ZcH0DfTjOJ+yoL5xNPYXWTDNWDCwbyBjW77KPmVBwECxA/e5/EMuIHmQGEiAhrn9xyz4z9d+c5rFlAXNfWlOy4ssuM9YMMjvuABxOWVB+w0smHeczn0cJYGSHFmQKWRBeWLB48zmyII7sqAi2saCabliwX1kQSYHzRUL5gg693GUBEpDmZjSk+S0uJNNCYxNzCgRbDUi5CgJlOSJEldiq1OiPChRDWrXO+tqif7wjoHlwUqJ4nCXDeraWnIa50CJxwikTj0lZ5USJVLP3qmn5OyJEtNIiYwPGkKJjJFARko8GCpSVxolCnQlDa48UWIcKZEtg+agRLfsZNBGFjwuHWFwpbIgfv8xxsGVJxYMJxZMg4awoBtZ8Kgj+5EFIyrCyIJHrTqOLLgfLLhcsWB6ZkE3qxTKc6VQfBkKw5ehcP1VKORfg8LEXoNCtcygMOhfOhpmZQI1pUN340HJX6NDxWZ0GNy3jMY6pUN/42iIF+lwndJh/IbRsMK/R4dQEJQCSDCBJEGCXwXAooJfc/t/Jx2yMKXDcGOa5Yt0qGd0GJdveVkQp3QYv4MOFZLgipXCgFI8VQqRDlk80aHG6oxHOtTPdJi1nQ7lFR3qU6VQDppLOlRIgitWCgNKcaTDg5qEH+lwQdxiYUqHCklwxRpiQCmOdHjwi/CdDuGZ/X/7fi/J###4568:XlxV32DM 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f94eNrVm8Gy3KgOhl9mHsCAMeCu7O8zzCJVGNtVdzNZzDJ13v0iCWSpT/vkxOnOzM3CTfxbCAEWH3Sf1cw+b7dvfnPzMN/+67eMn9MwtE/TPm37pOe2YWufO32aoX3i829LWeEG/Gf4/kdJ+7y5/fbHtlZ/i63+jKPnjLFrLQXx4Bhvf5Uc5jHbapGmuT5TSyUPs7Or67XE2lrvq11V0py3dIMb03Ej441w3Ah4Ix43FryRjhsRb2AXfCtxxSb+PaWlFuz3L7Udca49cPs6hakKre1dqbHfvuC9aoryPrK8zrXe21e/b6BYb5SSQGk2TikRlEI2g1ICKAvZbEqZQMlksyjFg5KqUopseR312xcYsTosGPCgArbVaksUcFRmDpTWFYWVgh3QO2WgJq5Cpq4orYlZKdAVhZztRSnQFSWSTVIKdEUJZLMoBbqiTGQTlQJdUTxEG72K1lQht2iPyhYZ07CTryxkiim14Q1KgZhSG96kFIgpteGdlAIxpTa8USkQU2p955UCMaWEMY0qpgEE6iB7NDqrmDbyFYRMMfnma1QKxOTbOE1KgZh8GyenFIjJt3GySoGYPI3TuCsFYqqXN0gVu6kZxc9uDt//Koud3Wj87T+lpgLMHHbrKWb36k3f7MBv+vGC+0Q5zRfMYYtxvtzlLIvVu558iu3JJ0B+KJzC4P0bpV3oKWx4l8JcmlQKi/cJSreypyFwk+7cuHL7syx+Nt9RfCOfaZc+0VNN8T3MmuoHleJbKr97u9Ncn4dXpE11I5UN55MlmyP3bDyfUptPZe120Le1x5oKMxKr9cJYzinrrVJ4TqWJasRp2dWM02NNcbZzXYi22aw8QSYYwdQmSMjvJoicD20NTOWYOCsMSdrogdweKMfMcjhmJTdhpc/Vt66e2meg+/tR82jBcKeap+BpLJJvU3Gxl6bimmGQnZ6K1a7Nx53+bX0q5vdT8dHMWzOUvKy1rdGhrlo02Vbfa7VTX6NrI0WfDK0P0Mu3rRFFC/kNYjb3Me+fijmNdzE783MxKxx4FzymCRm8sz347UHw5mLw73gpfS74cB/88szgF6h6e5Bz4vcqphp6bXi9ZLgYuCxwsXApM9q/3bXk6LGem34WP2sDY/tM7bM3fPkcntZ+8/ejuvZR3Z81qivy4Scg2OFrKx8cp8+Nfr4b/QrPV0Y/nUz9eNdJY6Ka4zA8qZNqrsdwfM31kGfq/ZrX4aXrJc+liKWvcKl2a+oshQpgas2jpHTIgflHXA73iMtXZ4QKPP8FBwCWJzSOXG2WBL4yDoIdMjMMMDFzjSKKKGrULYpe8lyKWPpaFwlyN7E7T1HU5QKULTpZY1l7ja3kuRSx9BUub38vvE+AZtY3oj+yw/q5MF6RmntVTd24MRbv9ecSqh3isUFCRdqjXHH0z7E5oCRF1YYGCTQyA/ZrH0dIggQJNDKWjL0wltuANTnRWuq67EgZWRmlQyT3lTkHlhzp0JCxFcaS0de8iQ4gh4kcZu5WnEmHww0dBnZolcOBjFdhrGDHStghNaPgmlA3HL2dJIxNKDSygQXfhH279anduCmPNfXUzLhKbgoE1hKelt8DT8Spz4AoHK4LEJXWV0AUHiM8gqg4mOdxRF6vQVQeXgtR2wlExcE+MfhyDaJwbr4QosJHEAWv3TLCBTYusJ1blx0u0CcF6Sp8AqLEBs/9LojK5gSi4uCeOKrLNTjK00vhKI+ncDS+Ao5q/uggtPVSHYBeGjUcZV41QZFwlBk46rxqcFTvNTgaslA7HC0MR5kX1mqijicP/qkN7ayz9VJtaC+Nmn8ENQR16LBmXochzMdkBL4aBW29BL5aadRkNApXjYzgEWIf75Sae1VNPaBgY/YJnYz4PBcbJNRGRkHGKMkos9PsmBtCJ6OBySgX5obAZJSNMNZktIvWKjLKTId5kA6JjAYmo7wqh42MNmGsyCgV0QGKjBLDTVqVQySjgckob8ohkREfvYOxIqNJkVFamXOCIiNsJwlRkRH2GAlJkRHO605GdVs7p3maN+aiKA8cQ7mARAKFHhKPBJh88RQoveQUKJwCjH9atl9xDbdnIGLgdJOaXcoHy7Bqdz5lj+l57S5wZ3qwyLu6yBc8GokzPvb5tbyv4fdr9f3azAuFw3cz8KKQ1aJAObo/0/NxvsvHnKuKVfmYsi5btwybdYbltQUEyoPFcpY81qSgVEpaeRHGOmlxdsn9yyUwbF/E0AB3WW/YovCoN2x8eFBLskpMS85yWso9LVWVN2xBGKu0lPWGLfVcYt0wPTidTnKD5fTpdDqyhr39S4+psRd/OkFZZ7afSlBBvenpB2hm3bs3/jivbudW1q77r55X4+T66a1WnQn2hVsta/f99LzaPAj+KpSHK1utGrx/4VbLOjuebrWsS7m+ZAbeNIsXWy9ugJKDkpnR/lF6ph77586ra7+50/Nq+6xRXd302fPq6cqWrEYRX7glwxz7eEsWdvekThJbMswzuNLiS0clGKhemuTqW//fVg1Sji1Z6xZU6vzDLRne6+fVUu1bsqltyVrQVG1U59UuCDs6r64DfH9ejVEgC2AUVIIoemmSfFD/P7I7J3dlllIC1wh8QDViCWtspUkxw2hEM3FXRo+0E+lBqblXRaprGxJyBETRnkPecGu37TTS1IjttaPqH96VtSRFMXqCgzYyuCtznuEgEBy0kbFk7ISx2JXV/w+itQJwqsJ9MFjpkHZlbmSHUTmEXVlL+N1Y4E9bB3sHCPypWZC7xmzKIeGPY4dJORzIeBHG4mv7NC0Cf5pKe6widmWtnSSsYlfWeoyETezK2tRuJGXsg/Pq/O682i1nvwYZb//2g2t/DauG5Rf3fR8vrngc8RirxieSxXgRq7ZXYpUbyilW+ScG765hFYLCC7EqfoBVDjjKekAo4Cg7QWmEUoASCNX+x1j1+0+w66jup1g1PXFU7TVcMuNLccnYU1wKr8Clmj86GhUuMTgZq3HJ8DpqrMYlcyzcseOSGe9PsFHtuGQZl4zlasfHJ9jY0E4/hUvMRsZqIrKyOeLEpD7J8DLsZ6wEvhoXFS4xNRmrWckLV42VjGVWGpWae1VNPbikMA1F/m6fuwUaJNTGSlHGKFnJMLoYwyQRH5xgOyaJeLDSLow1K62itZqVNlY26fDdCfaoHBoyLsJYsdIxbWCaSlYaGHeGRTm8P8H2yiGxUu8ANFZHRbtipWHp5BMGzUoMUcEoVsIeI8EqVjIjs5Ld0wNWWt6zUvn/ZSVz8QgqvJSVjD9lpfi8hSXt11jJ5JeykomnrJSeGPx2iZXsHl/LSuYjVgI4sgm4CODIwomULXDBc6h1Rvt/JSvZfTplpfzEUV0vsZLdl1eykt3TKSstr2Al45mLIh8yTVxKipVs/1MUUgQr2Z0XrzqviJXg3ntWMp2V0tpZyfa/VkGTE1Yynrko8jnSxKV0x0pROJSsZPtfnlCYj1nJeOaiyCdME5eSZqUkXBEr4SONhqJSc6+qqXx0ZiLTkGFW4hM345VKtrLHJSrZ/oc8WOogYd6jUtoYJExHJdv/ygaNFSqZJBqrUMnw8JosHd6jUtqVQ0IlE4WxQiUj49fHSke/BeXwHpWMctiOlbwwlqgUnD5W4h81hlGhkskseIlK1GMkTBKVaFp3VCo17Uw1hUQGpSK/7HfrGSNNN8FGP/hSv/rZ7r7gVuBhpvjjL7jLTeemcsoa5VmJuY7Uu/MV/vMjFN+O9n+wXrV1SPzZESU9mtnlwffVXRF5RL5jm95y5SBNZDqQXvpLu/UNju1/oEiNEHPa7scZ87Hf2Nqcbp3f5WPW1qVsGfODr3xXyd2j/83c/RneHj/k7XG49JuUxW8v5O1a/dk7EE2DE7MY+6tf+bpLvG1oxXjZr2tp4//wFy5meRD8RTJzl3jb0EL8sl/XLvgj+ZNf1y5TzUiL3+tlinAZ4JLgYuCSZ7R/+Isc7LF/8E+UCEIe/rrWlOeM6v8AEgRnMQ==###3960:XlxV32DM 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f60eNrVm02S3LYOgC/jA4ikSIrqyv6dIQtXiX9V3iSLLF1z90cSJARopPFE7rYrqYoa0xAI/gn8hIbffJRpnVZR/p++fwkur0nlx5cUxaq9fPythSqqx5sXSsXDjbN5/C949fgStmlVMshhZx9/hyV0Oz9XSVG7pdrZx19hs2uG/1JvRW1mtLI8vmm9FLuiceuW/KN+sdVmS/MRm6/faNq8g5YXEUtTzqzCCzk6aURvvvT2mw6tlW86TvCZl9Z6mmT7OzndvPwjZBuO/v6H8Dqs5ftHkeYZJYvS1qSv9VLs/OyLnfzeNZN8fDW2a8LQGLkmIZp1WMvIijoqQbRmUkVbF6BMKxhv2GxYyyw9vupcNVF6YqfT9vijLnBZRRjFQkZRRt1HMSSL0takrzr2vi7ozsIodLJNEzxtMcTRYpcsSluTvtbL2z/eZNLNsPhxS16aNjHtNprq2oidmdt34z7XtDittUNEu7T+GsnmR9WRGBijw2ZdW4WxMlOb16FVKrVVGCsjwdgSY1iPAA5nTXoLU7cp0BjUGOpwys3hgg4zcyjAeCbG4NDB1tCRTAA4dOBQ47TqxBym5nAMQc0TcziBcSDG4FDXEToLduXPtk5NuzXF0hUuPUY/QeG6IsDKOlRsXZHTY2ztoqhPuS6P8SrEGlcRv/8VvFzVLFKNIy2YuEd79uU8okfWLHokOZPoUSYEnncX9htivcEluGHrN4S9BWXrDWHrih45Qu4RRINhMv3T9oiye5hlbSCDhxIFaIip4TUcwqvUnwuv+RBepX1qeI2H8CqXEV7Tk8JrHbw/Dj5/avBaHgavxDMHr6fD4JUcg89PHPx2PIHd5wavj4P3zxy8qVs50ebD48/g9bp8L0pfhm5UvYR6mesl1ouul7Q2+7dDT/YZaz3ZEj5B5YmBR67Em/4p+qfsn6p3cOmfrn+OjnuY1yn1T3gyS/zunwLnTR1XNfZVldMTV9Xdw6W2Mk/AJXexpc0VLknxClwq8aOjUXmYhqRQMhyXNJ6jVUNxSSOClH3Vcal813Fp2oh24JJDXNJ41BYTgkuUiEpHO/2Ujg5JoWQ4ERGOKJqQ64GfwReezHWY56xUfQEXVV9dUigZxkp2Jq46K9VbgIasYtptNNW1iJHVUachM1jJTggRkWnBVtMhUlTSqCnSAAkzUGnaUWlDkDCISloRY4ZKmnaWoZLG2daSOgRUmnZU8swhoJKeiDFDpTmR8TNUmpFP58wcNlSaEJVUYA4BleZIjBkqeYZKTQvgExgqtX6CIjJUajMGisRQqW3rgUquhB1TQsiCoJQBlDoj2StGmh6Ejc4JZwcWr9torsBDhTBiVJXOY1RBKhab3BVrSPm0wAzvHurkXBPfm/Jt7/8H51U/h8Z5g0EPNppjYQ2izNCQOEKfsczDSPDUhIYDQxX9oc34gqM32gmG/3uLHvd07nu6T/5Q77v2zcuUQllnUWFgh++yWQh3lyB93FMvwe2fx+yg7mC2zJP8Scw+OY1lyvmSrvtpLJPfd7y6hyJB3qHrsu72hXRdmp8v6VqeDP4mhwVxh65L7/wL6brsp2u6Lkq/louql1Avc73EetH1ktZmf0bXMGMjWiFV67T9Grou87Zc0bVQz1rVKPMnk5ZhukPhZRT5hRTeIupV0nJ+0iQRCm9xphF3e+iGtKAU6HFV/u5cBJqdwvu0VE3df43C23eHpGXTdgoPU6fwPmhoNp8mLZtdT1rmd0nLNoqG420UQ1pQCvRoLX9v6G6hIC5zyy9iixW6ocUuLSgFnrTUpJsNxOGWnpacmXYbTXWtws70pGW/D5KWcmhrh4h2af2dDJsfJPEepKDZfqb3lTkkLUsQbJzaV0aC8UKMCYmXvzXpLSHxfiSAxlKHx6RlkMyhAOOZGBMSLzdNZAIItfRzF8YumcND0rKc69Th1BzmTIwZiWdC4l3buHqZCIn3foJCEBLvMwYKSUi8b+0NuCm790lLKd4lLa35NfD0vFylz7cgKuXXQNR0CVH6eRzh0z2IyvqlEJXVJUSZJw4+3oOovLwWoraPICpXTLLlUiClSEuVRJVcleTa7H8MUb8+RVnmzVxClH3iqoZ7cJT9S+Eou0s4Wl4CR9MAoaxQMig5DkcZsSI7Dkd5x5htwFH2xxRl03Y48gHhKDts1p+nKFtHO+tkhZJBiaUWGDVsNLdQ7sRDPJtLMpoGBWWFkkGJ5ySMI646GWWH7LMw7Taa6tq9MwrZZ0MyMqidmBZs6ZwyMMrINnlBbNjepyh9RGzYEIyyIcYMjPJMOsvAKCMyZU0dHlOUPjGHAEZZEWMKRikLMn4KRnCWgkYyh4cUpc/MYQejiRhTMFoUBSPQAubMDIwyZiIXzcAoL6gwDIyyJ2AUjilKKWmK0l6mKM2/SFEWP+mjFKUsQfWHKcrw4LEpXLKGe1ZgLoeTukxRNuXb3v8PzqsPUpRtIKcpyqahKcr9GROKhZFsEjWh4cBTBTy0Qo3XmZQj7QTb03uLaexpofqe7pM/1DRFKWKJIu9TlIpRdvqvpCi9v1UJENtvAk+m69Lq5Y6fOoqIqNPPpij9dqsAIBr1ygKAaMQVXU/LyeDvcpi7VQAQ2+H4sgKA2N5sLwoAYokXZW/kcimUWy5TvWz1IurFr83+tACgzdjvS1GWeZuv6Hpyz1rVqKZPpij9cqtQIDboelmhQGxcdkrh0/akSaKFAjXOQFFAfeiGNKNk2XEVB1OChhQKxMGibf9BoUD97lhXWbWDwpdRKBAHjDaT07rKagcpyrLA7+oq6yigYqCOYkgzSpZVEcSRUYSRklqBGGfaYqsLaC12aUbJspMXf/2r3YRagXYLoLZ2TLuNprp2n1LRf1iE+xqIY2VG6xDRtp8d4yLZ/OzFAnEQfJPgZ0dYmUOK0rv+UzqsjATjmRjTYoGIBRhtu5BigThSrU0iDo8pSr8xhwKMBTGmxQLRRjIB9IfVaBNqEnN4SFF6zxxOYByIMSNxVlcJWuBqVlcJ/QQFq6uEGQMFq6uErQ3FAtGqkxTl/D5Fmf9zKUp7D6JMeAVEme0SovwTOcLchKj8WoiKlxAVnjh4fQ+irHwtRJmPICpUTFL1Uh/A8o5dLvUVprxUl0ujK/MJiPoNVZTRTpcQFZ+4qvM9OLL6pXBk1SUcpVfAkdkQhEY9ZV2AISkOR1gx2DQUjrDeqO6rDkdWv6uirNoBRzPCEZYaVpPzKsra0cE6o56ydnRIivMPoQZeRRmxcLEN85yMzIYUNOopm68uKU5GmbjqZGSxThL/0QRot9FU1+IZbSKyD/54i3VVrUNE28nI0DFSMrI4eiuRG07KKL1GbsAyyoi1m9WYk1EiveVkhHNgMnX4LkdpmMNORpEYMzIydAIYGZl94gJzeMxRWuYQyMhsxJiRESujBC1wTuBkhPWVCyujhBkDBSujhH09yKj+eOvW0lvkIk1zlMt0A4kICv2gvFJ5dTMLtLwkC2QuASY/LdpHeywpZSAiMLH6Qb7WP3i/3eXPo9Pz+u3qOpmTQ16VQ9611Ejpfr3t82f5OMOPZ/XxbMaDQrVgYPBQOKtBHfeMeOwO8RhjlRM8Hreoi9Y9wh5+BNpD9ihMrc2MH3L2eGWYFoKW3YgxC1oWo4sdZavVEIJWX+Ch5i9slnjkL2z4pmsX1mQLS0piWFIjLBUtvrAZYszCUuYvbHtJtinzKlehy1uWFBhNDHnBUpg3ffeLR3vNaW/u/Qtx+i/ZLIk39bPv3R+/ge0tK/Nz+ey4f6E+fDfT90IbPBAzD23teZpVL/QQOigMbfPHUOf2L5ZTyjNuvgh6sw7v/N1GXD3femsDtJ95sOyzsXxqNsYknI9dXwTOWccnjv3eSxu8zsz8pa2P3f+bneCPO2E73Qk6XxealM5sxVsuAd5MvkpLlUKVXJXi2uxPI3/r5O9Lhf8fw1GUpg==###3984:XlxV32DM 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f78eNq1msmy3TYOhl8mu96I4nxOed/P0AtXcazyJllk6fK7NyfwiAMUK3HiypWuKEr4ABL8QV0itHgdL57+P77/5nR8BerfvzsjX4yH928hNRPu6Ps3Z44XPQVJ1zx5cXe+v3HnU7909Ec9RpWPf4TjLL8HnZ/7/mEJ5fkt5PIWJt7/dbY/Nz2uPtfK9x9OudZPHDSdsWs/1ayjq3XUMHiKStbwbE1q0S8T9Dtf0J8LplwwxV6nPLxPy8kbTIM34i/yxp/xyI7g37+k17FXuvzOZ7yfiX4my9nX/OPHn0SobNz5vbUc5/urkLWluCm38GhegZDcO11LYKnZBXNpTddTaw5IcnPpbKA5d0lOen/l0dcXiqFF5ZbcJ0R7IUjAjQDORD+T5ewr942AdwJRCXiQpeVU1yc6D09sZ6KfyXL2Nf9I/Xg8LmxOWbgnqtIc4tBs4GHQHLo9vFyEG3Vt9r2ZDc21d7z6lQeaaUSNx9kdd5YoQGSOEg/dWinnJQoQmbPGQ18613g4Xd1Hh5YcD6dqy3kBqY41tJpCeh9yNeWIxRTVTWGDKaSaoi6dqym6DY1jaMmm6DqcKBu8YnJLjbGMF3dWI3Uz8vO0YzAyFCNlN5IORh7VSHHpXI3k1V/SDy3ZSJ79pXV9X/q1jIjSakoDaQ06vIGtNpytwdUeZ2+grSGGN0yU1JCTiQop5RH+8q+TfP/d2fNF2Slz3lP5h36XFEMFZK3Ih6wVTjZmrXCSS9bi5c3pd+3aseUfHWq7ae3u80Qq8wPc54lUlAum3dme4GLLZLw+KYh2lC2zuf4AVmyM/nOBlgvVhpSfrrkvLwRyWghO/nMLAZsWguTImpgZebIQ2HkhUMhCoKaF4ISFRxy/cFlUszfiz3mDT96gBLzBfsob4IQ9u54lwQns5Bey64md6p9jFzO7BXb5j0bCXhLUoRyu73Pv/znLX+p7MiZNcZ5Ww3QW85lLZ+TIZz6f5emf+v8o9sX636Bbimkm9DmX5lidtTUl5iNpx7MdaTNQtaNuRzDcVkcfoR3rXE5LTzuSHmaDKT9x/sIwm7+p/CSm/Jj5F8IstMWUn6D/hvJTXeXpfmb6mZ2U32fltJPyk321DV35ya78+KUVlJ/ZKT85Kb8wtGyVn+oqT/cz08/soPyuWikkr8UsXWJ91UdkGVQTqq7/dD8z/cxOmpBd3gWa0HbRF+nQbOBh0PyRUrqLvtA1Yex6Kht1aW69w5Vz0IQfmSK6xgldE7KucXTXOGGnCcWkCd3QctWE9gIyasIuww9+NaVpQtpNUYMpiybkkyY0Q8tFEyp9cdqo/FjvwwZTqvI7uylyMGVRfmxUfkoNLRflx0blx7qO46Py471BjMpP9AY5Kj/5UX5JLZKXfaWccXThp6rwa5qPY5rvfKb5wudG/76Kvq2Uuwox+zeFmEKFmP9HFTkmxBwqxNgvW6XEkQ2hO0HFV7lHnd0KKjOsOgOERxUV/3UQJAOIjVKhSamQM2uR+Cq3/bwgASEyC45ZYMDiRsskd30h89eFrK4ecAusFH5aKfrSkwwdVoqyHvTeLff7Kff3lJBbSnrOz+nZ+7MB4YbmmjI1vfQeU+YnAeuWp3LHmjKHpKhLGih5pDzyHFouSVGTiy1jUvw8TQ0vq0lR9KRoW1LMrZukqMakqI+h5ZIU1ZgUFWSyUHNc/tfzWCtbg4cMRt7fXNmaev/HFU35Tv3KEz9D0bimpqRt8ylEDeOdw6OseH8zjtVxBuO62kCuzzL1WeQgCnrG/vI0zEqPNFCyGS4PxHwlNb+/5h8//hS2LZr5hvTCdF3JyqsXXtN4xS2vQXnJY16N8+o9rwZeA7wa4TUTr114beXV6pbXobznY16L85o9rwVeB7wW4XUTr194XeM9b3kDyksf83qc1+55PfAG4PUIbxh4Y53yA6+vvC7c8EZLMF4ZHvJWG3a8sc+pAbd2SLjZioKbr1xwCfMtQeY7Rl6y8IbKSyi5BT5RYP8YmKDAfA9MAPgEYDIBawA+J+BzAY4AbG6BKQrsHgOfKDDbA58ATAH4nIANANMJeMlY9ADg8xYYTVmSPQbGUlb0bg9sAdgB8JixFANeN/HShZdUXuVvcRmKax/jUjS+dI9LAZcBLp3ia4GXTbxu4T3bCqxveT3KSx/zOjS8ds/rgNcDrxt5oajOd4y8bOGlLb73GZqjvOYxL0Pje+55GfBy4GVTfB3w8ol3WYEpq7w+3vKiK7A8H/N6NL5mz+uBNwCvn+Lb5++0Alc5PvByyFe3A9pJDFg8DrARKPA+wKVDBnayAacrF2BKYO8w3zEGmC/AokkscRtggQZYPw4wRwc02QeYQ4AFBJhPA9pDgMXEGxZeWXkNveWNKC95zBvQ+Oo9bwDeCLxhGtAceOM0oNXCq2BAs9sBjdaE4nGAjUKB9wE2Cga0ggGtJmBYkZyaArzOYA3A8jbC6AyW6nGE0Rkcjn2EYQZbmMFaTCM6QITnGRwX4FYE6/uMdaC8x2PeiAZY7XkjBPgA3jjywlZzvmPkXTY5qIUA89sAoyNaysfAEgWOe2AJAYYRPW5ypABHCPA0os1SFdJWBZPjuI0wWhaK+HgKo2Whl/spDGWhg7LQTGUh7JvlO8YIrzmrlcGE3KsOjUZYPI4wnrPCPsKQs6yGCM8564AI6ynCSx1MWx1sb1OWQ8tg8bjuN2gZ7Pd1v4Ey2EEZbKYyGLY+8x1jgJd9O9rKYHdf9qP7dpI/jq9Gef0+vhriayC+euIlEF8zxXcp+1mrgtXteHZo1S8eb3MYtOr3+20OA1W/g6rfTFU//KVXvmPkXapg1qpgd5uhHVoFi8e7HAatgv1+l8NAFeygCjZTFRx6wpqqYLNUheyEJcndAqNloXhc9hu0LPT7st9AWeigLDRTWQh/+pjvuAJTEtcRTSFF3+no1BMV0mIjs8IdcjNjz7zVWa1Hgi6GFOpybSiWYluJy9nEvahLxoD7rl6i54HnavmcG9WXLiLcTWAWQ4B7LBJP+DvYcjZxL6KLQV1M2D03nsPEc25UdrmAcMvOTTu3nLhp56Yz9yJFmABufs+N5zL+nBsVI84j3Kpzs86tJm7WudnMvazQTILm/AtuPKWx59zoIu0cwq07N+/ceuLmnXvJa2bhhnKZhHtudENE0OfcBuW2CLfp3KJzm4lbdG4xcy/79AyqZmLuufGNr/M5N7pT7wzCbTu37Nx24padW87cy/41a8UzOek9N74/Qp5zo1vYTiPcrnOrzu0mbtW51cy97OsyKKLJec+N1ljieM6Nbu06hXD7zq07t5+4defWM/ey/ceglj7/Iq+htQePz7nRHUAnEe7QuU3nDhO36dxjAWLsskfEWkVt7nYQDL5HpJ9uAlYb9h/Sj+0uYO2RmA1sEhk7bBI18+oNgyD3y642awV1/yS01eMeTeLm8S6+5/gfDuy38T1sa3vY1vZ8/9nRj/nbta+lNPUGXiioL/XHH6Z8dvvwerpM5j78WGKqt3+Y3PrZTgHT+pmDfjQ47w/5BrjN6L2DxDbr1R7JQc7WGf/F2SHlNfu+f8lgyfp3uzP/qZoX4tOWL33NNxTnmdl5vFXn3t86zzx0nsWdpx47z+DOk3vnGXCeBeeZ0XkWHGTAeXZ1nhmcF9lS+nICQvH2gwpDdaLe1EPudqoxtPSN+91YBqUvg9KXDaVvs67eMGaWZTOWQ6l/3H5P8WgdpJ6nFnQzNiKZBTZjPezl+GEzNlL4AOynrRy/FPocCv3jdq/Oo/WPevz9yKNlftx/P/Kwd+VhL8cPNX6zrt5w5SVn+350zQbwxdvcZYN1PN9mg/QiiaYDHh6mg2b2Ph/wbYnYuuQ/0D3bp4gv5dp1B6gZmeZ9ngc5J7Sbx6TQZhEkhXSPWpzYtgt8uHMiP546UeM59XjuRIU7MSJOVN2JujtRTU5sejTjgRP14kR+jE6kdXv14sT/A3kfpO8=###3396:XlxV32DM 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11e4eNq9W0mO3DoPvkwOoMGaqpD9O0UAWQOQzetFlo3c/ddIkS67u/p14V8kpTZtSiJp8hNJK2du7Hb/rULsv1HV310YUwe+/GPvP4LLt6TY/d/gzc2y+4/k9E0Yzu8/gmc3KYwo1yK/qd0XHkp1XkqP3zGHsuPXjV+P5/ytGa+/b8H2taSY6+/fPynvZSDef7ZVldvvv+p/f/8IYx2ilAcKJcRC4ZIlRCmsC8WZ+oxt00xKmaxQxNa4yQ3Po3yhlP8ahRGKqxTXKCIQiq0U2ymGUEylmE4RhKIrRReK87oRyp/qPqllo393Kco8vOij/Hv/N+ziJvec700zvAi9Sz/r+1vZy5DuF7VwZQmJsQtL4CkMU4he/b9NoS4Lm0ISGlGQKUi2G0RBptCEuijYFGJkeB5kCjGQFSBTiEETyjKFGCi3ZQpxp9yQKRhsCp3aTYEV7fNbkfpND1MIap+mEKYpmGIKYZhCmKodUg9D6qFJ/U116RZVyyruDanabl3VWvmh6iTsVLUDVZtL1RYVhqa6yt0euevJXT1wl4u7vTSYaSBNy/OlqvN0XYbtoP+yv7KeajO5UWx1EnJQqhr7012roWk1eXqPhXuqfkPTb7IczdD1G0zToh1aDB6e81WLPBel8BvXt/JjQY9h6jEuPY63qIjF3ZLe7/N1GhfCfQp/XPD3o7w6wfD7FNy4M92L8p3sRuDGEy6uJ0x9wqV1wdYnvBzms5ZlRb0zrGWZdJ+GN+5oszcLHBfUfZriuMDu0yYHj3wHl/CmUrOvN22GizDdpSTX/RTPsRqaQeZVXFEzr1wYNfPiKYJ5qUDMC7bik6US9slRCftkziXsU6AS9qloC2y06twf3gAj+xJTjg9LFJqNJQZR5cD6fLnN+5aYwPuv3FPlLDH3MASgt0cBGEYEgHbhP9tFPu4izl3Y7+8i+oMap5fIxn1FjftRjeaoxvWiEPW5o+Y9sQ0iif3o0cyURHiBJNiBu+OTu/km9z+Cm2op6v1ns8py/f6zaXaO9jkqnOroV/2vAKu8+e7rGqXwv/8qr2KjBIMoZcZKac8Ia9FcZW1jrjna56hyLKMR0wtFTI51PZVjcQONEneYyzdvP/hk2xfpELmH7+A7RRMKOPpCkYQC7p1nmQkF3HuhBEKp4Tt0YUhLKBWohLEpWEEVd9uUl42SVA817VWem8pdyMU/91UC33JP35lLnaIIpe7MxT4jhxn9mNH1GWOEVQaY0YMYk0RkhILK9hKhAAoqy+CEAiioPGMIBVBQoXhCARRUKIpQqhg7DOLZuRpA3a38BAigcQbQ/SqAhvsRjw5CpO5gBtKvB9B9PdFinAvrwnY/hFgNIbZGVjF+n4iwI35+EGF7/PwwwqYvRdjdXkbY8BXX7M5VcOKRzf2LEbbJ+izCZqa/75H90SOXkDS4i0fuRk8BsKe47w/c/Yzf8pG7Dw/oe4hEHqUojlLc7giYl20dYf8CDo/bkk49APMrba34SZTk+QWAyOVw9m0l7foSQOhvAYjwKYCwnwIIczDXeAEgMlMvMFdxASAyY98FEDwbCAG7pY7ebISCHL0xhIIcvRGEMh19BSp1BbpSyss9QIlnMOJzVGQ5rwkKWSzMWigEsjiHKAiy9DzDnHSgE89gxOeoTDqvCYpdHAihLgxjl30JQc+gW/mMoGs1IhPsYiWhIOxiGaEg7GICoSDsYhyhIOxiFKEg7OIAfVS5Y+wyj8nNm4xNVTFh7OIBR/kOHX82p1eP5I25QeTBXPTtATDae86lT0NAjhXkHgv3tAX0GQwsYJ95GLf3uUG01cgwRNodMsyprQDa8oHYLYJIZicUgEjOu5EUKMBtLrIlBSSPsqV2OErtpIFoAsepHcjyPQNkDueaiWwokNn5JuoVfRLfNfiLrQa64TkT8ZzPhHN39I/mo3D+p8mjy7CuDSXo+KYZoiC5S5Y4oYDcC0URyvJYm6PcwGOVFWhCmR7r7y7EvlcAKm/hxg2oayZlgyAAlAq/gMWB9Jyk2dcWEE6QoHcodUfQHEnXzlzeBHO/VRoP5oU5bVHDm1bsQ7QneMt5K2QNOo/jp595X84ZgB2DwQ6s6pMYJXgzD4Ftjt3/CbtBU/UJgiF4xxF4g9KMvCV11VmSZWeP69YcR73n1y35cRY3l7y/UDr+KB1PpLN/IB0qlHhc7szZ+Pw6oXB5mMVO0Xv/OqH0Mg3NUmOh+M9NZjuYTDquG5ilF0pnO84COnAvlI4+SicR6bjPpSMP0smHdUMeyscXSafCvHrFvf9sjqcBufYqj5HkcC3OUbG2eS3BtQ2uZQwCy6s0qzOVgkBg8+OLgkDglOV759sAS7vWAYsQLiFyf1Cx/qCaFDmRWo59GUApi+7oKLmVJJsCaKCyCWCMJIdrcY6KAOa1BNc2uJYxIC3b9GhmBEgFb7EUZg5xztxHdeZxLc5RnXlcS3Btg2u5jUYBbr6w7+O5IcZtiTEicl9Yq8+UmySIcSNVGa6ApYhDjN71bTpEQRB1OtP3saW+DOVhGXtEZAQ/y03AUnkMOsvfsEARJtY1nZtFFAQoZ8Sb0h7LsGsZAZHHg2MZBpaBAWV5RdnWoMhWi0kARep5rkMReYoccWl2wUAKJfcDlBwpMHfElv6APnHKy5IM18xsfalUJA6JrJHZ8mcV6wcIBIiGNXM6zV/ZWYBkYgIOuT9mBg4Jgf2YELBfryh4nBAoSxRXNRxlHpeo96tUzH6WeRFMXcKA+CiBQ0bg6RDEVL6CAVE+zkLTZM/P0tLJ6qRYnZV7nMXSaKeP2TGkRXXUor5/GCBZCxPqLOOk7KPSrCZK++i8tB8nthdqvcQvcXuRWmuErp5jK/6nmlGPslXVc5RI0qWHs3l3D0n17jlKJDixbXq9xgcHp2ZMwKcFmMZnjBIJNQyiPJMjt9Lvaaf1MjQwTR6+t9rR8L1sS4iMIxFrBSX53m/vnQJMkiRMc8L4Hgv3rE4B1kLhusfAPZCYKXwi7MHgxEyheFgfjW0MYEX1IHPfEfYtBSKjqlFhaQkFkiXl78VSkuYYNitljYKbY9jGCGU1xzBpCWU1xzAZCGU1xzBNuUG2sMyjCQWyhc573HDRRet7jNS1gyre9C1BhOQzQmocIemZ/OQMfog3p0ftJ07YrEHe05NqSK/zxkZe+fwQXzjLduWCQnjhLPrqCBX86yLLlj88QgX/5KmbNc2fnpzC/mK/rOvLYMT0xkbCaIORhpEiZ6PuudrrVFsO0dmovjSLgs9GQ0jvne9wpeXadKU6IjI+GyH3Vm7HZyPki8x2cjaaWxwhxEgYbTDSMFI0wGiPeD8GGODdw4qRMNpgpGGkaNBZ3shIchhh2iEKcdjLhxpBTg5MG0RZJ4da0NlUcWGhuLAILkxMF+b+Q77x0bed+7QPasLtILadZAkzHybOM8/3f5QrSMTnchaK8b8WSFvO7TJXWCc8nebJzGHZC7sqHvP82V6+WptTlzVQnl4+l7iqMvL48rnkVc2Rh5fONVuYWpFObbP2p6AyqKAyqASMJK0MCigIKUkrg6ubRknSzJQF1D2VOPdSbT2jLKigaKigaKgEjCQtGq7mGSVo0VBAp47i2MfgVhx1qMkJqE0phn0MbrhRjJa75FrBNmt05dqs0a32I7Xh7ES5CUqQNbuCshM8M9F619UN+nRqQ0N3W564LdxDTFIQp8WrB7925c9wl6i59Ffbt1s4UnObknqo0Ulx0rLn9WUD9dlBs7A/dlBDAkPrrzRq2Os6HGlPiPbSIcoX9De6SxcoXtDfOM6fTeWzl9HCyGFH0Mv98+bZjGhh5AiW4AxK+5WC30UmEIW8i2y1xVnyxqU8X6mq3lFgrnP3AnPKq2vOjBeymtl8IRlDZJIuZBLxxWcxzmapvDLqpfJ+zzqVcVhvvwdOZc7v88MED8/1lvaUc89CloOWhzd9m2/6/vCmP12v3q9f+U8a1jfSsG6OKcWPmuU4zjFelVfzQOk5Hcqr5sHxiEvH417geMSV43FnvWPxqnfsIfe1HTwQv/JA1nzFA7mnMltFavzSA/lve6DU+lvPO+bdtzrmD21eUV56uld0zB8huAUZmRdY1vGrAkiz6v2pkEaSqB/ENnXxdVDW/luxzV9YlroExfoFlqUPUnMABOxTlvXxhwetK+UcZavvh06IKXUb6ITew6RpwQYgbARYGyWMAP5GBSNNoG7Kq4NcEaibsoLpFQREtQLiir4bBMRZTSzkiMgkh5sz4ksytzlBQNwgICqauQW+/Z7VSJfy+giAHPILZYVgCTuRkJWFByuZZGXnZ46DstrcUl6t8vyAI1bE5jAZX2Jb0ESA2MQS247IGEew6BBfktNtDctdbALExml2F9bb71nZ3Q7QpjFNWAZntihhBGe7qGCkyTku5fWFhiantZQ1suUpFT1VgGHObLbMqcGcQGEO7zCnECLKMA8zGZ/06VaFVbd44w7wj5r4JxD8Q+HOdYIGvip4qKg++xEBpK2PBdVPW8bWlDY80TLGsw1XGEfOxu6s1GuSQXr7MBlUJjxPBtEAdYl0Cr64Qh5yxqPMwmuSJjZefVcg2cvlZpbc/gfcizTp###4660:XlxV32DM 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121ceNq1W0uSJCkOvUwdAHDnF269nzPMoswAB7PedC16mVZ3H75CwsMjqypjFt1JIT5COOjpiQg2PaJ2x3+C18c/welH2tjxH2n345tL4RHP8/gWHHtsIqjjWzz5Q+aWf0tpHuyRJfbhojqOH8GEXHH89IKzlEtb/o99fAt1/NCHtmUIqx6Cad2H3Zwdw5oyrJ3D2qNUuDJsHv5sw/PEfS7tePhzaG7b8Dyx8HwNivXJgshjn6yM+bdMps4Rmaj/jlaOuUxc5jJbn0ukMZeUz+fSYC/2S3OpslKB59rxtuQJv7It2W5hXQvsuHm73dI619gjEd9ut3O1WyR2i1+127msxfJhN/1Wu/0ruC4S+/FXtmAex8ojl7gbpXwGRp2Hugh10MMkqGs9vpf//fw3/7usQ3w0Sdbj+K6yuYtEBSTJmhVJ69Ps+9HGLX3+qnXZQlVsBBK3jpK1jn5IcvNs4eO7TK0P32Cy0NSQ+bT//Dcmj9af7dXX30t5/aPOQ12EOuhR9Ox1rcd3efa1WDRxVVZG3SQOlhFhlQ5WqSMSt45nah0NrNL1VQbTVgmWKerWVTrb+igkaaO5rX4ArM9Tb9F86WWJbaMpDRqcoKCeCnok7kOKMiTzDA2ZL9gy5NmGlKC67qrbvkEcFHRdddvttCFJm8duTQLflgmg4D4V1EjcO4rWEeyUmzc1ZFmzdc0YuWE8hvru+FkPpXzwfCjzfx//BC8eW1D5PJfjycPZz1zSx4+sXDtzVre/p8RnLo/kLu5kXPFsuJN4mj8+0GAu58lRFMYgCfpIBZsHznlqfC7xaGD8egvGi0H0MEicBhkG+JFPd9U1n//FIDze3nfq/3Lfta8pLjeVRBJ6U0XcZ95U7fKALmDRYh2ZzfDI5zE8uAL7mGGfhO0zPUFU4ShfUNX6+iXZAA21KQ1db+h6Q2fb3zBHNOKYW5BvkPY39hFj75DmyKaokC/UT/asfkx4z1Qaeybf7W+rgbC/1YzAR/m7/nZf/K26O5BbfDtOsetcdsy1v91ufrUbhd37V3GKvsXF59vt5u5w8ba93W7xJS7OE37RbuYWF4e3283f4eJNvB0X85e4OE/4RbvZWz/h3+snsk3AJebdIrhNTmDmBurIdYA6BBIT3CYB8ObmBLex6WA0xW3SIQnCbeNw13ksqOGnGgyJETrLjQCR5uYEg7G5ZkVhgNRIQjCYBH+aPcJQw4AaKiExwWASEGlujjAYCUkMhBUKQg0LdRrqIGDh0MNAwMLt4ujBNNwujh5LaEgC8NR4gJp8WntHYhKSSDBAbk5CEpbQF3YTkhgIKxSEGhbqNNRBwMKhh4GAhdsFm2R8kbHJ+bAPwQCb2I5NPMFuUk7IwSs7oiZYOWuFnhXuuMIZzLBE5YFh6RXxAKCT/5oOdGYPrUsPO3vkrSoVflbI44qNcsU5K/ZaETtYWkBTkP2v6n/1Ap4wmqpzhameYbViqmc4xlsNZ/3o9wzFWak0TFNLU62X4qwoxpqIy5emGntb0W+/7NbXsGGTgZBccl6qgW6ji45uo4v6WO5heyxEmaHb6KI/CGNm3W2IY74Y4pTR4x2GYvt19N/1Yr6MrChq6naW19HtSZwXsrNc7byvdt6Oq7+jdhbUAXq+qjZ4Tn1d+GboJ6DW/dTrfhqyn1QT/ZwatekOArLt6xvt3fLJGzXWG5988uflkx/rXpbr1+WG45YJnoeErNvfQTim37DudXTLxrrP67qVI+v+42UN1yuL67HgUi3wfRZYPkuphXiCM/e+k0ipQRuzI0khU7IkNokmksISpcYS6ZNIwGc2zzjU697NAh1ngYSznpJwFjCZ9RTMecBk3lXFe++mfTwlEjftg2vacyIp2ocG2bQiEgTztCMSXSRNDU1HU0XSIMmkc6pEFklfFMxjE4WGvvTZah8Oi0oD0TVdPKzMAvvoJ3dmsZjARyNh8L0uvE1DaL7K0M42BtogsFn5zdlGQ5tiFusnxTjbKGhTDGTbRkxCp7YpBrJtIywY1S7EoQe87U8wkBu7nrxA4rbr0i1wtkrKkqVdEKA/MZzFNGSVlOVJvWD0KimLkmoJIqqkLErKSlAmRFB2Y1SCUrCw59iL+4efqG5zYTBO4wZKkkI0wRaIJji66ScVhZHZAGQDhw34RVHXxgB19ZHP4zVXtekFTG3VIYazt0yYUJ0kVpod9upS0wSHe1UCwa59X2DXzgF2XXkvQF8xFLU5upKFLLHtBkGsmDgApSbZhbcQw1HsFlKTblzlVt1d5foegiHHJFgll7HL3EaMbCAV6vYxnw+fusyhxzJ9eIkABUulrcR6dLQa41WPxUGODf/MUeYR3JL43XxfrUzX1Sp/Z13/0t3nXWTLLm7h+G/Idyj/qMKfbWne4S2tU7kIX27+YtuCFGt/Y4376wTVgRJzdRwVE3+fuU6zzLLLsSlXcy3A+Tc2Ja2zDNSmnqzFaAKg1QqgNUHDn+DljbwLYDWdQzQxQxN2/TwMPXyvAiL/i6fx1KsCdmwre9O2FtRmGyyqp64itPpBjZKBksaoLXuM7uSbZNIdWZKGxMXmIGub5iBzkUHHTvrUXW/gIfc2SIzYkCzpwKA2r+ChzoDQX/VjuI2BNoAD878DaaOhTfGuybdxNKwhde+aHEaR1VwVMVZzjZKBkqZZspHwrCc+n+kCxVKbaoMFK4wvBa+8EcwVzjFXLxko6Vr6Xv5XRrQBzxXZ4M3yXBGW5WBrFGyNc0iMEGvuyIkEcGmWqCFJFtOPgsWEJDhtzNwJo3mcNhbMByRpGtjYJJZIADCijHGTAEzMEkkkAA7zouloAAlzn0QkAAmzMaGPAeNlA+eLOIvPNKBk8fblY27SfF03Y0TUmYA/a4lk5pP7uip+HFJXBbwLUoRvt+K4jedzz3OQn/8Dbs51FHfuONEMpJIjyTuCf4w9PqOd/Eo7Zd/n+S5WGmTEoDKNLPWeP4gRe8c7rsF/yjVcolS3emOLo9RqobZPRUkcbe5AlxcJijY3FjmRwH2TJZJIJkO7Gzoa3C0bh3i3ScbdUrcvXrbPj+2T5J2AQVC6E5X+U25TAbdJwXXhScuuyRuGqOj3G7sWPt21yQm+ohSqPYapJHlfskMGo0jQRUE2S+KLgmyWJPHkbuhocFGQzZLoosj+WXhdmPCtZOk1bNeImU5FmHD7q1n68znPDAEPIrcjjm8+TdKfT2OUNTcveH3JIJ/k5qPr7GtuwwDm6T+CeXx7mZWvU/XQiCI8e5OHzzrxRe/BGke/X/WuYPL3QTDnK9Qe7HF0+o3Wca9y73WqW+tQo4hV3REZ+O2NRlmB6kivR6feaJTwKrFep/rskxHLJ3Oueo/BvHijdda4aSTRo5NvtE58lT6vU/3aJyNWdUeePHr+JqOUqEO0NGW9b1qEUU7wKCkoCShpKJ1QGtFJ0RpHJ1yK8YpQGJymrbf2lOC4pZvwo43bApNS1wMT4QQS48CEbwPOluY4HOH7HPLEadr+nm4YoMUMxQCjpKAkoKShdEJpxBt1mSjeEF6gmWlUwfDMNYKoM/eSgpKAkobSCaURfdSZUfTRz+lH79fNGKYZORKjJw65kQczBsyKZzNu0EeQGEM4jSTkaermQKJADTfVYEiMH6DyzYIajgQafJs25fiJgxA2IAlii4ejG9buahhQwyYkRk8cciNY2WZQwFCIgb0gxLwBLsMMAB7nAB6aAA+9ZtwNSZ/fJdifQRS7Jsndmmj3a9b8KfYk6PRVXp1kyZ8k2Pnx7LkiTrDLhRN+jpk6VgIMxKS5w0AnkHQifJXqEuf6w5ORqDPndRbPyL2tV6rrnsgSK5EFuX8TLvO8ILLcnxJZ0t5Bs9NeF/qn/GSd9yk0O80bN23lJyHBb/x1FqvuEvzq+DXC8n5bN7Y+6Rj5fGOfbKu8e9Lh3/qkg268v4Ofp37fxm/8LtFvrqd12/mdIexxk/H//MO/JDQ0TQHU13tPkeap3mSIAqoq61KYJAm0rQRSVzooeSiFJ6/8xwidyZTAc0oHJQ+lQHnOHYhTGSjuqI/ZYOzGXErgNcvYveShFCivKfcx9sYHAScDsJe7RGLCXu6CSCayKK4USxCvuSUigXx7/rcjEsi3C6boPJBvz/OA6pL+hIZJoH/zgR6L8rAoALLVQo0tF5Mt3zkSk9/R7Gyw3ALY8jwDYU53PDdhTrdIemvojTjUCpRmGwVtEJtaKezZRkIbxKsCfK4fKwJPTMLqBGQSpJ22AeJXQiZBnGAbwJP1OCBsxSooa1qdwzYiYlo2twlobvzElClGemvoDdl529H3oG5FBOp2w78RaqboKXhVUF3e+EcATBcHpjM3P/kozyrnC8gLWfQc53RO6AUHVH/wtT1DDHa+YoOfxIbzxROicQsO91BXGm/xgHifW1Dp1vnw981Sn2E8v9nZG2fhd0F5SG/zHwxilWI7kspRG5KQ60vBEVWRHl4B4Vz+nPrhVREOr2JITJ9w7yPtpeJwVCqNUjb4KHGakdzhOtCcxPxMKSQhucp5yvO41wB9aNGdnUqjVFr3El9+DrejEa8OEEZsLq6M2EplxF7iyO2VF32h/HpQsPI4Z/5cLo27wV6eXC8vrRc6frzFNmvcZ9dQ8Usvrc2xvvAhkeGfBILif8+RNEw=###4308:XlxV32DM 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10bceNqtW8uS5KgO/Zn+AB4GQ2b0/n5FR4CBiNnMLGbZMf9+eQoJp7O6qrzoThfCIA5CHAn8fP6lDv1gjx+Hs49o2LMU7FCwp1pgZg1VC+ysEWuBmzV4KQgqFzz/UbG0lf9OqIIvFZLvgmMKTBWELoi1Ba1Y+91ri39FW389T5Hnh9I8+/3jsCmrIp5/H25/pN0/f0SrHzwG88xts4eU6shlgT+UN7lx1RpTCsbuoi29q30WHLXAzIKqn7KzwNUCNwvy0P45TB3Bf1nFCtyGVZRNxZjSSUWhWVfxEAVB1nEwdfyRCTz+2vqxtm5H62cAxK4HAOyPWo9lgjRu3Q14zbl1G0br+4C3Q1INBuOsAecFXrHCKyuaB2hkVo2OodF+nnBDJ1yTSXqtwL4qYGB+6bSGFfgwgHffn9YQF7s2ug8zL62zXYeTXZNhvjNwsxr4sQKwrwbuFgO3CxJmH0jEG5BIa+txIMHOrTtJTFCvJvja4oiBlSoK9WdZ70+rM/KWEeTf2tNrM4rL8Cwf4Nlvgvdvbr3UEL9/1knK8uev7IyrJIIkm1rW59nq5LaKOPqExFnt/OLh6ovbRiS2SGyVSEskpkhMkwQi2YukqSFpa7pIdJNoIlFFotqg4J28Btug8rTXQRV4ZZFkNzEGFeqgfinbdIkHvH1Uyc/q5rIFtMYlEvfGRRu4gcZ9HXjrpkGQXV+to0gdA3WqAq2HjZM6O9QpsFjfBh9JHQ11CkC2TYT0Q9NapwBk20TMyct7TxuD7QAJeIcDQGbMeooWidusq9KZ4HuBRY8mrXp2gPpTgCcLT7E+/Sr/VWAVKBWbUnk3b73CTOe1N5SKYIrThrMrKNP0K9OBhqRAL7Z5SH0e/MAvvzPmYe/zkPo87KTODnXKPKQ2Dxvuu6GfKvrCGARIXokdkPEU4MnCU6xPvzItavMnCNhFe9UX0k4kRWfVF5IjkqKp6gtJEknRVPWFpIik2IkqGljf1lE2jgj25apAdUGKAEoWFHcl0oM/XHZY7vffhxcPeezZJRXHxYPrvintmfNZ2XyT3RsHdP1v1z3hyg2r6U2Gp3e9MD22X9CoJICKZJf5P2W35w+XGWUM4at7DjMXe3sS++19Xe2eSejb+3IXm00S6ta+stkxPswu91o9cJ7TKhEJSYgnYLDcmO1eO9q53FSV7GNBMVh4DBZZ6QsvMhFRi3gDzOQbJKb35dryEwFJ8P4S02xtH7tKW37iQBLkcrvnHJp338jAhzLwlwUL8Jd1qdm81Lh4HA+uYbHxsdj8XGyYb0SdQ7G8+kRbXXQV5t8ZaGUCX5aleL08cbQncCxX6dhp3dIQLjPIU8h2XtDbGrnoNIxRdmNMPL02xs/GMaL6Wryg2fN/h99nhy+7OTRhk4bEL5g0MnnpnI67F/EWLiK+PMrbcVMrbo7gJr6L23bpaP3tuK1M28Ac8dtxMwtuZiO48e/ipi43DXc7bqcADOaI3Y6bX3GLBDf2Xdz05QZo794ABbC4PFsk9mrWUSRbHCGIMBCCTMK2daacvW57EZiyMCTCigmCgbyk6G62IQmJlsTsJ4AaaqohkZhEQgIkuTqObWICfpo9It0gOZKQmEQAD94gIMtloAYW9xe7GsAWcnVEk/uea8c7fX+V42mDaKUg0ssilCkoS1CmSSwT02QIeuE2DkkItxEwQ7ndMcwZd07OX7qtL/YoR0BQJjyJYGI6kIWd6dIAYFAjOZ42iE6KsfSyCGUKyhKUaUSrykKSLJOTrfwDaiIGNTkwNXnN8zGv95eubLt3SXa7aIB5Gp0ygSRnKEFCAjiGW4MFXuDhBRruHjxXEICQHAgFQt5OSaNK4nAOLuqAkpBnducJq+s0r/yGKagZVxs73VtoH872R8j2jyT/yO2/oYHJrxl8ygd7Sr8X1JT5h7l9J68IIuffTm3HUEYmKSXsiWT5Iq9Id5gXeT6608SwhlrzYIK9SCMqkkY0awL35XEDySO67YqBcvb9JKxTV5yTpRumwq9TAacM4o+mghwqmA7NnIrTEQkcGfA/moplBuzFDOgrLstuSIO7/Yq9snDDDIRlBjJf7Unv9JkZEBczcKLe4zRDx0/NwGvgzdUOwo4bgLdX9Jf5G4BPK/DjdEOHrwH/2h3VdP/28lTj+JY7uloMl5km9t3TMcLvHLA6B1zOAYNzGp4g9+Ig9+Ig9+LcwgYgN+QUpr6C6UHTildBqf8s0T2dXNxZSzm3OkCPcx0Fb3ua8GeQWXIboccxOnjHjey42yA7PlP2TnZaWba2QStZQGLEnrMuG2oXpZ+zRMJILIzEEYbNNIO3LU1Ec4g3HM3uxQTvZGscI3FzJBN0CyNJMBIukRgR5KxLQO2iY4AsOWAk4xig1QESnet4GEkiyX9Eoh1QZweE2QFNdhqeIDfpIDfpIDfpltwkB87pDM1Nxgg6weGcMxOpOak7IBUmUhyJUfyYx+pQu+jsLkssIBVgzskpXq5j4O1AT/E4MGGnacYUTtvKWhgj0XMkHi20MZIRFFmv+zmEcmCD7YBixycXbZk1gemCw8EImsDiI41mBO1IY6s0c89OeAeivg2iHvGRxteOMHIPQa/8pm8hcvj4jYnP+MKitj/tHH3Xk+brjdazNvnCbcv9i43+KxlYc2keR8sN+iFBviK/M0y8jPMcj21FEsa6q3XaU+kBrbHNCdQOWmOSs+HJazsoY7J5gyTTmqut1LPbHNtJsBU1bCV9bCtl2uKVLdivIoxi1NI8Gn/G8cASPErHkYSMMhl1Cu71GCW7PuQbo0QhnGWXefFh+kmpm4J7CNRzr2g7R7kxS60js08swekqo3BjsB//5wWLvMT26hEe3AI++8CHY3xq7u17oT2N4N8c2Nj1Al94H7HDwU14GYav5zWC15yzehGOx9gPDwVz22siDMp8QIgzuuzdSU3tqud8d8KFLbnpM6lv1nuNbSASt9vQu85fpb7OvKe+C9MVLPEFFrjeF+MZFi2wUf8xLLwmrtWra35xuxF8+e64p3b1EfgbAZ8lseo9bsnF8AId9kV01jtbBuZA3oiOeneoU7v6LDpy1RsaO25Ex6y9wByIG9HZ3x3d1K4u0aGgbOsFvHEjLvqbQMlktt9x+VknARGMtltk1l8dXmUVdY23J94T4T+rZY+yHcoklBko2/CeI1hIqGPESATXHPd8hNFzfao99zIBZTuUSSgzULbVp1/lv9JzHEPm/fbCz1rWyHauHpGYhA1xGypHRcMGz2AwAtOLPMyAJCgkGE7mdx9SV0NONQ4kJrF35KCGpLF3cNAZp7cvWI8A6zZQ44+GaVVVbK1dBj0qUIhNhRwSkxA6RFCIkRCa7xZNZU0yNNXqE+/HSR2bXrZDmYQyA2UbZjQZdwsD3jClzpoIJEGUeizQ391E+jD3OcyExCS+HvfzanUSXwcL7wScH7DeocitS12nT77Qp3KJjE96aQZ9EuRkhLKkN9davsKS+J+zpHesyF6yIn6jc3XvWRH/LCtiSV3SFnfj1uMuaQu7EZ3wnrawz2/M+pK22BvR8Ve0JaT70EnsLW0pXX3WdvZL2mJuQ4clc8kD9tt4QPPUprowC95WgQd2UKahzEPZ9NmG+ucDdsxkFv98IAnxzwdsb2k/M5Kh4mAVCpiGgzINZR7KJjcxlIdEi7o78xDor3MJBfzCQZmGMg9lk5EYyj7S3GX92H4S7LKcSSSm7AN22cQW9jGplKbsY25ZSS/sI0A/DnbBMNUQSEzZh4ddMFD24eeUKpxFwMQpKcJLWJykwoIabqrBkZhwjmhADZy2LwvGl7vZ3JadNcLOasfOKt9cGEX5B/nyoujVVYJesD3xXQK1ZiL0uum+vG2Ab5vibwvTE90/+Gi/Tna9duDOFxT8ekEhXV9QmHcaTjcUsvtRl6mFc2Qltf9kaiFcphaSvi21wM7n1uN43J4ZjNzkF44G56dQZHiXuYGk7ttGgrzaZNONmRN32hLHAbp9QXSsvvpQcntefrb2Rx9I5l7M5ZeD53yUNOrqy0G7auJWTfbnRxZgLux6u+IPSd438ZXz76+OvE16Ydf8408ol/G7D7+c/HAFqCuKk8SNqY7+oVO10vqhU7USdIKX60hSR0Md+CIva+tJHQV14Nu83A5svGEJ+w+I0bPD6ZF4EP0kML8okLh9embjEtxXCd54FZGgg3YPXCrQhAA7gPY4BWpwUCNgMf4CDqU6nFpum9r2KVjrrBHCIOBJwtMGT2qhi9B2UAsphDSKs6CumqhhcVM3NdS8JxIUtE/WVCXm/wTbVcM=###3776:XlxV32DM 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ea8eNrNW8mS5CgS/Zn+AEAsIsL6Pl+RZojFrC5dhzmW9b8PzupOCBubmYrIOVRKWU8ChD+eL5DPL5X88+9/CnadD/YQv/4UzNmHUuaZkasikiAaEFeQ4AmiALEZienKgAYg8IcK7Al3Ytwd406OO1XuvlRQtdPYm87PRCYyEg0gXHPctg+97XZ3jDs57lS5+4If0Lafwz4f/hxPp7PC1+j6KP8JD5r8YJsoh+A6spAqYjNy/KqPK2WftQe4y33b+gzuW6kTEOjWXrXX/Ksb7+VZ/vsSJxcP/nDw79df/hKPw6n4/MPb9OAxPP+IMA9JP38qAZZ6/siWaFfdrqZdz3a17erq1Tbch3oN5f1LmBNu4CH2q/QXFXv+5fPXOZ/7tfohDOd5KC5/tzCijeVy/8UYap8/NAPzPn9ms5TfY0hw7ZyCmYNRAU06V8xpEZJf6JbmB48IyU1nxBYWwZxOBDjwlWevtHZI3E+2wVcxBCCMIGBVVaxqhCcIWFWdFTEEgWWlTEUEQWBZ5R/ABN+YkBdUR1VhgkkrE8w1mJAmE1ZL/swsrr+nNuupzXqZVLj6dm3vpVitYXRjgtYLE/RZmXCGTzOBi5T61OVhFbPmgZZJTQIh1ax1VSOzZqSaNcXFrAUBs6awmLUgYNaqlsisBZlqicxakKGWiL8A3PM3I4i/9gqNCQm0pDbYmcAWJnh5NCYkhjXBN03wzQq+WcH3Nd+s4JsVvLvTgh8q2s4EuWpCakxI38CEMKZOtgUe7TLbcjvbEs92mdOJVPL4VROgtUIev2pCQabSY/JIrPSEPLKRx6+aUBAgj6+aELt3KJpQ0MKEQxxuYcLJU2cCx0ywbZZtm2Xb1b9pgG0aYJvlbdUA5ey9d4gsrkwwlQk887VSITj1afcAw8IGj0IjBBn8YGVNdKSyx4HxyqROpFLBFuOFwHA/hQq26EjwZASFCjZURBMEqGB9RWhrQAVbdCRctDWggnWFCqlRwYIoVLRRgZ8LFS5pOxXEO91DiH7jHnhwn6bCwdzR5g7GhfxDmaGJYP8w7QoI9g/TrhWZ/mHatSLTP0y7VmT6h2nXitz4hwLcEhgQ7B9aL80/1Aabf4hrpHAx16lwvFMVjNIbVbDfGTOqrc9VxOdyERNCkCiUOZ0IFgXkH5QmooD8g9JEFJB/UJqIAvIPShNRQP5BaSIKnmNRqGj3DxAp5HA3E0L0qDHqzgX5+/KHN3gYcWzyDx74h2UF/J3c+jv2Pf4Okk2YJGD1n2WAr8LRnwGS12eID0R+Ri4+kCGE+kCBEOoDA0GwDzwJgn0gbQ37QE+QQfeDhb584ctQYncIGRGCEzvkuWHGUGKHPHdBZmKHPHdBZmKHPHdBZmKHPHdBZmLXPrQldhVVBTioS0fRHberjpuh4+qduX+IYbv2ru+L7mBYO+cYKLOdRAjhCLcIuedI6eeWIxW540hF7jhSkTuOVARxRGKOVLS7dL6Wga6rU0G/tQykdmUgG77TpW/LQEotLj0iBJeBYE4nsikDqW0ZSG3LQGpbBlLbMpCiZaCWnPQykFJIFNaUzzPemWDeG+fHbZzvvyHOV2MVxSXOdwjZxflxG+fHbZwft3F+3Mb5cRfnx62URRrnaxrnj5RPcOMzDc7H8bCdCtM/nJ0Kps92tovNNovPddob4J9j/nM0J9r1IPaItskCPwE4EBlMk4UEtahCBq5NJ4OznQx0OC4Ho2M42cq+hVtcw/9I3LzozfOX5g/bs5rrvP04Fy36uEamNoNLN0ftJp4adfMPZXOs7BJkYKF/k+4E9wImiLVVUz8lMoEnDPYuzk4XmDssA+LoVIbx5DeeX/ADxOs8EYL3SPjJ8TtlJyLPAiCmh2EwiXWHo7xd1wA/BRoG7GvkF0V9MaIXsbbVaTrG0GFXpD4zVM560xXLDdQ1mspG03PQdPguO2k6ydZTCnfQFKErWTS4LIlIadTWnPGVlP+RAaF1vbYeeuvhN7RultZP01v3/2Pr3eqy0EUViv1ZvqffGUw7bQdTMwC8aYXVxsfeTN29g2b6naEcNRK1g/bx9DkJr1sHrjHtQEh9xR3lldmWaq9UN86NQMhcCdlXcndl5h3wbzDPd+a5PfNG9FNaWGSuMcrJVvHmMnfZrcL+vVXwsi7toynLv1uMzM9sI+kI/kwBza0hQc/xI3tnSMBLA3chgR/yCcr5mf2AkX/CsPDOEJLRdJKIgF8YwREBHzvfFZkRAb8YQWZEMGzUkBkRcKcJchMRFABFBIJ5hJCI4MQRQW1QNSbIl3rP6brYRv6+vaHfwaW02Vu60oe5BIORO2LbbyC2HUyQC7ElQiixL4RQYmuCYGILgmBiB4JgYhuCDGJzEebY0uv23NGAWr0qL7+Qvz9Tq1fwDN6yE2dCHeAtO7yqE9myw6s6kS07vKoT2bLDqzqRLTu8qhPZsmsWa1t2Fa3VHkfXrkRrd03szGn6yhXvVXG3I7v8BrJPq7qF7A4hOxV3WxV3WxV3WxV3WxV3OxV3WxV3VMUvygTXmZBkWms9om/vx+ONROBO7g56HLolddyx60NM8H1Sy7gQE2CCJoCIwN3BEYKIwJ0IBBlEyIglyCBCRiRBBhG444kgr0SowCQCd6dBCCGCR0RoDVYiqNfdG3cMby7fV/b7DVTSuwryAar2USoBsc2W2PLjxHZCDSoYyivBCLLw6gBA1xp4e+SFYf2Z4jPLM7gaGnrFsTyDqqHJaASgYiheU5qUxfGa0qQsjteUJmVxvKY0KYvjNaVJWTwLgUezgoVA4emiQiDJRGIhiATBQuAIMoTA+oCqsW141ZtHunTN9OZm3bsxcXjzt+7d8Og2Ky+IT3tz5Bfj1i9GRwv2V0IILtjDnE4EF+xRABAdKdijACA6WtSaAUB0pGCPAoDoSKUOBQDR0YJ9wgX7ijYmaLlm50cvQkT91rguqI3qFQZ+OK5zI3oLisZ1WiJkE9cFtYvrgtrFdUHt4rqgdnFdUJu4LqgdfwPZcLKBnMupDVZ3bsIqCaMOGs1b4zqzy2aPXrn8oPsLU2cNSWeTCQjYxHVG7uI6I3dxnZG7uM7IXVxn5CauM3IX1xlJicCJczAo1dPxtUyTTdK4cP4/H8sRzGzcy3V+vkwT0uZUztiR/LCvg5IFTFEra4S0KWvAM62sEdLi/6a0JXIGDWgzEXwoB1V7QiKHclC1JyRyKAdVe0Iih3JQtSckcigHVXtCwodyuBh/DgRfRry2NQi599plxm69dkXuvHZF7rx2Re68dkWm1w7kUE5FS2AXyKGc+rFNxNXLX2GwvnDtG+O6/BF+m1HpT4s40kPtd3qo/ZJ7cISQ3EMhYJd7+G3u4be5h9/mHn6be3jKEElDf49E/Ho5nTXiOvfOU7Y8+J3qpW+M8IPfRkh+UTiOEKpwuDWqcCfuhyicJAhWOEYQrHBk1EThNEHmKdugqCQgJtj173EsTHplwvXOXE8wtnPG8fuYAKO6ZwIghAlBIYR6DYaQnddgW6/Btl6Dbb0G23oNRjVBU6/BkCYcLzuxgwn+rVl/kBsmRP2dmiC3miApE5xFCGGCPhCyyfqD3GX9Qe6y/iB3WX+Qu6w/SMoEQ7L+gEJ8ux7YtH4U8eM7s35RzHKX7F3h81l/mIuI06zfcoTcZ/2A3Gf9FbnL+ityl/VX5C7rr8hN1l+AjZJxmuyRPfnaYDu664EFHM72cDaOoYR+DCXiYyhEFch5Pb2e00Mn+q5xhK79h3suR/vC3dG+fwGTqT1O###4464:XlxV32DM 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12e4eNq1W0my3CgTvkwfQBJiqgrv/1M4AhBEeNNeeOnou//JlGQi6dXz6+qF/Sh9iCFnktRjeTx/xmV7wN8f0cr89x+/+mOFVv61/P4r2PSIenn+HZx+KLs+/4pWPVa/bs+/glseYnP5GbwivX7+kFLBe4DYh4v7Mz/Q44EoD8x4sJUHdjyQz+fPYAKuREBL0ZVsfSXLaSXCHn0lZlqJnVdi5pXoeSWuPHB5JbCiA1e0z7QRdUV2CWfaKNFWFDYYLZRRfshjqX+TeVxx4Ne6FQqI399gvu0Bz5/fysy59T3/V/oY0gfGbH1y67s8Sh8fPO0Tjt4HWt/zf7lP2dH2u82wbIBYAUgQFgHxABL0l5MpqEN0K8++FcEB5tVRNwK3UbeC7DuuCQgj7bNOkFvf83+5jwysj8E+JvcxdRzH+mjso3MfXfto1kdhH5X7KOjjVlEWCj8dou75D/B69/qxPkT+9/vv4LeHAIY/C9e33TTGJv38CfSqDLW6MbgwEkYoDXEhLSI2YdmXISwLFZZrIUHGZ9Lm4Qm7xbooiqRMLFsIkbcykMFk2KVNK+zQwCpt36Vb+i7t2GXfFazIdy2JpuhRCg04BlDUJ8WydiWX+ldLKuh5bjPRx8RKn7DsjUD2CGhpLLM0erYjpilrNx/2yAvayfB26cNvp+GFFcx8mLopahPspU3IFJymWes0IH9kmv9JC5tyQK14HMj07TXTh2XYNiEbI/Os1B7YpCiSWQz0rkjXxUyQqsi5T1VkaGp80RT9/Q4Mq4ggL1YFTUdF1qZY+Z2qoLVPlrkUah9Jxq1qmTwgsQhQXykRYLfuTRdTxAGLLm6r2U9SunYpdVRKgx5CuGZ+BTMeFDkJyNGoY3ngqNr+lEeqf6Nm4gqL8LO47pXRaW/iuq1KvxZXOXsfRd0ejGEngTKqz7Od5rmS2zasn52avhLgQtxpPl3ny40x31sFuMxKBBilogBEKuC3pa8U4xV1RXAwIFmR7Pp2kWxoOnzRV8kG3lZEkRerZAdbkeaeyjtFslufLNmhjWvIuFWygy4CLJsAB4fvNQEOYAUeKygCGAMU4a2JsGCG1hIBVZljtgmoHZZXF1baMB4UU2yHCdaF+zaOBxCP/ZROVOEOex0zyKEeRS6DGg+WJ9eopi9Do3SaNKrpnJt0rqtWalY12dlVuNmpEC8T0Mu0B8UQU3fjz+6G6G3ZgaZuOLSgLctxle8s2lWfhGL6JGf7r5pj0HOw+JHmBdS8oYpUBQvVqQrqoy5R+3Ra4qbWP1A6GN3tEwG6QbEhnAmwijsChOerwFrPlDD3gfWgFaOEmWL+HhMUVz1TolBnGFk5nz7UHCRoZnX5WsWHxxEgo5zI2OMJvcgzGY17LUeManqWn8+RcVDvV1rWbplAoIh19SJ1ADaRLeX3FsdLBALz/tBRdUsYTA3Uy8skDoDfnvUx2AfjgG31C+ujsQ9GBNBnZ30U9smBenK1j2F9JPaRuY/lPgS2z3yI23H/e9t/2AthKJCtdTHe+RWbGEJ8RLAMGZ5hk4Yh6BnWZSytIHlfQdXR+ArybkJddHCUm8XxOVERjYjuji9vufE0ErTuyca6Cs2QvCdbORkUQ8rZofKvyP9A8p6sr758ZUjek620CxzJe7K2eEhFQrzGv+IhxbLG7CETRHlrQg8pepAX6IFra85rKFVUkStVVI4rVVSTUkW9cqWKarLSUR3P0/EOfjcn9qGzVcPZ/pDO3jvdbXK6zcd+FMYucxibaBiLaQbJwlgZ7eSDL49rw8PieU1pxR1qKkTUF3kZK3rAGD3mZdbtzhD6l4bwlKgJz9tD2bCMw5+IZVM3GZtNmNNaJ8/6yYwNUMSt80m/hRhqC2eK6JVR5KM4wU670fNujr4b/b7dSH8TL+jVXPA3fZ2/p8jJzvw1V2cWIISZCNHPLFuJ395FCDuxFT3+eiHoQd+x9SSkZmKrnXbTUwhwXnrTbn6BhT2qVS7UoweppPO7siCqJgqLqPWWwZalyUOgT/ddWWSIW20i1BHqVytNBzL8akK/VZHhVxP61YqgX92SORgy/GqSkiHDr6ZtQTrolidztlIoEIR63IQBRFb1ulNr6juRIMTbbskqhgxvmwgnFM3UwWiOICQdC7twuB/TVrBVWmtPkLoCWWltV4ZgihUQwRBMrAIiGYLpVFgbnweTqLA/PlqmtZQjld0lq6SyK21by2DL0ngVeKSQDrZSCNxQXUUiCEl0wdwBV2FpkAvvaIJUCqXKI5MYMmLbtAmiLZVH0Y4MLGpLTr1XSWotgy1LgtBsTmCy9eHhnOcxwNl7gHPcZ5TnQOKlj7/33M7cekPxRm9ob73U9sZZ3K0LWN84i781zcu7TPNQk8KhohKFir3lsOWZmsSIIg8IURMq2PkdoiYxojGFcS8Fu6yiCHFZRW85bHl2uiJGOK+UOhYV6YjZidQRW8thyzPHEuMwt5aaaJgrEISa6JjGjg01qvCOIwi9/ii2E04d6yPfxaBSyq6Ukebl6OHiwECGnynaqaOpaQtbpN3aX3GO/9c56SZfJd1I/M9zbe0ccG0bhg0oxoFKtEr9DtOfJVpjULP8kd7o/e4WebuY5f4WWV5Tml4e0yRN0vruznhz55Dt/s7Y3c2rLzg88ldJm9sbYndhL8TXrJJ2NxG6sWerJKS8i9DdHKGHlxk9e9r/VUzbopIr82zXdxvOPas2iHUzkhpNqPYXl+a9dzNmGk2dnszaiKu0vzBrOE41YRoNnGbGLAi0jsC1mqwpXeotRUwLgWmkHKNiCImUMc9XkREpx3gwZETKMVqGjEg5JsEQEilrdBXa8OIADKi0xj0ZLA4Yr9WL6G/FHtTigGaAOkyKA5rZF79r95pzzBPQyLWa+dHHYJ8Rw1a3OPpo7IPRbHODo4/CPqQ4QJPigIbW4gB/5OIA99hIKKe610jMa8jZa6g5aaXnlJSZU1J2djCOpbWIZ2HGf1y1+0PdpGzMRVHPnxgMPxuM8PJIrz88DRfa3pjQ9aIA6V9Zjlqioi+sREfOBTWIsDIaTUejmhIRUFhGo/vtu98PApOzWyuUGchcHjOQuShmIHMpzEBQxmG0hSH97JYZ4Y4cHLl8aTnEXDcxlwsT85NDYNlTkjW9vN0cV5T8mlPiNeerhGuWoZFgbZd0H6ZR5V0YFa/CKHZ12W8sX11Uug8uKolyujBnD5ty6nIzPCmniqc000cp0MLGu5AkvUmf8iz+5pZVC3fexBq/fjs2ksKvsqeeE8Kn+W6x5zXFfibEoU+x4avsZbiLjfS0EHt3k9iP4ZRW/nwhe7Mg/9L2Xt4bgmHDYj+gEQlC4HdkCAYhbRMDwSAEDIlnyLgGCzoxBIMQeAeNmvM0wbb6GAlCr7M8VjZVBBNstKrReXqdRQ218/Q6q6nJQPA6C+ZxDMHrLPg91nZwsz+2E7rZhy7d7EtBYGb2pWLIMPvEYeW5iMPyHlfuWeKL1mF6lviCPR0MGcVdYVkYMkq6/CEZghe4MJpgCF7bAvcSQ/CylrrZTJhrN5sR6mY9lZ+RcAadyqK1Zk/1kOiqTHdV60flmncxUzB3RzkRxH8Qh+T5ruOQjHACHRShBOolURUhNaBD9co8tAY0y/dMOttJt7HqOu4U7/KMa1iXm6yZ8O6/IB3MxzSiXzIUhOTFiC6Xd0idJCF3fudSHguC5IZTbq5nmwsTXSeduLyz1nP4f3Jk9CIas0cz8YHIe5qKhnoiZ1/imchafT6RU/y5mIMS/AxAnUcPy121o5pd0M6qajZxKn1qwY88uqgc4sCEzf6VKl3GXSAb566mCMlCjmLFvEhy5bIGoeg7tfzdiV7+HvqdUIFp+Tsp7XeinXDz4MTQj8N9BUZ4HwRaP8cq3d1q6EG1vudafXfRazioDt32XUD3P7lzOLBqW9xUtXu5vKx3/kyRu2/Fw+LiBsHv7i1ztGKhWsMs2gcUeVoqGqQCOkmahmbVzZKmoVtt9NbHJRbYpp0gLA2dS0pnLoXOJfkFLrUS1ysuRbu9LOr9FJdaIewVl6Jxb5ljcKlsqObpVu4NaTUv+jxn50pdwyuoDFZdGXYDC781QTiXvKlFvOAuD+TT0dM+np2HeZ0RYdzFYXa/PMy6821By/Cr+VTbI5lP17rPp9up5p0V6PrnZ4+7aT7umrmuyD3P34Fsa0kBXJ1/HdbokMLKcNwVvIdxyuouoLAt3MRx6XhVW/vpjPxashb7VQXQcq7gFSq9cmP6RZ2sP27uWFN436ZKuM1y+J1y7jzJF2+K1qIJ6uKzCoUXBXSW24pf8fzs1dEpJNl4oW/R0as8geqBFSv0FX98h/TZLzPK4fvqDiX5N0puvElGqJ5uZeXx7nVq+FVWIrzMCNupKPzuOJHsm+iQa4S37mrs0YuQbeDFuh7dRulDinUdlsn6g7saLAPKNqIV6/oDv1IZdcaWpTdgSM0QUq3rPENIta5DjwdWj9YPrVjXk81tX0bAZThFYBJ11nBU9RHLvVrZYmslbMXeCuwwBsioY2ZHLpgKK6lBCHsd84Jr8prAtGxn9YIhpCTdG4aQQnSXGELKz51jCCk6d3yeqdS8U6XFJf7AVsJW7K2w8KjFY410phz9rKnUmuHYAQWmtRK2Ym+FhR1cVjsIF5DXcYjcEJJ2einy3O7n4PRM4Lqy9t1USXcNFbGoIqQ6ftT726N/E1D6kC+oSrQ6+mjsQ76lsuxbKhvwWyodU7l7g389CFt6ugKjyqTmOvHZOM1+Fw3wXWYIZlZZHByxQ3LpmfRmh3S2mc1TYd2z+8IaWjZKFfUbYU2skRr92CGvKgtVlyyNH8xlBF7A7NCWwkD+DxPuTQQ=###4388:XlxV32DM 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11e4eNq9W0ly3DgQ/Mw8gNiB7vBXFIGNEXMZHXx0+O+DHVUg2ZQszRxssZkklkItWQXw8fz9kxEnH9uD/vpBOPUPr8PzTVCeEMI5B4gQNiHpv/TOFglCTEZMRQRCdEZ0aU3h1lRGVBlBkAiRGZHP378d1VQ8yMM9+MP9+sc7+mA+qudf3uwP6vzzrxjIQ+zq+S4MS208/xZG5b/vwrbf1tS/PtS/QVQ8qvo7FvxdqnL/b6lk+RtN+e2oLA3lH9uv0m9U7PmPt+oRtEsDMPJBpRFpTHZ7MCpJG5SnsNOt/t116SxuFHbyO/fC115C78V+Yy9i6UWr3ov5xl7k0oshvRf9Tb38pDLuuZdfP8oKpfvPH0WK/UqMK1mu3vJ/+T3flK0gqf3nW1rzjGRdm0jqMSPtnYmI+k7Sm6zUVGswijTqNop+JcaVLFdvSf9qXxy0WPpKGln6CgG26ENvsV2JcSXL1Vv+r4xxtsjbGK2pfTGA1L4sq+9MhLV3jKrvUIDUdwwrJhk1TyZpk0naYZK6m2T470wy9+zTBT8xRSr2pliR6qFY28cVq8wrrK03E6wtfbF1o5fWu+lVA/hi60W0/MTkqKRfbD35dNO8fekHmkzWhYkAk2Gbjh1JMwcmE3fX9DsvZ7WOLPp2lR+uV82eusVETUCD0GKi9bDFYh2lxXqVW6xXzZ6axaQhdh0vTwOLiUoABFgM25QaiEcWE6UFCLQYEnwOYir/GxZjusVEaDFV9GkJsgWkxTJJTfwz37Dzhi433Lyxlxt+3jDlRpg3bLkR5w33fOZxZcNSUGu2qjXatHBAgohda0IfqtOpNSF6aza63LyQ84YqN9S8USYh9LxRJiHMvFHGLOy8kcb87otNZkcbugsuo64sZS+8InICkMpS9lgRipDMUvZQEYaQvIy7rwhHSGYpuyuIwq1llrLbimwIERkxZemjystO9kcS5T4W3/bF3+Hil5CAJBulx5KNMmLJRumwZKMiWLJJL7FkowzPE+dsmuqZ+Way5HxjvpmMPt+YqqdK72aqnuLlxlQ9VVTBTNVT+nkIBe/Ct7l7oPhbftMDxafPk6BxZjJ2NRm/moxZTUavJrOfmMxghUlNwmI6ilbTMZydmI68Mh2zmo5bTUevpuNX01GvTCeNtXjOMwZLOoOFY/0z1pck4leJ+NqL2vZDL4y7K4noVSLm1pmoVSJ2lYhbJEIv2DbpbPs7JFKCI4MhX9ZeJAlHiXiFJPLKNeLZhGI05278ZDaBfaMuHiTvX7vxyFuULBYEUsriKSEyUkoyonFDZko5Ym5DRkpJInMI6SllHoFBSHbWQtQQY4cbNzjEAAdvLkOMWUIMQQgIMXJHCAgxIPiYJcTgfnqI6RkIy/NJdl64U9FvwJ3SbwafyWyoPjPZUPo9JJb0ts7e84p4gNTZ+zoqxhGSZ+/LqIIdK5P7mdwqzUQDBHCrNPu5Zr0QYbL8XQwAqAMwTfw7QvIATJlOCAYhhahV8QuCkCx+U8UvGEKy+I2tqqERksVv2kSH2mbRTkKYJioBMgnhT7dDfYYFF1ok3dep5K9VSiN/zW4ljZIkPkEfchAK1wiF304JhUGxv9knjJ2v4p7PVDGK1Zf1eCfpdvRlilz5Mgv6Bw5Z0KX57sIkpZ9p3r9ylWiFU4/YxDlAsIkrhAATF2MhBUcLCVyW4NjNTfcjOHBzWQgsJ9Yk6Vea7Fha35eWzKVtbrt76+6ku2/GS94IoUUcsvM/wPtesTq9sjq+sjr1hCxOrKRtMlhdhuMng1WF0nrAYIsKnjPBG+LnPp8r+ZX4mdUALCJ+TFwQPx2ONIf6Y870oVW70WTXXO9ZLUR5ekdhbqlLCIeiZyNz2h0pI6M7muUrquY+SV5DKVGpExKli2zXkbAP56h2JTfqEzkqGmLwV/xLnzBfp6+GaD+fRh/EqVdxGuQA6YzljMO6aJpF7AwjeOwaB5fKCHKNLCIEsh+OEJhgU4RA9kMQAtjPTNeDP2E/fT6I87CZ4jPEZ0JwAEF8hguETD4z3XZF8ny8rq3tCMnz8QoHjork+XiJWXBF8nx8HrXfwpgogxQo/d4AgjgQowgZHMjt+BVAgQbXrgigQExC/ZikpTm+iogytCbzoiR+8wAFAc9FiwBA6yd5LMik9cFjBNB6ZxACaL3cENJpfXEhJa7mijWZJevQ4yq9rMEspZfwXF32VcXFnUfck0ir10gr10jr7iPtEmC3JcC2EDwHrMUaYMlSaskheImwS2DdR2C9qz26U0IZ2H4RR9U2/DqbTtNextGDO78rl+ibdJpvF7FPbeE4MsmvYp9bnbX5VLKcFdddxD4TTuqz0d3J6FBJcbe1pUMlRS9D5Bexz8izIYa7IfqrZdSfqvFAJ5KvQDzzQgAAhjMYGDgKZ9DJcxzOBEEICGeCIQSGMzyCEc68kANwFzl4RkDM8sIhAIQsxhEyQxYsTbglZDGEgJCl8DsjZLkptGQ4MGRFowCCQpbxCJlpezQMISBmmR0hIGbpETSTUwFpmAsaACgLG1l7RUBU0jtCQLHJUoSAqGQFQkBUcgEhICrlIaSoRFLWS+iISrFHJQazvQ95ebJ6ebp4+ZZX2Vebrx/cgnJrWqXXtGq/3YIyMK0KpQBw6urcdnC61NtPuzr7CeqMEi2nL85MEE2OI/vDWnEQl35U0ZNwGL8xzfG3W3H6KodIskE5xHStguMcYvoCsTjdmSkI7HSBlxCL052+QCxOdxqpWJyuFQg5zSGcxjmEhQjYc05tOPgOrKO6wbpbiak9UwURZlQYdaaafAShEQI8+fRWBRmenFInEAI8+QwYBQGefMaFgnRPXqhPUrPHnonyNlzS3l0Sv9usdOtm5QUn67uYV2VJQ89d1HBNr8o3N/t2bj1nJfduzeJozWrsyWyfsmaehSAhhezWnE+vHXoZ1qwWa2arNdMreiRXIxbFZv0YkVjLRb1+S/zRv1hcRnnlNc8LuqHkvvysoEvMCYnWH+7vZoMJOqelwMEHuUqDw86JAAQVOAxHCHROGiHTOUF3gksS0Glw5DSAE+QCV5ItnE8e8I8yk7S0dRgBTrfm63QSGfarPp6HXhtHZMcw9IwezwDaA1icRLQncI0QQHsAv5Nwj03Gmr8XHtb7spUPJSUpWboG1e99685HoOo3Tr7BYYaWqb48s6Buq9uHnFvAMwuwur2N6vZlUXtJtcWHTjUc2FhjbZBz+cG5LqnW812KDZ1nTTInFzs5ltmjZfpwZZl+2l13AIUuXR820N9Hlzi7OGxgpDv2sov/gC7615lxdOzyjIH8RkHoK95sj4JgTN3v/V/SxU9uUDhxyZv5N84/rL3EHmnZsReLI+3JdOXVdDmOpyXtl2d8/WR2TOPSzEm/7qrfsz2HHuZ48ftjp9ixcSVg6HNuxLc0bBj5Ap+OOpSY8pYcRnXhcYSG0MNHehvHQIue0eMZSNUFekaNZwBpL/F3PiPHM5O+16jaJ9yOOTg2rsRC3McevxMnxH20U49CODauBCbzduTvydA6mReDzANKoTGZBwFdYzIP6hgal2WMQQgg8yCeakTmYQzWsCyT3plkg+FzFnZWbNiYFGuTgjkFX3YaZk7B2VK2UQgBZZuZbfBlqwGUehg6bZFsCSHztEU0dEyK4O0JO4VHxqRIXylQ1uEE8hvZ9icK4+tqVxmJI4mPPEKKlXHwEdL5iDzUZ1CR5UWh5rDffSjUHDlCqe1ccoNX29v6thxvczleEHIVR2Kvcoh8jq/6MyL//PSeen6J4td1Wc7VtcjCiTqMdTnsfnWEPklgPRM4PHrcjhKQ4sNb3venE9EerZfdYvKQoLf20gEE5il+VKErMn20H/WGikzP7CVFyPTHM4PJooZ+tYq+I9CvCrKN1rr9lbfb0BkDMKxfSwxMR+nlhpDpKL2ICJmO0guPkOkoZ9W/IrPqQand12/MdtrtXP0f35gRSi9Ic/L87fMNQrYvfpdF6BUjTbHiG3vhF7wv9tOo39KLuPjGLPZPF77cy09KyqnL/GVJXqH6PVmWYr/i4wrxLUr6ScaCwA9msq5NBH5jRvqZgNLu+TdmeRT165g8in7FxxUiQamvCFqEX8yQYlqjxfJ1TGmxXfFxhehQGqMZLTL0xQztRKnKB3xjRjpDqX2BL2ZoL21U6cJvzFQM5RszMr4xc6KXAsIwSXm1YX91tGow6W7Cq8mmnmX2cBYoluhhoH9IpQgZlbt+eMDZPxhDaO5gI5Dd/x3LZuP4VCoLKI8qr2pfWqUNQNILg7HS3QIkNT3Erfop2oKAGhNVnaPVfuY+WUI2hIzSUZq5R8ggVAlRCBkFo4RQhIyCkYyul4WyOVW0Ome9+UUTlO5HN4KfmnDzYchaQlkrJ6NgMr82VHpbNEHqdg5A/t+aQBgZC56GVZa1f7W6eYAAugCXVW+QLsBl1RukC3BZ9QbpAlxWvUG6AJe1ICNpA/qbgXP9TQjQXxl9p+Pm2RusmsC3ogWJ+M0wzbomhI8e4jl8PxWW76ekvz7NA/Ym2oqNEM7cWvDuGwvK9+87adjPNxZuwx0rm5CnGwo2nLQeDhsKCysvZY5/AV38Xb8=###4216:XlxV32DM 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12a4eNq9G0uSJKfuMj5AAsmvKrx/p5gIfhkxG3sxy4m5+wMBQpCZU93ushddTSFAoL8E5ezDJf58/h1MeGyP5y/PnD1yS+a/7ecfIX9Jmj//Ck4/VGDPP5JVD+aMff4R3PYQQofcF9lDevP8LqXO8zKkLOuepcOMDg0ddnRY6HAFcd5AhA38YJGp3OI//4St5P7nN8n3CvEd4mSGhAyxvEBckmRORpIh+SNDQirHEW1O3s+zjzFljClj/JamMRrH6DJG5zEatsl/5q8Ooe75qxAsZoo83GN/uJ9/Bc8fIopMlEI6IX2jzqGff0sryhG/S6vhyNK1787W/yHW/1FWeNL1ewL430pD/3elC4GeGfOx58ZOWSUqq8SRTqziamubCZwi2+r/wwCStPEuCIdcV4999eMNq6tldaPr6vu2vWF1vaxuWV+dfXH1IlNbl7aMJ8Of3zJPQA6jIpA8o0AkzIkHQlSdk/maIekoQi0BsD8y0iJemfS9pbClofUti0dFJcmCgCoLTBXnQFcMsa/YWgpbGlrfygdsMeGKsm3R2YprJ5CKy4k6JyJkb3OsrnMEgdQ5VoDGxM1ljQmZPwE1JnaNCVRj+F5ZMOxKUn62K0ml2a4kFYhdyQai/q9czNz0ONDAwCOMDrBZRxwdYKKOVPVPbk3vvFs1Y2smMtqzdGUT1UykXkykWE2kWk3kvthmsSLuttmrs20eiM2Cx3/EFJeD2lVJUz+o+cxB1XrQfd2AWA7KV/3tFPbyMwe1Kx5z7XM2h/6DN59zgG+IHJUiEwN8TpaDagVU9xoZUtxNnV29zwEq5dk2jTE4pijKEaqiBIKh+pzD112hv8uMnzwhR2uSZZF6wgBOQzRI35WYfCLxdzDG4JjhE91QbBhDPKGfPaGonjADQgNk59OP6ZrCFxepHvyhUOFTV/j4SuFHINF5eVLvIqr7rU7unxFVfsZGBdOkWw1kHxLM8xmoGKL7yHhmhqOA5oPODOfIzL0zPM++Y/jeGQ5jKMMNwTAxPE4Mh3nAV649y3w1ma8G+Xo0vuZQhPAVre8w0waM0OFGB+gmtc/23j6fzTLX1txYK+ld5Q3XGWsTgcIlIgJyiIAEEVCrTOgba5UXjUvI3K2V9PaE+Dchs3nemq8LcQHyA8tgB8RqZQjvkEwUYrW47q4c5hBbxXWKEwQtFNeuiQ+sBvFxG4O2Kq8rCcZMvQJxADnMBJEFYkGwEjEYbcUqWIZvWbB8ZqbvgrVvXbDUvxdTf09WVmFSNq1pUIuto2nRbx4jMYJkH48gO5JfBcsp2YodS3ofFrctWHqsHU18Ixa2agHrWMKbsPzgCvK5HNwCh3L/80+gYmvlpXuLQetb+SjzQteVAiExO8jagJCYPc8ZkI3G7IwbQ3YBATrsorXK6NZiNGjnhh1kRRK0cwX+FlcsAXpdsbbKiq3FaNDOlccVy+gRtGdciUBI0J7nDEiiQXueEwlkCtr5XoJ2lrE/mEClZF0p9aSUzdrbYe01GFU7rL2GcoAd1l6D9bPD2muIGu2IxjVEjTY1TedUs2fXcrx0LX51LeE+9B/OB+1FtxOMHccaENgq9Tr0LJlx3qUe6eS3D+gU41sZoejqrq5uj+28OtiMS5cmVpcmn58O0ec6UZbE9eChRUIHP21NOPbhEF1f5iJ8L5j1hZO1KZ7xbXHCR0gRVlLo56vKlb/PIsYhpr26m/KDxPIDYdtsCl+ZwGNjLZgrsgfWDhASa5e/96wFIKQOwXePkAAxQx3T0h2+cQIu7hi8czYNEROCChlJTj3tgJDAYZcTZKQ2XOwTBMOF/F1NEAwXaqGkn7sWRWDnpCiSzVafrFyLiGw7WK/ZwOyjhMClr8RGABYE3IwlxNdVwQvaMrzG12XxSgEbK23sNMbgGDCtFcPeMdQxhRa2hk47nyCFFtZV3GyCFFrYGjodLXSyCXFB6CQ2XQ5qH+Jh0UrzbqUNtdLvCpXivt8EMcG0ZJ1Hrr8YXkSQpasgJpj9jVjUTRATjHgTliwvpvB1z2620K4GLOV8vaWm0CUq3ZxygZDQpfG6Q2joEpVCiDyXGzvqGqXAkNZSVJ/EphJZhsYrUR10HYhNYJ3WUlOUEpXEdXYapWQMkUBGlFIkOU9akwDRJdn+F0lAFPEmCQgqvU/mRLrTHxXfKNl3SUBQ4Y1Y7pKAoPyb9acEy4VDTWtEQv3ZsMUWTWIobGzWJCKgbNGkoWPbZeEeNtH0RyTUpA1bbNGpnSx41ilcsWqSSKhTG7bmHCBK1FKRFu3iBEJzgChR7wqukQPkOYxAaA4gNufXOt6+d410VCNDq+OFUcfTEJSHUbg3UFYJJGzfoKNV9uDCJCthkutdTrb3NdDULZjiiZu3V9t5EtuKWDXEezoh/mq1/QdQtxK+YK7BS9gBEjqDCzFq9S8eADGt3AsQiE5gdo1OAiSCCcs3dYzBMYXpAQpGOa8gGGp0EqD618Q/f3U4r0YazDuQBkakQXZp8JdVXbVWdZshptc5/lzz8mwXp0So1123fiGwbxj9yzTx4jLYX5hkfldqg7PWSGxH3tTK7L4bAqkRM9TDxZbYBMF6bIbICTKqsLueV8MqrGB4tVghJUrMH5UR4cQI1RkRLsuwbs2VL6uuS0bs1ow4p1KZNYwvrMHqZzKfYU143pZDb/VnaNjErH6jUvZGb3N2TFUKhKQ3lFlsusOhzGLzzc2u59UwvaHMAkhPb34VSS7M0uUPmaU7s+KrmnlYCxv+Zc38eL5iowE2QqxzlV+rTZ/Z6NVdfu3X/No9X5W5w/MVgzVlMNCw68JU+GbcJgKhDGZ4aV8hg8FUs6bCt2CaTRDCYDXjwfw1Q/wE6flr0dOgTnpqOuvTK4O5qEe/9x6WM3vD5SLcz2QEo1sUNt7YUnmIzyisXRnrXzLW/JaxQKGuN3E2s3InkBszy+KdmWVxNrNmXu3SzLK4mFkXM+tizqwjss929h2X0Y8cSgYFtzD4aYBboXkiEhbphGFRj4ZoADXnMMRK0Fsxouk9mcnbPxYF7+GMVRd2WqQPF9DcnU/VJ586xGCUy4Cw12+BnDw7d67EJ8plxTvCHfxV4VBdGDY1385dbN5OtoibZovgGCTbCF1iYQfESGWzchAIMVJ5H3KCkCKbMQQNzSeYS3QDI59oHBcAqS/p2myI9kPVq83i7KPtJbjJYDYIBpSNXwOCYeTQngbBMHIY5gYpehUUkElMgGIvg6xXDqakG3v5Q4VzTeHMdl8AwDsBrNKXla5fynX54sahfPHPlGPb2lCky62RL/1gQmwUQuuznZsAIdxUaJgAgGlZCRwyp8rtS44nkBq+U4MNagwTgaYhXb8ftHUXF5oRZNcMc7CuGWG2CGuBvkqSuEj9ndwutHh7TWWQT93tcV6fvrVDyYUWrXFb0+eUE9LwwOIzigKhmjc4AniQI/lgWsPN1/7IgRs+8dz7E0/DKel/559VWP1zvHqohrLcDLpN053ZqG6R3Lql0mZNpe2afbu5EFZz7FEQu3Ii5uray+yryVZHZbaP7a0F01LgtZf61LVXfXIiLh7zZKN6Xt3Fz7w7I3dY9cnS1WuesJsTHlEurz94h+Uu77DMHm7MkI/+fK6PqMhEtbRSrd3IBX7midDbK0fnnvPm0817YI+vHv/55s2+3qMaJI15g0AdC2l6DSnwcCFQ6p8KlLorGQXuvyRQ5lqg5HYTOfmovy5QUAm8ipwCt/9EoPQsUJLd3JL6qL64+WzqdXcP5RjnUEpnSLFi9SKxaGZvJWz1a8ZC5t6airnZN3QsZQx9ha373QwIRb1ohXWqJ9Kqv+AENHAfWaS03UdqrAMVcF0XKn75XIasS8KyDOlPP8tC9RayjsEALY/p6U0dMwI0rTVinErFeY2Ec1I/yZ76SayWBFx9qk0Vsk8QvDDNyCQiC1PMpFXAOQGRhUG2iBMjki0OsikCbuvCNa7tYSasSx9H1pigki12sskw5YtWj9lTvsgsvJrrwlRv4+FMrZWw1e/qQVBaa7qegECjC9N0CZEhjAhzFyY2WOAmWcewRrdafnu7WY8Fj3XbxUAt6zYxqQWqEPnp2q2/zjfiP7h2Y9bJm2s33yv+OX6zX7uqyljUzbWb19sbseibazevjjdiMTfXbr5fVH4ZS5F13X5YUjhUZbhQsbc0tswk1zZ0pS0QGsMXWRuQKYYPASH6+vcyZRPVKpdN9JbGlpksdYiMLEgttQX5xBXhtzGwYmtpbJnp9zI2eFxRTb+XCXEjEGpLbcAExMnp9zIhHAQyPb0LUDdkoiQgo2jcH9DD64eRgMzlv4u0QpP0YrzN6+/pLrT4RpvX3CFZmkP0Z9m/0fLT21dMIaQ9y+z8cu7jmlHfcM6pxP+C1wRVRRD0FPTd/jbFwpvFS+sk4xs1er2u7+8KvTRvpA5fqeMm6pjPUyfcWVUZ3kgdvlpV5IF+I3XkQp2sa5Q6+jfUmYkS75yA9G8kilixIOnVG4miV6KkiSjqw0RJdz5Lujf7LFvMan8lDhrcPdWGfQH7OPZF7BPYl2bf1t9SA2TybXiXYftbavRtWJ/K69YgtvS1IDYQvyLaxPqTMzuWDHrKaaxHF2vj2V328zfXaD06yQ37AvZx7IvYJ7AvzW41SIL47FYRc3WhBXNzphv2Bezj2BexT2BfWtwvYi7zGhXloKIj4CmDCjtSUc4ZFF4cw6aoRx9zbFg8+ghhNtwGH9swBEwfltqAAUngU3ZkPQqA9UuQIAiE5k02YMhhD9zGNrahCbgnRv8HcX4pJA==###4924:XlxV32DM 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1194eNq9W0uy3SgM3UwWYIz53VuZ9ypSBRiqetIZZJjqvTdfIWGT+9K5ySB5PI4tBOhIQvix56dg5IMpY59/CXM8P9noH+E8n5+83R58VzI9cbKHcNvzb3Fuj+2Rfkadf34N215+D0bkn/86pqxMrdy7ff/kTXwEHZ5/eaee/3irHi6w+2E8DKOSeJHFJ8Q8bJDP51evfZevWWodSL5hXbTtc1HH/SBya4P4/fVcvqW55J79++c06vZI+POLCKoivCPePJKE5+fSl/QssNsQXF88Y32RdSQ9nuaZEK8LomRHVCwivwhrCpJmOZAqzfIqbYyjQY0N1LABwe3FvYoEJD1e1TD1HSVgsNDUMHXOxiOkSjNVDXPCOKqrkfpADQy3F5sariPp8aqGKKthQt4U098x4tmGra08ndYXoc/0Vt6s1mehj5XWl/xfmaaGrWV1mjJZetFWIKRoK1V9x8IOJbl9teXY9B3B9UWx1RcPWG3ZphnbaitkYXW1Q970EB2afzLVNv/Wyrvd+iL0md7KolqfhT5WWskO01wSj7wPD/ZwiUnu+z8+qc7PNMvCKG5to0lUz69pjytNjCo0Ebb9nshZfvqz/jxFxYOqv4eCf5XFoJ5/y2LfQC/HjLapIRCTFW9MzpoUJhttgLsMcxcGfeWPjHbzKGcf5XjfKEZOo+ju8NKk3jZKcR7izvep/U2jZOrlDRTJ9PIOVfrkVWytNEhrWUop402z5YxgSmVbGwimlPHdj2a5F/vvSlQbzkq0Vn64tiy26zyUQQKxyzbFPkGiP7vE2soSaytLTK0v+b/8nuusL08jv+ydRwj2y8Y6QCxxop4gw4lmRtorI2VnpPsjjCwCbhkpzzdasV0xUvo38t6vGCndG0c5V4yU9ncw0hpg3+Cmh9ZJGQmBNyOEkZAZlHcwI+0war9gpDXAvsFND62TMhIp4VeMzBIb+wY3PbROykgfwZ1YysjzQAhhJHJBhjLy5AghjDSJMOyhH/yhgZGqM9L/DCPvmYiYF+yU1QLzjtjt6PRgR/tP5LFZupuld8Yd4Q3S/SQdmHacvyg9bVzMS3bk7Qlg8QGiUfDY4qXp+XAGLsbbpTRDDRBOgicma4JBYpDJSi0AoLGg5qsdQZYnNZhkoKGgsrojNBT4/RIKdDe884+EgiLwPhSwN6ZNehkKtjeOYlahQMQ3jmJXoUCE3xEKjIKUTEMLwoOxNBQ4C3mRnZKzHSEkFLiRS5lFKDAKUjINLQgPxk7JGUMCF6EgS2wpmYYWhAdjp+QMaGc0DQV+QwgJBQ54ZxQNBS4ihDLSuQsjTWdk+DOM3JeMfONxqah/z8h3HpeOZXL2xuNSad0nZ7/luJR2qLOPQ+uAlpgYCbEkIYSRziGEMhKCSZK7YOQO7OPQOqAlKCORWziWjNyBfRxaB7TExMhxouPTcckghDJyuKB9YqRGCGak33QipMr/gJC2EzJiQtadSztoek0xpE3PHXZ0xNLhRocuHb692owhhvGAfSZSCpF7FDaxrZqYdp2UgvFmYtxBkVPnIqcYRc4ynJCjw5cONTrUs9dF88/mTIQdD5hSJz2rWeblqQuXVUzdueSk6Qk0I0lCRgLN1CtiMnLSk25FRgHLn4wgKiOuIjtBZEYszbgrIjJi8qa6M63XIzzSVsOmurapbsOb6o/mTcXYEZZXyMvRsZUOWMOgyi57PTpC6eie2VaPfGcwbjYYDQbT7aQBZeOKwRBbC9WLC+kng9GyG4y8GszGVgZjZ4Mxs8Ho51RIrxaELWcYTNZsW5my8lfNhPywZgo0mxRyoBBRmWr2zZ09XmcVqSkHhBBThgJ8RbAp7wRBpgzOtSLIlKEEVBFsynScbsrf0u9As7TlVWt/lOlIBFSlvaWULUDW2WdZXp0EQHcGuyFIVtnXYj0TBMkqe0nPyBXJKvtSE/YsH3fPdNw9gX2+sS/ZO2Lf3th33dQg7Y2ViZK7LKgVZ2rZ2Rebiy8mJAyEfI7Jcl/CcQ7TLFkGsGTfLXl3htw8Kexh0cWT3C/Fsb1LVRepXEXCjxvr/zEd5ZqOPl4ncfIVHf1POIqJjuo5hRiHQ0xa506/vOL5FqTf60iXowJvSDblz2X9qlGLQhAJtykVGXc/klvytoK3s32LbN/ZVNvLk0+QwiME+wRpdoIMnyAPigyfIIF6cvIJ8ogEGT5Bak2Q4RPkrtGUq9Z79glK1Sj6JevbJ2vLwUMyewmJZyeluSXlCInS0c0PMtz74qAY9cWdx4OW8ny+JPAcEhepky4sZXEy8M4n7fXVwCP/cOrkVvHGP18ZuH0SDjK34qBxVxXD8ZqDs2aLXE5RorGepWeNiLUfBiHE2g9PEGTtYicIsnaoVVUEWbu2BMHWLgkC1u7ZACI29qSaRkhVWlRhhyAI8haDogVB3mJQlEXsI5JqG0Gy0kJWhBMkKy3qvaiUR+Ibz/+Ab6Hzzd7yzRCOUNLUgCT5HJAgdOib0EGTPjOnVqucv+jePQ+nS64DQsiSC02QvuRpKWwpf9vH8bCwFLEvxW+8kHLMbXJRDuexn9wtOrlvHz+5/5ulq0U5nEf+Bul6UQ7n8XiDdLP4/IVH8YvSU24YOy/yOLgmYaEknhFck/BxB0Tf1yTydtb6Q1763tLQMqQmYaGUnp/BNQm3eSyx1B+KxNbS0DKkJuEjA4mK1CQs1OAzgmsSPm6ASFKTsEEihFQJT+5KsOYjWKdDaGMMvTBqzt8M55EWOncM56FKeDIjEVYl1Jlx2Ew7kDtGRqyO0hEqzeCQ3CIPOgrrfX0UJsfplsCfsZ1fy/GJRG3fQqKGgke5JKsFj+X51cxR285pqZvPr3odvnHUdts5eVt9dG97QxFHPzyT1zRYkA/QrJ/r/P0EL81VPFf8cg5YzU89l+4ee/lsZNX+siroZNn4US3zbAl5/ezMF6rzhtSEPL+NTpnpGYnk4mOm2wJBxjHTHhsakRwzIxxNk8lULU2RJgxDSI1FJpSTsSdAVs3UlMUrgozP1SR8QFKRrJqpKYun0rJqpoY8TqXl6G9MScP3loZ7CwtU03CbfOcUCxNBGrPP3xsL7TIWyjfEE7eMheqXpdsQlrFQv0F6XMZC8+uxEMpOeRwSC/2JEBILobaTZ76IhRbiXr9/Lg+3VqSxEIw4P7OKhRbiXv+cqUhsrTjFQgGMdVMsdAihsfAAxE6x0CKExEKrc3HeJEc8GLN3xqAbs8EEOFt+rBa0qre6UW/9KsVGb9GqKyMW2exdeXe1mRzJfuLjZ7fFOTaEKt3Im9wPimoj9DTPf8zBkD+vX0X/MEqVIoS8Oboa3stHdnM9ShlDotRPlZXdh8JW3EYOFshFWDaUZuNJaXy6rcvZ36kf3Oa+9sGtYxsWiT64xeGu15+ycFIILuFuPKPhmXEgrtYynlHwzDga1xA4npHwDBySK/thHoPfSvEWcNKhvb/WAk4Syx6MJVtlOxCIdwJFTCBc8QlzxWfKq/oZ9UelH3dziu2B7T51FS9T12NOXSWkrihjtTsOjoO29mCrYpENV3PmcZV2uvXlBLHeH1WN9I9O4a4ZxF3AVt5edJ2unV+6GMvmr62U7StxXqUbR1yMmD2KJA6ErsROPQoLi8xfcXbdAqiVvK7X2fVVJ3FC96Vy5FnyyiPPMmiXAUQ7r/qRNU8K5aZ+G4BvCXT9gwnLInoF56Z2PwgyclNbbgx4k9a8BwskS7X7SZ6R8MzIVy1n5BkBz0Dmmma440VAf5xRqVMRVibb1iPWGWMUFYa8osAoxY2cvyKjFIdOJgUZpbgN7tYqMkpxlluC9FJc8o1H840mwISbb+S5Jp47HiyCbzyabzTbL1TFidPU1wKff+JbLewJJwfoZgcoXjvA4TunC+4X99paTIf5dro38823nU73zc3++NMIP6dg8cPXcbmc3g80w5ezc+HLFd+vHiz6/1H4X34zQRzKXDmwTK+KG+7Gxd1cgb/6iEO/9my3NxGWrz8buK4Zd/srzS5pnX9+/HJ+oeLyssTebWv4/9vqP3xhOUVmbhcHRuXNTWTmP/Olctz6wSoPQxJcfmIEnRftcJjcdd/MbfPNDqqxGcWXOxt8wliRkdVaHgkCuSyKkpze7ZzcE2Tc7djjIAjc7aDIysknni6ON8hXDy0l7wj67CGNwglyW5HiflWR4uTDB78dBBgFKcvpK/27h/QKbBzTpFJl4fOKjKBKVQvbA0HpAGcEGenABl+RVAQlASi50DT0o+RC04DPhgYnueuxTCIE3/Wg+MxOHNNxQkT/DhMF+4LchnR2rkJ6QdDtmj3jpYzW/+rQsN9ZRrMlUN1l5cf262U0G8OijHZsbyijxbgoox2bfkMJcFt4xWN7QxkNXRxttIx2RoSQMhrcAOWZ35bR8na2klmE4lmMUFrbaBntDEjgfRmtSKwlswjFsxihtLbRMhpcHJWncRntPBFCymhwcVTGwmU0qHxnBJfRduVj+RukffwNku5/Fej5xz+J7BnjlCj+B6tHS3w=###4864:XlxV32DM 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1220eNrVW0mO5DgS/Ew/QCTFLQP9lQK4CahL16GOjfn7cHd3SkpFZjcwmEMlosIkyrnI3MzJcPbDJf56/ZTSfmwffwRXvpCv169gQv7i9R/PjHL5k8z/tr//CPb4SEa9/gpOfwTmX38kqz7yNeaVb94+hNAyfxfZh/SmNKuhWVOfY+ALvT7Y1S/K40oAcQSgVf604wB0C8DbdAqAK94DCDy3FrfSyk95mNpq2nj9f7Kyty5NaV2j1u3WWjdu661LrUfrKZDuybV7au2Nbs/H/Q6z36O7MCCz379ZcGUK+N9/1hhzS68f8vAV8ZEgqiCuIFpYgsiC2IIYPZAynnk8MpIKkg6fAVGB/SMP2Ktfkj/9kFG2Zg26OQ9iuVkXxEY5kLxOcvAZCXt7oJv3mIyE0tpREQVPNDlI+2p3l0/57h7uRq4x85oSeDA1KubINXpeU4Yq6NbOjqJoQxVUQeREZH5Wi9yaNvARIXmGCpIakghS4rWxTclGkBKlDQ3hBCmx2T6NO0FKbNY1RBGkTKPt46Jnf/Y+jbb3VCKkzZEVGfFphmZk7yjf2xBwhLSOyraOuCVI6ai0bdAlQUoAsg+bJ0jpqNStO4EgpaNStYWlCVI6KuuSs8miZZnf174sy6cf5U/pGEOLvXXsMK1jgrwGpWNHag+kSOnYEVuXNUFKx44yg1q3Sc8Lx80Vlkcpk0cZDPbB/EcmifT3X2WqhcpXVSIRcTDRIQlXJM4oVyS+XXNF4opyZOLiRUgj5Zl8/coTXektL+DWhEV3VB6y6A5fv/DwRaxfBPjC1i/i/ELU+GyCKyqHBQhUyPoFPFbUQAM8VlS6r3SRA41HCzR1Gjzgzr0mpAPu3Pf6BQS813CO0G+FOPf6jAPi3MtId7Iv0xUWruc9k2g5uZ6Jkcpya+9yvX7m+lOO61/4F0527fXCyY6bFuKu0ilErtiXkl1jTDwAgvUB2I/zAGzy7QGwryXb+8dsH9aRcGQkpIzLSAjfYrXqYrKUJbGaNTS7RnI7BVKuq2TvU2DlxSBJdjdIdh0kvw6SnoP0NDZmCdEvY7O7ESJZJW1tiNwYa2shf9vkVVsTP9OWutxAzJgHgHAmMGNFgDODTwSZnMlC5ARB4iUygoB4CSESBMRLiBCbz7ktUfFSgPLiIMkS9mPeEWtuaPeWUamdZQhunQ098ymCgCQJIRAECxE7o3BESkCGLQiWEnKm64aAlJCKIlhKBIIgKTElS0OQlHCeICAlNDdo7JBgyP9XEwl98Or4Hr27BsFENjBHkCvZ0BCQDZpTBGQDiJCGTNlwbAxHjhXBgdZJKEDTnGHHCxUvB96i0+RJQ4ZUfxBKimcfIv/pKT7mhnuKH+/YoXNS4/v6Jie1vMlJFbLJErldGUAUmJr2gurAZImk08y1NMUauaRYs5W2D3NKqcYvKdUcS0o1ZqbU/kVNVCi3Grvk1qzoX4WKSqQCUZHmI6XEC5qOhC3typafUJ5dWHnYUKMvnpPXyQ0r+8nK3yZjSyOrny4dpN7PDvLgd5G5NV+E+3xxl9vMZ7ntd13NQ+RGKpmVRAiifx8OAkz2D5oCk/x9SAQA7sfmIVLu94EgwP1SASFb7DB9xADi8KAjARCFx50gQOE4w1jiIHEms8RB4kxme8yhJh8zHVeePey4kLXMCKZO5J4qMqizqLbMg5mCInYZ0apBQfslBUnCOMRtqEjXVdKMrqvBWojG3EpjlZSQzdB+sRl6X2yGlovN0GraDOoudCmESNc9zedcSTgSdelYDIrZFoNi2GTPky9BJPoeRS7M6LHrkHplrsGQJoYLfrDfqDARwvgH2lfztMYaeqzhgmX3Wy4L9w7prhxo78pibgnRLto38393SMc/dkgtIlJs3PsApPMAcD/yv9fLAKh1AB7KrJqXT+oiv+nqMJaR13SVfHOgP627SsOWwu/Ia3q/yGvhuCv86m/N9CBLUSlx1AnLMGFGR2KZB8roIJZ5oIzuPGlXzXYxt0OmMJjbs3WYkj6vxCabXZPNfKrf/Bp12ZyvGbKZewRjL4AkcEXACyAJXJHpBQJo8AogKxACQcAKIA1eEbACUptZb7Q4YSFBrS3OV4FFAkylj7Kytljoo6ysLdb5PiUCQHVQBU2QWR1EBqDMARiAvGih2MmIwEGWLyPY3ypUuGRLTVARBPwtLlwyrHGQIy1Tj4vo/EALEgmZwBJaa6hSrrvC6pXHtkZr5dFnuZIlgcxMxfQsPMYuCSYrHfJaEpwLkPsiCXrh0awlys8qkS0pw1OEW7K0UEuW7kVCsxQJcRlxX8uIhTY/LR+ytXyo78uHpMCI6ohirSPy6nVqkf+qfmgLDy6MKDh7O5P7x0yuHwuJiytx677WLJ/lJXSKVYq3M7l7dCX+0ZWsscrbipu9iNW9Pa7h67E+jut+W3ozONb3S28+Tf7JjZOqxdyFcXJULfIlvWqhvEAwZjSpPUGA0aQ6CAKMpoIjCLg2JSJBwLUp2A9zkro2HVCfUMUu7BCaIn0SrU8Mwbgwh3KUU4sG8AQBDaACvQc0gBKOIJD5UTZwCmd+DxbRb8TVKagM+o24OuUPgkBBTFpGECiIoaznN1IQU0EQBGdK+hxUwFLel1Th8vvF4nSPeqQK5B4J3xdPOPaVqNFTXzd6/g2jR1JHt29qtW+XVTHiCT8rjzXHF6njS3pxfCOlOOQAF+N3vGf8jL0pjbmdnWktxLsdjAAMNHR6mdhoF32uxTBC6qzPqRGao/B8PsLdOcJ4wc18e3s35NmohPccoYrrCRVwhPpfHAh/V4D06cLG79/fO3tOUg97Zyr69cyOHiNi/sUR4TeFT73L89Lwx2lE1krsd+a/m4E9c195I9pJgbIkxie/GASwAZwYBMS7GSEGAVi8IpBOESNXBKfTQBCUTtHpHU7TaaDPmem0mYrRxXZGp3RxfPLEaKi5K1c7j07r5KHH7YQ42umffP30o/wp7UDCy2u/pep6Ta8YW4VgkqpRldmTVF2SEUYgVUulCYJStZcEQanaG4KASVfezSFwxKQrKOcaNzvlRqeQLjDLhh2oDEM37JBmMXTDDjtLumHX1j8g06UHRgMAk668nn2yZL9OQSHa2NmnWXhQcM7IYEuebWQqm1up7G1t00WmIQ0kPr6CfZ1afZ1YfZ37//J1zt56pXjhP8zbOzj60dd93SuZW68ULmLl/1OvpG+9kv+uVwJfoalXAsBMX6HBK3EEU6/kCIK9UiIIJndLEOyVAkGwV4oEufZKmnoluMWSPp28kr31SvbWK9nFK2mCXHsle+uV8A5YmXtfK1Rl+ie3RGsGtyi8aUV2eBbdzya1PMj9bhnczT4OVvWwf003ePwX9sBfv5Tcus6v8kBe7BlYcbHBY8Npz2B5EyU5TYbeN0G2DKQ71r2KuSV+VnnCyjt/8QkHkdc5sMXPmDT03tnPcMdJP9W6N6LvtkJkzVdXulKlCzo27lZX3lXX3Bf20cn2uQdrvmPxGIBEAmsl3Lw8Vp+/L9pREwTRS11QorfWDja3axDRVOUJ16h5DdaTgTxhUo4HEZTXEC5F71Mq+IMc2m7aVHSkbcaUmwm5gKipCFJ3UKqqdwO5uH0jCCIXKLFXZKo73Wv8vSzenuUqwDqQqX10up3UVZkR2YfPq9dPMrKDjDQmo1ny0LdHarWeJZCl8rHfb3GTUggqgRhcAom9dKDqbx7Ehbe3fL7aATY5t+dNzjoI4tbLp1OrwvlnnfPlAyrh8w1oVTOXuPDylttvdhz9xEH1Hzb8WR9ETNP8fURBiGOoZ/ja3WKo63J3O3zfkudM4eUabBvULMU2BNmGmaQbgmzDZJOGgG1o6wIQ2NxT8zxhQ5BvmO+Rmr/8aD8ZUBoj4CjKPKg80MUX5I6P92Wca/cGvy8zw16Uw1xR16pu0YpLOnfnVafZ6YTYJyLzd420d0JJaujthhBi6KUjyCDl0vE8WuzDEaLwo+MWF0ujvJcW7lFahDekxa82qaikqOpRXHWRgm2Q59dD+yepsV+kYvoGq9enIkQJe5OsrWIXs6uekrV9TNZvypW27rE8suOwe9wvqER84aAI2oEuj8EFJjV/K1WR8lLlaWzIpBgxbXq+ZizXudlcZhlrCFX38kRHWu4tTRA1UXsL15h5DdIV9QczcI2e1yBdIRO5Rs1rkK4ARqzXyHnNUrEao4CIVhuOc3S7refo7DPqOTeJz7mF8fI5slNxVT4kx9vMclYNbV33826OnHe7+BHNOwnerAleva72OP4Vi3Pa0WieZ+xkXB38Da8vM9PxePDX4F0OJfzd8TYfz6/ZsstxO43vvPcPB3Obb90vRJQOF5F98aSYqqdp1JWY8uHcejSnA1tfLrfYh6o/U3c7FPaivwd7ouLbX7A+zwQ9vK34dpckPL+IzD0f3n47W4THAps+7yY04nKU2PlE+EaFBg8IIUJDbARBfD29UkMQS0tDEMTNlraGGBkEDd/ueNhhHvZpOLKybPAPd5WzCCFlJS8Igur6LBAEnB/4u4agstLc7WgIdn6GIHCweoNbJP6hjU8cAUR/z7N1DUH6WyiCIP3NN4Ig/W3pc5D+nock6rrB1XkBUzC3UcTYcQhbQig9O8AIAmcHoCDXEHR2wCmCoLMDibZWIv8vsAYmVw==###4684:XlxV32DM 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11d4eNq9W0mS5LYOvYwPIFLilIq+iiNIiIrwxr3wsqPv/jkToMRSZtnxF11VnY+iOAEPD0Tujhm7vZaXCP+WX3+AOV9erfvfYNXLCbH/4Y18MaPN/gfY5bVyycJnB3sJ4PtfAo7wXPh9LPn3qePvn37h6f/exH733/8w41X4i//6kd4XPt//jD9+/+NPh4DQ0f6nOER65BAYgSMg4UdEQGPk1AExKiIAgF+z8Iis++/fjmm7vtiLxaky/utvcPy1Htbvac7ruZZpnSpMQ4g8HSHD7zBx8/LS7/ED1T840ge6faBY+sD0Fi59YPsHsO8/w3jKmqWX/CxrFtauN9Q6PplWpnxg0gdQWpZVP33qQYoFr3acKgt/KLylPG8pbHVLtYKypSvXZe5O387dekfnbr2lc7ce6Nyt13Tu1ocZ/ASdRl52Y3ltd6duWy9D5JLjU/dw2kLv0g2966P0bo7au9S1dyXrAizv9X4MFqN9WV7mr707VXtXw7LycVnXtqx1NeOaQXtv/ESi95qlvvc6q9V4sq3ovWp8r76+t2xe37NowxFZg3HF3Yvm+yOtNLLmYLRbMcA42vBsMMBgnwHREhriktH+SCsZ5pfhE8HJcsO5johirr42NA/D23Pn8a/Q+ZGf9qSNbm2ibzjzG9RK2qjWRsU2LrVJzrC3ka2NjG1sc1h1FaLDKjNCrkvb6rrSSjU3FJGlISytT+mnLJI5ERy2IDwobJ6hI0ice/iRulwJEmcsdF45S5A4T6HyWiwEibMLP1JvnCAiInFSSufOwjL4tio2ulYHPnhW9eIv1fzqWf3q1v3qT8G3q1+F0a+6wa8Wz4v8qt378RSGZ6cn9DnyWLGOsPHFOoRS1Sr1NrPKbW6V5QM5Oju+YzsV2o++jdeR8MtIVsOJnerR7ZrRcAe7jMufdyy+OJsc3xJwNuBMdhZOIY+bLF095hHJJhUfxsdKOk3a6NYGHTBu0BvwAetEnJF2wJR25RiFw1N7TMeICREZWodzpOs5Cg65nCOBz1GjzH4odFoszKHQOLRSJyHXYyRXQqYuGI8evG318mqrXl6wtXl5S86T6Jsm9uGAyXbAhv3m436v9FyJbeL/5ckuI1qNm/l/NxuAmrM4JoK4UWVzw5Cwk1eshnlx+dKRq16cV/KISDly4WnsxdWqSBvd2nQvrtaNtFGtTffiignSRrY2zYujA5rbRD93mnRAAfu5/Fw+oNGfBqf9Wl/QDiirB1TeOjoxhoeyAGr0b5h9iWu0xPEFh1damhINmn6SVTpaJp9kYatnVH4SDqrVX/2RM5dwkAR5lxnUA3WZQQr6aBSoSBSoePxrxSOzxVMCXG0MGLGxm/dtxGDsokdHDMVgvCzdq1XWidvl4oin08Hm0Gk2vjCbg4nmAKzqlDjR7IAtH04xrzFNfDhbgxmtgdeYJrdJeqdYQw004iYj3w8KAziQkN0zq8Hjd75Q1M9nLuhI9/NytQTpgYS0jiAokDiKgRnfppQNTCqIGu0ITo4dzcR4NTH1YGJFkn0UXNj9GvIWiYZMrSsxlVyi6XSiUpf3Rlg+iIde2CL7bA7rBZTxQx+/TgQAxcCgD1slFwF92DqRCiD6S94FEP0t+4PGPOcac0aUthFlJ90Y76iJf9FaXyOv5ikv/sWOTGnmQuXCWFfLjOfJjf6lqEzDXR0ZNP8il2eVmeK7S8YEamQgr/50Xcl8b93mTEVf/Kfd6fxgnN9R5wffn58a0wda1v1UV6/s9Ww/3Ywv1OPE7dfpAyFnoZDW8hoKST4LheCDE/bOnvzjjuZEJY2NwHqEZJccQoyIuIUgPSKKHhAjPQ4CtxGkRz/gJEFulGu0i6xc4wnCylWo9rBiZfiQxMRxICCPHmwCPAHi4MEkCqJPxLFDXomWJMhIHDtk2XCsBIljB5kRTpBIJyAoBaXJpGygzYSmACFZhtskw4Vu79Ebpuzw/wUheZ7GZ4QRpDO17HuhN8LPiDh13SXj8thcG5sjKQLpWBNeqqQI0oalmSV2D0hbjdAG07uQgiCd3oWiSKN35xkBGrs7vxCgkzvYgyCV3FOQHLMBzIS4i5nG4Wvh8EO9HyYTUv+Kw+FCArfxshs5G5G4aCQ+cHeMKDtXy4Ff7zmaUrM6GzVPpKvZn9K/5zT925k5htPrLNDfruH0KtxzoE/c8Vdu0tzvwTXi51PudNchwjbjThgHoN8cAPOjrJd1AOYT5rjEJmomgu5EdFyJZdisSmFqszebNY2a9P6U3oVpeveGXKOeOZtsWQiFyVMhBFOY9AdBOoXJ0xCkU5j0J0E6hcmT9tZlu2zXRRlpsj38f2uC3mPmCu9RCEHUFRBBkMZdRXx1pJOXPFeCdPKS3hCkk5firI2aE7qRfkUIpht5ngRBwnBhBEF0c1Kk043ibabBSSChGEbgEIKpJJ/QjnQqyUbUEZxyPgjSlWKWvB1BSvEUBEFkEiVpEoTixXwjk62Sif5YEI63eIVubslkdouXnKExo+Czo0Z0RAFSvtlG0ShI5mYdNGLJ1X2mALOaPCa3jQYpwoFtYBSCdhSCrmdM+7WjMFMdeC5XXbTot3Wg25+8v3m8f6Q0ICyMY4WaozdXzer5bKxm//iu9K0sazj7KfoSN+Juk8d1iN+6mI9iVo+XmVXs+fO6aVJeCPljKeeGnTgmPKjNTXZy4dPL6id1beYjQ/R3Nu8aNwDfbYou4OxBeFFoQAjmxTzCjiBeBEUQxIvuJAjiRVgJgnjROYI0Xuz1FXE6ROo1bZKQXl8BvIf9mjCpaJeQEcFMigWJJkyKMoRaUya1tDfEpC0TmfYACTd5NEEVLLiIozj8shFGIpiot65YEtLo1HVhmYDOpkIBQRqbuq5SExC3wYzJ1YTEbTBZfZl2VWYUydS2aCsCRMp1wWaIlEO6zMyUnCFKDstCM5VyRo3sm9KxZwiXOWvsKyr7mkvJDKFQOSZZv5Bw19qZY2Rdv98lZs3IsfY7GdttzNgmRr/PzE7kX6HfLwga6UCiGAeCTsHqm0TtRqI+97k+xEQ9uxDSh7u6XAZvk5961Imf0oNM6aW78rRNuv+OBe0yCwcOexMOqOfQ5eNcr3pIeVo7y8ramyw7uOes7EzJfqO6Sw2bNtZiaFU3Df7DTeOzyEGz61sO927k8MX8vxTOQnbi5pjs3WEIgLh+9QRBXG9pZ4jrEcnwK9enBG+wmpLgDVuBWV+2apGIZGr1qscD7Wk46tOo8lIePWixlX5jmzPTj0MozhF7IECPDoRlBOnRQfbYHenRgZCKIF1nS9gI0pLEwHpny5DvxQiJGFDottB8LwrdliHfexIE5XtR6LbQmAGFbguJGSS02C3sCMkRHy3OMb7tgy/7AMwhlFz+Worgch9GkC7pUdBnppe/hlz+gqKPtLvfHFzXM5ZLCNM5JGG2Q8ebpJ/6bYjlKMz+7eILYwka6yVoTtY4xT5lCdzTtTHKEkxL0XqYEgn2nBCs6TdonWA5ezu3Z55zezM6ccRXoZsJQ0u30G2GOWmipp/7hLRtxft90uxSN4j0CK5DWAmCj6IjSD2K0eW7FJGG/UVF3LHANu+0+7wG5/1awx6Y3sef8jn+HMJOt3952aDH0PEh2ROXx05v4u8CO/d+pc/7pYm3N9XC+UmAZdabZMZ5Poec79YgwUMmyMFYK94uBG5sVZpZtab+KLKNfNuEl4NBZmuEEJktD4LcymwHlEi7pTtPk8/d5ztPuc9ZgnTuy8vVkcZ9sG0E6NQH7dYgI4j6uqt3nsrl7gOcJR4F0bKz1KN09essvfqUjiCd3OCUBEF3nxsBkBdcFUGwYA6KPbgnHdPVvYZVV/cE//7u047parc/FQ3eC+ev5LAa/ZLeJwVL7FEW80EWF9F7fz16k6Z+qD7qolZaOb38vMk+O/X9y0+1P5m+eRC1KbOz3dYlqZu6nfWjb7/kkvj7ssebjKrUM4/2sVZP1Yh3EtVs/DKtL640nwvB3HeT6lYNFVPt1nW9SXcD9fZvVwGhJHLYahTdgqpKMI6EBrcnQsjdavOSGWmyEuV2w1uIymuXbXFPELeA0gggd6EgCIKoBSxBUAYXDoKgDO6xEKRrtOyKOtILeYTpgedwS4oiwuGW1G0EwUU5miBIpLW8atocLKuSD0nyJPxVS28ELb0xbWtDG8Q/oBQBcGEtRVBhbQuCM4Ki8CbyM4Kj8JMghH9srr0Jp9g2/jGVf44p/1DaKTz0Ton65CuOODz++G7Uze9GSXr23xbjdLZJ6aq73OtNJjWVvEpxTjOoy9XTbe7pG5awvxvOPnyxUjg2y2TGe/NLmhD+/9/9zBEEibi3QhOgr+yn3dvf1OJ90dDXAKTaJlecar1Wya76nNUcfVjhE62Rck3Nghpuv1+dm8o77xhMu/WGwfSFwb4iLiZ6Cg1E+c7CcSa/I1rmUG2UIHyrWARRvqmQ2yCqaN9myG1Ua4NIQ3H0bpLY8w1xjObvDEMIogZYJAFu03eOUWbomVXHiIax20IQfOV3EgSl71qeMroLcuVnEEAkDLcEQRwiOUEQh8iNIIhDGO0NcYhMi/M/0QYmbw==###4624:XlxV32DM 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11f8eNrFW0mSHKkSvUwfAAjGTNP+n0JmBIOZNq2FlrK++wdncoigsqpVUi9UiorH4MDzkaifX6gU8SGEeH7NP/754Yh6kAf7+YWKUz6c9gmIOgFUnhEhQtiMBEDcMSEmIz4hIZ4VkMo+hCcJ8AK6pN8HEghLSFB5fsU7wGH+2hmEUDoA+lU4+yxNsiD//HNSydiDPlT+9/Nvd7LH4U/7/MuZmJ7C86/gaRpEPb8Llmd4fkvrTf//5ax5BOmf+YUcLwK8UP2FovBCjxYWXpjx4oQXdrxwz2eRizzyQOQnSBMUe/7trHrocCaxjHxQ4Y4kqSWP47CuinrqSUQb7CyiDecsog1uFtGmDZ1EtEHPItpgns/vaZPzhuRTAVlh89NTOXzGAeEOIeXw88ZnRE9IPvz0A0bjE6IzUqjE44SojChA9DyazIgE5LAT0hgLRy/SsVP34OlHP/yzHX58cfj1aGUFVP3/9qiXE060+S6MLoAZXFAi9zCjpYKdN+d4AWdj3Hgh4YUfLzi8yIRPk7gqtxtya5YbuEFaBaR1g7QaxHBjJZrAiyGohrU7JGjMS4p1SRG1jLllHC018C+OJWkDL8aSNOxbHEvSsAsxjBdVRfxORQy7qkjSjI2KuLcPEivEogcW6UESiPJVIFcF0u4qEDt2AumXOmtXnTWrzqqus5OIB11E1LKKmCzsRUQhdiKeq4jqpVm5iGhXs6Ln7WRikdWQIqs6bkwgt6/Pd5pYrRv+vu0cG4BN4NFNYNrhYgJdMYGCIqSYQFdNoJqQbAJdMYGcT0g2ga6aQD8h2QS6YgK5mZBsAl0xgeKYkGwCXXGnh2wI5VVqU+ZhDiFFalO8NuzsQLLUxhfETkiW2rgyD5mQLLU5Sx89IVlqU3ZHzBJkqU11EKGbdL+4G4aQ2d2ICUHuRsx9sLtxE4LcDXJefnY3yEV5HCBVNhdEzBHScSBkipAkm5AeISWET0iWOpa9FmpCstSx7DWLE5KljnZ14KJKHQ04SRuSd3zY5CNtd5GuushAsIs0R/VnqrgeW3+31W46X/73ouChGtoA+Hep4P03qcAQn/QkWXE4tqZHUX9ObFV/m5xHUX8mmzCO4clI9Ujgmb6niLEalxOeptF9G/38hNH5MrpWbXT3CaOLZXRD2+j+F0f/QV1o6pXnyRz9ms4kI5kLA4HoO51a6eM7wkufdK49lBcAUAjlv8DWtyfen8QU6NtwoAFRoJ9+d3hE59uI9Yn3JwFPX/MPEPHsI7IqojVlLoqQMpc9Sh/bEVr7GFX6EISUPuYAjfHUJ42RD/aQXWN80xh6G1SqNYGocRROEyzy58KwoiMW4roDs7i6SBn4lQmWNxepFgcox7TJq7lKNGtzE3ETYUmnL8Mfak5C1BotXFZ1H6X8gC0su5slwBbe93A+Lz1JmvedlRM5UR9s4V2ETap9sq1sbYatP0mY2qjeplt9pWNNIoXtaEkiPTHpyHMiMfKI0I6cvTpy/3yZN/QjRzH2ucbHrgJ+Da1LLiAFqaQ55Wr6Gmm8vJLGsB1pxBo1sSE4ZpEh63yNRedxZdGYT78Mw3G4aE+92tzQlqU+siy2I+vxnJe1+qcWnsqTv2tZ2yx70gXS4ro8IY4bPOtakpYOupDOuNitzviEZDUovXEEcVIytdG9zYglrD/RDDiW8ER3qcisoT1ytFAJGhrqwH0cFWlSkUlXkR5CG93bDF213qIZsIYaMmko9LMA0AqkuKotE1SXSW5zESCkEIfRrryxKC8n4f1FgE0FSNpVvd3LClCpD0zx1Jz0a5zjt0ALpfQ1YVdrjq/XKoCZMvia0t8Eaz7ioG3J9FuCv1ilc83r3ZrX26t5+hYMTJlO5pKqNrORdx30i0lme3rv3p3+XbJp9TL9u1TApsyfSRVWR1ljVe+vsn4oImsbkmeBNOq4qS8Ebq87Is+dIT3vagOsZFziJiT23n3eIsS6Vbpv1XURTMm2CPKxrRLrLLxt1c1atJqcAeIKf269wxQ67dxEkoSvksgmyXk9NC13MdSFpOfzHQ4kb7hfBVBtw89PO1Zl5cb7irNtuNJn33AzbbiohlWu0REEGWg3lV3PtTldcZ6Xad6ISO3L3TR37pjJKEv6ATqf1v/8AorTnsY7D09f84/UT501oYElIDeeEN4Rid04U16iPsh5MxXNhHSXnX6vDhRGg0C2tunOO42r0IyoEJDGtRPSCgEjj4NlQ84Gy25P453HeVxyrzWCKBsy8jgmfcAj5pytjFifxjuP8zjW60+gWXDTU9qU3ZRC9gkDvPwCxiDvK8gTEFzk8bEgum5cbg7RCcyA6nIQLOA2urfpFTpWKoGjjepteq2O9SpebdNrdaxX8QqpRi6afue9D+nrdn3drcQGT6hgx3qZsSK9LMd6gascwUhvmVQcISO9zfMcfTSKAz/Wi29sFDoh+kq/xwnp4R7rBUg2Cp2irueckB7ksXzziJFefGO9yMdGoROKb8owdP9Xj6MEhgcKDKuilMCQ6xMKX2LkdI7UsJCiNP5FLncJ9m7y+BbrXWtmJfwaMZGQayolY7XlMVbzxyW9d54vbThXZFNNCIJdR7fy3Ykhn4w4V3STEAZBL/McRuzimPddeqRd21USfQzXdc0e8OWuCbmrJProf3H07G+g1pc4nc+++Ja8nvbEsJcpVro1LhY5N25PbLbNutkaQEZFDLg/EGyFuLYdoZNh4LpW0eB4i32CuYt94pr0jqTa5cy3apc5koW0cVmRUqNxJ+OhVbW0eaBijUsbZEa07L3JnCtylCvWfkXzVTCg+bSXvFUr4HHaqzlyTQh3d4iXmsVI6eYsK80MoZpFVBJVAY1owQ0d2t0rCvZfyFBNi4Qqe9eWb6FkeugjDJAqU6bxRvWzykjq0GusLEqEpKG7Q1EB98FuQx0cz4PchuourSDj5FWrMVRknLdiakKG21DtjqMi3W0oIxoTskoVVFQm8IUJJ2+lAXr8XiboHRPsf8kEvWWCXphAETIzgSNkxwS9ZYLeMkFvmaC3TNAzE+TMBN2ZoIlemKBttwl8MOFaOXmzUrKWbXs5pF+DMaXcwgSp6y24+dNMoAdtEVYWC4613A3BBg1kym/GsSYEXW/iYwUE5TfjWAFB+c04VkBQVjOOFZCe1SD+ZuCevwlB/FVGtbgw5wFlwMIEmZhNHzqFSbrHhbQxQXzkQvT+IhQVwCLbhS396OGapwYW7ENhi4zHLmxR+hNG312AeqV+cfQcFMUa5+Q9qgl3Wk974jgokqZnRnG6m6QMQos2TE1g0zDtic/hUjdpMMFIZaXuaUfujOIoGQlCUBwldc+vIpszrxARgi8W0wtTmWc681hjntxlJNsLRbdPRK6JhyLb1ICF63la86GLxtRV7DIC5i7DH+Z4dZdi7kthYITvNYqiaf4nTJrLxmwT/L/maMvx895h/8OOwReDmVoJ2ZCZfAH3wQl5L9nkTax1gdy71gViRGKg65iEnKjjFFjDNh1ddChzBIHdqzIah88FreEzoReaHo2mCtO0kux9V5k3dwX9mxFEU73QtFUhA4sfoSnb0FRurvwC859HU3X58qV93+EV+2SaDjLmWaeKJZEYGV97pN97pSfISjlFeqqnSHfRRM8FTXKgjpPDhyUftU+jnJxdPxFoXOT6kYOvH5lUtVHG4PJOGRBYehBz+UrD8cZS/eEr+zfu9MbnGixAKe725l3Wm3AWmP4XN+/87UuIcOzsq+TkMvEbV/DmPXcOP2B3y4mEQ+Ag/yCuucS8GcgeHUS1AmxGSgE2HLNlCr26Xdro3mYE/mnv0QxTym+xzSr9ChsYj0t4b2MP783vTPQCDHiX6FHfdN1b8aczvSwWjpQDkwhBkfJB2m08ICjTg00dCM70vCd4HpTpeTdJgI7eOzkh48C9m0cbntaf82go0ztxplfQEt8nXc4fBJBkGyjppkE0MtgPm4bz+ZHA65O+nkzLOHZfhil/NTVWvG1qzK6WG7jYfSIm6dWywNzvu5DTz3c5y2DtJqZjUl0X+rFPLdPo5yZLYlL/+ujwd0l3WRKT5hNGj5swgkn7i6Nnc91y5zwP+kwUNGggKHCoJr4g4fYzUTjOkn/lra9POvSnOIXFyNbrMF0vBuvwiHCVCCOWJx36U8TXi8lzdRFza5TMhV4UzwhK5lIf1RE7ZXOhl8szgsL2g5yhe6nFQw6DmnR48pBQnzoqUj0kXzxkL2kUBPnF4Tuht+q9kYd0k4fk2EPaS1G8R/Xnb/WQNGw8JCPqP/SQNOw8ZEJmDykQMntIi5CNh8zz3HtIQG49JCC3HhKQWw8JCPKQfvKQgIpCBUHXWqjsVHC/sxYaGN3UQln7k4A/R4Wkjl3VklyoGAo7NBBcDMWRD52KoTjymb7UnCKf6fvMKfKhUzEURz70vhgKwCbEo3MxNOBiaBmwUoHzCxV6FuV/KxWo3lKB/XkquB7qUj1Tof0pFyAbKlC9owLVOypQvaMC1TsqUL2hAtVbW6ZnKsSJClQjKsBf07KUUVPW70h0I0P4PBex/FVr+/K1ffDavnNtn7duv2ptwfPJfNzdu9Jg/jCZMrXNKk1s1D7+PLURTU2h9v8B56QT/A==###4616:XlxV32DM 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11f0eNrNW0mOHLcSvYwPkCSTUxe09xm8EMAR+BtroaWgu38Gh2CQldmS3K22YbQrVY/JIeYIRslkH9+/puxfjhfx7ROPOb7IKB+feGK2Pn2G/33/yhNXZEyKuY+Bp88yxDJG8FOWMfxbQ4KJgJzwdoycIFI6QFxFQlwQC4htiFkQA4hpyDqbBkRXxIcFUYAo2Nvhz47A/tXBCmJ13TW3BGm75n3XB0HarmXftV8Q2LXsu1YLAruWfdfrbLBr2Xe9zga7lrBr7dor5Z/Ak4bKCrAOBGQWAN+9OFR4YS8S/r79HTx/EWVLjz+CzS8ny48/UixI1o8v0ooyx+N/hQzts3KifEZZP5Otn57HEwbCP45vdZ6kxePv4HQhVpk5WfXCI9dljbJdwRXriwROJz3aZwamPr6kg9NFgAiGDSKU9cr3j8/wvyGdAygToUxGlSkS4pDEgpwUyQa5DeQhyxwcEFEpx0+gnIO/TjnDYqccPwblVKEcP9thpOyfqn92SkrTP23/dK9R2hflAuo4QmF5NArzww4KOzkorHnfjHf/YBOdvUUFKieKwDdOxNw4MekN23q2AQOhmn9ETZBFu85AkGvtqutcaldDrrSrIVfa1ZAr7WoI0S5OtauhVYmYzbaIgXkRLxaVSA9RYFOJkJqyEq3wp1hEYx7wRehAnICrQKp0V/Jon3pVN+YOAAQRBpO6uh2yCQOzMQxhcHYIgx7Mr6u5xB8oBYXLdTtwtAjrn2R6e4zpxdP0wooxvdllqi9jHyhcQ5g6BbdlWFvGn4Ys86e05+MPV6iVYkQTwqkJ+aHp4KL7nboqMR3l34kioO2F3g1xAykEAblsY8BWVLiblsqOQr3yYtHJinjyYhPOHBtim4us74BcjjEgpjm0MZHM28Q0e0C4MWSrxMxpJ7qY5oQzuiqm2uQipqyYrDKAo6SaIamKSuoUjaQ8ikb/okrm5GpSkXBVWt4/h8eYwq41DLRhfqHqF1Pq9Vm/aFIvXZ/K9anC3JVhMDDMXelUv+j2Kyz264ts9uqLTPpZAy1q4KJ5cdfRH6iiYbuuqNyFOPIuxFoKtMuD3v74sdgW7slzU3Q9NFGcz7M7dafoYuVm1Xyi8bp6CHqK4kD6OuxpHWHlk8b3afVjU313qfqG5X09Maj2vB5Xxy8oe5m9+spldjtmP96BJ2rniRu0Er/CE7nz5Nx4ovdThLEO/xWe2J0n+ponnO3rxU61kN+BJ3yb3QyOh/QOPDG7QzwHrY438WTXk91llfC2rcPzP9OTa1aIfRk9iBXfgRXnPjsyOrwDK9xdbMLTm0zWrh7+Lkjh8beoh7yLVoJ/I0+K00+A2OLawaFAaPKpGsn+BLF0f2L4xPFJ4NOJT3KJcrQZsUydq+Y0jgNiUk+qqsFpwYqNDTl6sAImrwUrbUzNlWqwYmLGt1UPVqxvK9qxIpwDs6iCKInvyB5XwZgeV+mRmFVSwJefqh+ECKvOawjc520niYnMS3KCgkQ8yYknkTQ7KGMcvn3S7KCGUIN2cokQtfL4jh8nKWPwJJPoJ57EzZMkArd5WwBpkibz0gDSJIUncXgSvwSQJk36OhpAtrRtCBnEj53w7ammckcXsvHE8Ung04lPkkah5UARDzQS59RIqCxuySKhxCQU8hQW7IQyk1CBwG3eklnWo55kXlIaKohAQhkk1FIkKmM4vm1okais6HFFNtSlC68m6jJOwuZJFNGzcRLVT6LdOdJJhyLoKiA7YBNqWQPUqOI4PEEDNA35mwy0kB9khEO8r1/YiPhFFiPiNyPil2uAz9kW4HP+aoCv1yjd2bVwEfIai48YPNklkFZarQG1PmFLjNhZLh9/Bo+WNfDpMYg/MFX4qH3m3WcGNsIyoyP6A3XnD8zjp7JXk8JW8iqUbf7AjFDAOH3tD36y5AWrxG0Vwccq6f1WMXu8IcLjr+DlC/tWwe99SUkJWRdyCXldeHz0ulH7TEfCY6T9GCPkMPEdiZW3Vc4R95vwTqtQmwOnolbORkBkRUItNn6qDBxPCZ8yLUUyY9HBFFoXKk6XFhiuFXuR0hH7NhBqoYxHtwK7mIVN4uoBoS7ZTAtr4rBqBmx4KnDMAwXlBFPW0MLn+vLJycuL30U/1pDpbW01A4NUPWaBg/QnjIFSXuIYE9C+phYxFF+spmccCPXSJgjCsEYQcqmB/Go+Dejcn9BHprz4OaMT5VeoRc5cjbKh9r0duhvlwsnyn4HiccQyjB1G2d+VYeJehkl7Gca9aqXtXnVxe12GFGrkXqgxv1aokbN4ctS6jNoLNa+UcgzHUk7/om4nkA3nx1NlHB3LrMjUiyR5VZGx/tkKrOnNz9saZ+4qM+eFYfbH6xmnvcs4TfWr8qoycz5bTmFWt6b3Qgzxc/4n8554d7XjrXs/091M51XJxtp3ZJrbVxmlm/PCQdg1N5VLKtpvUxYuPmWvr7AV1E5fFXdOd8HWNXuVe3Cidj7rPZ75J4yXO7GGz7bm/RjvwkYIrKicz9oqTvbThNCPX9aAgISYtFsoojaKYFmmONj3ii+aa1TgXSKm+BFT/IgpfpT4pJ5vQ8cE3YVFTN8ipm9R4pNaHVxAjw5TP4U4OHcLZ6LApxOfJD6pNdgJ6DwL63uoAWNaAmXGJV2FSRtAiWvigpBcb0ZJFSEZnncLMjM84+WCYBtA2UxYELjcDI0sHuO0KNeYK8y9YSEgynkonDKOQgDYop7fGk/hpTjje9tFHQ5nbissZZoZ7zm/Fme8Xd7W+PYs05ja9DDHKBwDFLGN8nHdhcQxQBvbeOAxhY9ijS0D5tIOc/8oJm2QRZEjbcykjSLwUu7xAndlkDZ2DUC9Jms/l3vm2xrfxsKPdnaJ5tzMvR3N1hsp+nUbEyXM4/CHQZ4bQV5YWiv6PWkNpma4BVPU/OLCNTgxEkvJsLBZq+fTIrrFvKHx+lp31oN4dvZbdttqFtwSpKlcOVg5TtDQJKLgD0/j22lENvQ02O6g9sCUthosV4tL8dszqUG51EWgo8UIdKRGRyDzcuxLu3+b2D+7u69BD3sAGyFNCEwFTRDShMAU2oOGTLlTmHI0ZMqdGq0GHZllRjXajzoymhCKVEFMvjfshMEHe8mHV8nexY2t7q4mG7BYvIk4jbHPjBDHU8T5o4LKk5t1i6S2DKQSwi7dVkwaiqys8AtCWDGZZNcctIUPExms+O6zslubj89u0NvNNp/nZCR3rc5dzLIjN897ywdeL48qmGdO7W0+qleVhB7hkDv8x7T5sMgGhWBftWenZdsZ67kANBY1c+4EI0hjUU4V4XFBZlHbcbsgs5Tt+LkgsxfCsbwgoC3Z0d6kBszeJOaMJgjpTdLOj1oqOJE2Ye3y4by8s0qCg+aeJgn+N0oCZ1nfSELuN/+cQV/MhwgCHwFM3RYRhEqgiRBJ4GxEBBUhklCQc0FQEgpyLAhKAmfOLwhKQkHUgjxLQgNIlxo/6HEWSQhEEvqEXRI0320C10MSwu9s/WO11HfV+hftR0sCoWkSdzQtCKEp41MQkqCdf5WmE6Gdf2x5h3b+EeGpyOz8I8JTkdn5R4SnIrPzjwhPRUjnX6Sdfw3tkiBrSxWHMG9EeU6gLMTfJwtvtyq8pptXspTFB8tSEex45+yS+2jBLpIwusxhW6uB0QuyGRhoeAeytqb4OuRJLcaY1hQPYxYFwdZYGLMoiOUEuVaQuvalgjTkSkEacqUgDblSkIaggjDuJCHL4hNkJsjqE/xCSuoT1IJQn8AXBH2CdomqaNtfa4fMixWPs2vXJVmt+IlWPIY4NDfdt77f33P+3P0mrBxuWt5EGgVjBwH2rxeP6rniTfOWSPnts9dvrvqRRD7ePLs/xE1njcjsjbN/ZSGNQBHWoTdGDvskAKE3RiGNPANOfnlj5PDGyOGNUR1cn+pSpKDmsNMAxtCCmq/2AWesJTOHd4Z1xvpUZyRltIB3eW67GXRRE4RWqULEcH67GXRYo3HLzSCkQucW9tiohsJk6urCSW6BxuXPuPMZVz0Xzbrbb0q6AhWhqw1ei6vq9zhC/hup0KhLwr6ajSYiMYCbfKMgxOBn7HByvW2o/wiKZk+9oWNUP0n2hC1BrfpJsidsBGrVT5I9Sb9UP0n2JD2tfmp/kF8NdVQ2Qdh/+qJ9z4TO43f+9KV4oLv4V+j00YJA00txm16uAXBkhiDEv2cVCEArHTSNXuLfJY1e4t8ljV7i3yWNXuLfJY1e41/PiHPtaBMEaZ/CX+vHTfbB/sPhL3P154eXoiTtB4sSWLjbYo90H27hHEfvILdaCz8W5DkAroStAXAb8qQWY0wNgOsYqiABf2kDY6iCnIkANwpyyjsFOeWdgpzyTkEqcqkgFZnxbzwovWhxTFoCrMWxcyEkLY6lBaHFMbcgM/z1fNHQur0a/nqxlLMkLWcdT7ob4Fah6S7/L6eurAZyV7o7fkDwkalrvlPd0aD/76Su+TZ1zTepK6vNTTV1zXepK4zpqWveUtcwqzF5q+1kgtzVdvJtbSff1nbybW0n39Z28pq6BknIspYzD4LcpK75NnXNt6lr3nT3XKtLGXVXrgVIorv2fArAwtBc8bsi8f8DK90znQ==###4648:XlxV32DM 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1210eNrNW0mS3LYSvYwPgHkohvY+w184AmOENtZCS4Xu/jElmECRPajbshdSsflAAMzhZSIBPg7PGBEP8nDlH/nxR7D5kWQ+/g5OP7w//khWPRi14vgjOPLgTLNyL9KH9O74KqUsj9VfNX71+DXj145f139jb68Irb/fgont7xRz/f35nbJYn2A/vrRplXbHXzLZgqTsEVA6KkD57+f38ndASOmqICE2xAqElMEqIipCvcG9SVcR1xGxILYitiNkQUxFTEPcMjepK6I7ohZEVUQVRPsOlD/lAWh5nZ+eRhoe9FGk/lA//g6ePXgM6WiaEUQM6Wd9fJNMIKkX/dhHUu4A8Y8b/gA9jBvhmAr5Ji2rv566UPviyAg06UagEu9WQJ2xYAUO5uH1Mr5LbB3flaernkPTbxmnCUTicdgYp0hsH4frAOOYbRy9j2PW93TFas73HIZWDKxKt2mkTaXbBBMN4RaQUK0lFMSyirjk0DPdJmS1CRpyE9t4ptoEtKnWIat1FLNJSxs921Q7kbpZgx7WUCwRUFetIStdjIGyYg2UDXPwWoA5SDAHhc3hnU5p9bCFgduBW8D9+A3jN47f1H/daB8idvKia5l3Yhk2xbUDXRP/W5ilzibts9EwG/ubZzPYrNlEEVIlsi9tgojXihto1KbyWm+DGK5YMwfLLEinS1cts9rNCXQzt80cHRcI6dRnU0NYWpBq5jZ2xC1INW4bOiIXpJq09R0hC1Kpz7o+6XMGeUza6jZpgwDsm45ThPRJS9eHiQty+qZjdkFOj3RMLMj0Q+poXpA6adn52oCHdl3lztcFsAOwFpQIRE5icVtf2C4Oz+XOgedq8Fy58jVjG18z+szXxddy/zsPA2z21B8Qoj6Qh7PmeAKt69y89puSpHtpsf5yQZFfMHn8GTwHTwjs5PqTyXOqlifwY8OdJB1pQ44aeNyqhcfNztJ25/GVtn2OaRuNh+N/wcsH/VGxn2Nkh0Zu47mEhJXI8Mr+mxoxN27wYeteqBGVon+OfpbdRT917KQwALFGQSv38cwYrwjoKQqe45mb7m9iHZm+UQbs/pRNj3XTn8qrt1hXDKJFtGSBdQpSXak/3T0rxy2itTZmtqk+ljsxxIxG6D6WKzHkOCZV9VZUU7ks1ycI5EoNSATCb7e0er9c1JdoDYryChYzvGE14/oeDSwa7j2680lMDZRIDExm0N6hONxB1+77cT+n+a49PpvwHJ+rA3QvD58Xn/f4inx/tM8OccFOAdPzvyqtRnw28i4+K/b747PZlyHKwGzo747POK4Zgc0XxzUDKX12a0wvgh0x3Yi7mF7ajJhuxBrT+Qy2pQ0OjyYi4CY8GnkXHo28C49G3oXHhlyGx4bM8IiTZzPWbcXO2qQDAjAHoUTEwBos74mIEQvzoETECMw32oclPrfp9fgcwXUtKKTH56yKzxaDK/+G42o911nxdNx/wPGaOV6aupa/3dQjOdM+u6hOMQSsqqMIWVUXFwSrzi4IChUoHbOrr6F0zD772gSePAwQ5Ffap8UQWofdEIpN7BxuAwVTyP9pDtfujsMt//0crv2dYdcK0r/H4WVeNxzekCsOL4IdHF6bXHN4aTM4vLRZOfwcwK0czhFww+F16GsOb8glhzfkksMbcsnhDcEcTpFUFg4XCLjh8CbISw5vyCWHNwRxeF44vE2vcXggi+u2x7rryvicfjEyXJeS/7TrSn6bfuV/oTxym35p8m+6rrxNv+Rd+lUECyWV2/SrtIGSypZ+kbMIwRfXlQEBd9UJflud4LfVCX5bneC31Qm+ui6xSCrYdWVEwI3rytv0S96mX3JNvwJdyyN8ui5bo+5Mv5jStPpuS8HErHTn4bs8nJXutX4dj1kHKb98dVJ7ljvK+5cGbjR0fCtWnj3qfFy4d4Siwei5rYuPb0pL7MZfk+3VTqZM2irbamyjxBDGPopibjrQrIgQPDgZXNEc51siDA/ShNbMf63T/xm8RkONso1eihSoWCBxLaL06PaKPB+dRfk8bwWcGti75m3yPoqFKftPlA7fpeMW6fjXpSM26fh93hGkIz5POpZsoxjQQXCfKB25SceIRTrudenwTTphnzd0FvnnSUfHbRRLYRT2SaN8ZypXhzY/vjRPLvePL803xpXJ856Hq6I1uBfmVWxXf9X/aq9iMGZDKvUOYi5/M4SU+VRkPKMnEvozeA8UplheaUxxXJk873m4KlOEe2FexXYF+6dKZTRcm0ghvYa0quscr8THMV6/quONex6u6njjXphXsV3Bruwwwx+jdXm9L+1erd5V2BgE9+nE3B8Uc6Jy2ZpVYnZZp9Ik5jqiAkJ6b4733jgg9UXGNPg5DY3g8SDrD9LZJcfbJGUap0rdmIbtklQOIb03O6ZB5jhpToOc01AIHg/2aag0uyQotSgOI7wtkbUuamdcjZAT84h3kPfwORKzGdRE20EXF8EhkZGjMmHY8aes6ztXUt4U47UjvsEBQRJ1VORElE2TqAi2XWE8RpDEhbe4tynxyifF07cN9girfZ7uxfOcROziUlnfiCvqmQOkeZZCsXcIqPZu9t4hFmn/wd6/M01GbtzeYrBZaY0UMVPs1mSwSWmCNKLM9MQKYE/MCiHIE5WZbl17xV6TJUI2HdaFnyw6lFOHDHSY36/D2qPfT0BM3Tkk3V829THrbYypQfEpY4CzdCXNMJA3yp+HaRqyaCkiZOHLbCfiNzUFhCxq0qGykClqMlNNfKhJkMuzLHI/uqLOG+nYTrvE/bSLe8tpF6bbEQdxcdqlxqiuB21mslh34lA6JJd0CM8QNgD1XbKtmxVeHX+Rc5FwDvzC8Re3H3/Rbzr+0hTSdVWnghaxBZETsfj4C9NJo2fQIpYZ4hZkLmKZdmOLsPXWDr2MNnM5W/o1aES0nC39hgWpK/ixnORog2706LqpEfnECHBORtBfYQRN+C0jxE9iBN12Iq8ZQX4OI5ysXV+oE0IdFhNCf9Um8IogQtBEIgQTgiZ0InwhBE0EQjAhcGLTU+yVoCWGtXRxssHYebJh3GjejY44GHdxxIElsQdOk8Z2uwLaTcy8vr3Pd69Tx4urxyTINrCFU3WCPg18tc8/uvVv8u4m3S74OjKq9nAS6EQM3vDnRI8N/4a0Df/2NKr7sDS9ubcxs82sALE0M+3eZpbsgHL65vl4rvtsYjUTs8X+3bQGBdbAL8OD2rle7/HC7PHi5WjwnMX1txUXlZzCkc/mojVejb+axSX3VAkZNmEVf+7dmMUY1X7S8iPWyerD6iIY2ZYG15lEJ6d12sU61R579H6G5932myejVBU8JZ4AYOKqFjQQtsazLuf5TFtY1XtjYZXmad421rmwKk7kwNhdBodgS+ArbezSxsw2ZwhETuPyCIG9zRkCY6synm3UbHOePBtxeYS8jrpOpoo3U6Io5GlwH4Hrp3txcy1qnqYfW1H4qqATjAGTYHoGIPpLpZZoQM91PFwuiTIj5Kn0MYHTAoYQZmeofBHV0tksQTTJ+SfJGZCcfEFyt+XfyPNNkSoY/Y9ILq+SQ2LIuNA03nU+cxaasEzz4lVYcnmTnKdPAdyC5BSm7DAoO8D+2UnMpnEXLsE3pg4Ol94LQcmdiI0Y4VObN8Xt1wiRrYTI9+W7gWOAUnwoXOvrcO0n33GNv0/gJELWldrx3QBFME7a03wgg524XsphiHnGcV1oc36zkAxBI6BvFnSYXya4+VzjG2ovFt1woFXoX0ixS493i24v4fiCjeEjKXab9XWK7YX/lDHQoru9Ucux27jIqca7sh8DOXPsMUNAUI5d/rYTWRbd5e+AEJxjU5uec2w4kSjMB+pbped8U9/ykiFR/lJ9q7wIualveUk/2HsVWAYVpVHLbyM+FxqhDaiRXBa4OoC1mBJCrgpcvVesxBQRsiyUaKHLqkSKlBhAifa11Di8OzXW5zHzs7biqWjb7Vc5Yj253nUiCANKlOkuR7TvzxHDOqNW9EDsSQNs1NdJ4v14IRVC0H48J4kuCMroklyQcz9emLW3mb1xGlcEcrZiyzo9l+AjqM+9owRPL2pV4HMZvpjSJcX4hBI8ssc66mUJviGY1rQlGEHWrZPFvWGKqg/t4oGzl42UZ/71St5FTVsAiIu8y8PWKdWS/7JA4LXrOFggBopiDUH5FhJIe+Yi3+qPTBkWeRhRz6JS9dAPelZK4SyEWM9CyN3PX1gTD7d++mQAGMEtjADWiL4FW89TjI++xg1xoJgR5H6g4pyWIQckguOGPN6eEY4W7U3WBcwLZtFkoC94KwjyZBZcroVWufPWS4vdcPfNh9n5yyP+qjqXd47t0wcttwog71lPGAJg8lkAmiwCuFypnwJY3sLdBW1vP+Et5KZGyMgDd+9Rozlei0fheHsSfxGPqiR2JoK1s/fx45IQ/o7n5idDH+U5WampWGVPjqpm4UrNK7+w4Nw0aAhmQQN74f2ZnQVhqJ5j1aHgSs0rv8QZw+PsUOF1fjESCMPVXNoXQr2fftBtbnk0GH3rTeHUGiBzBUXhsDggc91E4RMhQOa6icJHvIDMb70LwhekbmeE/lJizkC4JfM3ioxU1IxvIYeYeoAdb3b2m5dPOeHELCDnp5yGhzmi/D/aczSc###4500:XlxV32DM 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117ceNq9W8mSJCcM/Rl/ALmwVYZ/xRFsGeGL+9DHifl3swqJTLqqPTU+eDpdIhEIvSchyEdg6/EX19vx83NRXD3YY/3xZ3ySD6f8EZ92/uCnKuKAxJyb+GL8J0qk1USik0QXiSMSlSSqSFYikUkii4QTiUgSUSSMSHiS8OPnT7uoIB/Lg6f/fvzjYt+bD+z4w+nzse/++CP4KDnl8RHnGvs4/uZalr/Ol7+e579B57+xxzMpS//DfuR+gtyOf5yRD6ts7FCLx6KMjDoMe2yrYFWJW3GnrPw9k2WPj2htrCROSQcwXdQXfz/+Sv/8/AynRYLYUZyr5/kVv2OJ81ES/0kr5BSWnMnaOts0mQepgUXPlmPRajbO1IHllma50C33N8/uEaeroymWA0z5wU01qdF3Jv3goZo6z/X4ELKYWkhBTa59mvOGTb4Wk7voAMXkkq/V5Jtr62oVGZ0JLo4u+m/Ryk22dZqpmq1otMV7VjRp0aMW37Ssb9RiBi1KNi3LG7XYQUvsvGphb8OAsltzzmi74rYm04fyHkmK25rCVR7gEVeVsJgRVZLcqbJYbNNYzBskxoxUoMhblxGFVW19MvBkMVDj8PtQbBl+9OyCOoYkeZDR98s7gMfYb5ly0AD7NogE+2qV+mTgyRJSUD6gDos9gux0AT0633qsTwaeLCKTtPguru5j2R+RWSVQw9qo4cSkuu4VaxwoQkQQxh8E4Yz4g+wtzNFwm/5qBNfawKYG2vUuVP4hUNpxXYfKOlzXIc/8Q2cuteYfdG8R8g/mnrr8SSisRweTBiHvqGoXF2Rs1hGq4p2qNLVS5i5sJRNX8UsrmaA626VlM34kUVdHtqjryISdkWg2fiFP3L2XU3oT7yMeP5KoAqrer1qkaJNg39KScxCiZW+mMlctkWGrFjmsGR/XbDsGY4qjLV79Yc2L5mAkyzgS0Uair4umBFk0SXzhbhX16E7XZVXTeMLfnO3siYuiG1U69UCxXl0zoNa40p4HKvSKEqADRvXqhgChn0J2HgjQK5pDeeDsuCY1fHgUPhZQU2LVn9mN4lKWUWgkLqPwZ5GkUWw/SvOUHhcNJVt2JdxlJuttFLRJ8cGVAZiTtJHQJmXQTg55YG6TMmhXIpKD3DotAA6o7mySSCBt3hLmbTwSl+Rfh/LiRiQ56SzG6Ol6ZMvU5V8xUBRJQBK8lUDBNEv6VgJlCVnSAzcKplnStxI92BdJ30ootxBJ20p8yupH0WIGTGtyQBRxpjEg2kfEgoeAuNWAuPpnATEMAVEMVN8ipBoCYEdvEP4YQmSOoRqFs8w0ureQe/7B9h84RNX0t2L3ElT5Nbjyp8GVDcG1xmMzht/bDcJHJY5IIL6/kHWcof+QZgxxuNjzLg4rLStv8WVrxMnkLA7bMQ7rkdPdSK1qpFZzDJFZksjMNRvHWiOz3Nv+g0vg2LQLezFnkMc0DIw5Ax6Q8G4Sy3ehrwMSy3+K5cX35E1sU/a8aNm2/TLtZxnSJejppytjD2oIP4l+uzDvM4QcM7O4icpaRLgxhGTEEHo0gCHzhdl8nmypESKtbwmtaYJ4z8Jlq8ukQRVqLkTPhUaSQs1nJnrhHJEkaj49BOqmsITnpBCHZ+HariwPBYXnOD38dg7K+W0UlIVvYSs5UwlOuU0dszZIXMbsTJE4IumxVkDYKpIeYbmQRNLjKtcLkfS4KhwjkhROXJ34ChN3JOIKqOMkYmiTcjApzpEYR1yuBZGkSeliJ3sSSY/FXDkiSZPSNkqcpII0J21KZ5ZI0py0LhYCe0dcosBuw4kEKK7bEIgAwrr1ggggqjvpiQCCupNUR4/prhs0S3p50MZkbHmEiL0AcXtvcTvcxm0xxu1awyKkSvaxhV25Xuvf2vDL2CzH2LyPO94SrEmQTpTKR+KuTKKVuvKV3mcbF/H11MZtSpnUfhdt/VXvpsVlb/nSZqQkIXeBUil2VWPly4HSzDfXl6B+Hdmn9UCOcYjF8bUqMF+QBKMVEU2WILTClqVIOlqFFUQCaI0STSQYro5IAK5xLws4VhitGPo872DiG2vpq21WkqRsVtLLOB8XwNuljYI2PTPHFMJJZo6ZimMUy7p3ycTReqz5t7Ep/96iAy474Jg3HJ+kVv1FIaom0beFKJKI31eket0bIO5HAAdSsvrgbkdZNcmmb2tXNKuuafZtyQpn1eMJhjBulhu7Gxht/o0wcsdLxaq0pAOh1DqPdOFZ4vU84cpg2W555JrWbSLMEi75dfrIHZtkuHJfr3rWdWZoNzf0s73Hl0P8rIbOaUj0CoLRzRBJxygX9J0eaYVdiAR2zyX3LAJ7f5yVBDgz5JAgJTMWenJ7GfOJJDitQ8zp2JDWOSLpaZ1wtLfbtM4xnNY5aYgAsjobINOILkbiwOaQhMQBqKAUCc7aGDYaOssoCG52rimisZAiOkaWoZdRevJYJI22o7P6JZ33icf6EMChonLoxm5zITkWJG5yIHfNgexiMhHuN3mKAAYySkOespI85baeOrj9TvITk5Otu/wkRqKLvk2vz/ITfZOffGYTFusmhbiw5RcOkkBCqguuhsskKSE1vY1DqmWBtFHQpsM1pmRIA4KrrKXHGjjLezVwxpUsS97PcWRb8gWHzeEwvBRiWv2ln9z2ELNuky2tCsCwDsovzlwY9rYukT3v7thRL+ul11Vs/6UYjagqqsOb46IeJP3Yzm0nCLYGx9gE4CiRGG+ded/9rtt169xUkQ3zKrAEH8z5RV0QrNpyrhjBUE/rOwyVgXr2HYbKoQRX3MyBVpyzCmU7Fi9UqNDy7gpls8+gLMZUgW4xjBnPZKBI4rYrhKWbnYTYUY88XgR3K56noeDSiN8AetYXcEfzFFBK9A5a38WdrRiT3qmQNmuF9OkG2Oc2EtokcJ82g9tUcEeHatICbs/4xRt084btmTfY0Rvca96QU979zhugpvcSsfOnB2UDw6tRMbiHZS8x/OxcbOINDAhd0UKZX3YgYuoNLsCaa9+oXpGSGaF68AvliV8YL5EG4g2WeIPy4A3uNBdvMM0b9mfeoMEbXnMCN3WC8Duiu7KztTf8fdE9mbAtuR2WfIMFcXTJc8DcqqQtuZ0uuYMlt3TJnUUayJI7uuS2E8CyXJbctiXn04RuOGkK85MmnNDljPM2ofOv4f4Z3PmQ0JlpQud+Ce5mQv4L2N/QzG4DIsjbFJzZ+baudTNS3p5kdnVb0trgzG5DGkhm52lmZxD5h8vau7b24tupgB7J396nAmGGe++/g/tLKrA98wY5JX/9HW9QL3oDC+ANckgFYK1sGMjfQDDveb6cMYHteb6kTAB3x0obxASBMIGWyBvcxRt88wb5bGs3FsGulHC/x7N2SgnmO96wfjcV0PuUG+RvSQUceMM+cENfKztwg4KVtuAN+4wbrAVv2Ck3wPW+0gZxw0m5YQdvYGHJF3v3hwVvCM0b1PxK9Pvu87LLJdVW3eOyusbpf/VUlV3uqLZDbN6uir1DyTk5IObt6vAblFxunLdtL283h39VSd31ptugDC60snqh9c88zfpEb6MvTLZclLWr5fWSKwsLkuBLrkyCJPZ7e8mVwYVWVi+01sblabj5zoAT80DRITIzeFrlEJnVC621x/I03JhncJLJ2t3devWY+RNJ8Lkt4xtIDLllz+BSMoNLuPWWPQv8AsazgVH/L2A8lxkY243xd7jwOgUje5+SbQZGdb5PyawGxVV4Pxjj4jTgrfC0wRMtUDEFvnnuAxg5khAwKg2SbQLGOIgGvBWeNnjaBzDuqMMJGFOPFXgrPG3wtFMwKgBWao3BGLCEgBGuCWRdGIxQKM3GJWD0fgTj2T4W2sz/A0Y+A6Py73NhMQOjcu+LjG4KRvs+JX4KRvMbwMgBeAIio4MnepWKwWdxSULACF+v5HcwGOFLu9TvBIwcgCcgMjp4otermHeowxkYOQBPQGR08ESvXDENsSy1JmCUSELAqDv78AGMAkkGMIbxy72zfX+22f/y5R7Ll43uwaXf6i3F4OH+oDMJyBoZ/ArNQnYsIRlFwGqQ3Vbp1mgzFTd7CuzWPs7hpNJHLh8Mdw7W4UpvvYTwxeWDesfX4O9j4mjynbT95lMK7ioNrDIRQv2UQpNd4M0lT3FcK8V98xf18ckHE9yZi74vjgnM01u9t7vBbP68Mnko6Ng6SjaQiLobzN8ArLJF5/wOOrZeFVNEAsfWqzR1d5h7y4cDtQ0cYMd+BdKIDrBjv5pI4ARb1s8cyjX32mPeN27MXKoIZ7vkzvnvqSmtgatZTUnWvc8aVvX2mtIatmVWU9rPi+Jfrill65YVSZpRTWlj7YJCNgaqKW1M1SpCluQqQn4b1ZTWAH5S2ihoAzWlNUiLNOCaUv2qpdSU6nvZG+I7iZ5NtJABb2hXJ7n4fblS1Hw5Y2o0vkp5dYnvfJKU5nW9muBb7+oNvZ+jO8vWu/713s1YhW/p0NrqKq/1/i/U40SY###4564:XlxV32DM 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10f4eNrFW0mSHCsSvcw/QADBlGm9/6eQGaNZb74WWsr67o0zhTsZSFXdVaWFKkP5IoCA93yCPB7Pf8soH0f5VAeDz+/BxPr/FDN8/sdzffpy5cq/4+dfweZHkvn5T3D64dTzr2TVg2vGnn8FdzwE17x8F9lDelcal61xKVX/1P3T9E/bP137/M1gfjDBAeE//8W1MY9y3/ObtLog3DCJkPJkQfgJiBYnQkpfBSl/KnIQxAJiK8IDQQwgpiGaIBoQ3RBOEAWIglHzNEdQJrONOkE/KcPcnuORKJ/lSvlxdbarb/AHOjAW3V0mpd/dr8529U2GWO+OGnXaJiT0CZEIaRMS+oQIgsCEhD4hmSAwIaFPiCcITEjoE6IIAhMS6oSIY06IGhPiWj9ZI6SN2rZ+BEbaqG1qCCcIjNq2OeCJIDBqGxpiCQKjtr4hgiAwaguzo6OpQFnVujp1kWUFbAesHQvYAdeBMNcTgKIqmfyDPcr/H+HnP8Hzh0hHkQ7o61S+ayjroZWiLvtImj2f36UVVRzSiSYa10UUIhbRd5m62FLFvyvdxaWbGJOt//dcJWhIIIEXEVeBJ3N0hZ/q6AoXhV1d4YaMzqXwvCTbJQ1vmqFpiZsXrfnoY29eej4MCHRUmw8cv9PRPnM1HN/LXOF3qL2cay9x9BI+sBe59GL06MV/YC9q6cWy0Yv7oF5+lBaGNmDuyn1TgzIZhAAvCyIaoiYiOmIb4odhBjqBbts90G59UCIY21OV4UE5mrTy2bvtV3JeqXr1Df5Ai+EaimrDL8xufXmE1EEW7rdn+ERkf+Vqhxk3Bo2iTF4fxbiS80rVq2GSm7hGi21CUjV+KgbcYoijxX4l55WqV81sg78t+mXF35Z/3TI4roZlCMMyqBvB5+5VczcIuXvV6mTgM/TP/lxO2CCAp7eLp1eme3rz5Z6ep2nUy7Cqi+jrq6NESHMR2SyeviDNReS0ePqKgIvIcfH0FQFO5LB4+oqAi8h+8fQVAReR3fTnE3jx3QNBflpH331Ers6jNth8hDlSYQErDCh/Ohd0SoML8eLC9xLq9PmV01ucxR73BelfpOdYmf6Ff1IHc8bny1oVh8PvHcz/zTcLwIn4dvbIUkY2CGf8tHPnIJwlL+pSoi/q8kFf1KVYXVMYIa0Ni4GVx+j4uOk4EKZfzWZO58/l82b+OrehX8M3AtPn14fSbHK1DAsLzBwZIRuBFWQjsIrcCqwitwKryK3AKnInMADuBVYQEgiH4c5g3UlmEOYzhYqFH+DOeEWmD4FncGYAosQIygwcIKK3Bq8z7kE5QgqoR5QjlPzlIAi8WQ8iwwg73WyxxaORWI46U81y6BpdYh/iDz/sRsJ2I3S7ETq9QqdX6PQKnV5hBJnuzhaMILP0LPMmW7RfT3Ge58qXYb3kXQPY0KgghEYJP0PzqRO3RvKpgyA4nwoEwfmUJgjOpzhBZj6lYyJ5RkUrE0q+/BJNeD2YkLce5B2rYPUdIzyPaY0mhpFlUXcqRCe/hgrXgsOw8IKnmaQCghZcHO5ACKo11Em9EGxRYsTP4FpDDGQEyKLEoAhyWZQYaGuXHSnpBkGmHdEx4yS1oT2cKBaGUsFw06mgj08NLI3Y+T3xB/ze5Y8E9XuXCTZi6/fE1u+Jrd8TW78ntn5P7Pye2Po9QQLLdFD3IKZRAGazR5n1h5rFBzGYwK7iA1p5P2NEU8PKuuT9C/cca9+/sM9Jgu9KHo0E6XRLtGdSI4FSo5CYKiErC+xkgV5iObUEXekKuvoXgkR7qVIHd2y7IVKneOlYXB2v9Q279mOer1EethvQM6KROMIoLcFk1HijTE9FtO+xAyBAo/Y0JlSa8UW7x8x7LmollVAPiFo6scGGNJ9z1S5EnapdkA8/2XAONnBcirLXGhfFQAmK35ei3luCitouS6RtW6IgR10lajUthBpLdLylnhJNXRDcunv+HbxGXbSGgyaks4RjiFJRr1we1aagLBrv3xKiHlfEkmKc6QTH9Zrfj16HVTdj4Ip9eF9plQobk5Q+tK8fnNcqNBRIYPVbkQfmdVyFeZVI4afNR3V9BcGFn6gzQnDhp61XQ8Km8AOjaEUeuHtchXmVSOEn6ohaRIUfZc4JOFJWi9ojBJfVOkHHIDIoG74DC1EftAjuD/KGDLnD7VfluyxloXdRdXgIVGCWQ9UC2/ib0oFaSwfKLaUDlZbSgfLUOiYVny81hFG8vqLG7q6nJQgWpkJhZXVjHdnwEsHkwTnPiGDl6hSumkDiz9/5EbHad0lEH/yL6PkYmpxDS9OP6J0fMWs/7nlXLYAVXPoTQ4zudSreKb9LRtAPEliXxEAw6YM/MVK53XbfgsfP4MJw1MdEHImVgx9RNCw6zr5j9SeiI80bwtM4am6zc91j5j1X/By8QD3g+Dl4RZArD7/E1pArD+8FyZ6Ht76qBw0HZNu2eBg7pTYqtvq8lZpedWNW7d0K6RIjytzR/lB+jlS9R2LyOXL2/kVRQckEDFs3SzqTjR+pmRFh7vgIwmS9MvlXIZKjY3fFRmKOm1oRI85NjZHYm5HIN2sqrB171PEPWLK2ymaWuGoyLw6VEYKS+RKjMYLMZL4ggiAzmQ+HmwDD5C/dJISgRLE0dhBkUr4gnCCT6AWRBBlEr7F+qn7gRH5gFAC0fDs5F06GO+N+ly3YNVsIa7bgb7MF6VfjN4J2Ld+TLYj7N1gjulQzvDvjriR/U5KwNG9vbXqS2yRoloDf+VrEm22dV6o7+7dJkGTvSYL8W5zXj0q7nogIQZOgyGZ6tCRBxo0ER84kSNCsOvmD3GPmPSgJmrFZu2cmQWVUeY7qpHqMfD7jsTMqo5qpmfRzVCdxRig1k36O6iTOKM1Yrd0znZFOAjuW9lwt8PZjIyNnE2J4HMHPtcBbWhmqVp9Z1kssb8p6/DB/rqwHw7ov6wFCynoRI6Ssd+LW7st6tZ/bsl5D7sp6Dbkr6zXkrqzXkKus1/fPe1mvoa2sx619qfDOkyT8M6nAj12FNw+TwiBP/FomwKgwE/gREIKYwHhMCMGHyWBOLwQzgc1At/aDmMBmcNyQiwnMHwS5mMAcGTViAnOKIIgJCjOhoZ0JZVLWAu8wCkp8ZoGXVeCuwBu+nAllWYcph2HhAi83ESG4wHstKyC4wHsta0MuV3Qta0MuB3Qta0OuAu+1rA25KfBW4Ja/gJACr8YF3tZgZULWbjUJLA8inJ9oEpirMfKdSRCyH/Zi7vBfbBPqsNCcMmc0QrBNiMNvVATZhDxKSBVAJoE5wXA3l0lgjkeCTJNQEEuQaRIKchJkmgTmWCYIMgn4YGJHGxGMbCdI+HWCxIlRBlLy46jw4TvJRSl8RyX91VQCYofNvrYYldGvIzaL48RrHdfLxrYAQLXzEe2WV/KPe+rh4XoPkgHw5mofpceF7CdCUHpciJsIMtPjgjiCzPS4IJIgc6+7IAdBrrPDkU3tKk4UqjwCNgpVfKdQxXcKVXynUMV3ClWcKtQShSo+TggnfEK4v2uTrjxfpFsc7ZCu+kjp2o7bjtuBd/dvu/u3Xao2/erkcRFL3eq7la7SXy/d1x8w6DEa82d8UhUfbNA1gdJz/lig5Z4uUHq6n8Vj6uMkJ+iBNxeADtBj6Z7kAD2W7kkO0GPpnuQAPZbuSQ7QY+me5AA9C3nqo7wYlq4UCNhI93Q76Z5uJ93T7aQ7t0dfpFsRJF1PpFvRJt2ATv33d+1ed83IDLNDuPoT4/DCnGMThwtr/oCXmrFUGRcKxLOxCEBxOF7uuqE143C83HOrK8dluc2B43C83ObAcThebnPcxuENuI8ZC0LicHwOrzfYiWDWKk2ccbj5VCLovCWC/gNEuNx8pkQwCNgQQecdEXTeEUHnHRF03hFB5w0RdN4mD5kSIREi6HwlZOLFmQcxc3P7eSnZB1BJ7ao8woivd+bK7Yhtzi8nNnKCylFeXU5QuVdetejbjgBAuW2EbkcAoBwNANj02crSRJUjYBcG220YbLdhsN2GwXYbBpPaVRl0RrOCDYEWCKCG4CQTiQ1BIgg2BI4g0xDolGkcboczzweRrnKzqqYUHKRg8hEf7NrfnQcn9e0WmlkPSrz5XMRbj1jhXd76c4dV942k6xmsl623seX2i98H1m0ZvFuseuob568lFHf3h7Pe/KM3pdR6SOtAh7RqV787pEW3vFSd29vfNeo8fkaX596yM7/e8lq38to83f6uMdrXaaHHM94+LXX3Sd6cjIshf+Dk21+dkKtdve+EnNJ693vMaG5m5/gfZ2f9IY8ZaxDSB86OX2anuBo8O+n9s2N2vyOdZ+M/Ynbi2stYA/gR738B0xE5sw==###4668:XlxV32DM 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1224eNq1W8mu3LgO/Zl8gC1bUxV6318RQIMF9KZ7kWWQf3+iBoqU7Vv3JvXQSOLWsTVQEs+RyDqseggl3PNbcMtjE1o9vx1xfUi/PP+RIT6WR/43LvXfZODf/45FlP8/rIR/f3mhFLwJpcvPb8Gmx2GO59/B6+e/welHDLE3EHRvQOcKpc2fZMQ+3CGfz/+CCb1GDZAkNdq1VRahj1O/1dKqDeLz/f4h1Oah3z//yu2ZR37v+V0eNiNHAsACYNwjV/SEV1R/Mh7LNJYFLDNYFrHMlqfvMsrSsJKk4dwxaFgXJB605Wy51nJ9gpZbmcaygGUGyyKW2fL0Hf4qLeOQ4bs85L9KWTZ9gc1G4NqxmOqHriP59Tx1UKWtVlQ4GN2s6CqiNoLU2txWEYvteOyGHd1YCdw+FPVDjd2wrRu2jWzBxlT7xtbGLNS2AWJFbgJtWroq9vo1DgLs3jqksEM6EbhV3jq0Y4dU65Cso0+KTGVeda3Z9gQDa2UaywKWGSyLWGbL03f4q9gd+wSTDIPJ1dc+GYKU3irdFl7EcUQcZhx23wlcP5RL/TDgMGMbZqp2l9iNbF0pwab5r18/dKqTmP/XPTvqnr/y9pYhPNbHah7uscaf/wYvHtux2GfZ6rs2bTen4iR0dxKH8k8oMKPgeDI3cihXClzZ8HmG2r9bdQR2vJjbgAI3CnQp8KNgLwVhFKhSEEeBLAVHbcS1xlxrLMjxYoIXg8ICs5SCMTKzloIxMiNKweiwKY0F0uEydvR1srZ+aOrjsqVjnBypSt0ry+ZIpRd/SADSw6A30opeaitHmcypFb8wFtCDBbbnRAuC0YL0+zQaLXo7+tTOZnA0ZmrH8IXkDj83rMlCyi6jd6C4Z9aBrZtzPw/0t3gJWklzK7a3sr1x0uTciuvGVOdWrGKTJoepyr6QinE5N7eYrbtN0wofa9qT0HuyX0yrZNMq51kkPXFzT/Q88Xbumrme+GOZjRX7lIj3TbzXkyHyEm6GOO/WbV/vDGFmQ9jZEO7lDghoiGE7ZpF1sohBvbe+ySJAotCKyuwCnqwSIWzC/pT6U56f/rRSmlyFMaSGqseghv6U+lOuoT+tTK3V3gLDlbqZWgu07qK4St3tKfUnqLs9rUyPydiFEMx91SblnWRq057AQJ/5Q1cRw5Chx4BcKQKEHFptkiEaEF2RhSEKkKIlKqMMRALSzOLQLAtTdzKOvikc1IKDilglWKiIEHBGTYRUXuwwFX+VQref9XUYc22BysDKmb3tOnrb6t3Z1xq/BjtYX97xib2j8B2wiK2WP3gvJL4DtrFtDjYcw8HEqIwK+7d328CS6bbBKYoRbbMN26wEpjpU+gN7taFtdqZI894jbROplsck2dcavwbbSF3knKByrqKuAFsD7IGmqDovZj21Pnb4gyrPdZVnh8ojEk1TPTN0TPAwrfsF8QZpm7cJJqG3EdTbvPQy0fZtBu3Q6Yo6UOTkVzpC/UXwO0XKKcPqKnxzn/J/e/bxq0aT+G6SQE0i9trr4dcPFbhf7wKYSOQ4S2T/gUTm+tYwOdtlrJoVZ5uh4n+6Ru3S9EKRFi1zpUzLjOpLLbecuc6HO66zM9f5l1xnPqn2vJllbdcl+5n0t2xq2sUTt541hbjVFMv7NMUxa2bTJas/3igm53OG2bupLoSx4fdAapaKbY3JtsbKVHHFGObmulDat08dBE61X07QdidxfHqzxNkLjwoUMTs+bRdup7/dBcuOTxuXLhE9PtRzki5YTxMnOz5tk0wZOiQgo2+DtVByQBWNtfBaQcadwPRWSYbBtxFZK3A9E1f2jsF3iLLxjr2j8R2icSJycnmHaJyI6gdmgCkZ1DjZF/RxCxy3NwSu8iyTYBnYwRAiQ/wwpS1V9jsoKl1sq026IXwGQijdHwwhlE7I3lIib2Q/EDCEVLN0tE3QSFk4fm8cHxyatt3lZF2Q1zz8QUILndDiRxzPmYIwQ7l9vTxke/nmbVfGmvwNswPC7m3HOk9+2iAbRZDzfxT7kHZQW2TT+d2d5FHspju+Io+8WO/kUXLNZD7rjL+lzd7YpfA4Yrw24GuxZPqAoFViuHpr3gFqN78aihDrgAlIZcQ62yK3IhDEYyilo1sn0SvCm0sweVTaULpaCy5fmdWiOG78eyhSDKwWhUY7rb9FwFGkm1hG0P5NrcCsdC8Jo6rcAS3TG+O496taQMiNcbN1R+iNcdwPRI5zjKQ3WOmnVDvmPVcryMeUfqJK9OtCOuVr3FNlBSwn15LaCjDL77iWKMKNawn6ePNc1GGH6x0CAN0h1R6IEM8S90CRsXeKeUgz1LPIBOcMnz2C75Zbl245eW+5ofudvZbzn91bufZbJ27fJ24LcimhvXljK/ZWB+o3tuLuYp5evZn2ZKGjHneCt/uTxSfHfEdVYZXGHIs2yUQR6juICEqW+o5Gsb0XTbsmg08WnxzXs0ciNZ71LNZYVWwy+GTxyXHiHpInGRa9lMdBEKYKh1BLmpP9EQjCyV6tM9mva9+SitJZ22q3W8uXIN5+RSip37z6Tb6b7FVkC4Iwt4psQcBIyTdjQRCBoCKZV7BOVgjrI0/NI6B1RLeOZmRP7x9ugmXtpsJ9dBPxgX3TMtm3n5jD0cUUXCpcnphfbnNXnMl2cVKOWzzX7tQpVjZdLigWS3HFi+wXJ+O4hVP1m5Uf31m8vCPxaVaeqKEOex7Ol5Yf1C7ulvph/rB2WNy6nYFhyqvfg/H0J8HV04qrNwm+4Ie8TYIueHJahxaqT4MW+pOYZLLCenigwS99s8H81nNoqaeeQ/1i8cOlnb9hnbXzt193AtPzd1xpvfTUHVfbBBpUVE/d9Z1x6o447voOnrV1kvS4WL+rx0UvD7gBFY/wWBVu9a1vdR76t+xe8yKg37YDDcpDlOoUjEc1M/uIm1vKJm/y2onVVxSp9ZHPWGef3OPsIR2vDmBf9CB+Xad0K72QdCto8LKZzyZfeXV7157kW/kFxnLMbdneVny73bbZbo7ZLf6p3WbX28VoSPvb7ZbuOCqFt9tNzul9O7Nb+KrdxGQ3f0chaXu33cSJ23GO/Nvtpj9Ki4QGP2s3bq5wK//E/0X+QQ4bOLjGi6qfEWDz9jKHZQnLeoYbGL2XhUlEInOqwDlVHgShp4pm1p+13kp2UNbJbrcEpjlshF5XzXLY/I6I8teJoDD+xtqqn05g/L3MYVnCsp4mWvrZyvix30tHGmaMv0rsbMJRyjFKTWBK6YTsV8ko3e+IKMeOOl5qgtCjTvOZP9tgWze20Q1JYBqr9yseHNaNRej9Po4Ull8G4i1UWWMkDNsor89D68Y6urERmIbF/bogspKbc1DKeeusD7i8FqhD9q5DWHA6tUBROsaRIzwz6zu3TDvctrw3h2LbwFMV2+FgYtsxsY2a+kfpWdNV+bsaIqhCz3lLkBoiyHRfhuPgMnmFO591XPrIPiB3GVomwd31+eVky8gzhEp4Ooszc862VHO25T5nW/o521JitmWPSlOBF/ZTlmXLkFQN0PPx0Mzpl3ZOv+TJlWTeyZsl2pzGm6YEl9MYiSnJnmmMxJRoc4rnNeTrGoLK1EUcXAt3XkOY2VDXkJrztb6U5OjmFC/LUryM2W7y8rSw565J9ekQvZ77Gu5D9FMX3dTF/SZjTgvzlS6OzIqpZ/5lxqD7OFHOOT91sTsJLfxXuvg6qe9kRf0ZK/5oa7C6Fc8dDv4gAJDhcDKiLUMGmzojGQIOPoX6jWcIHBiTr9/w2iAmmVxFNEMgJpmAtYLurh0WQe102MvFOMYsACFZcxlJDEFyJJfpFcFT7rbgrxgqgqfcjHiGYEQ5I4EhI2vOmPHN1nptoZ2gEgFILDlXFhmCVJqRgyEYZd4WYpyNprhlRDAEE9syIhky0tmcG7PjWMza6Y0gNGbt9MqQEbN2eOVakRGzdjoxZMSsnZYM6TFriBLthcflw+S/kPhUJz7/gviUe0V8jRrtnIblGDWeQylXROhnIjRf/9mBfk6MKJ+nq45rhlzm3yHI6XcI7ZcKZr5JpTlejDI/jg4NBnWM9ThhhpkwHRImo9SDsfD9XYyx6oZRjel3CgZzBTcR7xhVv2TUMHOBfX6g7LyI+11ULBjxtoizMcsNbxvtf48U71Lr9NfZ0UwWuYvgBbO+zyIlTeZKJhinT0tCHJ9XMq9Vl/6ckonC3SUjmOV9hii/hVMXYsTgLww+tTdOv6x4rZPCi5Ug/G2eRHpbbN5hKhWYgkkQPB5XZEiQiKEumKTT9QAEHWFjtxyI3WA2hMMnz/MiSFKFu8iLwBprXsRuMEPC4RPPPzIeNUJe6kQM5dk0BCFiyCfHANRCPlkGjAt/hz8gqMhIrnOY81wRKoU0Q4YUivgj0DLCcR+RlYgiCL2PMKgGwckR+eQxxxAAIp+orlq4eiJ6Z5nUk2AIVU8LQ4h6IlpsYeop4s8xy5zSDA69E4ReeBiLfbOKKS5jFEGY4nIrQ1Bx5b7xb4jiwguFihDFhXknFRlZgjW9pa/Rlmq0G0w6cvjkp/Sjkf3iefoRSUzy7LLP2IVsSnoyMcax7UpOJpiVWRE8mWQ7WIb0k0n2PrsXF3Ep3VSkFSwuxdPrP4hL8ez6D+JSczD7ZVyKy6XXAaq91MgDVP8DiCVJ9w==###4060:XlxV32DM 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fc4eNrNW8lu3DgQ/Zl8ACWKWwtzn2+YQwCuQC7jQ45G/n24lqropjGG250cEqn5RLJYrOWJKp//eqtukcXzWzTyth9Wn38Lc5zfbPK3GML5zVt247uS+Ymw3YRj5w8R2I3d8jXpcn2JbK+/oxHl+svlcVy+K63s9Zs36RYVO//2Tp0w4d1pPEyj8vCiDJ8Rc7ORn+eL136MX+8OPD7vQ29qrEXv9yeRrE/i9/+1liDnucxYRni43uKsN0v0Fj6qNznpLcxrCUNv8uF6U9NceuwR84/Wm9smvemD6M1/Vm9xXssYehMP15ue5xp7xNzD9XbMeotEb+6jejsmvaVpLWYbejseqrefeS3lif31r7pbGT+/i6gasg0k22Qe4fyrtmU5GxwR3DqGVBGbBpIfz+vMiNcV0QdMFuqQ34U1rU9ASBvN8oZc88ghRm4DMTyCe8e9dQQkP97EMK2P5jCZ72KYtmZrEdJGM10MB/MIEMNdYmC4d+xiGBDDdTFE1YZMRfVm9DHi7NO2u7Kc3hagTUFbhDYNbanefS//1WVKWExqy5TZ0qu0HCFVWqlaHwc7lMcdm37AMj1DcOsoWOu4w6YffZmpa1sgC2vajmXTt11rpIBsq10B/a5sd28L0KagLUKbhrZU77Ih5sVUR9W3bLA3eQuv//osIY+bPqtLHXlbm5+k6oxmOGOUNjtj3rzqMHn3mwMZ1X7b/rvuanEw0dqjar9jbX/J6qy/s8Kxw5U4NecSmUbYkA+PU/Z9PiEXcUqROGWuOLXTOGXYkk/wR8d3sy1z8P7wufZl3toePhdfxnr24FjfAo6s/gYhJe/huNvgboc7PoUUiI8ZoSFFI4SEFA0BMI/71v+HPN2HszzjboO7He448vAyq0Jjk+ylL3k2mmqcRAhJNfoajdG84ARCSF5woJEQIGBaCJhhQzDJCw7Ukh/PXlbygqlhS29H9toth7rbZnrgcsyMwCVG4JKDRdAAdoSzNNgewEYg6w+aHriM7VfXr75fQ79GHOhehD/aby/6VfZrD3y+j+/7+L6P7/t4PuGAOQJldgBRBNiQAxypBCkORm5GNDI4+IiaqrHj5ETUHOcYTpoXCaOkMYq9qzWbDqQ1Xxl/mUYd5c7iaXossIOKqRIUeoDeySx9qaKrSnRVkdlhUlCNZBsW4kcMaQhTDZQI05OHtU8XRtg5+udw9I/PnrK9VvBXlSy4A+9GFchGMIicOVmfqF3zW24LVxvfB9ko686CjMARUzEZXoCjxI0Sqcoj5W5EhmbXpXMRJU9WSGilp6rGo9E7r6f3Lnf5mVB7A+msvSMDty2+eQmVtVL6HHVcrhCS9VgQ25CdIMXVfY1Fao8Euaiy2g1BVEFUQzhBZEFkjadxRLaysqawFvNUMAhpUps2Dz8Q0qQ2sSGMIEVqE5oEniAXs1a7IkiR2riG7AQpUhvbdG1A17bK1rRejjt+/QwJ6L9obLuh2VxqZ8FQ5yuKZiRwggDvVqlp6XtZ7EBtBVQHjDmHnKICugMeTE00hqkySd2yR+Z/PVBbHkegllegfhF7j58f9UOjaBwNnUiqw86xoMc/q54cC7pDts21xA2VNghBLpaNlSOkGWtLtipIhDRj3Y/ZWG03VmFnY6V2gI2V2AExVtuNVajZWG03ViGrJZhhO9USKlotge9cTJbgEliC+kpLiMwsLGFLI/YGK55tCkUsbApxlwhBpsAZvFUWBJlCVeqFYFMIAffBphA8kQCZQvCSIJcpBE9Hu0whODoaMgWLTaGhPSjEN6ag2TAF/aVBQaxMwZjfGBSEWQUFYWhQSDtCSFCIAiGLoCDMKigIswoKwqyCgjCroCAmS3AkKAhsCX62hN0OSzCYx9OdfOkvcfllrms9da2nTtdTp+up90sRnzfkmSWbLEHqbgn82ZaQtxU2XLK2rf21sSjoQtq2ppmYZKRta5qJSUXKtqaZmFTkOoRC21qRsq1pJiYVKduaLLXfAty334wg+1XJd0tIlUHUAXt62PIb3S3/ly/7oArZgLst2K+LCp+3pcjsMsGIJycYt4fKcu9Z9haenu5y5hjmU+TChhXgZLohk2HxmlJsf32pj7xJluOZ9pJSnqFpc4PUZKe0KRGySpt2mTbtMm3aZdq0y7RJGBRnJiC1oFhQXeRCcCwIgSr5igXBB4JcsSB4TRCIBSoFmrgt0PyIvbd1a3Fc5+w+e69RfHiv+5O9Vwm/4gTy+ScYKiycV+lnpyX8jq3ClBQ4Qe74blFrP3pQ4U56GM/0AwYVJqJz0Rk/ER2NkBXR8Uui45dExy+Jjl8SHY99d+ObRGrBeVwzrEqaxxVRJc7jO0FwHo8EQb6bKNXy3Xc1YyTzqoBezHjxXXvLl+sl3Q/f9Y/z3c8esn5F5tbLzM1/Q+ZWi7PULTyfR0SmVjwi7c/nEYgtKHw+xplLkEr1lOYPhKzSvF6meb1M83qZ5vUyzWua5qE8oOiZpHnOEULT/IYQmuYTQXCaNwS5KH/wgiCYmdHRpuh+jOV0Zqb6XX34DUcbTw+OpvpdeZqwNRPRBqPD2cx7OELw4SzmPYoczmLeo8jhLOY9ihzOYqqq8OGsZhtlRBqi6o5PRFu3BnAcbpsaxyuvfEuVPLzoBBxu/7RwqVRcBCilnk+VhF29wevf8AYPhEjY6Q1eImSR+YVdZX5hV5lf2OkN3hDkLlkTdkHWVBxkTdgVWcvPdLIm6FE13y4KE8l3Fc0sQhbfVcrc97+rVOTudxUVV99VKnL3u0pFIG9odpCvGRVtvisIVRIW+a6ajqv8sQ/PjV97cOlWLym/82tGlmp1cOkmPn8ghPJ5hZAVn3dLPu+WfN4t+bxb8nmHk7RmkrJpB5bgeGpR3N82CbVTUIKQSO2Uvmqn/Lp2qofz9mB+2yvFVPv9oip/jaj3EwX4kO5VW/XA3jsUEWT9LPhOGZaTYlGG5dM4KXdcPKQMy3H9XhlWmfBT5aJuM4syrMAGkXWrmtQPlis5uSrr9kk/XG/uvbLuMuGnypPdZhclZYFtD9fbqqzbJ/VwvcX3yrrLhJ/Um1uUxwXGHq63VVm3T/LReju298q6y4Sf1JtflPr5lB6qt59ZJ+P9oOwWLozr1lEQOcq6S1svWHMHhnFZt+Mj9ZTHca2KY9dkltTaOW4RgmvtunPXeSSI4S4xPIJxWbfjBsRwhCQ5Bn1yRMTlew6YaEFw+V6PzXUeAWLoSwyHYFy+5+CIvTxO3pb13quaa59aR1mnbXdSQpuFNgVtDto0tHlSg+lYgsV4UoPpDoYQXIPZTfu1jduXeUAtv4MqmjotKusuPKAjx0b4uGMRWRgq62z0aay/1W3WDWl3UkKbhTYFbQ7aNLR5UtXNd8Hmj6rbOM6z7Cs/qsZdLD89Pfs47SdnAQ5fslzkiAX2syD0iAUj9IjFEQQfsUiC4CMWOho+YqGj3fmqWoH79SEZQeRaM0UOG+qAnabGYgqbvOUd0EBTxxd2uxGaKghN7RvRG1rJrLr46XZOzNae058JOKgX7Q3xBM6LjjbCNaY64Qzj4rz+EkvXSUlhbe8Zz4kVi3Mute0AO9/8UcI7LLh+hVCYAe09k4txIGvjqKHlYpyVO030abPfE32WPkSfNvpzyo3qnP62QFN92uhOXIjrIl+wXA++d8n6YZ5RXZ7j0X3XBLdvNaEY0YSZFz5XEbuoF1TT+/gA4fm0jVp24Y/0kW205xyfyGbpeTtxxLosgaz7WFBFH/bPrzuaFaHy4ZOjjzwuSh6LfOTiCFk5r2zcGZqf5TiOKgjJz5EhBOXnFhTHVD3tRUiAeapxZ8ifPzjIAFUczPLgPKIYRyuqreO0NODkjmBcq+xEIshVq+yEJwjif0IT5KpVdkIQBGqVM7IRpOQB3xcFEkRNOWPNx7z2CbAoPaheX9k1Lq1ndiIS5Dp3cwFYauSUHiZgeUnAjBzUmDyC8QmOE4og1wmOE5YgF3FELCwJcoLjBCcInOBgup5EV+P47rm/rThyahzh2P3P/e7p9pDE6rtl3J//3TKRiqP/ABfHMYs=###4004:XlxV32DM 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f8ceNrNW9uS3KoO/Zn9Ab4ghLsrv5IqDLhqv+x5yGMq/364yhI2SebMZCYPaTO9MBchLS1ocjwC4PM/Z/Exh/X5T9j0Y/EWnv84Oz3WBZf4nZ8fsNvnvwDwmB7pqesT69PU51aftjx9qa+nOT1fnPH57+CP9PzxLRx7LKzfvyz+gEes/kwlnUtf08ePb0tYNKsTX611UukrOB/rrJNNDS/fCxK7i4jdErIsC0PiACKymdSu9xyJQ05IyIjzAtkS4gtiBGIS4goiW8OE7BnZnUB0QmwZ9YlAHfWGZdQzQ8qoF1VGPTGkjBpsGcEukDRq2AqiBZJGDcUGTraWRg1YRi1bS6OOHz++mamYIP5ZViuhkIGtAtvWljEBP/Y4HfOYHzb9+/6f25fHuk/R19x2PJRdq4MdOjqM89xxXuCojnVUxzqqY2W/SU9Xn/W9IxSHw+ygexxFqpBemr7n/oI2zdvNR3v7Ou0rGdWVBY8jLQtuGFIW/DD9gru64EfoF9zVBT98v+CuLvjh+gV3dcGPvV9wVxf8sBSjBFwisyEsHs1kqyscxRUccwXduQLu2FxBna7wEv29WveVq7BVXLpScgXbuQJMzRXwc4ivmM4OjWolye0zQyRd8HdGdGGHdGGHdGGHdGGHdGElXeySLuzpCiqa/jEvjyV+VGfY3NKcAf6cM7ydV8I8cqZlUh/sTGk0+4Dllgk+2rVZKkzjkhzjBNJxzJoBW3VArnKrA1KdogNSHREifqYOuhBRmiH3IZL7vg2RgtyFSEHuQqQgdyFSEAqROGpuMJEWFDJEpgVpZJ4WvEB4WjACobRgJseDtIyv5HTPiby81ohcXaLXrbZFr/6bo9cfOEwFHx+9Pk/nXqN8ZvSmcd1Hb0FuojcZtql4M1TxSCredCo+UAfYJbiVIaMEh8MEh8MEh8MEh8MEhzJ67cHMIkWdYsh99BZT3kVvQe6ityAseoNMsUjRe0gZZlju3XoZhkeLXfyTijzMfpir9Mcrcq+IEn1HvRtD7hV5Qu4VeUHuFHlB7hR5Qe4UeUFuFHkGbsVjQrginydJ5L65wmHshcct7NUXjPuLeXy2Zh3w+Kqn4kuznfaP4fE4mmXg2SscHzyab7NdoLhCHhfzq4hMArnyeDZs5vFS5fSw+DeyOpnHcx3ma7NfDXWwch4/zM4ARuOzXWeGMBqPo/UCIRqPyCYQovGIKIEQjc92PgRCNB4HjcwqjAlSgJwAI4I4aCUMSUQQBxAEQkQQESuQk8XnmbF4HV5m8XlhoVtfK6GrIYWufazxo4aumZsEiwN9t9B9ga3iW8W3htdQ3WqobjVUtxKqYLc/FPq5cBv65vj40MeLoKyHquv2CUQEo0OvmOU/gYiIbhD5+efsF0eIFjyBBwMGPIF6xBOoRzyBesQTqEc8gVryxEwjAHGGl6LxBCRPLAwRPLFOAuE84QRCPBERIxBO7KtAOmJXbTaF2BFbCdwNxbfaleIRWwmcJHtmd+RH74fh685O3jlvIvKTd86biPzknfMmIj9554kOkZ+8m3kVjIqaGFWxk+r6WgFAUC24k2r7Y8t9bnrZhD94bBkH4UdEh+ajg5mUZx7W1WkaIhxkXhjCo1xrBgyiHPwoysGPohz8KMrBj6IcvDi1nLVwHWBy+XpoiTY0Vzi4K7jqCq6ugqur4NpS11VwLUfaOxf4F8L2Xjnz4kpHy1LwCTkzjLLUpj88S3nGSUHKP2TAQP5FZCD/MnIr/zLCaR0EcqvXM0K0HgdNhI8ttMImlTx6IvwwUvLoieYDj93DaNZ+mbu75OEWoe6Sh1uEuksebhHqLnm4Rai75OEWoa5EKNYIdWVynjjcCA7PJiuhi/MldHdsv0Nmnfb37nQ1DuXu/PGhq0cnlqtZPnOnq80ocrQZ7HQ1ySBtRvGhSfxo0+U2UmkapYKdGDDIbRpHuU3jKLdpHOU2jaPcprFTsJ5ZhVMdzgwYUJ02I6rTZkR1Wp5XzptIrvqUX1aErjan/JpvfmyAFrrz37vTTQJuGLq4fsLe0Ix2qqg+R07mEINzNzIMQzj3IF0YTqcqNGIPomcGDPYgYEZ7EDCjPQiY0R4EDN+DcAoCI3e/07nDk9yhJwaMdPGQO2DIHTDkDhhyB6DUxbvUxWfoOrGlAgrdRZl0+Sduudx5ShXmdsBs6YAZm0NF19tiRtmfzbPqF+HZXKx+4Z7kazFsl/pcWXiWipHcKE5fwK5MhdcKx7PJ8fJFzGJNl9cv5icT6C2rFz9+gYAse9cXtmdL4/WLOJ8XjSUiwlYvpQDknTnPpFWSB7pHoPRM4dh+Vt2nNIypdpvD7yVMC288mV7n+GKtY6WegOHaum0nhrtcCxtWuRY2RIvGcHbUj+1mEXmj9rNc+imbjdyP6Zrd5RLbsLElrvTxI1nt0t/arAbXeekm7dzye1ZzvdVcbR2ua7LiJGbzG4N3/eB9G/z65sFDPi7grRsyzfIODuU70xjVTKNvHEr/3w4V+lno1g+8yaHsYE0u/WGz2vwODnV0VttaGML6GocyNPhzNmIWRzeLqIzqLKY3zuLbok3NcXk+TOmVLI4RSGwWG3p+yRHaSo5KnkqBSkcutR8wVdtt5zrJZeOONv8ArzBQ92UfXtspP8oq9PSiz19+yd4afaq0qxlc2o0CIk9LsXbZfjUia72ykBpKSbPVoZ1rrLPQ22LnGnsE6tHVHu1ahuroHUczcW0m2swM5veSdTtRrch5L1mZlTqztbOtdmbpHUud2dNsO724k9n202yKwbXdJY8FDtYuv12hV01m28ls8paUxvPtXdyz0AcwZ4reV8fbSo5KnkqBSkcufU0fefSGRn+U0ccEXKZ9MF9uVjnOJdDC1Wm7Y+Z2Hyp+16ZlM9DuYDhLbmKz/gEVov6JMnCP0Uf6xzX944X+gVOTZMWRlbaQOz9TSLZXSF4SRtZQTSJ1Ox0hlc43MHNO3vvUL/DZNkH1C3h2cksJubV0sgt62XVO0eSmuDALvTCbnv2BKRdoTZiRIGMVsnGOcyIm2/M4J2LyVO81XJRuMJXnRcJl8YN34kdfc+IKTrA7nGTu5II3/YA9/7P0huP0diZAkSHmgXDy8dW3aw/oW99a6/rN2gMwtax567bZ+UY3bVLMMjur3s66tzP0dl57Oy9CrkA+ONF3ilHf6F8jXUD3cgX79TS9C2y9C1wFjR6ITB/erpAhn0binTzT7sbl/cjlTb8UrjcA9gbYnv1Bw0ALLQNF52MTbzeA6VsPzQD7jQ5ehS/q3hex90Uz9rQ0NLiVktONMJZSEntP+xmVmIFj4UBj+qDerDGBLt2l9ePyDzQh9UC11Gk6RhkGs98jFkUXKoFOVYu+U3TTFehUtag6Rbf1gE5Vq6rbZWv0e0REDoGkEywHZVKnNNVCCQI2hZkYpE1K50m1/6YGeOpIqAotUWFVaKAcg2vjWaGpfBe+NK7yxEs3Qje6IOoYqnP+zzaVs+xZB6nO+X/clENRR1MdOu+KdUhL5jrJQNtW5nDqtFmoV9AkT5l6nduqAy4M5pd/9ZFcTbcmqzwEKmkqLVRCIR6TbGuDQiEeQdNKx2hsg8LTFU9PNXmZvkbtUCywsxf59VCVr6Gu9Z22DpO4KKpy9Jx1kOqcV0aV433znwqXrIWbQdrmC6ikqbRQCeXWbN+FsU/Fr+gKK3Q6X7lVIKfOV3SZvCB0xBiRIJDkJ/WMsV1njtuh5l9ZfC90uTWQUar4jqptfsw6JqvZkPj2TXyH3xbf9jk67xZi/JdS2/dCOrxCHk+dPK7HlKbXy1uvqH+uk0nT1p8bubaFoba1b9K2+HN73px19Ep2HSpZ8w753Y+OANXxmhOb0XGTGaqzdzgC1OtQnanXLJr55Ybk1yrC/erISg1lGr7DhmQbipXl7QdiOcdAptSVsoihkqLSJo8l/HlYs5VcX35/zWx1IiznVPpufTWCNlRSVNoEaYM6z3dUJ6iSXf4HO64tLg==###4744:XlxV32DM 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QA/cKJhGPLedCEVDvfXoSUwc8H51FZca+cLZR/8/DmFSlg==###4724:XlxV32DM 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SD1fGYAZvvL6u/fvZ4/zXLbhe2Ru+NZdWEl5X7iVp5y98vvK+TtAhv29IM/dUMPURWmxN558NslnzzlvwvpY7CJoLH21/KqR7Zrk/Vzn0m+0fdvZMM6exnx2+D4+CXU23v4Se+Nyw0qHvXF5f7Z6vvlwPDRfj4eW8NDXHdPpoYm93cSbygllLbdGaTUPrZiHid6qnzu071gku4D6qmd7kNTr8fBug/sZi5TOXyav6kft7fJc+NOwkcrOSifmPJNIqbPScZ84vIM7vufD2onv+XCGKv0aqmBDta8qNx9/RTFYFPcOPOXyq4PBOljPXHy+2x60ve9lx5K/265Mk3Havr7brozgOG3X77Yrwd3Fj7ivtvc5wG779Lv8atv6fa5EN3//atv6vYvfFtuvtq3fp/gRsbbv9v0N9me3Xb/b7s+Z4WdqNp++217FjVvob4v63fYsXuN9ih/x323P8f4f96ubRg==###6472:XlxV32DM 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F+m1Ooz1U8KRrUjDqj+u/i3h0DqMheqP+6eEI3uRhrG6v1pa7iUcsjhS9P9HrIRDpprTASujmDdKOG5l1m4vALl+SjiEm2/xXoQBoOKFEg6vF0h88/+WcAh3qC93RAlHRAlHRQlHuVDCsbyMolxvEUb5KeGI1o0Sjo4ijALu7lDFcX5KOKJ3m+4af0o4JMSeNuee7aeEI3q3/c7hJUixHlvQsU4/S58A/ZkWDbEzwL0TSjiSJXWVLr9Tx/MDiXLvhPKRTT8lHBLeG6VV8fyEg3ETFke3z8XpsooqrfDUNEUoOTCF0iN9yDUxskYu+baRzdNpoQhtZ1pBuI/rGNcxrvu46gmSUB1thDYbNzFuYtzEuGn4j67XSfNOaxtvu2krpfLIKkHn8v9SuDBW8y2hJP8RStLTVv1m2/xmrpSIawO93Vyb/F8R79Bz2fQIcaTlslQxXbLbbEZDtpEEyxssz7CcYHl1yzPshQ9qUbP/Jcy2BtvITSpu0nCTSNCWsquACNHiwds2UrNkwZLilhTXL1mizuaGdc2p/drZMa8FFmOGZUGq7RW2L5tXnmohDia4uTfTvZH8sDU7q82Z4S70d4LRJkWPaservUD7dl2uVOfysnXyQLjtItGfqZF6Ngt6mcInMRbviV9kWYEQpLM1vLD31ipTFlevH3EZK2eZOEkwVVx3cR3iJsQNFRchLrh1NX14OVxUSIOQd74Qml0jt+YfcRlreLm4CikIoddHycUVafaWij/7Kcd2XjkzlHd5qL1BwhhP/95lw7YPG0bI/qrjt4y33ZcJzcW4GN9+u2FS/veZy+JRhmWv8v/+u9Px706R/wI86xVxkolxRb/x1ux/+1SbEqno5/B+1OYerCRX//HZrre5Nsn7VN5wSn4FUskZkrf9NWDaxvRn4EJevac6husY8G1CW4dHHRPU7W8FzZKFknFqVYEt759M021R661qXR77/ADVJzn5w7Ic1PCmbOXZofoPItxtKerBDyzt/v7Aoon19rayCc8VfqvjPw1diretunG/wz2wJ3/MKH6a2xtMN9Fm66qeh7AcqaHWm6xd9VBvLLl/zmaicoc5vXtK0Tl7MNfyH7moHnvtn/zPb+HbhA7k6eZevVRRCK5wTq9dpWr14sYiN4JJ/Uchgy//1Wr6MLdtYqpQPpaJHLk0kh+DYZ5m0SmUGCECJf6EOqrvxK9AuQVRtS1bKf1Xsto5pQLHK3BBoEwJ1ruySHzKOv/YQGCZMouSQPNHOjV7uBa5NepAUmOXDVTZDd43DFxqRPwZOGBExMCt0+3JnKIqv2KG6ak9lWX3M8X39jlRZ5b/uUr+WGrMOrW7fpmlmGbu+cM8wNzArNO4+w/QwTXLQhYxssx1xkDJa9CZ/gePCtRJLvbUaq4UF/gRUyBmQ8zrlEKw29cpKUIRazQihHmA+XVqqQ0bzP8HBeA47A==###6464:XlxV32DM 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J1tUeqE8a5dPiRSXEE3UHz7uk6kiPVHfErnGMN5y5cdevhQFIA/kLrJbt6IA5IGEL4Mvgy+DL4OvgK+Ar4CvgK+Cr4Kvgq+Cr4Gvga+Br4Gvg6+Dr4Ovg2+Ab4BvgG+AD+NHGD/C+BHGz14OFQUgDyR8C3wLfAt8C3wbfBt8G3wb9jnY52Cfg30OfB58HnwefB58AXwBfAF8AXwP+B7wPeB7wKcvX4ruFHyifhA696HH0DOAlqGdgTpQADLZiNX/ELnUJ2rm862bs9dQBipAFagBdaABBH329sHxMrTB54A8UAB6gPStIoSl5VAHWTkX+8nvAmdAqn71lkGqNlz8M4MwNnE+fJ3fcH7D+Q3nN5zfcH7D+Q3nN5zfcH7D+Q3nN5zfcH7D+Q3nN5wnOD/h/FKftGbmOvrjvIzNM7TUTRizOP98nM+2qhnKQAWoAjWgDjSAoM/uteJ8tplqfA7IAwWgB0jvoeHp+qUjPFMPk+wInF9wfhnjRfxBVxjZeTetHtdZKcrZVjx+lslWppydffDNXLnOzYTNhpr+RXVoQ5t9S1ZBXa3a7dCs+fRtRnLf/E2O+2ZvGEke5xyVka1gRraCGRkJI21LeLaHGdkeZmSkf64kZRTL+OzKlvEJmJFodPZ1WG0cZhmstaJau2OrjcMsg7XKSHt8bBxmGazVp6OGV71qlZBiGaxVjW7FXxsJo6cI5Yw5918buTkXr1nB1kpBGe31ayNh9BjNexSUD+8trV8b+abUsj0UsbWi0a38sRF5tqfZaBlHHxuL2dhho/7h5NzHRuQea2Qb52Ybs/vYWMzGDhtFo1v118bXsoRx1KSwb5TB38K1fC8Sa2/NcEZvMvPPKMfw9esW62a3EoKguc4lxFd35oeejDy6G2Ws1YotqpTW8UiE35F4/V8WLbkqHOhV97znaNY9vE1cRu+UkZ9oWg6/g8dXQB68hFDrjCr2abnxM9wdk1Ks4I3RO8tkTNwan/EeyFYbeUtwsoIpV8kY71LIi/pFsqg7LSXgENEnRG9glqE3B7uEqPhPiAZmhwXLpnq08GdvBbbZaioErQIRNidX/4nqu44iqlwZy4hLVU9U4yeqw6LKk5WjKrppalFnoP58GHlKTCvvZCRJJn8hvYnwhn8ZeueTzvScPokwMNMtJWzZepYlwi3OA6Pct9uj5giy3Emf3HkzZhmid+/Q3MHegSomRrxMcBbpwoMKL9f2hxGIC5o4i2SaOKx+kjsVGVMtY3hlOQHGvhQwla3sSHJHjLi1sRr+kD6MBbmTDanuahWLkjHVMub+Sqd5UiVPbGWd9hylK3SzoMvqT8tZngwrhpHmN0+yITFi+mS6OU8qsqNadtgaa/tp8/l3cZAd4TEjfItW8dLMWm0uyA7kieou9not2VGRE9VyQqx1e//O+TQRt2ZoY9eWUOeqK8v/AZAsvQY=###6536:XlxV32DM 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FcmDdBVkuw2QTgD+XvYK5HzTb4Rn/ReKX4KyTDCR5MEkhARiv5vYE9y0u1yo7zbizvE1w4y4qGYaVCKVlbzjMGQDzzuBB5Wn2tt72pHQsweHzRsZyjrp7CTTND2Mr6+y3QQhqhzOtRvBll6R9D8R6S5Bktmu3S12N9jd6/+bdTnkhIqzoAJwXkhvLDMqyavpfc6q+nTrF/4i8C9Sa9jtTM1UoFcVPeFeMe2KlCcR0FhYwLHQTOdwmBwOOpbWMXifhz3fT9cHPj8ipUQpUyqUKqVGqVOivfP2atKitNnuonRTcpQ8pTP3usVk06cULMZN2LAyaQZGZDt7iORVH30THmTl1dJfCVtfFabRGRit2OHRX9loo2Z6nufUIJiILsCrYCmpbpTHyDQ4l5utjU9hp8pid7fN1lOrPDZVSarif1QCVIb2gvmhKvpoH7GgVDCvXMsdjsXrxzHl+IRNFQfHMiaDNhTlAALlI64flQAV2fpUpZmK7d1FbhP5P83ieJ/iK57OZTjrM3nFM7l4EJuBJw/msps/kWAFqj1+s6ngRXCMdTRUgNc4LDoGQ1VAo8OD/gjfvGnokake13cwvMNscpV+mvVVjdIpql/DEYbP9iC1BvuwRUcNDxpeNFxguCkGk+SG+B0cinTAyquGGwxPGm40zIlR1XK8bcXUMUSXLbf3T24HLC9arrRcabnDebmuBWEKPc77W+gIskpmGw7PKmlPI/4uxqTwd7VLu78b9uhjRaksd75BnwoX/m8Jl87Xf6RsCb1RVZRQJJfxbsSUtYTAI5KjdFMSPtEhxilrwSVKFYwHobKotCAdttGR7nGuCk6ZQw7/y4hB2SlFelk55uEdvg1lBxTppc4ofX7j9zJzkRZXJlXHGrZvww2LMgalod57HrH90KkKwlKeU4xfYpVef/eNP/IkOxrWkSws/lGx3fVtqGEdqbFh00l5z68TcaF6kW0k530lRCmRxfmv7UEnLBMkw5/CT8MNJ5AJEroPwGhYGVZFWI7sU/4hp2Ta88E8k8w4nbFzlH6TybQVzmv2P0zbaFxa0GX3h2krp+9Tq+4p9eZl2h7Vp4gk3QSmbUOvT5HW7nT/MG0juLTa6zVJl51Gl5WvYFWYtuWHaRuNS2sOX+HLtHXGw7WR5fz+YdpGIcPulyvbyLTdZNqml2mbfpi2on1+4YX2Tabt0lxpNZi284dpK9pyfDSmbSHTdupfGm73ATLsoc1+mbYRVFpwZfeXaetAxEXcd/9h2qrn/eXpJjJt+yduMm0Dmbbhh3HalGnbfpi27q82BNs1TTJtmy3LrsSXaet/mLYO1WDaJjJtk52ynP2JItrjh2kr2qehrk2uXOC3nw/JMiOFSmt8VVD4jGnrrBqel0rPcU05ZdReP0xbZ9Vk2i4ybZedOpRxqllbP5CItjTUJSIvUu+H3SSlDFnbP8NBtVd+ubKI+0jadx6NHOH9MxRVe1/seyPuFLBQC5V2GNP2ZxqYdoV2uRyZts4Q8/v/9dNW2Q==###6664:XlxV32DM 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0JmGbGzzwjZgP8jerk296nzukko6j6yrJHhmaMFMPoy08xGAjfAWZIwCTZ83JFgndYoNGWXMkM8eRAijg96fpxPnFoLR3NLxjH3+OxEw1eoUUQMRVRBRBRE1EFEDEVUQUQNxNBFHCXHUEEcVcTQQRwNxNBBHBXE0EEenybVrwCdO7d+dYjt07vqCw9GTJXo0BqNqnx9wNEDf+Cg4kx5RMRAVA1ExEAsFsTAQCwV+KIiFgVgoiIWBWCiIBUCCdfIivZWhorSTN4eMLdibE96s8GaFNye8OeHNCm9OeHPAmxneTPBmgTcnvDnhzQlvVnhzwofwnNBBvy7Xfc+O51rirgp3Zbirwl0T7kIKlYXvdr1ud2TlTarAsaS6Wt5kxHEVjqtw3ITjKhw34bgKxwESrNNPWyy+7LM0UIcQnkY43z/9QMFLReFexKOb8HLFMZq7iXLfwpwUQowevPj4LF4FLTOq09q+C/6i7a70A/pt7+5ojcz1uRuOjO7oRbr2ZT1KwG4wfRavipZHPPP59O02etKp2DczPZ5wY8//CLEWmjmxCqOP6Ic/ljyJ8XxWmejV/XzmpdBUaCT8tvBbxm8PfisK0fiPfzOAKrAOv126BqzHb5cO+s3ziRe9w41LB53PkFCgq/3VGZp2SDvDK1kZms77G3Y+sd95d3l3hPXkE8TzBImPevgJ0uFBEU+L3HsY+oAxKOHrYRUQVUnmfo2Ys37UlrN8l2lzw3f3OccP2iuaX/i70da8e/7oa0MWk79uxhtNJRGjqRYNRfvf0J1wh1KUO+AoEpq4GU0DvaXHYUPylwD7uKqaL+3cBe0VzZqfB8v3SW14xJQ0EHHOI875vGkgAB0+aEkD67N4FzTSQP6c1IbpmMwclJt/pKP6rIue7zTAox+5z2nx8lm8C1pkO/+8VQsFT7a8b/3Im0cxz0XLvhP2nT5o3ncM78WdFTT2Xd+qhaJTRk1/ARvT11EeQkr6e4B+sO+K9Kef5/LiJDvjzzD7ZtSxvtVXIqkzC6NPerT5n97OHbdzwe2ccTsT1JqOh2fQOrm7N8TVVOaeUWpxrpJm+1TgSWso6T3kz3ZSi3dU4AkV+EK1PVFjV9TYFbtDPT3wG+UKuu/NT/4nCnKRN5suWAyWefTOrijV29T6IVtpxan2oORDEP/DhZcuWPqyLG7R9IzyRguUnayifK8kO4XP2Ia0lyGQfMji6Jucdf7gus9to+9qjqOkGCdXVLgCDRIvTQ6oMPu1Q8buO8y+YPaELzgKHHB3Qk9gVv8pKczXKxk7mboT/m+MpVHQZYH7BtZel5mn0emcr3I+xdldtHxpxJADZAGdAHNWv0hiyAGygJhugG6AboBuKJ3Deg7rOaznsJ5zoHOgc6BzoPOg86DzoPOgC6ALoAugC6CLoIugi6CLoIP9HOznYD8H+5kMO2fYOcPOGXQFdAV0BXQFdBV0FXQVdBX+gP0s7GdhPwv7mYb1GtZrWK9hPdjZws4Wdraws+lYr2O9jvU61oM/LPxh4Q8Lf9gJugm6CboJuYg/g/gziD+D+LPwr4V/Lfxr4V+7QLdAt0C3IBf6GehnoJ+BfhbxYhEvFvFi73l7QPeA7gHdA7nQz0A/A/0M9LOIP4v4s4g/gsz/34PAWw==###6680:XlxV32DM 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zesDrGADyPbY4t4d0rm8zUHnq1RJk70JWwIJPVGjewB+rEZZYkHOz+wJNj0TagNZV49yTUBsOtxhkaUUbRoWprZ7qE3HTy0mlbjUkTgKGznwQI/seuK3/UI5UBaUISoDl4HLwGXgCnAFuAJcAa4CV4GrwFXgGnANuAZcA64D14HrwHXgBnADuAHcAG7y/zmECkRFyEbIRshGyC7gFnALuAXcBm4Dt4HbihtGccMobhjFDQOcBc4CZ4GzwDngHHAOOAecB84D54HzwAXgAnABuAAcxm9g/AbGb+j40Toe/Chq+fe7plzwSCnhaRLOp3nDj2Ler4tywVOhhAdCRQOnlMD0HgFvfEiEH+wkDV8ND3aGXD3W90sbEuFnM0nDScP1IWftdd1d1+Vb1r35oms68mh0TafUUqopdeMBB457YSfcu6iJKvcok1+q9UfLEI90unMaYOYNVE1FOGuc5fp762TEyDBvDp8UeZMiqKTUKTa0DbiYQVmlTrjXtgGJh/KgOnBoi9B8/Ci7/WH0heJ8nnfNpGXBNZ8+j4Aar+gtypDJpa9zxcs3ueJAeYu2DcooZQeoAm4FJRPlIj1GoIesW9Pb0/GnsiULY56IYNm9rrHZQqeTeygZVwoyHI1c02nmdzGNcBESQakGLW1rgLLxc15Ny4HUyPtLv9/JP4U35yNqA7vebL7P81FT/hg1x05b/+VFsZypm9MLtYXil5S0Q7IPstu5EU8pqXom6nk1yc9Ysr6hleeVUTTK5M+u50Fz6APcObU6JIqr4knnalGBFIxZJCqQoiiLQJjOHvrGApxbEkqSpQHtUQ98g5P/OxxqSl3R9VLZrhblHmzVLSMycN5CmkmWbeH/xzmqeOmfICbJVDprQen0Ooc250B5UAFUBAV9JoMqoCr6gD7T0AbNpqMNfdBbXubCPot+7QIXOPt82wYXOAv73L0/7PLfSuXCZmtAPdY/NsPSgPXoaD3Sn5+Cx/8P5QyV/4kof6KiO/CgQApJDMQ/GvkPU6Hp/0BWltMKb+7EU1q/7ganWtWbooetNwdL0f4qcAJI1UPTZwd2Gt0zbaLmHVPfNN5/r5EeAU4A+fB7zs8LYoPnZ4i0z2MyibS5fd7xGjzQep46eTzB4npzlc9rWoMnTM9jIERafeTjP29aDR75PI9fnoc69GdLU4eO7f0v0j0+83dbyKeOLe5437+f8tO9reeMtulRoG1LqzVm8wvBGTGgRgaUgY+eyRMcMMHpNcE8/2eC7WeC3a8CJ4CJJzi9J5je+902ffK6zGeCnU4wHR8ykP6AaFqGPVn+Levs0PJnZbzJzPzXogtc4vaPuR3mNu5GgAlA+lui0WSDG++e8fdKTL5m6nXnHXs+q7lNOvYzv8ee5pXZPPbLfsbe6di3CuBkPRrDLsWlOd0HqZ76HrNsfhWYACQ901uMvfynYZeAEa0Ty0weiHj2h3QKsVJ/s6kwXXTOwCOaNTTdjFt2OF6gr+dAYugfOHdQE8ce+h/ppoei0kj7f8xn/6fPkHlITwD576RNj1l2kRtV2+952qWIS1tB/r3KU407eRLJd01QCmbpyH3hj17Mpv8L4r3UkQ5vdmqQFuUf6VTBFmn7YWeweXDxRo3ZCWyeOb8/7Ag2702/Puyg7MCm+flh/w9zoq4B###5352:XlxV32DM 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e76R+YYruc5n9Z1XD6OyzPd7N9zKld7z9cw3/2b3fDPzTVdyzTd93y9130jmG775liu950vdmH+ze77UjelKru83HeeRuALfhSuYNaj+ffn1Nxs5m+Vk/y5fx7Wfvmu/Xel9Tkau/fqb3ddC5Vp4/vwHTi5yuA==###5888:XlxV32DM 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wwXrW9m4A6gtrHiwNbqWHe7A6JoTrm9yiV/XkMBFo1z0m8+saxt25SnN0ErENtkEboofh6fd2xXsPODFw+EGrDvVDWcYiiuw7Xg3HGIY7oJ36sYphuEH2HTjpEKxREwwdO8On4apOzssXbNV84vT47BEbGMieVuXFQ+2hlsuhzuwdQ1HSoYfw+gazpRUo0RsW46ruAaU11zPqw6cnwcEWV9aXfmH0tYmehB14CRdj8L4nuseIBxxbdKpRVKlJg5qkVSpi4uEFpqnTqbKIMd/FDjQB02VInCgD5Yqw3GjyYlUKSW19Iq0lDvNcG5rE7X0xIG7Hr4xj5mlZ12bdGpRSyUxUotZyt9hpF5helVLz7EKHOiDWYpVlgiEpTWjyZSjls6SxbTC0puXrkK91iZq6Sw1NqnM02ap3Chkk04tFtMKS2U/KtMf7yhpvcLpQy3lUl/wQB8Q0wpLb/5ZG+QamzQpOywtOy1tOGO9eUW78uabTAYPU7NlT14flYeG44cjMRbZkv/sTY7mRs1bX4KT9aRkQn0B7w39SVgwWsWbKbOjJEsiaaIX6LawrU16RUVNS3L2cqCJXsnb5Mz6ZpMb6U1LrbOEAysVKKVof+y+fa0sscVUYqUDpT74jNragY3DdjAlXVhWamfUiXKMRPMGezPgEV2oTs12IVFvS2iTHT6OCRGICRG4eW90435IJwlaqn6PiX4/Pr+PtUmnlk4t5ndeXt3wH7VNJoXetvGSVomDnRjoBEzlbVn9Ii5N5ICmIi76S87AFyuJgZkaz7VJZSjFVCk1NlFT9UYQm3Rq6dSipnbc3Lj4i8+G4xsbTUMF1lXgYB8G+mCWdl6fTYMRavaxZD77PwWPz/c=###6224:XlxV32DM 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.twx b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.twx new file mode 100644 index 000000000..7adb4c324 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.twx @@ -0,0 +1,341 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +]> +Release 14.1 Trace (lin64)Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved./opt/Xilinx/14.1/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -e 10 -s 3 +-n 3 -fastpaths -xml b200.twx b200.ncd -o b200.twr b200.pcf + +b200.ncdb200.ncdb200.pcfb200.pcfxc6slx75C-3PRODUCTION 1.21 2012-04-231103INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.TS_codec_main_clk = PERIOD TIMEGRP "codec_main_clk" 25 ns HIGH 50%;000000016.000Component Switching Limit Checks: TS_codec_main_clk = PERIOD TIMEGRP "codec_main_clk" 25 ns HIGH 50%;TS_IFCLK = PERIOD TIMEGRP "IFCLK" 10 ns HIGH 50%;0000000Component Switching Limit Checks: TS_IFCLK = PERIOD TIMEGRP "IFCLK" 10 ns HIGH 50%;TS_codec_data_clk_p = PERIOD TIMEGRP "codec_data_clk_p" 16.276 ns HIGH 50%;00000001.639Component Switching Limit Checks: TS_codec_data_clk_p = PERIOD TIMEGRP "codec_data_clk_p" 16.276 ns HIGH 50%;TS_gen_clks_clkfx = PERIOD TIMEGRP "gen_clks_clkfx" TS_codec_main_clk / 2.5 HIGH 50%;4890322009931212.189Paths for end point slave_fifo32/EP_READY1 (OLOGIC_X4Y173.D1), 1 path +-2.189slave_fifo32/EP_READYslave_fifo32/EP_READY112.263-0.30910.0000.235slave_fifo32/EP_READYslave_fifo32/EP_READY10ILOGIC_X17Y55.CLK0gpif_clkILOGIC_X17Y55.Q4Tickq0.992slave_fifo32/EP_READYslave_fifo32/EP_READYOLOGIC_X4Y173.D1net210.468slave_fifo32/EP_READYOLOGIC_X4Y173.CLK0Todck0.803slave_fifo32/EP_READY1slave_fifo32/EP_READY11.79510.46812.263gpif_clk14.685.4Paths for end point slave_fifo32/EP_WMARK1 (OLOGIC_X2Y175.D1), 1 path +-1.341slave_fifo32/EP_WMARKslave_fifo32/EP_WMARK111.0290.07710.0000.235slave_fifo32/EP_WMARKslave_fifo32/EP_WMARK10ILOGIC_X17Y78.CLK0gpif_clkILOGIC_X17Y78.Q4Tickq0.992slave_fifo32/EP_WMARKslave_fifo32/EP_WMARKOLOGIC_X2Y175.D1net29.234slave_fifo32/EP_WMARKOLOGIC_X2Y175.CLK0Todck0.803slave_fifo32/EP_WMARK1slave_fifo32/EP_WMARK11.7959.23411.029gpif_clk16.383.7Component Switching Limit Checks: TS_gen_clks_clkfx = PERIOD TIMEGRP "gen_clks_clkfx" TS_codec_main_clk / 2.5 + HIGH 50%;1codec_main_clk_ncodec_main_clk_n12.189codec_main_clk_p12.189codec_main_clk_pcodec_main_clk_n12.189codec_main_clk_p12.18923530353004890301238816.00062.500Tue Jan 29 17:12:06 2013 TraceTrace Settings + +Peak Memory Usage: 536 MB + diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.ucf b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.ucf new file mode 100644 index 000000000..6c9af6954 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.ucf @@ -0,0 +1,415 @@ + +#################################################################################### +# Generated by PlanAhead 14.4 built on 'Tue Dec 18 05:17:28 MST 2012' by 'xbuild' +#################################################################################### + + +#################################################################################### +# Constraints from file : 'b200.ucf' +#################################################################################### + +## SPI Nets + +NET "cat_ce" LOC = Y1; +NET "cat_ce" IOSTANDARD = LVCMOS18; +NET "cat_miso" LOC = V1; +NET "cat_miso" IOSTANDARD = LVCMOS18; +NET "cat_mosi" LOC = T4; +NET "cat_mosi" IOSTANDARD = LVCMOS18; +NET "cat_sclk" LOC = P7; +NET "cat_sclk" IOSTANDARD = LVCMOS18; + +NET "fx3_ce" LOC = H20; +NET "fx3_miso" LOC = G20; +NET "fx3_mosi" LOC = AA20; +NET "fx3_sclk" LOC = Y21; + +NET "pll_ce" LOC = W11; +NET "pll_mosi" LOC = AB11; +NET "pll_sclk" LOC = Y12; + +NET "FPGA_RXD0" LOC = AB8; +NET "FPGA_TXD0" LOC = AB7; + +NET "SCL_FPGA" LOC = P21; +NET "SDA_FPGA" LOC = W22; + +## Catalina Controls + +NET "codec_enable" LOC = J6; +NET "codec_enable" IOSTANDARD = LVCMOS18; +NET "codec_en_agc" LOC = P6; +NET "codec_en_agc" IOSTANDARD = LVCMOS18; +NET "codec_reset" LOC = Y2; +NET "codec_reset" IOSTANDARD = LVCMOS18; +NET "codec_sync" LOC = M3; +NET "codec_sync" IOSTANDARD = LVCMOS18; +NET "codec_txrx" LOC = M7; +NET "codec_txrx" IOSTANDARD = LVCMOS18; + +NET "codec_ctrl_in[0]" LOC = E3; +NET "codec_ctrl_in[0]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in[1]" LOC = F2; +NET "codec_ctrl_in[1]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in[2]" LOC = F1; +NET "codec_ctrl_in[2]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in[3]" LOC = E1; +NET "codec_ctrl_in[3]" IOSTANDARD = LVCMOS18; + +NET "codec_ctrl_out[0]" LOC = D1; +NET "codec_ctrl_out[0]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[1]" LOC = C1; +NET "codec_ctrl_out[1]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[2]" LOC = H3; +NET "codec_ctrl_out[2]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[3]" LOC = F3; +NET "codec_ctrl_out[3]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[4]" LOC = P1; +NET "codec_ctrl_out[4]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[5]" LOC = J1; +NET "codec_ctrl_out[5]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[6]" LOC = B1; +NET "codec_ctrl_out[6]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[7]" LOC = H2; +NET "codec_ctrl_out[7]" IOSTANDARD = LVCMOS18; + +## Catalina Data RX + +NET "rx_codec_d[0]" LOC = T2; +NET "rx_codec_d[0]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[0]" DRIVE = 4; +NET "rx_codec_d[1]" LOC = R1; +NET "rx_codec_d[1]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[1]" DRIVE = 4; +NET "rx_codec_d[2]" LOC = V2; +NET "rx_codec_d[2]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[2]" DRIVE = 4; +NET "rx_codec_d[3]" LOC = N1; +NET "rx_codec_d[3]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[3]" DRIVE = 4; +NET "rx_codec_d[4]" LOC = V3; +NET "rx_codec_d[4]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[4]" DRIVE = 4; +NET "rx_codec_d[5]" LOC = T1; +NET "rx_codec_d[5]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[5]" DRIVE = 4; +NET "rx_codec_d[6]" LOC = W1; +NET "rx_codec_d[6]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[6]" DRIVE = 4; +NET "rx_codec_d[7]" LOC = U1; +NET "rx_codec_d[7]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[7]" DRIVE = 4; +NET "rx_codec_d[8]" LOC = W3; +NET "rx_codec_d[8]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[8]" DRIVE = 4; +NET "rx_codec_d[9]" LOC = U3; +NET "rx_codec_d[9]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[9]" DRIVE = 4; +NET "rx_codec_d[10]" LOC = P2; +NET "rx_codec_d[10]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[10]" DRIVE = 4; +NET "rx_codec_d[11]" LOC = R3; +NET "rx_codec_d[11]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[11]" DRIVE = 4; + +## Catalina Data TX + +NET "tx_codec_d[0]" LOC = M1; +NET "tx_codec_d[0]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[0]" DRIVE = 4; +NET "tx_codec_d[1]" LOC = K1; +NET "tx_codec_d[1]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[1]" DRIVE = 4; +NET "tx_codec_d[2]" LOC = L3; +NET "tx_codec_d[2]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[2]" DRIVE = 4; +NET "tx_codec_d[3]" LOC = K2; +NET "tx_codec_d[3]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[3]" DRIVE = 4; +NET "tx_codec_d[4]" LOC = M4; +NET "tx_codec_d[4]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[4]" DRIVE = 4; +NET "tx_codec_d[5]" LOC = J4; +NET "tx_codec_d[5]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[5]" DRIVE = 4; +NET "tx_codec_d[6]" LOC = L4; +NET "tx_codec_d[6]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[6]" DRIVE = 4; +NET "tx_codec_d[7]" LOC = H1; +NET "tx_codec_d[7]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[7]" DRIVE = 4; +NET "tx_codec_d[8]" LOC = M2; +NET "tx_codec_d[8]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[8]" DRIVE = 4; +NET "tx_codec_d[9]" LOC = G1; +NET "tx_codec_d[9]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[9]" DRIVE = 4; +NET "tx_codec_d[10]" LOC = N3; +NET "tx_codec_d[10]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[10]" DRIVE = 4; +NET "tx_codec_d[11]" LOC = G3; +NET "tx_codec_d[11]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[11]" DRIVE = 4; + +## Catalina Clocks + +NET "cat_clkout_fpga" LOC = J3; +NET "cat_clkout_fpga" IOSTANDARD = LVCMOS18; +NET "codec_data_clk_p" LOC = K3; +NET "codec_data_clk_p" IOSTANDARD = LVCMOS18; +NET "codec_fb_clk_p" LOC = P3; +NET "codec_fb_clk_p" IOSTANDARD = LVCMOS18; +# | IOSTANDARD = LVCMOS18; +NET "codec_main_clk_p" LOC = K5; +# | IOSTANDARD = LVCMOS18; +NET "codec_main_clk_n" LOC = K4; + +NET "rx_frame_p" LOC = U4; +NET "rx_frame_p" IOSTANDARD = LVCMOS18; +NET "tx_frame_p" LOC = T3; +NET "tx_frame_p" IOSTANDARD = LVCMOS18; + +## Debug Bus + +NET "debug[0]" LOC = C14; +NET "debug[1]" LOC = F15; +NET "debug[2]" LOC = A18; +NET "debug[3]" LOC = A17; +NET "debug[4]" LOC = E14; +NET "debug[5]" LOC = G13; +NET "debug[6]" LOC = D13; +NET "debug[7]" LOC = F13; +NET "debug[8]" LOC = D8; +NET "debug[9]" LOC = A6; +NET "debug[10]" LOC = D7; +NET "debug[11]" LOC = A5; +NET "debug[12]" LOC = B6; +NET "debug[13]" LOC = A3; +NET "debug[14]" LOC = A7; +NET "debug[15]" LOC = A8; +NET "debug[16]" LOC = B18; +NET "debug[17]" LOC = C17; +NET "debug[18]" LOC = H13; +NET "debug[19]" LOC = D12; +NET "debug[20]" LOC = H14; +NET "debug[21]" LOC = C10; +NET "debug[22]" LOC = D10; +NET "debug[23]" LOC = C8; +NET "debug[24]" LOC = D9; +NET "debug[25]" LOC = C5; +NET "debug[26]" LOC = A9; +NET "debug[27]" LOC = B8; +NET "debug[28]" LOC = A4; +NET "debug[29]" LOC = C7; +NET "debug[30]" LOC = C6; +NET "debug[31]" LOC = D6; + +NET "debug_clk[0]" LOC = A12; +NET "debug_clk[1]" LOC = C12; + +## GPIF + +NET "IFCLK" LOC = H21; +NET "FX3_EXTINT" LOC = U20; + +NET "GPIF_CTL0" LOC = V20; +NET "GPIF_CTL1" LOC = T22; +NET "GPIF_CTL2" LOC = R22; +NET "GPIF_CTL3" LOC = U22; +NET "GPIF_CTL4" LOC = P19; +NET "GPIF_CTL5" LOC = N22; +NET "GPIF_CTL6" LOC = T21; +NET "GPIF_CTL7" LOC = V21; +NET "GPIF_CTL8" LOC = K18; +NET "GPIF_CTL9" LOC = R20; +##GPIF_CTL10 is "FPGA_CFG_DONE", defined later. +NET "GPIF_CTL11" LOC = P22; +NET "GPIF_CTL12" LOC = M20; + +NET "GPIF_D[0]" LOC = T17; +NET "GPIF_D[1]" LOC = U14; +NET "GPIF_D[2]" LOC = U13; +NET "GPIF_D[3]" LOC = AA6; +NET "GPIF_D[4]" LOC = AB6; +NET "GPIF_D[5]" LOC = Y3; +NET "GPIF_D[6]" LOC = AB3; +NET "GPIF_D[7]" LOC = AA4; +NET "GPIF_D[8]" LOC = AA2; +NET "GPIF_D[9]" LOC = AB2; +NET "GPIF_D[10]" LOC = AB19; +NET "GPIF_D[11]" LOC = AA18; +NET "GPIF_D[12]" LOC = AB18; +NET "GPIF_D[13]" LOC = Y13; +NET "GPIF_D[14]" LOC = AA12; +NET "GPIF_D[15]" LOC = AB12; +NET "GPIF_D[16]" LOC = N20; +NET "GPIF_D[17]" LOC = L20; +NET "GPIF_D[18]" LOC = N19; +NET "GPIF_D[19]" LOC = M22; +NET "GPIF_D[20]" LOC = L19; +NET "GPIF_D[21]" LOC = M21; +NET "GPIF_D[22]" LOC = M19; +NET "GPIF_D[23]" LOC = K22; +NET "GPIF_D[24]" LOC = J20; +NET "GPIF_D[25]" LOC = L22; +NET "GPIF_D[26]" LOC = K19; +NET "GPIF_D[27]" LOC = H22; +NET "GPIF_D[28]" LOC = J22; +NET "GPIF_D[29]" LOC = K20; +NET "GPIF_D[30]" LOC = G22; +NET "GPIF_D[31]" LOC = F22; + +## GPS + +NET "gps_lock" LOC = Y17; +NET "gps_out_enable" LOC = V22; +NET "gps_ref_enable" LOC = AB13; +NET "gps_rxd" LOC = AB14; +NET "gps_txd" LOC = W12; +NET "gps_txd_nmea" LOC = AA14; + +## LEDS + +NET "LED_RX1" LOC = C22; +NET "LED_RX2" LOC = L15; +NET "LED_TXRX1_TX" LOC = C20; +NET "LED_TXRX2_RX" LOC = D21; +NET "LED_TXRX1_RX" LOC = K16; +NET "LED_TXRX2_TX" LOC = D22; + +## Misc Hardware Control + +NET "ext_ref_enable" LOC = Y15; +NET "pll_lock" LOC = AB10; +NET "AUX_PWR_ON" LOC = AA21; +#NET "RFUSE" LOC = "P15" ; + +## PPS + +NET "pps_fpga_out_enable" LOC = AB15; +NET "PPS_IN_EXT" LOC = AB16; +NET "PPS_IN_INT" LOC = AB21; +NET "pps_out" LOC = AB17; + +## RF Hardware Control + +NET "SFDX1_RX" LOC = W4; +NET "SFDX1_TX" LOC = T18; +NET "SFDX2_RX" LOC = F18; +NET "SFDX2_TX" LOC = H17; +NET "SRX1_RX" LOC = Y7; +NET "SRX1_TX" LOC = AA8; +NET "SRX2_RX" LOC = J17; +NET "SRX2_TX" LOC = F19; +NET "tx_bandsel_a" LOC = N16; +NET "tx_bandsel_b" LOC = M16; +NET "tx_enable1" LOC = Y4; +NET "tx_enable2" LOC = R19; +NET "rx_bandsel_a" LOC = T20; +NET "rx_bandsel_b" LOC = U19; +NET "rx_bandsel_c" LOC = P20; + +## FPGA Config Pins + +#NET "FPGA_CFG_INIT_B" LOC = "T6" ; +#NET "FPGA_CFG_DONE" LOC = "Y22" ; +#NET "FPGA_CFG_M0" LOC = "AA22" ; +#NET "FPGA_CFG_M1" LOC = "U15" ; +#NET "FPGA_CFG_PROG_B" LOC = "AA1" ; + +## Special Pins + +#NET "VFS" LOC = "P16" ; +#NET "TMS" LOC = "C18" ; +#NET "TDO" LOC = "A19" ; +#NET "TDI" LOC = "E18" ; +#NET "TCK" LOC = "G15" ; +#NET "GND" LOC = "N15" ; + +#################################################################################### +# Constraints from file : 'timing.ucf' +#################################################################################### + + +# codec_main_clk is 40 MHz main tcxo clock +NET "codec_main_clk*" TNM_NET = "codec_main_clk"; +TIMESPEC TS_codec_main_clk = PERIOD "codec_main_clk" 25000 ps HIGH 50 %; + + +# IFCLK is 100 MHz GPIF clock +NET "IFCLK" TNM_NET = "IFCLK"; +TIMESPEC TS_IFCLK = PERIOD "IFCLK" 10000 ps HIGH 50 %; + + +# codec_data_clk is the data clock from catalina, sample rate dependent +# this clock equals sample rate in CMOS DDR 1R1T mode +# this clock is double the sample rate in CMOS DDR 2R2T mode +# Max clock rate is 61.44 MHz +NET "codec_data_clk_p" TNM_NET = "codec_data_clk_p"; +TIMESPEC TS_codec_data_clk_p = PERIOD "codec_data_clk_p" 16276 ps HIGH 50 %; + + +#always use IOB for GPIF pins for awesome timing +INST "GPIF_D_9_IOBUF" IOB =TRUE; +INST "GPIF_D_8_IOBUF" IOB =TRUE; +INST "GPIF_D_7_IOBUF" IOB =TRUE; +INST "GPIF_D_6_IOBUF" IOB =TRUE; +INST "GPIF_D_5_IOBUF" IOB =TRUE; +INST "GPIF_D_4_IOBUF" IOB =TRUE; +INST "GPIF_D_3_IOBUF" IOB =TRUE; +INST "GPIF_D_31_IOBUF" IOB =TRUE; +INST "GPIF_D_30_IOBUF" IOB =TRUE; +INST "GPIF_D_2_IOBUF" IOB =TRUE; +INST "GPIF_D_29_IOBUF" IOB =TRUE; +INST "GPIF_D_28_IOBUF" IOB =TRUE; +INST "GPIF_D_27_IOBUF" IOB =TRUE; +INST "GPIF_D_26_IOBUF" IOB =TRUE; +INST "GPIF_D_25_IOBUF" IOB =TRUE; +INST "GPIF_D_24_IOBUF" IOB =TRUE; +INST "GPIF_D_23_IOBUF" IOB =TRUE; +INST "GPIF_D_22_IOBUF" IOB =TRUE; +INST "GPIF_D_21_IOBUF" IOB =TRUE; +INST "GPIF_D_20_IOBUF" IOB =TRUE; +INST "GPIF_D_1_IOBUF" IOB =TRUE; +INST "GPIF_CTL0_OBUF" IOB =TRUE; +INST "GPIF_CTL11_OBUF" IOB =TRUE; +INST "GPIF_CTL12_OBUF" IOB =TRUE; +INST "GPIF_CTL1_OBUF" IOB =TRUE; +INST "GPIF_CTL2_OBUF" IOB =TRUE; +INST "GPIF_CTL3_OBUF" IOB =TRUE; +INST "GPIF_CTL4_IBUF" IOB =TRUE; +INST "GPIF_CTL5_IBUF" IOB =TRUE; +INST "GPIF_CTL7_OBUF" IOB =TRUE; +INST "GPIF_CTL9_IBUF" IOB =TRUE; +INST "GPIF_D_0_IOBUF" IOB =TRUE; +INST "GPIF_D_10_IOBUF" IOB =TRUE; +INST "GPIF_D_11_IOBUF" IOB =TRUE; +INST "GPIF_D_12_IOBUF" IOB =TRUE; +INST "GPIF_D_13_IOBUF" IOB =TRUE; +INST "GPIF_D_14_IOBUF" IOB =TRUE; +INST "GPIF_D_15_IOBUF" IOB =TRUE; +INST "GPIF_D_16_IOBUF" IOB =TRUE; +INST "GPIF_D_17_IOBUF" IOB =TRUE; +INST "GPIF_D_18_IOBUF" IOB =TRUE; +INST "GPIF_D_19_IOBUF" IOB =TRUE; + +# TODO not working... constraints ignored + +#constrain FX3 IO +INST "GPIF_D[*]" TNM = "gpif_net_out"; +INST "GPIF_D[*]" TNM = "gpif_net_in"; +INST "GPIF_CTL0" TNM = "gpif_net_out"; +INST "GPIF_CTL1" TNM = "gpif_net_out"; +INST "GPIF_CTL2" TNM = "gpif_net_out"; +INST "GPIF_CTL3" TNM = "gpif_net_out"; +INST "GPIF_CTL4" TNM = "gpif_net_in"; +INST "GPIF_CTL5" TNM = "gpif_net_in"; +INST "GPIF_CTL7" TNM = "gpif_net_out"; +INST "GPIF_CTL11" TNM = "gpif_net_out"; +INST "GPIF_CTL12" TNM = "gpif_net_out"; + +#NET "gpif_clk" TNM_NET = "TNM_gpif_clk"; +#OFFSET = OUT 5 ns AFTER "gpif_clk"; +#TIMESPEC "TS_gpif_clk" = PERIOD "TNM_gpif_clk" 10000 ps HIGH 50 %; +#TIMEGRP "gpif_net_in" OFFSET = IN 6 ns VALID 6 ns BEFORE "gpif_clk" RISING; +#TIMEGRP "gpif_net_out" OFFSET = OUT 6 ns AFTER "gpif_clk" RISING; diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.xdl b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.xdl new file mode 100644 index 000000000..f35ea02e6 Binary files /dev/null and b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.xdl differ diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/htr.txt b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/htr.txt new file mode 100644 index 000000000..bf500d659 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/htr.txt @@ -0,0 +1,13 @@ +# +# PlanAhead(TM) +# htr.txt: a PlanAhead-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for PlanAhead to track run status. +# Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved. +# + +ngdbuild -intstyle ise -p xc6slx75fgg484-3 -dd _ngo -uc "b200.ucf" "b200.edf" +map -intstyle pa -w "b200.ngd" +par -intstyle pa "b200.ncd" -w "b200_routed.ncd" +trce -intstyle ise -o "b200.twr" -v 30 -l 30 "b200_routed.ncd" "b200.pcf" +xdl -secure -ncd2xdl -nopips "b200_routed.ncd" "b200_routed.xdl" diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/rundef.js b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/rundef.js new file mode 100644 index 000000000..759e0d89d --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/rundef.js @@ -0,0 +1,48 @@ +// +// PlanAhead(TM) +// rundef.js: a PlanAhead-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/opt/Xilinx/14.4/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.4/ISE_DS/common/bin/lin64;/opt/Xilinx/14.4/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.4/ISE_DS/common/lib/lin64;/opt/Xilinx/14.4/ISE_DS/PlanAhead/bin;"; +} else { + PathVal = "/opt/Xilinx/14.4/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.4/ISE_DS/common/bin/lin64;/opt/Xilinx/14.4/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.4/ISE_DS/common/lib/lin64;/opt/Xilinx/14.4/ISE_DS/PlanAhead/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "ngdbuild", + "-intstyle ise -p xc6slx75fgg484-3 -dd _ngo -uc \"b200.ucf\" \"b200.edf\"" ); +ISEStep( "map", + "-intstyle pa -w \"b200.ngd\"" ); +ISEStep( "par", + "-intstyle pa \"b200.ncd\" -w \"b200_routed.ncd\"" ); +ISEStep( "trce", + "-intstyle ise -o \"b200.twr\" -v 30 -l 30 \"b200_routed.ncd\" \"b200.pcf\"" ); +ISEStep( "xdl", + "-secure -ncd2xdl -nopips \"b200_routed.ncd\" \"b200_routed.xdl\"" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.bat b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.bat new file mode 100644 index 000000000..4eed28871 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem PlanAhead (TM) +rem runme.bat: a PlanAhead-generated Script +rem Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.log b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.log new file mode 100644 index 000000000..9fee0944e --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.log @@ -0,0 +1,4 @@ +*** PLEASE NOTE: this run was imported on Tue Jan 29 17:25:57 2013 + from ISE results generated outside of PlanAhead. + Original messages and reports have not been imported + but you can launch bitgen on this run if desired... diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.sh b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.sh new file mode 100755 index 000000000..f814cb32f --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.sh @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# PlanAhead(TM) +# runme.sh: a PlanAhead-generated Runs Script for UNIX +# Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/opt/Xilinx/14.4/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.4/ISE_DS/common/bin/lin64:/opt/Xilinx/14.4/ISE_DS/PlanAhead/bin +else + PATH=/opt/Xilinx/14.4/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.4/ISE_DS/common/bin/lin64:/opt/Xilinx/14.4/ISE_DS/PlanAhead/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH=/opt/Xilinx/14.4/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.4/ISE_DS/common/lib/lin64 +else + LD_LIBRARY_PATH=/opt/Xilinx/14.4/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.4/ISE_DS/common/lib/lin64:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD=`dirname "$0"` +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep ngdbuild -intstyle ise -p xc6slx75fgg484-3 -dd _ngo -uc "b200.ucf" "b200.edf" +EAStep map -intstyle pa -w "b200.ngd" +EAStep par -intstyle pa "b200.ncd" -w "b200_routed.ncd" +EAStep trce -intstyle ise -o "b200.twr" -v 30 -l 30 "b200_routed.ncd" "b200.pcf" +EAStep xdl -secure -ncd2xdl -nopips "b200_routed.ncd" "b200_routed.xdl" diff --git a/fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/b200.ucf b/fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/b200.ucf new file mode 100644 index 000000000..75ffef7f3 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/b200.ucf @@ -0,0 +1,241 @@ +## SPI Nets + +NET "cat_ce" LOC = "Y1" | IOSTANDARD = LVCMOS18; +NET "cat_miso" LOC = "V1" | IOSTANDARD = LVCMOS18; +NET "cat_mosi" LOC = "T4" | IOSTANDARD = LVCMOS18; +NET "cat_sclk" LOC = "P7" | IOSTANDARD = LVCMOS18; + +NET "fx3_ce" LOC = "H20" ; +NET "fx3_miso" LOC = "G20" ; +NET "fx3_mosi" LOC = "AA20" ; +NET "fx3_sclk" LOC = "Y21" ; + +NET "pll_ce" LOC = "W11" ; +NET "pll_mosi" LOC = "AB11" ; +NET "pll_sclk" LOC = "Y12" ; + +NET "FPGA_RXD0" LOC = "AB8" ; +NET "FPGA_TXD0" LOC = "AB7" ; + +NET "SCL_FPGA" LOC = "P21" ; +NET "SDA_FPGA" LOC = "W22" ; + +## Catalina Controls + +NET "codec_enable" LOC = "J6" | IOSTANDARD = LVCMOS18; +NET "codec_en_agc" LOC = "P6" | IOSTANDARD = LVCMOS18; +NET "codec_reset" LOC = "Y2" | IOSTANDARD = LVCMOS18; +NET "codec_sync" LOC = "M3" | IOSTANDARD = LVCMOS18; +NET "codec_txrx" LOC = "M7" | IOSTANDARD = LVCMOS18; + +NET "codec_ctrl_in<0>" LOC = "E3" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in<1>" LOC = "F2" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in<2>" LOC = "F1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in<3>" LOC = "E1" | IOSTANDARD = LVCMOS18; + +NET "codec_ctrl_out<0>" LOC = "D1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<1>" LOC = "C1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<2>" LOC = "H3" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<3>" LOC = "F3" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<4>" LOC = "P1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<5>" LOC = "J1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<6>" LOC = "B1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<7>" LOC = "H2" | IOSTANDARD = LVCMOS18; + +## Catalina Data RX + +NET "rx_codec_d<0>" LOC = "T2" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<1>" LOC = "R1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<2>" LOC = "V2" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<3>" LOC = "N1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<4>" LOC = "V3" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<5>" LOC = "T1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<6>" LOC = "W1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<7>" LOC = "U1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<8>" LOC = "W3" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<9>" LOC = "U3" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<10>" LOC = "P2" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<11>" LOC = "R3" | IOSTANDARD = LVCMOS18 | DRIVE = 4; + +## Catalina Data TX + +NET "tx_codec_d<0>" LOC = "M1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<1>" LOC = "K1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<2>" LOC = "L3" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<3>" LOC = "K2" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<4>" LOC = "M4" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<5>" LOC = "J4" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<6>" LOC = "L4" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<7>" LOC = "H1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<8>" LOC = "M2" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<9>" LOC = "G1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<10>" LOC = "N3" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<11>" LOC = "G3" | IOSTANDARD = LVCMOS18 | DRIVE = 4; + +## Catalina Clocks + +NET "cat_clkout_fpga" LOC = "J3" | IOSTANDARD = LVCMOS18; +NET "codec_data_clk_p" LOC = "K3" | IOSTANDARD = LVCMOS18; +NET "codec_fb_clk_p" LOC = "P3" | IOSTANDARD = LVCMOS18; +NET "codec_main_clk_p" LOC = "K5" ;# | IOSTANDARD = LVCMOS18; +NET "codec_main_clk_n" LOC = "K4" ;# | IOSTANDARD = LVCMOS18; + +NET "rx_frame_p" LOC = "U4" | IOSTANDARD = LVCMOS18; +NET "tx_frame_p" LOC = "T3" | IOSTANDARD = LVCMOS18; + +## Debug Bus + +NET "debug<0>" LOC = "C14" ; +NET "debug<1>" LOC = "F15" ; +NET "debug<2>" LOC = "A18" ; +NET "debug<3>" LOC = "A17" ; +NET "debug<4>" LOC = "E14" ; +NET "debug<5>" LOC = "G13" ; +NET "debug<6>" LOC = "D13" ; +NET "debug<7>" LOC = "F13" ; +NET "debug<8>" LOC = "D8" ; +NET "debug<9>" LOC = "A6" ; +NET "debug<10>" LOC = "D7" ; +NET "debug<11>" LOC = "A5" ; +NET "debug<12>" LOC = "B6" ; +NET "debug<13>" LOC = "A3" ; +NET "debug<14>" LOC = "A7" ; +NET "debug<15>" LOC = "A8" ; +NET "debug<16>" LOC = "B18" ; +NET "debug<17>" LOC = "C17" ; +NET "debug<18>" LOC = "H13" ; +NET "debug<19>" LOC = "D12" ; +NET "debug<20>" LOC = "H14" ; +NET "debug<21>" LOC = "C10" ; +NET "debug<22>" LOC = "D10" ; +NET "debug<23>" LOC = "C8" ; +NET "debug<24>" LOC = "D9" ; +NET "debug<25>" LOC = "C5" ; +NET "debug<26>" LOC = "A9" ; +NET "debug<27>" LOC = "B8" ; +NET "debug<28>" LOC = "A4" ; +NET "debug<29>" LOC = "C7" ; +NET "debug<30>" LOC = "C6" ; +NET "debug<31>" LOC = "D6" ; + +NET "debug_clk<0>" LOC = "A12" ; +NET "debug_clk<1>" LOC = "C12" ; + +## GPIF + +NET "IFCLK" LOC = "H21" ; +NET "FX3_EXTINT" LOC = "U20" ; + +NET "GPIF_CTL0" LOC = "V20" ; +NET "GPIF_CTL1" LOC = "T22" ; +NET "GPIF_CTL2" LOC = "R22" ; +NET "GPIF_CTL3" LOC = "U22" ; +NET "GPIF_CTL4" LOC = "P19" ; +NET "GPIF_CTL5" LOC = "N22" ; +NET "GPIF_CTL6" LOC = "T21" ; +NET "GPIF_CTL7" LOC = "V21" ; +NET "GPIF_CTL8" LOC = "K18" ; +NET "GPIF_CTL9" LOC = "R20" ; +##GPIF_CTL10 is "FPGA_CFG_DONE", defined later. +NET "GPIF_CTL11" LOC = "P22" ; +NET "GPIF_CTL12" LOC = "M20" ; + +NET "GPIF_D<0>" LOC = "T17" ; +NET "GPIF_D<1>" LOC = "U14" ; +NET "GPIF_D<2>" LOC = "U13" ; +NET "GPIF_D<3>" LOC = "AA6" ; +NET "GPIF_D<4>" LOC = "AB6" ; +NET "GPIF_D<5>" LOC = "Y3" ; +NET "GPIF_D<6>" LOC = "AB3" ; +NET "GPIF_D<7>" LOC = "AA4" ; +NET "GPIF_D<8>" LOC = "AA2" ; +NET "GPIF_D<9>" LOC = "AB2" ; +NET "GPIF_D<10>" LOC = "AB19" ; +NET "GPIF_D<11>" LOC = "AA18" ; +NET "GPIF_D<12>" LOC = "AB18" ; +NET "GPIF_D<13>" LOC = "Y13" ; +NET "GPIF_D<14>" LOC = "AA12" ; +NET "GPIF_D<15>" LOC = "AB12" ; +NET "GPIF_D<16>" LOC = "N20" ; +NET "GPIF_D<17>" LOC = "L20" ; +NET "GPIF_D<18>" LOC = "N19" ; +NET "GPIF_D<19>" LOC = "M22" ; +NET "GPIF_D<20>" LOC = "L19" ; +NET "GPIF_D<21>" LOC = "M21" ; +NET "GPIF_D<22>" LOC = "M19" ; +NET "GPIF_D<23>" LOC = "K22" ; +NET "GPIF_D<24>" LOC = "J20" ; +NET "GPIF_D<25>" LOC = "L22" ; +NET "GPIF_D<26>" LOC = "K19" ; +NET "GPIF_D<27>" LOC = "H22" ; +NET "GPIF_D<28>" LOC = "J22" ; +NET "GPIF_D<29>" LOC = "K20" ; +NET "GPIF_D<30>" LOC = "G22" ; +NET "GPIF_D<31>" LOC = "F22" ; + +## GPS + +NET "gps_lock" LOC = "Y17" ; +NET "gps_out_enable" LOC = "V22" ; +NET "gps_ref_enable" LOC = "AB13" ; +NET "gps_rxd" LOC = "AB14" ; +NET "gps_txd" LOC = "W12" ; +NET "gps_txd_nmea" LOC = "AA14" ; + +## LEDS + +NET "LED_RX1" LOC = "C22" ; +NET "LED_RX2" LOC = "L15" ; +NET "LED_TXRX1_TX" LOC = "C20" ; +NET "LED_TXRX2_RX" LOC = "D21" ; +NET "LED_TXRX1_RX" LOC = "K16" ; +NET "LED_TXRX2_TX" LOC = "D22" ; + +## Misc Hardware Control + +NET "ext_ref_enable" LOC = "Y15" ; +NET "pll_lock" LOC = "AB10" ; +NET "AUX_PWR_ON" LOC = "AA21" ; +#NET "RFUSE" LOC = "P15" ; + +## PPS + +NET "pps_fpga_out_enable" LOC = "AB15" ; +NET "PPS_IN_EXT" LOC = "AB16" ; +NET "PPS_IN_INT" LOC = "AB21" ; +NET "pps_out" LOC = "AB17" ; + +## RF Hardware Control + +NET "SFDX1_RX" LOC = "W4" ; +NET "SFDX1_TX" LOC = "T18" ; +NET "SFDX2_RX" LOC = "F18" ; +NET "SFDX2_TX" LOC = "H17" ; +NET "SRX1_RX" LOC = "Y7" ; +NET "SRX1_TX" LOC = "AA8" ; +NET "SRX2_RX" LOC = "J17" ; +NET "SRX2_TX" LOC = "F19" ; +NET "tx_bandsel_a" LOC = "N16" ; +NET "tx_bandsel_b" LOC = "M16" ; +NET "tx_enable1" LOC = "Y4" ; +NET "tx_enable2" LOC = "R19" ; +NET "rx_bandsel_a" LOC = "T20" ; +NET "rx_bandsel_b" LOC = "U19" ; +NET "rx_bandsel_c" LOC = "P20" ; + +## FPGA Config Pins + +#NET "FPGA_CFG_INIT_B" LOC = "T6" ; +#NET "FPGA_CFG_DONE" LOC = "Y22" ; +#NET "FPGA_CFG_M0" LOC = "AA22" ; +#NET "FPGA_CFG_M1" LOC = "U15" ; +#NET "FPGA_CFG_PROG_B" LOC = "AA1" ; + +## Special Pins + +#NET "VFS" LOC = "P16" ; +#NET "TMS" LOC = "C18" ; +#NET "TDO" LOC = "A19" ; +#NET "TDI" LOC = "E18" ; +#NET "TCK" LOC = "G15" ; +#NET "GND" LOC = "N15" ; diff --git a/fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/timing.ucf b/fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/timing.ucf new file mode 100644 index 000000000..82d68aceb --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/timing.ucf @@ -0,0 +1,44 @@ + +# codec_main_clk is 40 MHz main tcxo clock +NET "codec_main_clk*" TNM_NET = "codec_main_clk"; +TIMESPEC "TS_codec_main_clk" = PERIOD "codec_main_clk" 25000 ps HIGH 50 %; + + +# IFCLK is 100 MHz GPIF clock +NET "IFCLK" TNM_NET = "IFCLK"; +TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 10000 ps HIGH 50 %; + + +# codec_data_clk is the data clock from catalina, sample rate dependent +# this clock equals sample rate in CMOS DDR 1R1T mode +# this clock is double the sample rate in CMOS DDR 2R2T mode +# Max clock rate is 61.44 MHz +NET "codec_data_clk_p" TNM_NET = "codec_data_clk_p"; +TIMESPEC "TS_codec_data_clk_p" = PERIOD "codec_data_clk_p" 16276 ps HIGH 50 %; + + +#always use IOB for GPIF pins for awesome timing +INST "GPIF_*" IOB = TRUE; + +# TODO not working... constraints ignored + +#constrain FX3 IO +INST "GPIF_D<*>" TNM = gpif_net_out; +INST "GPIF_D<*>" TNM = gpif_net_in; +INST "GPIF_CTL0" TNM = gpif_net_out; +INST "GPIF_CTL1" TNM = gpif_net_out; +INST "GPIF_CTL2" TNM = gpif_net_out; +INST "GPIF_CTL3" TNM = gpif_net_out; +INST "GPIF_CTL4" TNM = gpif_net_in; +INST "GPIF_CTL5" TNM = gpif_net_in; +INST "GPIF_CTL6" TNM = gpif_net_in; +INST "GPIF_CTL7" TNM = gpif_net_out; +INST "GPIF_CTL8" TNM = gpif_net_in; +INST "GPIF_CTL11" TNM = gpif_net_out; +INST "GPIF_CTL12" TNM = gpif_net_out; + +#NET "gpif_clk" TNM_NET = "TNM_gpif_clk"; +#OFFSET = OUT 5 ns AFTER "gpif_clk"; +#TIMESPEC "TS_gpif_clk" = PERIOD "TNM_gpif_clk" 10000 ps HIGH 50 %; +#TIMEGRP "gpif_net_in" OFFSET = IN 6 ns VALID 6 ns BEFORE "gpif_clk" RISING; +#TIMEGRP "gpif_net_out" OFFSET = OUT 6 ns AFTER "gpif_clk" RISING; diff --git a/fpga/usrp3/top/b200/planahead/planahead.srcs/sources_1/imports/coregen/fifo_4k_2clk.ngc b/fpga/usrp3/top/b200/planahead/planahead.srcs/sources_1/imports/coregen/fifo_4k_2clk.ngc new file mode 100644 index 000000000..b379066c6 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.srcs/sources_1/imports/coregen/fifo_4k_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/sim/b200_io_tb.v b/fpga/usrp3/top/b200/sim/b200_io_tb.v new file mode 100644 index 000000000..647612a2d --- /dev/null +++ b/fpga/usrp3/top/b200/sim/b200_io_tb.v @@ -0,0 +1,155 @@ +`timescale 1ns/1ps + + module b200_io_tb(); + + // + // Xilinx Mandatory Simulation Primitive for global signals. + // + wire GSR, GTS; + glbl glbl( ); + + // + // Test bench declarations + // + reg [7:0] count; + wire [11:0] i0 = {4'hA,count}; + wire [11:0] q0 = {4'hB,count}; + wire [11:0] i1 = {4'hC,count}; + wire [11:0] q1 = {4'hD,count}; + reg tb_clk = 0; + + // RX sample bus. + reg rx_clk = 0; // Simulated clock from AD9361 for RX sample interface, radio_clk derived from this. + reg rx_frame; + reg [11:0] rx_data; + // TX sample bus. + wire tx_clk; + wire tx_frame; + wire [11:0] tx_data; + // Internal FPGA interface(s) + reg reset = 1; + wire radio_clk; + reg mimo; + wire [11:0] rx_i0, rx_q0, rx_i1, rx_q1; + reg [11:0] tx_i0, tx_q0, tx_i1, tx_q1; + + + // Set tb_clk to 100MHz. + // rx_clk is half the frequency of tb_clk, and tb_clk posedges are miday between edges on the rx_clk + always #10 tb_clk = ~tb_clk; + always @(negedge tb_clk) rx_clk <= ~rx_clk; + + + b200_io dut + ( + .reset(reset), + .mimo(mimo), + + // Baseband sample interface + .radio_clk(radio_clk), + .rx_i0(rx_i0), + .rx_q0(rx_q0), + .rx_i1(rx_i1), + .rx_q1(rx_q1), + .tx_i0(tx_i0), + .tx_q0(tx_q0), + .tx_i1(tx_i1), + .tx_q1(tx_q1), + + // Catalina interface + .rx_clk(rx_clk), + .rx_frame(rx_frame), + .rx_data(rx_data), + .tx_clk(tx_clk), + .tx_frame(tx_frame), + .tx_data(tx_data) + ); + + // Internal Loopback Rx -> Tx. + always @(posedge radio_clk) + begin + tx_i0 <= rx_i0; + tx_q0 <= rx_q0; + tx_i1 <= rx_i1; + tx_q1 <= rx_q1; + end + + // + // Task's for stimulus + // + + task siso_burst; + input [7:0] len; + begin + rx_frame <= 0; + mimo <= 0; + count <= 0; + // Now give configuration a chance to perculate + @(posedge rx_clk); + @(posedge rx_clk); + @(posedge rx_clk); + @(posedge rx_clk); + // Now entering main stimulus loop just after rising edge of rx_clk + repeat(len) + begin + // Drive I data so that it surrounds a falling edge on rx_clk + @(posedge tb_clk); + rx_data <= i0; + rx_frame <= 1; + // Drive Q data so that it surrounds a rising edge on rx_clk + @(posedge tb_clk); + rx_data <= q0; + rx_frame <= 0; + // Increment test data pattern + count <= count + 1; + end // repeat (len) + @(posedge rx_clk); + @(posedge rx_clk); + end + + endtask // BURST + + + task mimo_burst; + input [7:0] len; + begin + rx_frame <= 0; + mimo <= 1; + count <= 0; + // Now give configuration a chance to perculate + @(posedge rx_clk); + @(posedge rx_clk); + @(posedge rx_clk); + @(posedge rx_clk); + // Now entering main stimulus loop just after rising edge of rx_clk + repeat(len) + // REMEMBER! B210 PCB markings for radio channels are swapped w.r.t AD9361's channels. + // "Ch0" as indicated here is "Ch1" inside AD9361 + begin + // Drive I data for Ch1 so that it surrounds a falling edge on rx_clk + @(posedge tb_clk); + rx_data <= i1; + rx_frame <= 1; + // Drive Q data for Ch1 so that it surrounds a rising edge on rx_clk + @(posedge tb_clk); + rx_data <= q1; + // Drive I data for Ch0 so that it surrounds a falling edge on rx_clk + @(posedge tb_clk); + rx_data <= i0; + rx_frame <= 0; + // Drive Q data for Ch0 so that it surrounds a rising edge on rx_clk + @(posedge tb_clk); + rx_data <= q0; + // Increment test data pattern + count <= count + 1; + end + @(posedge rx_clk); + @(posedge rx_clk); + end + endtask // MIMO_BURST + + // Pull in local simulation script here. +`include "simulation_script.v" + + +endmodule // b200_io_tb diff --git a/fpga/usrp3/top/b200/sim/b200_tb.v b/fpga/usrp3/top/b200/sim/b200_tb.v new file mode 100644 index 000000000..62037ba94 --- /dev/null +++ b/fpga/usrp3/top/b200/sim/b200_tb.v @@ -0,0 +1,213 @@ +module b200_tb (); + + wire cat_ce; + wire cat_miso; + wire cat_mosi; + wire cat_sclk; + + wire fx3_ce; + wire fx3_miso; + wire fx3_mosi; + wire fx3_sclk; + + wire pll_ce; + wire pll_mosi; + wire pll_sclk; + + // UART + wire FPGA_RXD0; + wire FPGA_TXD0; + + // Catalina Controls + wire codec_enable; + wire codec_en_agc; + wire codec_reset; + wire codec_sync; + wire codec_txrx; + wire [3:0] codec_ctrl_in; // These should be outputs + wire [7:0] codec_ctrl_out; // MUST BE INPUT + + // Catalina Data + wire codec_data_clk_p; // Clock from CAT (RX) + wire codec_fb_clk_p; // Clock to CAT (TX) + wire [11:0] rx_codec_d; + wire [11:0] tx_codec_d; + wire rx_frame_p; + wire tx_frame_p; + + wire cat_clkout_fpga; + + //always on 40MHz clock + wire codec_main_clk_p; + wire codec_main_clk_n; + + // Debug Bus + wire [31:0] debug; + wire [1:0] debug_clk; + + // GPIF; FX3 Slave FIFO + wire IFCLK; // pclk + wire FX3_EXTINT; + wire GPIF_CTL0; // n_slcs + wire GPIF_CTL1; // n_slwr + wire GPIF_CTL2; // n_sloe + wire GPIF_CTL3; // n_slrd + wire GPIF_CTL7; // n_pktend + wire GPIF_CTL4; // slfifo_flags[0] + wire GPIF_CTL5; // slfifo_flags[1] + wire GPIF_CTL6; // slfifo_flags[2] + wire GPIF_CTL8; // slfifo_flags[3] + wire GPIF_CTL11; // slfifo_addr[1] + wire GPIF_CTL12; // slfifo_addr[0] + wire [31:0] GPIF_D; + wire GPIF_CTL9; // global_reset + + // GPS + wire gps_lock; + wire gps_rxd; + wire gps_txd; + wire gps_txd_nmea; + + // LEDS + wire LED_RX1; + wire LED_RX2; + wire LED_TXRX1_RX; + wire LED_TXRX1_TX; + wire LED_TXRX2_RX; + wire LED_TXRX2_TX; + + // Misc Hardware Control + wire ref_sel; + wire pll_lock; + wire FPGA_CFG_CS; // Driven by FX3 gpio. + wire AUX_PWR_ON; // Driven by FX3 gpio. + + // PPS + wire PPS_IN_EXT; + wire PPS_IN_INT; + + // RF Hardware Control + wire SFDX1_RX; + wire SFDX1_TX; + wire SFDX2_RX; + wire SFDX2_TX; + wire SRX1_RX; + wire SRX1_TX; + wire SRX2_RX; + wire SRX2_TX; + wire tx_bandsel_a; + wire tx_bandsel_b; + wire tx_enable1; + wire tx_enable2; + wire rx_bandsel_a; + wire rx_bandsel_b; + wire rx_bandsel_c; + + + b200 b200_i1( + // SPI Interfaces + .cat_ce(), + .cat_miso(), + .cat_mosi(), + .cat_sclk(), + + .fx3_ce(), + .fx3_miso(), + .fx3_mosi(), + .fx3_sclk(), + + .pll_ce(), + .pll_mosi(), + .pll_sclk(), + + // UART + .FPGA_RXD0(), + .FPGA_TXD0(), + + // Catalina Controls + .codec_enable(), + .codec_en_agc(), + .codec_reset(), + .codec_sync(), + .codec_txrx(), + .codec_ctrl_in(), // These should be outputs + .codec_ctrl_out(), // MUST BE INPUT + + // Catalina Data + .codec_data_clk_p(), // Clock from CAT (RX) + .codec_fb_clk_p(), // Clock to CAT (TX) + .rx_codec_d(), + .tx_codec_d(), + .rx_frame_p(), + .tx_frame_p(), + + .cat_clkout_fpga(), + + //always on 40MHz clock + .codec_main_clk_p(), + .codec_main_clk_n(), + + // Debug Bus + .debug(), + .debug_clk(), + + // GPIF, FX3 Slave FIFO + .IFCLK(), // pclk + .FX3_EXTINT(), + .GPIF_CTL0(), // n_slcs + .GPIF_CTL1(), // n_slwr + .GPIF_CTL2(), // n_sloe + .GPIF_CTL3(), // n_slrd + .GPIF_CTL7(), // n_pktend + .GPIF_CTL4(), // slfifo_flags[0] + .GPIF_CTL5(), // slfifo_flags[1] + .GPIF_CTL6(), // slfifo_flags[2] + .GPIF_CTL8(), // slfifo_flags[3] + .GPIF_CTL11(), // slfifo_addr[1] + .GPIF_CTL12(), // slfifo_addr[0] + .GPIF_D(), + .GPIF_CTL9(), // global_reset + + // GPS + .gps_lock(), + .gps_rxd(), + .gps_txd(), + .gps_txd_nmea(), + + // LEDS + .LED_RX1(), + .LED_RX2(), + .LED_TXRX1_RX(), + .LED_TXRX1_TX(), + .LED_TXRX2_RX(), + .LED_TXRX2_TX(), + + // Misc Hardware Control + .ref_sel(), + .pll_lock(), + .FPGA_CFG_CS(), // Driven by FX3 gpio. + .AUX_PWR_ON(), // Driven by FX3 gpio. + + // PPS + .PPS_IN_EXT(), + .PPS_IN_INT(), + + // RF Hardware Control + .SFDX1_RX(), + .SFDX1_TX(), + .SFDX2_RX(), + .SFDX2_TX(), + .SRX1_RX(), + .SRX1_TX(), + .SRX2_RX(), + .SRX2_TX(), + .tx_bandsel_a(), + .tx_bandsel_b(), + .tx_enable1(), + .tx_enable2(), + .rx_bandsel_a(), + .rx_bandsel_b(), + .rx_bandsel_c() + ); + +endmodule // b200_tb diff --git a/fpga/usrp3/top/b200/sim/b2x0/sim_b2x0_1/run_isim b/fpga/usrp3/top/b200/sim/b2x0/sim_b2x0_1/run_isim new file mode 100755 index 000000000..dd9215934 --- /dev/null +++ b/fpga/usrp3/top/b200/sim/b2x0/sim_b2x0_1/run_isim @@ -0,0 +1,22 @@ +vlogcomp -work work ${XILINX}/verilog/src/glbl.v + +vlogcomp -work work --sourcelibext .v \ + --sourcelibdir ../../../lib/axi \ + --sourcelibdir ../../../lib/fifo \ + --sourcelibdir ../../../lib/control \ + --sourcelibdir ../../../top/b200/coregen \ + --sourcelibdir ../../../top/b200 \ + --sourcelibdir ../../../lib/timing \ + --sourcelibdir ../../../lib/vita \ + --sourcelibdir ../../../lib/packet_proc \ + --sourcelibdir ../../../lib/dsp \ + --sourcelibdir ../../../lib/wishbone \ + --sourcelibdir ../../../lib/gpif2 \ + ../../../top/b200/b200_tb.v + + + +fuse work.b200_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o b200_tb.exe + +# run the simulation scrip +./b200_tb.exe # -gui #-tclbatch simcmds.tcl diff --git a/fpga/usrp3/top/b200/sim/sim_b200_io/mimo/mimo.wcfg b/fpga/usrp3/top/b200/sim/sim_b200_io/mimo/mimo.wcfg new file mode 100644 index 000000000..4ecabdecf --- /dev/null +++ b/fpga/usrp3/top/b200/sim/sim_b200_io/mimo/mimo.wcfg @@ -0,0 +1,112 @@ + + + + + + + + + + + + + + + Test Bench + label + + tb_clk + tb_clk + + + reset + reset + + + mimo + mimo + + + + RX + label + + rx_clk + rx_clk + + + rx_frame + rx_frame + + + rx_data[11:0] + rx_data[11:0] + HEXRADIX + + + + TX + label + + tx_clk + tx_clk + + + tx_frame + tx_frame + + + tx_data[11:0] + tx_data[11:0] + HEXRADIX + + + + Internal + label + + radio_clk + radio_clk + + + rx_i0[11:0] + rx_i0[11:0] + HEXRADIX + + + rx_q0[11:0] + rx_q0[11:0] + HEXRADIX + + + rx_i1[11:0] + rx_i1[11:0] + HEXRADIX + + + rx_q1[11:0] + rx_q1[11:0] + HEXRADIX + + + tx_i0[11:0] + tx_i0[11:0] + HEXRADIX + + + tx_q0[11:0] + tx_q0[11:0] + HEXRADIX + + + tx_i1[11:0] + tx_i1[11:0] + HEXRADIX + + + tx_q1[11:0] + tx_q1[11:0] + HEXRADIX + + + diff --git a/fpga/usrp3/top/b200/sim/sim_b200_io/mimo/simulation_script.v b/fpga/usrp3/top/b200/sim/sim_b200_io/mimo/simulation_script.v new file mode 100644 index 000000000..04e9079e1 --- /dev/null +++ b/fpga/usrp3/top/b200/sim/sim_b200_io/mimo/simulation_script.v @@ -0,0 +1,14 @@ + + initial + begin + reset <= 1; + mimo <= 0; + repeat(10) @(posedge rx_clk); + reset <= 0; + + repeat(10) @(posedge rx_clk); + + mimo_burst(20); + repeat(10) @(posedge rx_clk); + $finish; + end diff --git a/fpga/usrp3/top/b200/sim/sim_b200_io/run_isim b/fpga/usrp3/top/b200/sim/sim_b200_io/run_isim new file mode 100755 index 000000000..dc0ec02b7 --- /dev/null +++ b/fpga/usrp3/top/b200/sim/sim_b200_io/run_isim @@ -0,0 +1,22 @@ +vlogcomp -work work ${XILINX}/verilog/src/glbl.v + +# usrp3/top/b200/sim/sim_b200_io/siso +vlogcomp -work work --sourcelibext .v \ + --sourcelibdir ../../../../../lib/axi \ + --sourcelibdir ../../../../../lib/fifo \ + --sourcelibdir ../../../../../lib/control \ + --sourcelibdir ../../../coregen \ + --sourcelibdir ../../../ \ + --sourcelibdir ../../../../../lib/timing \ + --sourcelibdir ../../../../../lib/vita \ + --sourcelibdir ../../../../../lib/packet_proc \ + --sourcelibdir ../../../../../lib/dsp \ + --sourcelibdir ../../../../../lib/wishbone \ + --sourcelibdir ../../../../../lib/gpif2 \ + --sourcelibdir ../../../../../lib/io \ + ../../b200_io_tb.v + +fuse work.b200_io_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o b200_io_tb.exe + +# run the simulation scrip +./b200_io_tb.exe -gui #-tclbatch simcmds.tcl diff --git a/fpga/usrp3/top/b200/sim/sim_b200_io/siso/simulation_script.v b/fpga/usrp3/top/b200/sim/sim_b200_io/siso/simulation_script.v new file mode 100644 index 000000000..ad2e7fc57 --- /dev/null +++ b/fpga/usrp3/top/b200/sim/sim_b200_io/siso/simulation_script.v @@ -0,0 +1,13 @@ + + initial + begin + reset <= 1; + mimo <= 0; + repeat(10) @(posedge rx_clk); + reset <= 0; + repeat(10) @(posedge rx_clk); + + siso_burst(20); + repeat(10) @(posedge rx_clk); + $finish; + end diff --git a/fpga/usrp3/top/b200/sim/sim_b200_io/siso/siso.wcfg b/fpga/usrp3/top/b200/sim/sim_b200_io/siso/siso.wcfg new file mode 100644 index 000000000..7ef57498f --- /dev/null +++ b/fpga/usrp3/top/b200/sim/sim_b200_io/siso/siso.wcfg @@ -0,0 +1,64 @@ + + + + + + + + + + + + + + + Test Bench + label + + tb_clk + tb_clk + + + reset + reset + + + mimo + mimo + + + + RX + label + + rx_clk + rx_clk + + + rx_frame + rx_frame + + + rx_data[11:0] + rx_data[11:0] + HEXRADIX + + + + TX + label + + tx_clk + tx_clk + + + tx_frame + tx_frame + + + tx_data[11:0] + tx_data[11:0] + HEXRADIX + + + diff --git a/fpga/usrp3/top/b200/timing.ucf b/fpga/usrp3/top/b200/timing.ucf new file mode 100644 index 000000000..6264449da --- /dev/null +++ b/fpga/usrp3/top/b200/timing.ucf @@ -0,0 +1,46 @@ + +# codec_main_clk is 40 MHz main tcxo clock +NET "codec_main_clk*" TNM_NET = "codec_main_clk"; +TIMESPEC "TS_codec_main_clk" = PERIOD "codec_main_clk" 25000 ps HIGH 50 %; + + +# IFCLK is 100 MHz GPIF clock +NET "IFCLK" TNM_NET = "IFCLK"; +TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 10000 ps HIGH 50 %; + + +# codec_data_clk is the data clock from catalina, sample rate dependent +# this clock equals sample rate in CMOS DDR 1R1T mode +# this clock is double the sample rate in CMOS DDR 2R2T mode +# Max clock rate is 61.44 MHz +NET "codec_data_clk_p" TNM_NET = "codec_data_clk_p"; +TIMESPEC "TS_codec_data_clk_p" = PERIOD "codec_data_clk_p" 16276 ps HIGH 50 %; + +#always use IOB for GPIF pins for awesome timing +INST "GPIF_*" IOB = TRUE; + +#low speed misc output group +INST "SFDX*" TNM = radio_misc_out; # Radio Clk domain +INST "SRX*" TNM = radio_misc_out; # Radio Clk domain +INST "LED_*" TNM = radio_misc_out; # Radio Clk domain +INST "tx_enable*" TNM = radio_misc_out; # Radio Clk domain +INST "tx_bandsel_*" TNM = ls_misc_out; # Bus clk domain +INST "rx_bandsel_*" TNM = ls_misc_out; # Bus clk domain +INST "ref_sel" TNM = ls_misc_out; # Bus clk domain +INST "pll_ce" TNM = ls_misc_out; # Bus clk domain +INST "cat_ce" TNM = ls_misc_out; # Bus clk domain + combinatorial +#INST "fx3_miso" TNM = ls_misc_out; # Combinatorial +INST "cat_miso" TNM = ls_misc_out; # Bus clk domain (I) +INST "cat_mosi" TNM = ls_misc_out; # Bus clk domain + combinatorial +INST "pll_mosi" TNM = ls_misc_out; # Bus clk domain + combinatorial +INST "*_sclk" TNM = ls_misc_out; # Bus clk domain + combinatorial +INST "gps_*" TNM = ls_misc_out; # Bus clk domain +#INST "FPGA_*D0" TNM = ls_misc_out; # UNUSED + +#constrain the misc IOs to the clocks +NET "gpif_clk" TNM_NET = "gpif_clk"; +TIMESPEC "TS_gpif_clk" = PERIOD "gpif_clk" 10 ns HIGH 50 %; +# These next 2 constarints have never worked...either fix them or remove them. Probably need a virtual clock to make them work. +#TIMEGRP "ls_misc_out" OFFSET = OUT 15 ns AFTER "gpif_clk" RISING; +#TIMEGRP "radio_misc_out" OFFSET = OUT 15 ns AFTER "radio_clk" RISING; + -- cgit v1.2.3