From ff1546f8137f7f92bb250f685561b0c34cc0e053 Mon Sep 17 00:00:00 2001
From: Ben Hilburn <ben.hilburn@ettus.com>
Date: Fri, 14 Feb 2014 12:05:07 -0800
Subject: Pushing the bulk of UHD-3.7.0 code.

---
 fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'fpga/usrp3/top/b200/coregen')

diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise
index 8f58b6783..3bc65beca 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise
@@ -17,11 +17,11 @@
   <files>
     <file xil_pn:name="chipscope_ila_128.ngc" xil_pn:type="FILE_NGC">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="chipscope_ila_128.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
-- 
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