From b63507efb3cf1a8fa20794c452d57028e18da182 Mon Sep 17 00:00:00 2001
From: Ben Hilburn <ben.hilburn@ettus.com>
Date: Tue, 22 Jul 2014 15:49:02 -0700
Subject: fpga: Updating FPGA code for UHD-3.7.2-rc1

---
 fpga/usrp3/top/b200/coregen/chipscope_icon.gise    | 2 +-
 fpga/usrp3/top/b200/coregen/chipscope_icon.xise    | 4 ++--
 fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise | 2 +-
 fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise | 4 ++--
 fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise | 2 +-
 fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise | 4 ++--
 fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise  | 2 +-
 fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise  | 4 ++--
 fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise      | 2 +-
 fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xise      | 4 ++--
 fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise   | 2 +-
 fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise   | 4 ++--
 12 files changed, 18 insertions(+), 18 deletions(-)

(limited to 'fpga/usrp3/top/b200/coregen')

diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.gise b/fpga/usrp3/top/b200/coregen/chipscope_icon.gise
index a4f878755..29d14a154 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_icon.gise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.xise b/fpga/usrp3/top/b200/coregen/chipscope_icon.xise
index 669cbf101..5cb07142c 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_icon.xise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="chipscope_icon.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise
index 3af396d70..8f50adfb5 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise
index 3bc65beca..d89d10530 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="chipscope_ila_128.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise
index 6305e6288..85cc00a94 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise
index f8c51bac1..a9e75da04 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="chipscope_ila_256.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise
index 4bc01d034..e5487e74a 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise
index 9a9fb9459..8d210d750 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="chipscope_ila_32.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise
index c631a4815..ae7343223 100644
--- a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xise b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xise
index 2d8132c10..951b199cf 100644
--- a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xise
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="fifo_4k_2clk.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise
index ea47d0f4b..ddb581fc1 100644
--- a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise
index 1ca7d35ee..1f72b185a 100644
--- a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="fifo_short_2clk.ngc" xil_pn:type="FILE_NGC">
-- 
cgit v1.2.3