From fd3e84941de463fa1a7ebab0a69515b4bf2614cd Mon Sep 17 00:00:00 2001
From: Martin Braun <martin.braun@ettus.com>
Date: Tue, 7 Oct 2014 11:25:20 +0200
Subject: Removed copy of FPGA source files.

---
 fpga/usrp3/top/b200/catgen_tb.build | 21 ---------------------
 1 file changed, 21 deletions(-)
 delete mode 100755 fpga/usrp3/top/b200/catgen_tb.build

(limited to 'fpga/usrp3/top/b200/catgen_tb.build')

diff --git a/fpga/usrp3/top/b200/catgen_tb.build b/fpga/usrp3/top/b200/catgen_tb.build
deleted file mode 100755
index 072495479..000000000
--- a/fpga/usrp3/top/b200/catgen_tb.build
+++ /dev/null
@@ -1,21 +0,0 @@
-
-#!/bin/sh
-
-rm -rf isim* 
-rm -rf catgen_tb
-rm -rf fuse*
-\
-#     --sourcelibdir ../../models \
-
-vlogcomp \
-    --sourcelibext .v \
-    --sourcelibdir ../../coregen \
-    --sourcelibdir ../../control_lib \
-    --sourcelibdir . \
-    --sourcelibdir $XILINX/verilog/src \
-    --sourcelibdir $XILINX/verilog/src/unisims \
-    --work work \
-    catgen_tb.v
-
- 
-fuse -o catgen_tb catgen_tb
\ No newline at end of file
-- 
cgit v1.2.3