From 0df4b801a34697f2058b4a7b95e08d2a0576c9db Mon Sep 17 00:00:00 2001 From: Ben Hilburn Date: Thu, 10 Oct 2013 10:17:27 -0700 Subject: Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus. --- fpga/usrp3/top/b200/catgen_tb.build | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100755 fpga/usrp3/top/b200/catgen_tb.build (limited to 'fpga/usrp3/top/b200/catgen_tb.build') diff --git a/fpga/usrp3/top/b200/catgen_tb.build b/fpga/usrp3/top/b200/catgen_tb.build new file mode 100755 index 000000000..072495479 --- /dev/null +++ b/fpga/usrp3/top/b200/catgen_tb.build @@ -0,0 +1,21 @@ + +#!/bin/sh + +rm -rf isim* +rm -rf catgen_tb +rm -rf fuse* +\ +# --sourcelibdir ../../models \ + +vlogcomp \ + --sourcelibext .v \ + --sourcelibdir ../../coregen \ + --sourcelibdir ../../control_lib \ + --sourcelibdir . \ + --sourcelibdir $XILINX/verilog/src \ + --sourcelibdir $XILINX/verilog/src/unisims \ + --work work \ + catgen_tb.v + + +fuse -o catgen_tb catgen_tb \ No newline at end of file -- cgit v1.2.3