From eed4988cc266a63370a4332351d02fadedde3a3b Mon Sep 17 00:00:00 2001 From: Andrew Moch Date: Thu, 25 Jun 2020 21:49:00 +0100 Subject: fpga: lib: Add width agnostic version of Ethernet Interface The rnfoc/xport section is refactored in System Verilog to allow the following improvements (1) CPU_W - Sets the size of the c2e and e2c pipes. This can be run at a different clock rate than the main ethernet pipe (2) CHDR_W - Sets the size of the v2e and e2v pipes. This can be run at a different clock rate than the main ethernet pipe (3) ENET_W - Sets the size of the eth_tx and eth_rx pipes. eth_interface_tb runs traffic from e2c,e2v,v2e,c2e simultaneously against the original xport_sv implementation, and against the new implementation with widths of 64/128/512. A chdr_management node info request queries the port info of the node0 in the eth_interface. eth_ifc_synth_test.sv can be compiled with the make xsim target to test out the size of various configurations. --- fpga/usrp3/tools/utils/testbenches.excludes | 1 + 1 file changed, 1 insertion(+) (limited to 'fpga/usrp3/tools/utils/testbenches.excludes') diff --git a/fpga/usrp3/tools/utils/testbenches.excludes b/fpga/usrp3/tools/utils/testbenches.excludes index 79c3bb557..771d8bff2 100644 --- a/fpga/usrp3/tools/utils/testbenches.excludes +++ b/fpga/usrp3/tools/utils/testbenches.excludes @@ -17,3 +17,4 @@ top/n3xx/dboards/eiscat/radio/noc_block_radio_core_eiscat_tb # These testbenches only work in ModelSim lib/axi4s_sv/axi4s_remove_bytes_tb lib/axi4s_sv/axi4s_add_bytes_tb +lib/rfnoc/xport_sv/eth_interface_tb -- cgit v1.2.3