From 5b3d66e5b7cedb7098de3e4dbbee70af04a3626e Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Fri, 15 May 2020 14:03:29 -0500 Subject: fpga: tools: Improve native ModelSim support This adds support for colored output and support for directories added to the list of source files (for HLS support). --- fpga/usrp3/tools/make/viv_simulator.mak | 110 +++++++++++--------------------- 1 file changed, 38 insertions(+), 72 deletions(-) (limited to 'fpga/usrp3/tools/make/viv_simulator.mak') diff --git a/fpga/usrp3/tools/make/viv_simulator.mak b/fpga/usrp3/tools/make/viv_simulator.mak index 41b58bf8c..5ced4ee32 100644 --- a/fpga/usrp3/tools/make/viv_simulator.mak +++ b/fpga/usrp3/tools/make/viv_simulator.mak @@ -14,7 +14,7 @@ SIM_FAST=false endif # ------------------------------------------------------------------- -# Path variables +# Variables # ------------------------------------------------------------------- ifdef SIM_COMPLIBDIR @@ -24,57 +24,18 @@ endif # Parse part name from ID PART_NAME=$(subst /,,$(PART_ID)) -# ------------------------------------------------------------------- -# Usage: SETUP_AND_LAUNCH_SIMULATION -# Args: $1 = Simulator Name -# ------------------------------------------------------------------- - # Resolve path EXP_DESIGN_SRCS = $(call RESOLVE_PATHS,$(DESIGN_SRCS)) EXP_SIM_SRCS = $(call RESOLVE_PATHS,$(SIM_SRCS)) EXP_INC_SRCS = $(call RESOLVE_PATHS,$(INC_SRCS)) -# (NOQ) No quotes! -NOQ_DESIGN_SRCS := $(subst $\",,$(EXP_DESIGN_SRCS)) -NOQ_SIM_SRCS := $(subst $\",,$(EXP_SIM_SRCS)) -NOQ_INC_SRCS := $(subst $\",,$(EXP_INC_SRCS)) - -# Separate out VHDL -NOQ_DESIGN_VHDL := $(filter %.vhd,$(NOQ_DESIGN_SRCS)) -NOQ_SIM_VHDL := $(filter %.vhd,$(NOQ_SIM_SRCS)) -NOQ_VHDL := $(NOQ_DESIGN_VHDL) $(NOQ_SIM_VHDL) - -# Separate out System Verilog -NOQ_DESIGN_SV := $(filter %.sv,$(NOQ_DESIGN_SRCS)) -NOQ_SIM_SV := $(filter %.sv,$(NOQ_SIM_SRCS)) -NOQ_SV := $(NOQ_DESIGN_SV) $(NOQ_SIM_SV) -# Fetch packages from include list to compile -NOQ_PKG_SV := $(filter %.sv,$(NOQ_INC_SRCS)) - -# Seperate out Verilog -NOQ_INC_DIRS := $(sort $(dir $(NOQ_DESIGN_SRCS) $(NOQ_SIM_SRCS) $(NOQ_INC_SRCS))) -NOQ_DESIGN_VERILOG := $(filter %.v,$(NOQ_DESIGN_SRCS)) -NOQ_SIM_VERILOG := $(filter %.v,$(NOQ_SIM_SRCS)) -NOQ_VERILOG := $(NOQ_DESIGN_VERILOG) $(NOQ_SIM_VERILOG) - -# Modelsim Load libraries -MODELSIM_LIBS += unisims_ver - -# Arguments for various simulators -MODELSIM_ARGS_L += $(MODELSIM_ARGS) -quiet -SVLOG_ARGS_L += $(SVLOG_ARGS) -quiet +define+WORKING_DIR="\"${CURDIR}\"" -VLOG_ARGS_L += $(VLOG_ARGS) -quiet +define+WORKING_DIR="\"${CURDIR}\"" -VHDL_ARGS_L += $(VHDL_ARGS) -quiet - -# Working directory for standalone ModelSim execution +# Working directory for native ModelSim execution MODELSIM_PROJ_DIR ?= modelsim_proj -# Check if we want to load the ModelSim GUI -ifeq ($(GUI), 1) - MODELSIM_ARGS_L += -voptargs=+acc -else - MODELSIM_ARGS_L += -c -do "run -all; quit -f" -endif +# ------------------------------------------------------------------- +# Usage: SETUP_AND_LAUNCH_SIMULATION +# Args: $1 = Simulator Name +# ------------------------------------------------------------------- SETUP_AND_LAUNCH_SIMULATION = \ @ \ @@ -93,6 +54,36 @@ SETUP_AND_LAUNCH_SIMULATION = \ export VIV_SIM_64BIT=$(MODELSIM_64BIT); \ $(TOOLS_DIR)/scripts/launch_vivado.sh -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(TOOLS_DIR)/scripts/viv_sim_project.tcl) -log xsim.log -nojournal +# ------------------------------------------------------------------- +# Usage: SETUP_AND_LAUNCH_VLINT +# Args: N/A +# ------------------------------------------------------------------- + +SETUP_AND_LAUNCH_VLINT = \ + @ \ + export VLINT_PROJ_DIR=$(MODELSIM_PROJ_DIR); \ + export VLINT_DESIGN_SRCS=$(EXP_DESIGN_SRCS); \ + export VLINT_SIM_SRCS=$(EXP_SIM_SRCS); \ + export VLINT_INC_SRCS=$(EXP_INC_SRCS); \ + export VLINT_SVLOG_ARGS="$(SVLOG_ARGS)"; \ + export VLINT_VLOG_ARGS="$(VLOG_ARGS)"; \ + export VLINT_VHDL_ARGS="$(VHDL_ARGS)"; \ + $(TOOLS_DIR)/scripts/launch_vlint.sh + +# ------------------------------------------------------------------- +# Usage: SETUP_AND_LAUNCH_VLINT +# Args: N/A +# ------------------------------------------------------------------- + +SETUP_AND_LAUNCH_MODELSIM = \ + @ \ + export MSIM_PROJ_DIR=$(MODELSIM_PROJ_DIR); \ + export MSIM_SIM_TOP=$(SIM_TOP); \ + export MSIM_ARGS="$(MODELSIM_ARGS)"; \ + export MSIM_LIBS="$(MODELSIM_LIBS)"; \ + export MSIM_MODE=$(VIVADO_MODE); \ + $(TOOLS_DIR)/scripts/launch_modelsim.sh + .SECONDEXPANSION: ##xsim: Run the simulation using the Xilinx Vivado Simulator @@ -115,39 +106,14 @@ vsim: .check_tool $(COMPLIBDIR) $(DESIGN_SRCS) $(SIM_SRCS) $(INC_SRCS) ##modelsim: Run the simulation using Modelsim (natively) modelsim: .check_tool vlint - cd $(MODELSIM_PROJ_DIR) && vsim $(MODELSIM_ARGS_L) $(foreach lib,$(MODELSIM_LIBS),-L $(lib)) $(SIM_TOP) - + $(call SETUP_AND_LAUNCH_MODELSIM) # NOTE: VHDL files require a correct compile order. This script compiles files # in the order they are defined in $(DESIGN_SRC), then $SIM_SRC) ##vlint: Run ModelSim compiler to lint files. vlint: .check_tool $(COMPLIBDIR) $(DESIGN_SRCS) $(SIM_SRCS) $(INC_SRCS) - $(shell mkdir -p ./$(MODELSIM_PROJ_DIR)) - $(file >$(MODELSIM_PROJ_DIR)/svlogarglist.txt,/* Auto generated argument file for vlog -sv */) - $(file >>$(MODELSIM_PROJ_DIR)/svlogarglist.txt,-sv) - $(foreach dir,$(NOQ_INC_DIRS), $(file >>$(MODELSIM_PROJ_DIR)/svlogarglist.txt,+incdir+$(dir))) - $(foreach src,$(NOQ_PKG_SV), $(file >>$(MODELSIM_PROJ_DIR)/svlogarglist.txt,$(src))) - $(foreach src,$(NOQ_SV), $(file >>$(MODELSIM_PROJ_DIR)/svlogarglist.txt,$(src))) - $(file >$(MODELSIM_PROJ_DIR)/vlogarglist.txt,/* Auto generated argument file for vlog */) - $(file >>$(MODELSIM_PROJ_DIR)/vlogarglist.txt,-vlog01compat) - $(foreach dir,$(NOQ_INC_DIRS), $(file >>$(MODELSIM_PROJ_DIR)/vlogarglist.txt,+incdir+$(dir))) - $(foreach src,$(NOQ_VERILOG), $(file >>$(MODELSIM_PROJ_DIR)/vlogarglist.txt,$(src))) - $(file >$(MODELSIM_PROJ_DIR)/vcomarglist.txt,/* Auto generated argument file for vcom */) - $(file >>$(MODELSIM_PROJ_DIR)/vcomarglist.txt,-2008) - $(foreach src,$(NOQ_VHDL),$(file >>$(MODELSIM_PROJ_DIR)/vcomarglist.txt,$(src))) -ifneq ($(strip $(NOQ_SV)),) - @echo "*** COMPILING SYSTEM VERILOG ***" - cd $(MODELSIM_PROJ_DIR) && vlog $(SVLOG_ARGS_L) -f svlogarglist.txt -endif -ifneq ($(strip $(NOQ_VERILOG)),) - @echo "*** COMPILING VERILOG ***" - cd $(MODELSIM_PROJ_DIR) && vlog $(VLOG_ARGS_L) -f vlogarglist.txt -endif -ifneq ($(strip $(NOQ_VHDL)),) - @echo "*** COMPILING VHDL ***" - cd $(MODELSIM_PROJ_DIR) && vcom $(VHDL_ARGS_L) -f vcomarglist.txt -endif + $(call SETUP_AND_LAUNCH_VLINT) ##vclean: Cleanup ModelSim intermediate files vclean: -- cgit v1.2.3