From ff1546f8137f7f92bb250f685561b0c34cc0e053 Mon Sep 17 00:00:00 2001 From: Ben Hilburn Date: Fri, 14 Feb 2014 12:05:07 -0800 Subject: Pushing the bulk of UHD-3.7.0 code. --- fpga/usrp3/sim/axi_crossbar/sim_2x2/default.wcfg | 188 ++++++++++ fpga/usrp3/sim/axi_crossbar/sim_2x2/run_isim | 15 + fpga/usrp3/sim/axi_crossbar/sim_2x2/run_iverilog | 21 ++ .../sim/axi_crossbar/sim_2x2/simulation_script.v | 136 +++++++ fpga/usrp3/sim/axi_crossbar/sim_4x4/default.wcfg | 330 +++++++++++++++++ fpga/usrp3/sim/axi_crossbar/sim_4x4/run_isim | 15 + .../sim/axi_crossbar/sim_4x4/simulation_script.v | 188 ++++++++++ .../sim/axi_dram_fifo/sim_sram_1/default.wcfg | 412 +++++++++++++++++++++ fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/run_isim | 17 + .../axi_dram_fifo/sim_sram_1/simulation_script.v | 113 ++++++ .../sim/axi_dram_fifo/sim_sram_2/Default.wcfg | 388 +++++++++++++++++++ fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/run_isim | 19 + .../axi_dram_fifo/sim_sram_2/simulation_script.v | 91 +++++ fpga/usrp3/sim/b2x0/sim_b2x0_1/run_isim | 22 ++ fpga/usrp3/sim/ddc_chain_x300/dctest/.gitignore | 4 + fpga/usrp3/sim/ddc_chain_x300/dctest/DDC.sav | 101 +++++ fpga/usrp3/sim/ddc_chain_x300/dctest/run_isim | 17 + fpga/usrp3/sim/ddc_chain_x300/dctest/simcmds.tcl | 9 + fpga/usrp3/sim/duc_chain_x300/dctest/.gitignore | 4 + fpga/usrp3/sim/duc_chain_x300/dctest/run_isim | 17 + fpga/usrp3/sim/duc_chain_x300/dctest/simcmds.tcl | 9 + fpga/usrp3/sim/math.v | 276 ++++++++++++++ .../sim/serial_to_settings/serial_settings_tasks.v | 59 +++ .../sim_serial_to_settings_1/default.wcfg | 86 +++++ .../sim_serial_to_settings_1/run_isim | 24 ++ .../sim_serial_to_settings_1/simulation_script.v | 43 +++ fpga/usrp3/sim/task_library.v | 297 +++++++++++++++ 27 files changed, 2901 insertions(+) create mode 100644 fpga/usrp3/sim/axi_crossbar/sim_2x2/default.wcfg create mode 100755 fpga/usrp3/sim/axi_crossbar/sim_2x2/run_isim create mode 100755 fpga/usrp3/sim/axi_crossbar/sim_2x2/run_iverilog create mode 100644 fpga/usrp3/sim/axi_crossbar/sim_2x2/simulation_script.v create mode 100644 fpga/usrp3/sim/axi_crossbar/sim_4x4/default.wcfg create mode 100755 fpga/usrp3/sim/axi_crossbar/sim_4x4/run_isim create mode 100644 fpga/usrp3/sim/axi_crossbar/sim_4x4/simulation_script.v create mode 100644 fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/default.wcfg create mode 100755 fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/run_isim create mode 100644 fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/simulation_script.v create mode 100644 fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/Default.wcfg create mode 100755 fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/run_isim create mode 100644 fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/simulation_script.v create mode 100755 fpga/usrp3/sim/b2x0/sim_b2x0_1/run_isim create mode 100644 fpga/usrp3/sim/ddc_chain_x300/dctest/.gitignore create mode 100644 fpga/usrp3/sim/ddc_chain_x300/dctest/DDC.sav create mode 100755 fpga/usrp3/sim/ddc_chain_x300/dctest/run_isim create mode 100755 fpga/usrp3/sim/ddc_chain_x300/dctest/simcmds.tcl create mode 100644 fpga/usrp3/sim/duc_chain_x300/dctest/.gitignore create mode 100755 fpga/usrp3/sim/duc_chain_x300/dctest/run_isim create mode 100755 fpga/usrp3/sim/duc_chain_x300/dctest/simcmds.tcl create mode 100644 fpga/usrp3/sim/math.v create mode 100644 fpga/usrp3/sim/serial_to_settings/serial_settings_tasks.v create mode 100644 fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/default.wcfg create mode 100755 fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/run_isim create mode 100644 fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/simulation_script.v create mode 100644 fpga/usrp3/sim/task_library.v (limited to 'fpga/usrp3/sim') diff --git a/fpga/usrp3/sim/axi_crossbar/sim_2x2/default.wcfg b/fpga/usrp3/sim/axi_crossbar/sim_2x2/default.wcfg new file mode 100644 index 000000000..f52bcc090 --- /dev/null +++ b/fpga/usrp3/sim/axi_crossbar/sim_2x2/default.wcfg @@ -0,0 +1,188 @@ + + + + + + + + + + + + + + + clk + clk + + + reset + reset + + + set_stb + set_stb + + + set_addr[15:0] + set_addr[15:0] + HEXRADIX + + + set_data[31:0] + set_data[31:0] + HEXRADIX + + + local_addr + local_addr + + + New Divider + label + 128 128 255 + 230 230 230 + + + Input Port 0 + label + HEXRADIX + + i_tdata[64:0] + i_tdata[64:0] + HEXRADIX + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[64:0] + o_tdata[64:0] + HEXRADIX + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + New Divider + label + 128 128 255 + 230 230 230 + + + + Input Port 1 + label + HEXRADIX + + i_tdata[64:0] + i_tdata[64:0] + HEXRADIX + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[64:0] + o_tdata[64:0] + HEXRADIX + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + New Divider + label + 128 128 255 + 230 230 230 + + + + Output Port 0 + label + HEXRADIX + + i_tdata[64:0] + i_tdata[64:0] + HEXRADIX + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[64:0] + o_tdata[64:0] + HEXRADIX + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + New Divider + label + 128 128 255 + 230 230 230 + + + + Output Port 1 + label + HEXRADIX + + i_tdata[64:0] + i_tdata[64:0] + HEXRADIX + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[64:0] + o_tdata[64:0] + HEXRADIX + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + diff --git a/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_isim b/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_isim new file mode 100755 index 000000000..6c3fde52c --- /dev/null +++ b/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_isim @@ -0,0 +1,15 @@ +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +vlogcomp -i ../.. -work work ../../../lib/control/axi_crossbar_tb.v +vlogcomp -work work ../../../lib/control/axi_crossbar.v +vlogcomp -work work ../../../lib/control/axi_slave_mux.v +vlogcomp -work work ../../../lib/control/axi_forwarding_cam.v +vlogcomp -work work ../../../lib/control/setting_reg.v +vlogcomp -work work ../../../lib/fifo/monitor_axi_fifo.v +vlogcomp -work work ../../../lib/fifo/axi_fifo_short.v + + + +fuse work.axi_crossbar_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_crossbar_tb.exe + +# run the simulation scrip +./axi_crossbar_tb.exe -gui #-tclbatch simcmds.tcl diff --git a/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_iverilog b/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_iverilog new file mode 100755 index 000000000..268127de8 --- /dev/null +++ b/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_iverilog @@ -0,0 +1,21 @@ + +iverilog \ +-s axi_crossbar_tb \ +-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims \ +-o axi_crossbar_tb \ +-I .. \ +/opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/glbl.v \ +../../lib/control/axi_crossbar_tb.v \ +../../lib/control/axi_crossbar.v \ +../../lib/control/axi_slave_mux.v \ +../../lib/control/axi_forwarding_cam.v \ +../../lib/control/setting_reg.v \ +../../lib/fifo/monitor_axi_fifo.v \ +../../lib/fifo/axi_fifo_short.v + + + +#fuse work.axi_crossbar_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_crossbar_tb.exe + +# run the simulation scrip +#./axi_crossbar_tb.exe -gui #-tclbatch simcmds.tcl diff --git a/fpga/usrp3/sim/axi_crossbar/sim_2x2/simulation_script.v b/fpga/usrp3/sim/axi_crossbar/sim_2x2/simulation_script.v new file mode 100644 index 000000000..da0213c72 --- /dev/null +++ b/fpga/usrp3/sim/axi_crossbar/sim_2x2/simulation_script.v @@ -0,0 +1,136 @@ +// Simulate a 2x2 switch configuration +localparam NUM_INPUTS = 2; +localparam NUM_OUTPUTS = 2; + +//initial $dumpfile("axi_crossbar_tb.vcd"); +//initial $dumpvars(0,axi_crossbar_tb); + +reg [15:0] x; +reg [31:0] seq_i0, seq_i1, seq_o0, seq_o1; + + +///////////////////////////////////////////// +// +// Control and input data thread. +// +///////////////////////////////////////////// +initial + begin + @(posedge clk); + reset <= 1; + repeat (5) @(posedge clk); + @(posedge clk); + reset <= 0; + @(posedge clk); + // 2x2 Switch so only mask one bit of SID for route dest. + // Each slave must have a unique address, logic doesn't check for this. + // + // Network Addr 0 & 1 go to Slave 0. + write_setting_bus(0,0); // 0.X goes to Port 0 + write_setting_bus(1,0); // 1.X goes to Port 0 + // Local Addr = 2 + write_setting_bus(512,2); + // Host Addr 0 & 2 go to Slave 0... + write_setting_bus(256,0); // 2.0 goes to Port 0 + write_setting_bus(258,0); // 2.2 goes to Port 0 + // ...Host Addr 1 & 3 go to Slave 1... + write_setting_bus(257,1); // 2.1 goes to Port 1 + write_setting_bus(259,1); // 2.3 goes to Port 1 + // +/* -----\/----- EXCLUDED -----\/----- + @(posedge clk); + fork + begin + // input_port,size,tsf,sid + // + // Master0, addr 0.0 to Slave0 + enqueue_vita_pkt(0,10,0,{16'h0,8'h0,8'h0}); + // Master0, addr 2.0 to Slave0 + enqueue_vita_pkt(0,11,'h12345678,{16'h0,8'h2,8'h0}); + // Master0, addr 2.3 to Slave1 + enqueue_vita_pkt(0,14,'h45678901,{16'h0,8'h2,8'h3}); + // Master0, addr 2.2 to Slave0 + enqueue_vita_pkt(0,11,'h67890123,{16'h0,8'h2,8'h2}); + end + begin + // Master1, addr 1.0 to Slave0 + enqueue_vita_pkt(1,12,'h23456789,{16'h0,8'h1,8'h0}); + // Master1, addr 2.1 to Slave1 + enqueue_vita_pkt(1,13,'h34567890,{16'h0,8'h2,8'h1}); + // Master1, addr 2.3 to Slave1 + enqueue_vita_pkt(1,14,'h56789012,{16'h0,8'h2,8'h3}); + end + join + -----/\----- EXCLUDED -----/\----- */ + // + @(posedge clk); + fork + begin + // Master0 Sender Thread. + // + // Master0, addr 0.0 to Slave0 + for (seq_i0 = 0; seq_i0 < 10; seq_i0=seq_i0 + 1) + enqueue_chdr_pkt_count(0,seq_i0,32+seq_i0,0,0,0,0,`SID(0,0,0,0)); + // Master1, addr 1.0 to Slave0 + for (seq_i0 = 20; seq_i0 < 30; seq_i0=seq_i0 + 1) + enqueue_chdr_pkt_count(0,seq_i0,32+seq_i0,0,0,0,0,`SID(0,0,1,0)); + end + + begin + // Master1 Sender Thread. + // + // Master1, addr 2.1 to Slave1 + for (seq_i1 = 10; seq_i1 < 20; seq_i1=seq_i1 + 1) + enqueue_chdr_pkt_count(1,seq_i1,32+seq_i1,1,'h12345678+seq_i1*100,0,0,`SID(0,0,2,1)); + // Master0, addr 2.3 to Slave1 + for (seq_i1 = 30; seq_i1 < 40; seq_i1=seq_i1 + 1) + enqueue_chdr_pkt_count(1,seq_i1,32+seq_i1,1,'h23456789+seq_i1*100,0,0,`SID(0,0,2,3)); + end + join + + repeat (1000) @(posedge clk); + + + end // initial begin + + + ///////////////////////////////////////////// + // + // Control and input data thread. + // + ///////////////////////////////////////////// + initial + begin + // Wait for reset to go high + while (reset!==1'b1) + @(posedge clk); + // Wait for reset to go low + while (reset!==1'b0) + @(posedge clk); + // Fork concurrent output checkers for each egress port. + fork + begin + // Slave0 Recevier thread. + // + // Master0, addr 0.0 to Slave0 + for (seq_o0 = 0; seq_o0 < 10; seq_o0=seq_o0 + 1) + dequeue_chdr_pkt_count(0,seq_o0,32+seq_o0,0,0,0,0,`SID(0,0,0,0)); + // Master1, addr 1.0 to Slave0 + for (seq_o0 = 20; seq_o0 < 30; seq_o0=seq_o0 + 1) + dequeue_chdr_pkt_count(0,seq_o0,32+seq_o0,0,0,0,0,`SID(0,0,1,0)); + end + begin + // Slave1 Receiver thread. + // + // Master1, addr 2.1 to Slave1 + for (seq_o1 = 10; seq_o1 < 20; seq_o1=seq_o1 + 1) + dequeue_chdr_pkt_count(1,seq_o1,32+seq_o1,1,'h12345678+seq_o1*100,0,0,`SID(0,0,2,1)); + // Master0, addr 2.3 to Slave1 + for (seq_o1 = 30; seq_o1 < 40; seq_o1=seq_o1 + 1) + dequeue_chdr_pkt_count(1,seq_o1,32+seq_o1,1,'h23456789+seq_o1*100,0,0,`SID(0,0,2,3)); + end + join + + repeat (1000) @(posedge clk); + $finish; + end // initial begin diff --git a/fpga/usrp3/sim/axi_crossbar/sim_4x4/default.wcfg b/fpga/usrp3/sim/axi_crossbar/sim_4x4/default.wcfg new file mode 100644 index 000000000..229ca6958 --- /dev/null +++ b/fpga/usrp3/sim/axi_crossbar/sim_4x4/default.wcfg @@ -0,0 +1,330 @@ + + + + + + + + + + + + + + + clk + clk + + + reset + reset + + + set_stb + set_stb + + + set_addr[15:0] + set_addr[15:0] + HEXRADIX + + + set_data[31:0] + set_data[31:0] + HEXRADIX + + + local_addr[7:0] + local_addr[7:0] + + + New Divider + label + 128 128 255 + 230 230 230 + + + Input Port 0 + label + HEXRADIX + + i_tdata[64:0] + i_tdata[64:0] + HEXRADIX + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[64:0] + o_tdata[64:0] + HEXRADIX + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + New Divider + label + 128 128 255 + 230 230 230 + + + + Input Port 1 + label + HEXRADIX + + i_tdata[64:0] + i_tdata[64:0] + HEXRADIX + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[64:0] + o_tdata[64:0] + HEXRADIX + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + New Divider + label + 128 128 255 + 230 230 230 + + + + Input Port 2 + label + + i_tdata[64:0] + i_tdata[64:0] + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[64:0] + o_tdata[64:0] + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + New Divider + label + 128 128 255 + 230 230 230 + + + + Input Port 3 + label + + i_tdata[64:0] + i_tdata[64:0] + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[64:0] + o_tdata[64:0] + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + New Divider + label + 128 128 255 + 230 230 230 + + + + Output Port 0 + label + HEXRADIX + + i_tdata[64:0] + i_tdata[64:0] + HEXRADIX + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[64:0] + o_tdata[64:0] + HEXRADIX + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + New Divider + label + 128 128 255 + 230 230 230 + + + + Output Port 1 + label + HEXRADIX + + i_tdata[64:0] + i_tdata[64:0] + HEXRADIX + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[64:0] + o_tdata[64:0] + HEXRADIX + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + New Divider + label + 128 128 255 + 230 230 230 + + + + Output Port 2 + label + + i_tdata[64:0] + i_tdata[64:0] + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[64:0] + o_tdata[64:0] + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + New Divider + label + 128 128 255 + 230 230 230 + + + + Output Port 3 + label + + i_tdata[64:0] + i_tdata[64:0] + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[64:0] + o_tdata[64:0] + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + New Divider + label + 128 128 255 + 230 230 230 + + + diff --git a/fpga/usrp3/sim/axi_crossbar/sim_4x4/run_isim b/fpga/usrp3/sim/axi_crossbar/sim_4x4/run_isim new file mode 100755 index 000000000..6c3fde52c --- /dev/null +++ b/fpga/usrp3/sim/axi_crossbar/sim_4x4/run_isim @@ -0,0 +1,15 @@ +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +vlogcomp -i ../.. -work work ../../../lib/control/axi_crossbar_tb.v +vlogcomp -work work ../../../lib/control/axi_crossbar.v +vlogcomp -work work ../../../lib/control/axi_slave_mux.v +vlogcomp -work work ../../../lib/control/axi_forwarding_cam.v +vlogcomp -work work ../../../lib/control/setting_reg.v +vlogcomp -work work ../../../lib/fifo/monitor_axi_fifo.v +vlogcomp -work work ../../../lib/fifo/axi_fifo_short.v + + + +fuse work.axi_crossbar_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_crossbar_tb.exe + +# run the simulation scrip +./axi_crossbar_tb.exe -gui #-tclbatch simcmds.tcl diff --git a/fpga/usrp3/sim/axi_crossbar/sim_4x4/simulation_script.v b/fpga/usrp3/sim/axi_crossbar/sim_4x4/simulation_script.v new file mode 100644 index 000000000..7bd1c1dab --- /dev/null +++ b/fpga/usrp3/sim/axi_crossbar/sim_4x4/simulation_script.v @@ -0,0 +1,188 @@ +// Simulate a 4x4 switch configuration +localparam NUM_INPUTS = 4; +localparam NUM_OUTPUTS = 4; + +//initial $dumpfile("axi_crossbar_tb.vcd"); +//initial $dumpvars(0,axi_crossbar_tb); + +reg [15:0] x; +reg [31:0] seq_i0, seq_i1, seq_i2, seq_i3, seq_o0, seq_o1, seq_o2, seq_o3; +reg sync_flag0, sync_flag1; + + +///////////////////////////////////////////// +// +// Control and input data thread. +// +///////////////////////////////////////////// +initial + begin + // Flags to synchronise test bench threads + sync_flag0 <= 0; + sync_flag1 <= 0; + + @(posedge clk); + reset <= 1; + repeat (5) @(posedge clk); + @(posedge clk); + reset <= 0; + @(posedge clk); + // 2x2 Switch so only mask one bit of SID for route dest. + // Each slave must have a unique address, logic doesn't check for this. + // + // Local Addr = 2 + write_setting_bus(512,2); + // Network Addr 0 & 1 go to Slave 0. + write_setting_bus(0,0); // 0.X goes to Port 0 + write_setting_bus(1,0); // 1.X goes to Port 0 + // Host Addr 0 goes to Slave 0... + write_setting_bus(256,0); // 2.0 goes to Port 0 + // ...Host Addr 1 goes to Slave 1... + write_setting_bus(257,1); // 2.1 goes to Port 1 + // ...Host Addr 2 goes to Slave 2... + write_setting_bus(258,2); // 2.2 goes to Port 2 + // ...Host Addr 3 goes to Slave 3... + write_setting_bus(259,3); // 2.3 goes to Port 3 + + // + @(posedge clk); + fork + begin + // Master0 Sender Thread. + // + // addr 2.3 to Slave3 + for (seq_i0 = 0; seq_i0 < 10; seq_i0=seq_i0 + 1) + enqueue_chdr_pkt_count(0,seq_i0,32+seq_i0,1,'h12345678+seq_i0*100,0,0,`SID(0,0,2,3)); + + while (sync_flag0 !== 1'b1) + @(posedge clk); + + // + // addr 2.0 to Slave0 + for (seq_i0 = 30; seq_i0 < 40; seq_i0=seq_i0 + 1) + enqueue_chdr_pkt_count(0,seq_i0,32+seq_i0,1,'h45678901+seq_i0*100,0,0,`SID(0,0,2,0)); + + end + begin + // Master1 Sender Thread. + // + // addr 2.2 to Slave2 + for (seq_i1 = 10; seq_i1 < 20; seq_i1=seq_i1 + 1) + enqueue_chdr_pkt_count(1,seq_i1,32+seq_i1,1,'h23456789+seq_i1*100,0,0,`SID(0,0,2,2)); + + + while (sync_flag1 !== 1'b1) + @(posedge clk); + + // + // addr 2.1 to Slave1 + for (seq_i1 = 20; seq_i1 < 30; seq_i1=seq_i1 + 1) + enqueue_chdr_pkt_count(1,seq_i1,32+seq_i1,1,'h34567890+seq_i1*100,0,0,`SID(0,0,2,1)); + end + begin + // Master2 Sender Thread. + // + // addr 2.1 to Slave1 + for (seq_i2 = 20; seq_i2 < 30; seq_i2=seq_i2 + 1) + enqueue_chdr_pkt_count(2,seq_i2,32+seq_i2,1,'h34567890+seq_i2*100,0,0,`SID(0,0,2,1)); + + // + // addr 2.2 to Slave2 + for (seq_i2 = 10; seq_i2 < 20; seq_i2=seq_i2 + 1) + enqueue_chdr_pkt_count(2,seq_i2,32+seq_i2,1,'h23456789+seq_i2*100,0,0,`SID(0,0,2,2)); + end + begin + // Master3 Sender Thread. + // + // addr 2.0 to Slave0 + for (seq_i3 = 30; seq_i3 < 40; seq_i3=seq_i3 + 1) + enqueue_chdr_pkt_count(3,seq_i3,32+seq_i3,1,'h45678901+seq_i3*100,0,0,`SID(0,0,2,0)); + + // + // addr 2.3 to Slave3 + for (seq_i3 = 0; seq_i3 < 10; seq_i3=seq_i3 + 1) + enqueue_chdr_pkt_count(3,seq_i3,32+seq_i3,1,'h12345678+seq_i3*100,0,0,`SID(0,0,2,3)); + end + + join + + repeat (1000) @(posedge clk); + + + end // initial begin + + + ///////////////////////////////////////////// + // + // Control and input data thread. + // + ///////////////////////////////////////////// + initial + begin + // Wait for reset to go high + while (reset!==1'b1) + @(posedge clk); + // Wait for reset to go low + while (reset!==1'b0) + @(posedge clk); + // Fork concurrent output checkers for each egress port. + fork + begin + // Slave0 Recevier thread. + // + // addr 2.0 to Slave0 + for (seq_o0 = 30; seq_o0 < 40; seq_o0=seq_o0 + 1) + dequeue_chdr_pkt_count(0,seq_o0,32+seq_o0,1,'h45678901+seq_o0*100,0,0,`SID(0,0,2,0)); + + sync_flag0 <= 1'b1; + + // + // addr 2.0 to Slave0 + for (seq_o0 = 30; seq_o0 < 40; seq_o0=seq_o0 + 1) + enqueue_chdr_pkt_count(0,seq_o0,32+seq_o0,1,'h45678901+seq_o0*100,0,0,`SID(0,0,2,0)); + end + + begin + // Slave1 Recevier thread. + // + // addr 2.1 to Slave1 + for (seq_o1 = 20; seq_o1 < 30; seq_o1=seq_o1 + 1) + dequeue_chdr_pkt_count(1,seq_o1,32+seq_o1,1,'h34567890+seq_o1*100,0,0,`SID(0,0,2,1)); + + sync_flag1 <= 1'b1; + + // + // addr 2.1 to Slave1 + for (seq_o1 = 20; seq_o1 < 30; seq_o1=seq_o1 + 1) + enqueue_chdr_pkt_count(1,seq_o1,32+seq_o1,1,'h34567890+seq_o1*100,0,0,`SID(0,0,2,1)); + end + + begin + // Slave2 Recevier thread. + // + // addr 2.2 to Slave2 + for (seq_o2 = 10; seq_o2 < 20; seq_o2=seq_o2 + 1) + dequeue_chdr_pkt_count(2,seq_o2,32+seq_o2,1,'h23456789+seq_o2*100,0,0,`SID(0,0,2,2)); + // + // addr 2.2 to Slave2 + for (seq_o2 = 10; seq_o2 < 20; seq_o2=seq_o2 + 1) + enqueue_chdr_pkt_count(2,seq_o2,32+seq_o2,1,'h23456789+seq_o2*100,0,0,`SID(0,0,2,2)); + end + + begin + // Slave3 Recevier thread. + // + // addr 2.3 to Slave3 + for (seq_o3 = 0; seq_o3 < 10; seq_o3=seq_o3 + 1) + dequeue_chdr_pkt_count(3,seq_o3,32+seq_o3,1,'h12345678+seq_o3*100,0,0,`SID(0,0,2,3)); + // + // addr 2.3 to Slave3 + for (seq_o3 = 0; seq_o3 < 10; seq_o3=seq_o3 + 1) + enqueue_chdr_pkt_count(3,seq_o3,32+seq_o3,1,'h12345678+seq_o3*100,0,0,`SID(0,0,2,3)); + end + + join + + repeat (1000) @(posedge clk); + $finish; + end // initial begin diff --git a/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/default.wcfg b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/default.wcfg new file mode 100644 index 000000000..796071597 --- /dev/null +++ b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/default.wcfg @@ -0,0 +1,412 @@ + + + + + + + + + + + + + + + clk + clk + + + reset + reset + + + clear + clear + + + count_rx[31:0] + count_rx[31:0] + HEXRADIX + + + count_tx[31:0] + count_tx[31:0] + HEXRADIX + + + i_tdata[63:0] + i_tdata[63:0] + HEXRADIX + + + i_tlast + i_tlast + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + input_state[2:0] + input_state[2:0] + HEXRADIX + + + write_ctrl_ready + write_ctrl_ready + + + write_ctrl_valid + write_ctrl_valid + + + occupied_input[5:0] + occupied_input[5:0] + HEXRADIX + + + INPUT TIMEOUT + label + + input_timeout_count[7:0] + input_timeout_count[7:0] + + + input_timeout_reset + input_timeout_reset + + + input_timeout_triggered + input_timeout_triggered + + + + AXI_WADDR + label + + write_addr_state[1:0] + write_addr_state[1:0] + HEXRADIX + true + #ffff00 + + + m_axi_awid[0:0] + m_axi_awid[0:0] + HEXRADIX + + + m_axi_awaddr[31:0] + m_axi_awaddr[31:0] + HEXRADIX + + + m_axi_awlen[7:0] + m_axi_awlen[7:0] + HEXRADIX + + + m_axi_awsize[2:0] + m_axi_awsize[2:0] + HEXRADIX + + + m_axi_awburst[1:0] + m_axi_awburst[1:0] + HEXRADIX + + + m_axi_awvalid + m_axi_awvalid + + + m_axi_awready + m_axi_awready + + + + write_data_count[3:0] + write_data_count[3:0] + HEXRADIX + + + AXI_WDATA + label + + m_axi_wdata[63:0] + m_axi_wdata[63:0] + HEXRADIX + + + m_axi_wstrb[7:0] + m_axi_wstrb[7:0] + HEXRADIX + + + m_axi_wlast + m_axi_wlast + + + m_axi_wvalid + m_axi_wvalid + + + m_axi_wready + m_axi_wready + + + + AXI_WRESP + label + + m_axi_bid[0:0] + m_axi_bid[0:0] + HEXRADIX + + + m_axi_bresp[1:0] + m_axi_bresp[1:0] + HEXRADIX + + + m_axi_bvalid + m_axi_bvalid + + + m_axi_bready + m_axi_bready + true + #00ff00 + /axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bready + + + + space[10:0] + space[10:0] + HEXRADIX + + + occupied[10:0] + occupied[10:0] + HEXRADIX + true + #00ffff + + + AXI_RADDR + label + + read_addr_state[1:0] + read_addr_state[1:0] + HEXRADIX + true + #ffff00 + + + m_axi_arid[0:0] + m_axi_arid[0:0] + HEXRADIX + + + m_axi_araddr[31:0] + m_axi_araddr[31:0] + HEXRADIX + + + m_axi_arlen[7:0] + m_axi_arlen[7:0] + HEXRADIX + + + m_axi_arsize[2:0] + m_axi_arsize[2:0] + HEXRADIX + + + m_axi_arburst[1:0] + m_axi_arburst[1:0] + HEXRADIX + + + m_axi_arvalid + m_axi_arvalid + + + m_axi_arready + m_axi_arready + + + + AXI_RDATA + label + + read_data_state[1:0] + read_data_state[1:0] + HEXRADIX + true + #ffff00 + + + m_axi_rid[0:0] + m_axi_rid[0:0] + HEXRADIX + + + m_axi_rdata[63:0] + m_axi_rdata[63:0] + HEXRADIX + + + m_axi_rresp[1:0] + m_axi_rresp[1:0] + HEXRADIX + + + m_axi_rlast + m_axi_rlast + + + m_axi_rvalid + m_axi_rvalid + + + m_axi_rready + m_axi_rready + + + + read_ctrl_valid + read_ctrl_valid + true + #ffff00 + + + read_ctrl_ready + read_ctrl_ready + + + read_data_count[3:0] + read_data_count[3:0] + HEXRADIX + + + output_state[2:0] + output_state[2:0] + HEXRADIX + + + space_output[5:0] + space_output[5:0] + HEXRADIX + + + DRAM FIFO OUT + label + + o_tdata_output[63:0] + o_tdata_output[63:0] + HEXRADIX + + + o_tvalid_output + o_tvalid_output + + + o_tready_output + o_tready_output + + + + update_write + update_write + true + #ff00ff + + + write_count[3:0] + write_count[3:0] + HEXRADIX + + + update_read + update_read + true + #ff00ff + + + read_count[3:0] + read_count[3:0] + HEXRADIX + + + Output TImeout + label + + output_timeout_count[7:0] + output_timeout_count[7:0] + + + output_timeout_reset + output_timeout_reset + + + output_timeout_triggered + output_timeout_triggered + + + + Extract TLAST + label + + o_tdata_i0[63:0] + o_tdata_i0[63:0] + HEXRADIX + + + o_tvalid_i0 + o_tvalid_i0 + + + o_tready_i0 + o_tready_i0 + + + o_tdata_i1[63:0] + o_tdata_i1[63:0] + HEXRADIX + + + o_tvalid_i1 + o_tvalid_i1 + + + o_tready_i1 + o_tready_i1 + + + o_tlast_i1 + o_tlast_i1 + + + + o_tdata[63:0] + o_tdata[63:0] + HEXRADIX + + + o_tlast + o_tlast + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + diff --git a/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/run_isim b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/run_isim new file mode 100755 index 000000000..03eead1f7 --- /dev/null +++ b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/run_isim @@ -0,0 +1,17 @@ +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +#vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../packet_proc/source_flow_control_tb.v +vlogcomp -work work --sourcelibext .v \ + --sourcelibdir ../../../lib/axi \ + --sourcelibdir ../../../lib/fifo \ + --sourcelibdir ../../../lib/control \ + --sourcelibdir ../../../top/x300/coregen \ + ../../../lib/axi/axi_dram_fifo_tb.v + + + +fuse work.axi_dram_fifo_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_dram_fifo_tb.exe + +# run the simulation scrip +./axi_dram_fifo_tb.exe # -gui #-tclbatch simcmds.tcl + + diff --git a/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/simulation_script.v b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/simulation_script.v new file mode 100644 index 000000000..eb72da360 --- /dev/null +++ b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/simulation_script.v @@ -0,0 +1,113 @@ +reg [31:0] count_rx, count_tx; +reg status; +reg fail; + + +// +// Use task library +// +`define USE_TASKS + + initial + begin + clk <= 1'b0; + reset <= 1'b0; + clear <= 1'b0; + i_tdata_r <= 0; + i_tlast_r <= 0; + i_tvalid_r <= 0; + o_tready_r <= 0; + end + + always + #5 clk <= ~clk; + + initial + begin + count_tx = 2; + count_rx = 2; + status = 0; + + + @(negedge clk); + reset <= 1'b1; + repeat(10) @(negedge clk); + reset <= 1'b0; + repeat(10) @(negedge clk); + + // Send 40 packets. + repeat(40) begin + send_raw_packet(count_tx); + repeat(2) @(posedge clk); + count_tx = count_tx + 1; + @(posedge clk); + end + repeat(100) @(posedge clk); + + + // Recieve 40 packets + repeat(40) begin + receive_raw_packet(count_rx,fail); + status = status || fail; + repeat(2) @(posedge clk); + count_rx = count_rx + 1; + @(posedge clk); + end + repeat(100) @(posedge clk); + + count_tx = 2; + count_rx = 2; + + // Send 40 packets. + repeat(40) begin + send_raw_packet(count_tx); + repeat(2) @(posedge clk); + count_tx = count_tx + 1; + @(posedge clk); + end + repeat(100) @(posedge clk); + // Now fork so send and receive run concurrently + fork + begin + // Send 40 packets. + repeat(40) begin + send_raw_packet(count_tx); + repeat(2) @(posedge clk); + count_tx = count_tx + 1; + @(posedge clk); + end + end + begin + // Recieve 80 packets + repeat(80) begin + receive_raw_packet(count_rx,status); + status = status || fail; + repeat(2) @(posedge clk); + count_rx = count_rx + 1; + @(posedge clk); + if (status !== 0) begin + repeat(100) @(posedge clk); + $display("FAILED."); + $finish; + end + end + end + join + // Now single threaded agian. + repeat(100) @(posedge clk); + + $display; + // Should not be able to get to here with FAIL status but check anyhow + if (status != 0) + $display("FAILED."); + else + $display("PASSED."); + + @(posedge clk); + $finish; + + end + + //initial + // o_tready = 1; + diff --git a/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/Default.wcfg b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/Default.wcfg new file mode 100644 index 000000000..3e6d96fb4 --- /dev/null +++ b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/Default.wcfg @@ -0,0 +1,388 @@ + + + + + + + + + + + + + + + + + + + + + clk + clk + + + reset + reset + + + chdr_test_pattern + label + HEXRADIX + + start + start + + + i_tdata[63:0] + i_tdata[63:0] + HEXRADIX + + + i_tlast + i_tlast + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[63:0] + o_tdata[63:0] + HEXRADIX + + + o_tlast + o_tlast + + + o_tready + o_tready + + + o_tvalid + o_tvalid + + + + embed_tlast + label + HEXRADIX + + i_tdata[63:0] + i_tdata[63:0] + HEXRADIX + + + i_tlast + i_tlast + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[63:0] + o_tdata[63:0] + HEXRADIX + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + state[1:0] + state[1:0] + HEXRADIX + + + + fast_fifo_i0 + label + HEXRADIX + + state[1:0] + state[1:0] + HEXRADIX + + + i_tdata[63:0] + i_tdata[63:0] + HEXRADIX + + + FullPathName + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[63:0] + o_tdata[63:0] + HEXRADIX + + + o_tvalid + o_tvalid + + + label + o_tready + o_tready + o_tready + + + + fifo_i1 + label + HEXRADIX + + i_tdata[63:0] + i_tdata[63:0] + HEXRADIX + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[63:0] + o_tdata[63:0] + HEXRADIX + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + + AXI write bus + label + + axi_awaddr[31:0] + axi_awaddr[31:0] + HEXRADIX + + + axi_awlen[7:0] + axi_awlen[7:0] + HEXRADIX + + + axi_awvalid + axi_awvalid + + + axi_awready + axi_awready + + + axi_wdata[63:0] + axi_wdata[63:0] + HEXRADIX + + + axi_wvalid + axi_wvalid + + + axi_wready + axi_wready + + + axi_bvalid + axi_bvalid + + + axi_bready + axi_bready + + + + space[10:0] + space[10:0] + HEXRADIX + + + occupied[10:0] + occupied[10:0] + HEXRADIX + + + AXI read bus + label + HEXRADIX + + m_axi_araddr[31:0] + m_axi_araddr[31:0] + HEXRADIX + + + m_axi_arlen[7:0] + m_axi_arlen[7:0] + HEXRADIX + + + m_axi_arvalid + m_axi_arvalid + + + m_axi_arready + m_axi_arready + + + m_axi_rdata[63:0] + m_axi_rdata[63:0] + HEXRADIX + + + m_axi_rvalid + m_axi_rvalid + + + m_axi_rready + m_axi_rready + + + + fifo_i2 + label + + i_tdata[63:0] + i_tdata[63:0] + HEXRADIX + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[63:0] + o_tdata[63:0] + HEXRADIX + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + + fast_fifo_i1 + label + HEXRADIX + + i_tdata[63:0] + i_tdata[63:0] + HEXRADIX + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[63:0] + o_tdata[63:0] + HEXRADIX + + + o_tready + o_tready + + + o_tvalid + o_tvalid + + + + axi_fast_extract + label + HEXRADIX + + i_tdata[63:0] + i_tdata[63:0] + HEXRADIX + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[63:0] + o_tdata[63:0] + HEXRADIX + + + o_tlast + o_tlast + + + o_tready + o_tready + + + o_tvalid + o_tvalid + + + + dram_fifo_output + label + HEXRADIX + + o_tdata[63:0] + o_tdata[63:0] + HEXRADIX + + + o_tlast + o_tlast + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + diff --git a/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/run_isim b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/run_isim new file mode 100755 index 000000000..46141fcae --- /dev/null +++ b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/run_isim @@ -0,0 +1,19 @@ +/bin/rm -r isim + +vlogcomp -work work ${XILINX}/verilog/src/glbl.v + +vlogcomp -work work --sourcelibext .v \ + --sourcelibdir ../../../lib/axi \ + --sourcelibdir ../../../lib/fifo \ + --sourcelibdir ../../../lib/control \ + --sourcelibdir ../../../top/x300/coregen \ + ../../../lib/axi/axi_dram_fifo_tb.v + + + +fuse work.axi_dram_fifo_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_dram_fifo_tb.exe + +# run the simulation scrip +./axi_dram_fifo_tb.exe -gui #-tclbatch simcmds.tcl + + diff --git a/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/simulation_script.v b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/simulation_script.v new file mode 100644 index 000000000..4a94820b7 --- /dev/null +++ b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/simulation_script.v @@ -0,0 +1,91 @@ +wire fail; +wire done; +reg start; +reg [15:0] control; + + + +axi_chdr_test_pattern axi_chdr_test_pattern_i + ( + .clk(clk), + .reset(reset), + + // + // CHDR friendly AXI stream input + // + .i_tdata(i_tdata), + .i_tlast(i_tlast), + .i_tvalid(i_tvalid), + .i_tready(i_tready), + // + // CHDR friendly AXI Stream output + // + .o_tdata(o_tdata), + .o_tlast(o_tlast), + .o_tvalid(o_tvalid), + .o_tready(o_tready), + // + // Test flags + // + .start(start), + .fail(fail), + .done(done), + .control(control) + ); + + + always + #5 clk <= ~clk; + + initial + begin + clk <= 1'b0; + reset <= 1'b0; + clear <= 1'b0; + start <= 1'b0; + control <= 16'h0101; + + + @(negedge clk); + reset <= 1'b1; + repeat(10) @(negedge clk); + reset <= 1'b0; + repeat(10) @(negedge clk); + // Now activate BIST + start <= 1'b1; + + // Wait until simulation is done. + while(!done) + @(negedge clk); + + $display; + + if (fail) + $display("FAILED."); + else + $display("Done 1st pass."); + + @(posedge clk); + start <= 1'b0; + repeat(10) @(negedge clk); + // Now activate BIST + start <= 1'b1; + + // Wait until simulation is done. + while(!done) + @(negedge clk); + + $display; + + if (fail) + $display("FAILED."); + else + $display("PASSED."); + + $finish; + + end + + //initial + // o_tready = 1; + diff --git a/fpga/usrp3/sim/b2x0/sim_b2x0_1/run_isim b/fpga/usrp3/sim/b2x0/sim_b2x0_1/run_isim new file mode 100755 index 000000000..dd9215934 --- /dev/null +++ b/fpga/usrp3/sim/b2x0/sim_b2x0_1/run_isim @@ -0,0 +1,22 @@ +vlogcomp -work work ${XILINX}/verilog/src/glbl.v + +vlogcomp -work work --sourcelibext .v \ + --sourcelibdir ../../../lib/axi \ + --sourcelibdir ../../../lib/fifo \ + --sourcelibdir ../../../lib/control \ + --sourcelibdir ../../../top/b200/coregen \ + --sourcelibdir ../../../top/b200 \ + --sourcelibdir ../../../lib/timing \ + --sourcelibdir ../../../lib/vita \ + --sourcelibdir ../../../lib/packet_proc \ + --sourcelibdir ../../../lib/dsp \ + --sourcelibdir ../../../lib/wishbone \ + --sourcelibdir ../../../lib/gpif2 \ + ../../../top/b200/b200_tb.v + + + +fuse work.b200_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o b200_tb.exe + +# run the simulation scrip +./b200_tb.exe # -gui #-tclbatch simcmds.tcl diff --git a/fpga/usrp3/sim/ddc_chain_x300/dctest/.gitignore b/fpga/usrp3/sim/ddc_chain_x300/dctest/.gitignore new file mode 100644 index 000000000..7826d75e2 --- /dev/null +++ b/fpga/usrp3/sim/ddc_chain_x300/dctest/.gitignore @@ -0,0 +1,4 @@ +fuse* +isim* +*.exe +*.wcfg diff --git a/fpga/usrp3/sim/ddc_chain_x300/dctest/DDC.sav b/fpga/usrp3/sim/ddc_chain_x300/dctest/DDC.sav new file mode 100644 index 000000000..96ec87c67 --- /dev/null +++ b/fpga/usrp3/sim/ddc_chain_x300/dctest/DDC.sav @@ -0,0 +1,101 @@ +[*] +[*] GTKWave Analyzer v3.3.35 (w)1999-2012 BSI +[*] Thu Dec 5 01:04:45 2013 +[*] +[dumpfile] "/home/matt/fpgadev/usrp3/sim/ddc_chain_x300/dctest/ddc_chain_x300_tb.vcd" +[dumpfile_mtime] "Wed Dec 4 23:01:47 2013" +[dumpfile_size] 12968759 +[savefile] "/home/matt/fpgadev/usrp3/sim/ddc_chain_x300/dctest/DDC.sav" +[timestart] 0 +[size] 1600 843 +[pos] -1 -1 +*-22.573410 5990000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] ddc_chain_x300_tb. +[treeopen] ddc_chain_x300_tb.ddc_chain. +[treeopen] ddc_chain_x300_tb.ddc_chain.clip_i. +[sst_width] 231 +[signals_width] 313 +[sst_expanded] 1 +[sst_vpaned_height] 229 +@420 +#{ddc_chain_x300_tb.ddc_chain.i_cic[23:0]} ddc_chain_x300_tb.ddc_chain.i_cic[23] ddc_chain_x300_tb.ddc_chain.i_cic[22] ddc_chain_x300_tb.ddc_chain.i_cic[21] ddc_chain_x300_tb.ddc_chain.i_cic[20] ddc_chain_x300_tb.ddc_chain.i_cic[19] ddc_chain_x300_tb.ddc_chain.i_cic[18] ddc_chain_x300_tb.ddc_chain.i_cic[17] ddc_chain_x300_tb.ddc_chain.i_cic[16] ddc_chain_x300_tb.ddc_chain.i_cic[15] ddc_chain_x300_tb.ddc_chain.i_cic[14] ddc_chain_x300_tb.ddc_chain.i_cic[13] ddc_chain_x300_tb.ddc_chain.i_cic[12] ddc_chain_x300_tb.ddc_chain.i_cic[11] ddc_chain_x300_tb.ddc_chain.i_cic[10] ddc_chain_x300_tb.ddc_chain.i_cic[9] ddc_chain_x300_tb.ddc_chain.i_cic[8] ddc_chain_x300_tb.ddc_chain.i_cic[7] ddc_chain_x300_tb.ddc_chain.i_cic[6] ddc_chain_x300_tb.ddc_chain.i_cic[5] ddc_chain_x300_tb.ddc_chain.i_cic[4] ddc_chain_x300_tb.ddc_chain.i_cic[3] ddc_chain_x300_tb.ddc_chain.i_cic[2] ddc_chain_x300_tb.ddc_chain.i_cic[1] ddc_chain_x300_tb.ddc_chain.i_cic[0] +@28 +ddc_chain_x300_tb.ddc_chain.strobe_cic +@420 +#{ddc_chain_x300_tb.ddc_chain.i_hb1[46:0]} ddc_chain_x300_tb.ddc_chain.i_hb1[46] ddc_chain_x300_tb.ddc_chain.i_hb1[45] ddc_chain_x300_tb.ddc_chain.i_hb1[44] ddc_chain_x300_tb.ddc_chain.i_hb1[43] ddc_chain_x300_tb.ddc_chain.i_hb1[42] ddc_chain_x300_tb.ddc_chain.i_hb1[41] ddc_chain_x300_tb.ddc_chain.i_hb1[40] ddc_chain_x300_tb.ddc_chain.i_hb1[39] ddc_chain_x300_tb.ddc_chain.i_hb1[38] ddc_chain_x300_tb.ddc_chain.i_hb1[37] ddc_chain_x300_tb.ddc_chain.i_hb1[36] ddc_chain_x300_tb.ddc_chain.i_hb1[35] ddc_chain_x300_tb.ddc_chain.i_hb1[34] ddc_chain_x300_tb.ddc_chain.i_hb1[33] ddc_chain_x300_tb.ddc_chain.i_hb1[32] ddc_chain_x300_tb.ddc_chain.i_hb1[31] ddc_chain_x300_tb.ddc_chain.i_hb1[30] ddc_chain_x300_tb.ddc_chain.i_hb1[29] ddc_chain_x300_tb.ddc_chain.i_hb1[28] ddc_chain_x300_tb.ddc_chain.i_hb1[27] ddc_chain_x300_tb.ddc_chain.i_hb1[26] ddc_chain_x300_tb.ddc_chain.i_hb1[25] ddc_chain_x300_tb.ddc_chain.i_hb1[24] ddc_chain_x300_tb.ddc_chain.i_hb1[23] ddc_chain_x300_tb.ddc_chain.i_hb1[22] ddc_chain_x300_tb.ddc_chain.i_hb1[21] ddc_chain_x300_tb.ddc_chain.i_hb1[20] ddc_chain_x300_tb.ddc_chain.i_hb1[19] ddc_chain_x300_tb.ddc_chain.i_hb1[18] ddc_chain_x300_tb.ddc_chain.i_hb1[17] ddc_chain_x300_tb.ddc_chain.i_hb1[16] ddc_chain_x300_tb.ddc_chain.i_hb1[15] ddc_chain_x300_tb.ddc_chain.i_hb1[14] ddc_chain_x300_tb.ddc_chain.i_hb1[13] ddc_chain_x300_tb.ddc_chain.i_hb1[12] ddc_chain_x300_tb.ddc_chain.i_hb1[11] ddc_chain_x300_tb.ddc_chain.i_hb1[10] ddc_chain_x300_tb.ddc_chain.i_hb1[9] ddc_chain_x300_tb.ddc_chain.i_hb1[8] ddc_chain_x300_tb.ddc_chain.i_hb1[7] ddc_chain_x300_tb.ddc_chain.i_hb1[6] ddc_chain_x300_tb.ddc_chain.i_hb1[5] ddc_chain_x300_tb.ddc_chain.i_hb1[4] ddc_chain_x300_tb.ddc_chain.i_hb1[3] ddc_chain_x300_tb.ddc_chain.i_hb1[2] ddc_chain_x300_tb.ddc_chain.i_hb1[1] ddc_chain_x300_tb.ddc_chain.i_hb1[0] +@28 +ddc_chain_x300_tb.ddc_chain.strobe_hb1 +@420 +#{ddc_chain_x300_tb.ddc_chain.i_hb2[46:0]} ddc_chain_x300_tb.ddc_chain.i_hb2[46] ddc_chain_x300_tb.ddc_chain.i_hb2[45] ddc_chain_x300_tb.ddc_chain.i_hb2[44] ddc_chain_x300_tb.ddc_chain.i_hb2[43] ddc_chain_x300_tb.ddc_chain.i_hb2[42] ddc_chain_x300_tb.ddc_chain.i_hb2[41] ddc_chain_x300_tb.ddc_chain.i_hb2[40] ddc_chain_x300_tb.ddc_chain.i_hb2[39] ddc_chain_x300_tb.ddc_chain.i_hb2[38] ddc_chain_x300_tb.ddc_chain.i_hb2[37] ddc_chain_x300_tb.ddc_chain.i_hb2[36] ddc_chain_x300_tb.ddc_chain.i_hb2[35] ddc_chain_x300_tb.ddc_chain.i_hb2[34] ddc_chain_x300_tb.ddc_chain.i_hb2[33] ddc_chain_x300_tb.ddc_chain.i_hb2[32] ddc_chain_x300_tb.ddc_chain.i_hb2[31] ddc_chain_x300_tb.ddc_chain.i_hb2[30] ddc_chain_x300_tb.ddc_chain.i_hb2[29] ddc_chain_x300_tb.ddc_chain.i_hb2[28] ddc_chain_x300_tb.ddc_chain.i_hb2[27] ddc_chain_x300_tb.ddc_chain.i_hb2[26] ddc_chain_x300_tb.ddc_chain.i_hb2[25] ddc_chain_x300_tb.ddc_chain.i_hb2[24] ddc_chain_x300_tb.ddc_chain.i_hb2[23] ddc_chain_x300_tb.ddc_chain.i_hb2[22] ddc_chain_x300_tb.ddc_chain.i_hb2[21] ddc_chain_x300_tb.ddc_chain.i_hb2[20] ddc_chain_x300_tb.ddc_chain.i_hb2[19] ddc_chain_x300_tb.ddc_chain.i_hb2[18] ddc_chain_x300_tb.ddc_chain.i_hb2[17] ddc_chain_x300_tb.ddc_chain.i_hb2[16] ddc_chain_x300_tb.ddc_chain.i_hb2[15] ddc_chain_x300_tb.ddc_chain.i_hb2[14] ddc_chain_x300_tb.ddc_chain.i_hb2[13] ddc_chain_x300_tb.ddc_chain.i_hb2[12] ddc_chain_x300_tb.ddc_chain.i_hb2[11] ddc_chain_x300_tb.ddc_chain.i_hb2[10] ddc_chain_x300_tb.ddc_chain.i_hb2[9] ddc_chain_x300_tb.ddc_chain.i_hb2[8] ddc_chain_x300_tb.ddc_chain.i_hb2[7] ddc_chain_x300_tb.ddc_chain.i_hb2[6] ddc_chain_x300_tb.ddc_chain.i_hb2[5] ddc_chain_x300_tb.ddc_chain.i_hb2[4] ddc_chain_x300_tb.ddc_chain.i_hb2[3] ddc_chain_x300_tb.ddc_chain.i_hb2[2] ddc_chain_x300_tb.ddc_chain.i_hb2[1] ddc_chain_x300_tb.ddc_chain.i_hb2[0] +@28 +ddc_chain_x300_tb.ddc_chain.strobe_hb2 +@420 +#{ddc_chain_x300_tb.ddc_chain.i_hb3[47:0]} ddc_chain_x300_tb.ddc_chain.i_hb3[47] ddc_chain_x300_tb.ddc_chain.i_hb3[46] ddc_chain_x300_tb.ddc_chain.i_hb3[45] ddc_chain_x300_tb.ddc_chain.i_hb3[44] ddc_chain_x300_tb.ddc_chain.i_hb3[43] ddc_chain_x300_tb.ddc_chain.i_hb3[42] ddc_chain_x300_tb.ddc_chain.i_hb3[41] ddc_chain_x300_tb.ddc_chain.i_hb3[40] ddc_chain_x300_tb.ddc_chain.i_hb3[39] ddc_chain_x300_tb.ddc_chain.i_hb3[38] ddc_chain_x300_tb.ddc_chain.i_hb3[37] ddc_chain_x300_tb.ddc_chain.i_hb3[36] ddc_chain_x300_tb.ddc_chain.i_hb3[35] ddc_chain_x300_tb.ddc_chain.i_hb3[34] ddc_chain_x300_tb.ddc_chain.i_hb3[33] ddc_chain_x300_tb.ddc_chain.i_hb3[32] ddc_chain_x300_tb.ddc_chain.i_hb3[31] ddc_chain_x300_tb.ddc_chain.i_hb3[30] ddc_chain_x300_tb.ddc_chain.i_hb3[29] ddc_chain_x300_tb.ddc_chain.i_hb3[28] ddc_chain_x300_tb.ddc_chain.i_hb3[27] ddc_chain_x300_tb.ddc_chain.i_hb3[26] ddc_chain_x300_tb.ddc_chain.i_hb3[25] ddc_chain_x300_tb.ddc_chain.i_hb3[24] ddc_chain_x300_tb.ddc_chain.i_hb3[23] ddc_chain_x300_tb.ddc_chain.i_hb3[22] ddc_chain_x300_tb.ddc_chain.i_hb3[21] ddc_chain_x300_tb.ddc_chain.i_hb3[20] ddc_chain_x300_tb.ddc_chain.i_hb3[19] ddc_chain_x300_tb.ddc_chain.i_hb3[18] ddc_chain_x300_tb.ddc_chain.i_hb3[17] ddc_chain_x300_tb.ddc_chain.i_hb3[16] ddc_chain_x300_tb.ddc_chain.i_hb3[15] ddc_chain_x300_tb.ddc_chain.i_hb3[14] ddc_chain_x300_tb.ddc_chain.i_hb3[13] ddc_chain_x300_tb.ddc_chain.i_hb3[12] ddc_chain_x300_tb.ddc_chain.i_hb3[11] ddc_chain_x300_tb.ddc_chain.i_hb3[10] ddc_chain_x300_tb.ddc_chain.i_hb3[9] ddc_chain_x300_tb.ddc_chain.i_hb3[8] ddc_chain_x300_tb.ddc_chain.i_hb3[7] ddc_chain_x300_tb.ddc_chain.i_hb3[6] ddc_chain_x300_tb.ddc_chain.i_hb3[5] ddc_chain_x300_tb.ddc_chain.i_hb3[4] ddc_chain_x300_tb.ddc_chain.i_hb3[3] ddc_chain_x300_tb.ddc_chain.i_hb3[2] ddc_chain_x300_tb.ddc_chain.i_hb3[1] ddc_chain_x300_tb.ddc_chain.i_hb3[0] +@28 +ddc_chain_x300_tb.ddc_chain.strobe_hb3 +@420 +ddc_chain_x300_tb.ddc_chain.i_unscaled[23:0] +#{ddc_chain_x300_tb.ddc_chain.i_scaled[42:0]} ddc_chain_x300_tb.ddc_chain.i_scaled[42] ddc_chain_x300_tb.ddc_chain.i_scaled[41] ddc_chain_x300_tb.ddc_chain.i_scaled[40] ddc_chain_x300_tb.ddc_chain.i_scaled[39] ddc_chain_x300_tb.ddc_chain.i_scaled[38] ddc_chain_x300_tb.ddc_chain.i_scaled[37] ddc_chain_x300_tb.ddc_chain.i_scaled[36] ddc_chain_x300_tb.ddc_chain.i_scaled[35] ddc_chain_x300_tb.ddc_chain.i_scaled[34] ddc_chain_x300_tb.ddc_chain.i_scaled[33] ddc_chain_x300_tb.ddc_chain.i_scaled[32] ddc_chain_x300_tb.ddc_chain.i_scaled[31] ddc_chain_x300_tb.ddc_chain.i_scaled[30] ddc_chain_x300_tb.ddc_chain.i_scaled[29] ddc_chain_x300_tb.ddc_chain.i_scaled[28] ddc_chain_x300_tb.ddc_chain.i_scaled[27] ddc_chain_x300_tb.ddc_chain.i_scaled[26] ddc_chain_x300_tb.ddc_chain.i_scaled[25] ddc_chain_x300_tb.ddc_chain.i_scaled[24] ddc_chain_x300_tb.ddc_chain.i_scaled[23] ddc_chain_x300_tb.ddc_chain.i_scaled[22] ddc_chain_x300_tb.ddc_chain.i_scaled[21] ddc_chain_x300_tb.ddc_chain.i_scaled[20] ddc_chain_x300_tb.ddc_chain.i_scaled[19] ddc_chain_x300_tb.ddc_chain.i_scaled[18] ddc_chain_x300_tb.ddc_chain.i_scaled[17] ddc_chain_x300_tb.ddc_chain.i_scaled[16] ddc_chain_x300_tb.ddc_chain.i_scaled[15] ddc_chain_x300_tb.ddc_chain.i_scaled[14] ddc_chain_x300_tb.ddc_chain.i_scaled[13] ddc_chain_x300_tb.ddc_chain.i_scaled[12] ddc_chain_x300_tb.ddc_chain.i_scaled[11] ddc_chain_x300_tb.ddc_chain.i_scaled[10] ddc_chain_x300_tb.ddc_chain.i_scaled[9] ddc_chain_x300_tb.ddc_chain.i_scaled[8] ddc_chain_x300_tb.ddc_chain.i_scaled[7] ddc_chain_x300_tb.ddc_chain.i_scaled[6] ddc_chain_x300_tb.ddc_chain.i_scaled[5] ddc_chain_x300_tb.ddc_chain.i_scaled[4] ddc_chain_x300_tb.ddc_chain.i_scaled[3] ddc_chain_x300_tb.ddc_chain.i_scaled[2] ddc_chain_x300_tb.ddc_chain.i_scaled[1] ddc_chain_x300_tb.ddc_chain.i_scaled[0] +@200 +- +@8420 +#{ddc_chain_x300_tb.ddc_chain.i_cic[23:0]} ddc_chain_x300_tb.ddc_chain.i_cic[23] ddc_chain_x300_tb.ddc_chain.i_cic[22] ddc_chain_x300_tb.ddc_chain.i_cic[21] ddc_chain_x300_tb.ddc_chain.i_cic[20] ddc_chain_x300_tb.ddc_chain.i_cic[19] ddc_chain_x300_tb.ddc_chain.i_cic[18] ddc_chain_x300_tb.ddc_chain.i_cic[17] ddc_chain_x300_tb.ddc_chain.i_cic[16] ddc_chain_x300_tb.ddc_chain.i_cic[15] ddc_chain_x300_tb.ddc_chain.i_cic[14] ddc_chain_x300_tb.ddc_chain.i_cic[13] ddc_chain_x300_tb.ddc_chain.i_cic[12] ddc_chain_x300_tb.ddc_chain.i_cic[11] ddc_chain_x300_tb.ddc_chain.i_cic[10] ddc_chain_x300_tb.ddc_chain.i_cic[9] ddc_chain_x300_tb.ddc_chain.i_cic[8] ddc_chain_x300_tb.ddc_chain.i_cic[7] ddc_chain_x300_tb.ddc_chain.i_cic[6] ddc_chain_x300_tb.ddc_chain.i_cic[5] ddc_chain_x300_tb.ddc_chain.i_cic[4] ddc_chain_x300_tb.ddc_chain.i_cic[3] ddc_chain_x300_tb.ddc_chain.i_cic[2] ddc_chain_x300_tb.ddc_chain.i_cic[1] ddc_chain_x300_tb.ddc_chain.i_cic[0] +@20000 +- +@8420 +#{ddc_chain_x300_tb.ddc_chain.i_hb1[46:0]} ddc_chain_x300_tb.ddc_chain.i_hb1[46] ddc_chain_x300_tb.ddc_chain.i_hb1[45] ddc_chain_x300_tb.ddc_chain.i_hb1[44] ddc_chain_x300_tb.ddc_chain.i_hb1[43] ddc_chain_x300_tb.ddc_chain.i_hb1[42] ddc_chain_x300_tb.ddc_chain.i_hb1[41] ddc_chain_x300_tb.ddc_chain.i_hb1[40] ddc_chain_x300_tb.ddc_chain.i_hb1[39] ddc_chain_x300_tb.ddc_chain.i_hb1[38] ddc_chain_x300_tb.ddc_chain.i_hb1[37] ddc_chain_x300_tb.ddc_chain.i_hb1[36] ddc_chain_x300_tb.ddc_chain.i_hb1[35] ddc_chain_x300_tb.ddc_chain.i_hb1[34] ddc_chain_x300_tb.ddc_chain.i_hb1[33] ddc_chain_x300_tb.ddc_chain.i_hb1[32] ddc_chain_x300_tb.ddc_chain.i_hb1[31] ddc_chain_x300_tb.ddc_chain.i_hb1[30] ddc_chain_x300_tb.ddc_chain.i_hb1[29] ddc_chain_x300_tb.ddc_chain.i_hb1[28] ddc_chain_x300_tb.ddc_chain.i_hb1[27] ddc_chain_x300_tb.ddc_chain.i_hb1[26] ddc_chain_x300_tb.ddc_chain.i_hb1[25] ddc_chain_x300_tb.ddc_chain.i_hb1[24] ddc_chain_x300_tb.ddc_chain.i_hb1[23] ddc_chain_x300_tb.ddc_chain.i_hb1[22] ddc_chain_x300_tb.ddc_chain.i_hb1[21] ddc_chain_x300_tb.ddc_chain.i_hb1[20] ddc_chain_x300_tb.ddc_chain.i_hb1[19] ddc_chain_x300_tb.ddc_chain.i_hb1[18] ddc_chain_x300_tb.ddc_chain.i_hb1[17] ddc_chain_x300_tb.ddc_chain.i_hb1[16] ddc_chain_x300_tb.ddc_chain.i_hb1[15] ddc_chain_x300_tb.ddc_chain.i_hb1[14] ddc_chain_x300_tb.ddc_chain.i_hb1[13] ddc_chain_x300_tb.ddc_chain.i_hb1[12] ddc_chain_x300_tb.ddc_chain.i_hb1[11] ddc_chain_x300_tb.ddc_chain.i_hb1[10] ddc_chain_x300_tb.ddc_chain.i_hb1[9] ddc_chain_x300_tb.ddc_chain.i_hb1[8] ddc_chain_x300_tb.ddc_chain.i_hb1[7] ddc_chain_x300_tb.ddc_chain.i_hb1[6] ddc_chain_x300_tb.ddc_chain.i_hb1[5] ddc_chain_x300_tb.ddc_chain.i_hb1[4] ddc_chain_x300_tb.ddc_chain.i_hb1[3] ddc_chain_x300_tb.ddc_chain.i_hb1[2] ddc_chain_x300_tb.ddc_chain.i_hb1[1] ddc_chain_x300_tb.ddc_chain.i_hb1[0] +@20000 +- +@8420 +#{ddc_chain_x300_tb.ddc_chain.i_hb2[46:0]} ddc_chain_x300_tb.ddc_chain.i_hb2[46] ddc_chain_x300_tb.ddc_chain.i_hb2[45] ddc_chain_x300_tb.ddc_chain.i_hb2[44] ddc_chain_x300_tb.ddc_chain.i_hb2[43] ddc_chain_x300_tb.ddc_chain.i_hb2[42] ddc_chain_x300_tb.ddc_chain.i_hb2[41] ddc_chain_x300_tb.ddc_chain.i_hb2[40] ddc_chain_x300_tb.ddc_chain.i_hb2[39] ddc_chain_x300_tb.ddc_chain.i_hb2[38] ddc_chain_x300_tb.ddc_chain.i_hb2[37] ddc_chain_x300_tb.ddc_chain.i_hb2[36] ddc_chain_x300_tb.ddc_chain.i_hb2[35] ddc_chain_x300_tb.ddc_chain.i_hb2[34] ddc_chain_x300_tb.ddc_chain.i_hb2[33] ddc_chain_x300_tb.ddc_chain.i_hb2[32] ddc_chain_x300_tb.ddc_chain.i_hb2[31] ddc_chain_x300_tb.ddc_chain.i_hb2[30] ddc_chain_x300_tb.ddc_chain.i_hb2[29] ddc_chain_x300_tb.ddc_chain.i_hb2[28] ddc_chain_x300_tb.ddc_chain.i_hb2[27] ddc_chain_x300_tb.ddc_chain.i_hb2[26] ddc_chain_x300_tb.ddc_chain.i_hb2[25] ddc_chain_x300_tb.ddc_chain.i_hb2[24] ddc_chain_x300_tb.ddc_chain.i_hb2[23] ddc_chain_x300_tb.ddc_chain.i_hb2[22] ddc_chain_x300_tb.ddc_chain.i_hb2[21] ddc_chain_x300_tb.ddc_chain.i_hb2[20] ddc_chain_x300_tb.ddc_chain.i_hb2[19] ddc_chain_x300_tb.ddc_chain.i_hb2[18] ddc_chain_x300_tb.ddc_chain.i_hb2[17] ddc_chain_x300_tb.ddc_chain.i_hb2[16] ddc_chain_x300_tb.ddc_chain.i_hb2[15] ddc_chain_x300_tb.ddc_chain.i_hb2[14] ddc_chain_x300_tb.ddc_chain.i_hb2[13] ddc_chain_x300_tb.ddc_chain.i_hb2[12] ddc_chain_x300_tb.ddc_chain.i_hb2[11] ddc_chain_x300_tb.ddc_chain.i_hb2[10] ddc_chain_x300_tb.ddc_chain.i_hb2[9] ddc_chain_x300_tb.ddc_chain.i_hb2[8] ddc_chain_x300_tb.ddc_chain.i_hb2[7] ddc_chain_x300_tb.ddc_chain.i_hb2[6] ddc_chain_x300_tb.ddc_chain.i_hb2[5] ddc_chain_x300_tb.ddc_chain.i_hb2[4] ddc_chain_x300_tb.ddc_chain.i_hb2[3] ddc_chain_x300_tb.ddc_chain.i_hb2[2] ddc_chain_x300_tb.ddc_chain.i_hb2[1] ddc_chain_x300_tb.ddc_chain.i_hb2[0] +@20000 +- +@8420 +#{ddc_chain_x300_tb.ddc_chain.i_hb3[47:0]} ddc_chain_x300_tb.ddc_chain.i_hb3[47] ddc_chain_x300_tb.ddc_chain.i_hb3[46] ddc_chain_x300_tb.ddc_chain.i_hb3[45] ddc_chain_x300_tb.ddc_chain.i_hb3[44] ddc_chain_x300_tb.ddc_chain.i_hb3[43] ddc_chain_x300_tb.ddc_chain.i_hb3[42] ddc_chain_x300_tb.ddc_chain.i_hb3[41] ddc_chain_x300_tb.ddc_chain.i_hb3[40] ddc_chain_x300_tb.ddc_chain.i_hb3[39] ddc_chain_x300_tb.ddc_chain.i_hb3[38] ddc_chain_x300_tb.ddc_chain.i_hb3[37] ddc_chain_x300_tb.ddc_chain.i_hb3[36] ddc_chain_x300_tb.ddc_chain.i_hb3[35] ddc_chain_x300_tb.ddc_chain.i_hb3[34] ddc_chain_x300_tb.ddc_chain.i_hb3[33] ddc_chain_x300_tb.ddc_chain.i_hb3[32] ddc_chain_x300_tb.ddc_chain.i_hb3[31] ddc_chain_x300_tb.ddc_chain.i_hb3[30] ddc_chain_x300_tb.ddc_chain.i_hb3[29] ddc_chain_x300_tb.ddc_chain.i_hb3[28] ddc_chain_x300_tb.ddc_chain.i_hb3[27] ddc_chain_x300_tb.ddc_chain.i_hb3[26] ddc_chain_x300_tb.ddc_chain.i_hb3[25] ddc_chain_x300_tb.ddc_chain.i_hb3[24] ddc_chain_x300_tb.ddc_chain.i_hb3[23] ddc_chain_x300_tb.ddc_chain.i_hb3[22] ddc_chain_x300_tb.ddc_chain.i_hb3[21] ddc_chain_x300_tb.ddc_chain.i_hb3[20] ddc_chain_x300_tb.ddc_chain.i_hb3[19] ddc_chain_x300_tb.ddc_chain.i_hb3[18] ddc_chain_x300_tb.ddc_chain.i_hb3[17] ddc_chain_x300_tb.ddc_chain.i_hb3[16] ddc_chain_x300_tb.ddc_chain.i_hb3[15] ddc_chain_x300_tb.ddc_chain.i_hb3[14] ddc_chain_x300_tb.ddc_chain.i_hb3[13] ddc_chain_x300_tb.ddc_chain.i_hb3[12] ddc_chain_x300_tb.ddc_chain.i_hb3[11] ddc_chain_x300_tb.ddc_chain.i_hb3[10] ddc_chain_x300_tb.ddc_chain.i_hb3[9] ddc_chain_x300_tb.ddc_chain.i_hb3[8] ddc_chain_x300_tb.ddc_chain.i_hb3[7] ddc_chain_x300_tb.ddc_chain.i_hb3[6] ddc_chain_x300_tb.ddc_chain.i_hb3[5] ddc_chain_x300_tb.ddc_chain.i_hb3[4] ddc_chain_x300_tb.ddc_chain.i_hb3[3] ddc_chain_x300_tb.ddc_chain.i_hb3[2] ddc_chain_x300_tb.ddc_chain.i_hb3[1] ddc_chain_x300_tb.ddc_chain.i_hb3[0] +@20000 +- +@8420 +ddc_chain_x300_tb.ddc_chain.i_unscaled[23:0] +@20000 +- +@8420 +#{ddc_chain_x300_tb.ddc_chain.i_scaled[42:0]} ddc_chain_x300_tb.ddc_chain.i_scaled[42] ddc_chain_x300_tb.ddc_chain.i_scaled[41] ddc_chain_x300_tb.ddc_chain.i_scaled[40] ddc_chain_x300_tb.ddc_chain.i_scaled[39] ddc_chain_x300_tb.ddc_chain.i_scaled[38] ddc_chain_x300_tb.ddc_chain.i_scaled[37] ddc_chain_x300_tb.ddc_chain.i_scaled[36] ddc_chain_x300_tb.ddc_chain.i_scaled[35] ddc_chain_x300_tb.ddc_chain.i_scaled[34] ddc_chain_x300_tb.ddc_chain.i_scaled[33] ddc_chain_x300_tb.ddc_chain.i_scaled[32] ddc_chain_x300_tb.ddc_chain.i_scaled[31] ddc_chain_x300_tb.ddc_chain.i_scaled[30] ddc_chain_x300_tb.ddc_chain.i_scaled[29] ddc_chain_x300_tb.ddc_chain.i_scaled[28] ddc_chain_x300_tb.ddc_chain.i_scaled[27] ddc_chain_x300_tb.ddc_chain.i_scaled[26] ddc_chain_x300_tb.ddc_chain.i_scaled[25] ddc_chain_x300_tb.ddc_chain.i_scaled[24] ddc_chain_x300_tb.ddc_chain.i_scaled[23] ddc_chain_x300_tb.ddc_chain.i_scaled[22] ddc_chain_x300_tb.ddc_chain.i_scaled[21] ddc_chain_x300_tb.ddc_chain.i_scaled[20] ddc_chain_x300_tb.ddc_chain.i_scaled[19] ddc_chain_x300_tb.ddc_chain.i_scaled[18] ddc_chain_x300_tb.ddc_chain.i_scaled[17] ddc_chain_x300_tb.ddc_chain.i_scaled[16] ddc_chain_x300_tb.ddc_chain.i_scaled[15] ddc_chain_x300_tb.ddc_chain.i_scaled[14] ddc_chain_x300_tb.ddc_chain.i_scaled[13] ddc_chain_x300_tb.ddc_chain.i_scaled[12] ddc_chain_x300_tb.ddc_chain.i_scaled[11] ddc_chain_x300_tb.ddc_chain.i_scaled[10] ddc_chain_x300_tb.ddc_chain.i_scaled[9] ddc_chain_x300_tb.ddc_chain.i_scaled[8] ddc_chain_x300_tb.ddc_chain.i_scaled[7] ddc_chain_x300_tb.ddc_chain.i_scaled[6] ddc_chain_x300_tb.ddc_chain.i_scaled[5] ddc_chain_x300_tb.ddc_chain.i_scaled[4] ddc_chain_x300_tb.ddc_chain.i_scaled[3] ddc_chain_x300_tb.ddc_chain.i_scaled[2] ddc_chain_x300_tb.ddc_chain.i_scaled[1] ddc_chain_x300_tb.ddc_chain.i_scaled[0] +@20000 +- +@8420 +#{ddc_chain_x300_tb.ddc_chain.i_clip[23:0]} ddc_chain_x300_tb.ddc_chain.i_clip[23] ddc_chain_x300_tb.ddc_chain.i_clip[22] ddc_chain_x300_tb.ddc_chain.i_clip[21] ddc_chain_x300_tb.ddc_chain.i_clip[20] ddc_chain_x300_tb.ddc_chain.i_clip[19] ddc_chain_x300_tb.ddc_chain.i_clip[18] ddc_chain_x300_tb.ddc_chain.i_clip[17] ddc_chain_x300_tb.ddc_chain.i_clip[16] ddc_chain_x300_tb.ddc_chain.i_clip[15] ddc_chain_x300_tb.ddc_chain.i_clip[14] ddc_chain_x300_tb.ddc_chain.i_clip[13] ddc_chain_x300_tb.ddc_chain.i_clip[12] ddc_chain_x300_tb.ddc_chain.i_clip[11] ddc_chain_x300_tb.ddc_chain.i_clip[10] ddc_chain_x300_tb.ddc_chain.i_clip[9] ddc_chain_x300_tb.ddc_chain.i_clip[8] ddc_chain_x300_tb.ddc_chain.i_clip[7] ddc_chain_x300_tb.ddc_chain.i_clip[6] ddc_chain_x300_tb.ddc_chain.i_clip[5] ddc_chain_x300_tb.ddc_chain.i_clip[4] ddc_chain_x300_tb.ddc_chain.i_clip[3] ddc_chain_x300_tb.ddc_chain.i_clip[2] ddc_chain_x300_tb.ddc_chain.i_clip[1] ddc_chain_x300_tb.ddc_chain.i_clip[0] +@20000 +- +@28 +ddc_chain_x300_tb.ddc_chain.strobe_unscaled +ddc_chain_x300_tb.ddc_chain.strobe_scaled +ddc_chain_x300_tb.ddc_chain.strobe_clip +ddc_chain_x300_tb.ddc_chain.strobe +ddc_chain_x300_tb.ddc_chain.clip_i.clip.overflow +@8420 +#{ddc_chain_x300_tb.ddc_chain.round_i.out[15:0]} ddc_chain_x300_tb.ddc_chain.round_i.out[15] ddc_chain_x300_tb.ddc_chain.round_i.out[14] ddc_chain_x300_tb.ddc_chain.round_i.out[13] ddc_chain_x300_tb.ddc_chain.round_i.out[12] ddc_chain_x300_tb.ddc_chain.round_i.out[11] ddc_chain_x300_tb.ddc_chain.round_i.out[10] ddc_chain_x300_tb.ddc_chain.round_i.out[9] ddc_chain_x300_tb.ddc_chain.round_i.out[8] ddc_chain_x300_tb.ddc_chain.round_i.out[7] ddc_chain_x300_tb.ddc_chain.round_i.out[6] ddc_chain_x300_tb.ddc_chain.round_i.out[5] ddc_chain_x300_tb.ddc_chain.round_i.out[4] ddc_chain_x300_tb.ddc_chain.round_i.out[3] ddc_chain_x300_tb.ddc_chain.round_i.out[2] ddc_chain_x300_tb.ddc_chain.round_i.out[1] ddc_chain_x300_tb.ddc_chain.round_i.out[0] +@20000 +- +- +- +- +- +- +- +- +- +- +- +@8420 +#{ddc_chain_x300_tb.ddc_chain.i_cordic[24:0]} ddc_chain_x300_tb.ddc_chain.i_cordic[24] ddc_chain_x300_tb.ddc_chain.i_cordic[23] ddc_chain_x300_tb.ddc_chain.i_cordic[22] ddc_chain_x300_tb.ddc_chain.i_cordic[21] ddc_chain_x300_tb.ddc_chain.i_cordic[20] ddc_chain_x300_tb.ddc_chain.i_cordic[19] ddc_chain_x300_tb.ddc_chain.i_cordic[18] ddc_chain_x300_tb.ddc_chain.i_cordic[17] ddc_chain_x300_tb.ddc_chain.i_cordic[16] ddc_chain_x300_tb.ddc_chain.i_cordic[15] ddc_chain_x300_tb.ddc_chain.i_cordic[14] ddc_chain_x300_tb.ddc_chain.i_cordic[13] ddc_chain_x300_tb.ddc_chain.i_cordic[12] ddc_chain_x300_tb.ddc_chain.i_cordic[11] ddc_chain_x300_tb.ddc_chain.i_cordic[10] ddc_chain_x300_tb.ddc_chain.i_cordic[9] ddc_chain_x300_tb.ddc_chain.i_cordic[8] ddc_chain_x300_tb.ddc_chain.i_cordic[7] ddc_chain_x300_tb.ddc_chain.i_cordic[6] ddc_chain_x300_tb.ddc_chain.i_cordic[5] ddc_chain_x300_tb.ddc_chain.i_cordic[4] ddc_chain_x300_tb.ddc_chain.i_cordic[3] ddc_chain_x300_tb.ddc_chain.i_cordic[2] ddc_chain_x300_tb.ddc_chain.i_cordic[1] ddc_chain_x300_tb.ddc_chain.i_cordic[0] +@20000 +- +- +@8420 +#{ddc_chain_x300_tb.ddc_chain.i_cordic_clip[23:0]} ddc_chain_x300_tb.ddc_chain.i_cordic_clip[23] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[22] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[21] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[20] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[19] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[18] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[17] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[16] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[15] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[14] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[13] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[12] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[11] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[10] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[9] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[8] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[7] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[6] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[5] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[4] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[3] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[2] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[1] ddc_chain_x300_tb.ddc_chain.i_cordic_clip[0] +@20000 +- +@20001 +- +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/fpga/usrp3/sim/ddc_chain_x300/dctest/run_isim b/fpga/usrp3/sim/ddc_chain_x300/dctest/run_isim new file mode 100755 index 000000000..6a3e532c6 --- /dev/null +++ b/fpga/usrp3/sim/ddc_chain_x300/dctest/run_isim @@ -0,0 +1,17 @@ +rm -rf fuse* *.exe isim +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +vlogcomp -work work --sourcelibext .v \ + --sourcelibdir ../../../lib/dsp \ + --sourcelibdir ../../../lib/control \ + --sourcelibdir ../../../top/x300/coregen_dsp \ + --sourcelibdir ${XILINX}/verilog/src/unimacro \ + ../../../lib/dsp/ddc_chain_x300_tb.v + + + +fuse work.ddc_chain_x300_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o ddc_chain_x300_tb.exe + +# run the simulation scrip +./ddc_chain_x300_tb.exe -tclbatch simcmds.tcl # -gui + + diff --git a/fpga/usrp3/sim/ddc_chain_x300/dctest/simcmds.tcl b/fpga/usrp3/sim/ddc_chain_x300/dctest/simcmds.tcl new file mode 100755 index 000000000..3dcfd3eaf --- /dev/null +++ b/fpga/usrp3/sim/ddc_chain_x300/dctest/simcmds.tcl @@ -0,0 +1,9 @@ +# file: simcmds.tcl + +# create the simulation script +#vcd dumpfile isim.vcd +#vcd dumpvars -m /bus_clk_gen_tb -l 0 +#wave add / +run 1 s +quit + diff --git a/fpga/usrp3/sim/duc_chain_x300/dctest/.gitignore b/fpga/usrp3/sim/duc_chain_x300/dctest/.gitignore new file mode 100644 index 000000000..7826d75e2 --- /dev/null +++ b/fpga/usrp3/sim/duc_chain_x300/dctest/.gitignore @@ -0,0 +1,4 @@ +fuse* +isim* +*.exe +*.wcfg diff --git a/fpga/usrp3/sim/duc_chain_x300/dctest/run_isim b/fpga/usrp3/sim/duc_chain_x300/dctest/run_isim new file mode 100755 index 000000000..0672e32a6 --- /dev/null +++ b/fpga/usrp3/sim/duc_chain_x300/dctest/run_isim @@ -0,0 +1,17 @@ +rm -rf fuse* *.exe isim +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +vlogcomp -work work --sourcelibext .v \ + --sourcelibdir ../../../lib/dsp \ + --sourcelibdir ../../../lib/control \ + --sourcelibdir ../../../top/x300/coregen_dsp \ + --sourcelibdir ${XILINX}/verilog/src/unimacro \ + ../../../lib/dsp/duc_chain_x300_tb.v + + + +fuse work.duc_chain_x300_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o duc_chain_x300_tb.exe + +# run the simulation scrip +./duc_chain_x300_tb.exe -tclbatch simcmds.tcl # -gui + + diff --git a/fpga/usrp3/sim/duc_chain_x300/dctest/simcmds.tcl b/fpga/usrp3/sim/duc_chain_x300/dctest/simcmds.tcl new file mode 100755 index 000000000..3dcfd3eaf --- /dev/null +++ b/fpga/usrp3/sim/duc_chain_x300/dctest/simcmds.tcl @@ -0,0 +1,9 @@ +# file: simcmds.tcl + +# create the simulation script +#vcd dumpfile isim.vcd +#vcd dumpvars -m /bus_clk_gen_tb -l 0 +#wave add / +run 1 s +quit + diff --git a/fpga/usrp3/sim/math.v b/fpga/usrp3/sim/math.v new file mode 100644 index 000000000..cca10f60a --- /dev/null +++ b/fpga/usrp3/sim/math.v @@ -0,0 +1,276 @@ +// All code take from the HDLCon paper: +// "Verilog Transcendental Functions for Numerical Testbenches" +// +// Authored by: +// Mark G. Arnold marnold@co.umist.ac.uk, +// Colin Walter c.walter@co.umist.ac.uk +// Freddy Engineer freddy.engineer@xilinx.com +// + + + +// The sine function is approximated with a polynomial which works +// for -π/2 < x < π/2. (This polynomial, by itself, was used as a +// Verilog example in [2]; unfortunately there was a typo with the +// coefficients. The correct coefficients together with an error +// analysis are given in [3].) For arguments outside of -π/2 < x < π/2, +// the identities sin(x) = -sin(-x) and sin(x) = -sin(x-π) allow the +// argument to be shifted to be within this range. The latter identity +// can be applied repeatedly. Doing so could cause inaccuracies for +// very large arguments, but in practice the errors are acceptable +// if the Verilog simulator uses double-precision floating point. + +function real sin; + input x; + real x; + real x1,y,y2,y3,y5,y7,sum,sign; + begin + sign = 1.0; + x1 = x; + if (x1<0) + begin + x1 = -x1; + sign = -1.0; + end + while (x1 > 3.14159265/2.0) + begin + x1 = x1 - 3.14159265; + sign = -1.0*sign; + end + y = x1*2/3.14159265; + y2 = y*y; + y3 = y*y2; + y5 = y3*y2; + y7 = y5*y2; + sum = 1.570794*y - 0.645962*y3 + + 0.079692*y5 - 0.004681712*y7; + sin = sign*sum; + end +endfunction + +// The cosine and tangent are computed from the sine: +function real cos; + input x; + real x; + begin + cos = sin(x + 3.14159265/2.0); + end +endfunction + + +function real tan; + input x; + real x; + begin + tan = sin(x)/cos(x); + end +endfunction + +// The base-two exponential (antilogarithm) function, 2x, is computed by +// examining the bits of the argument, and for those bits of the argument +// that are 1, multiplying the result by the corresponding power of a base +// very close to one. For example, if there were only two bits after +// the radix point, the base would be the fourth root of two, 1.1892. +// This number is squared on each iteration: 1.4142, 2.0, 4.0, 16.0. +// So, if x is 101.112, the function computes 25.75 as 1.1892*1.4142*2.0*16.0 = 53.81. +// In general, for k bits of precision, the base would be the 2k root of two. +// Since we need about 23 bits of accuracy for our function, the base we use +// is the 223 root of two, 1.000000082629586. This constant poses a problem +// to some Verilog parsers, so we construct it in two parts. The following +// function computes the appropriate root of two by repeatedly squaring this constant: + +function real rootof2; + input n; + integer n; + real power; + integer i; + + begin + power = 0.82629586; + power = power / 10000000.0; + power = power + 1.0; + i = -23; + + if (n >= 1) + begin + power = 2.0; + i = 0; + end + + for (i=i; i< n; i=i+1) + begin + power = power * power; + end + rootof2 = power; + end +endfunction // if + +// This function is used for computing both antilogarithms and logarithms. +// This routine is never called with n less than -23, thus no validity check +// need be performed. When n>0, the exponentiation begins with 2.0 in order to +// improve accuracy. +// For computing the antilogarithm, we make use of the identity ex = 2x/ln(2), +// and then proceed as in the example above. The constant 1/ln(2) = 1.44269504. +// Here is the natural exponential function: + +function real exp; + input x; + real x; + real x1,power,prod; + integer i; + begin + x1 = fabs(x)*1.44269504; + if (x1 > 255.0) + begin + exp = 0.0; + if (x>0.0) + begin + $display("exp illegal argument:",x); + $stop; + end + end + else + begin + prod = 1.0; + power = 128.0; + for (i=7; i>=-23; i=i-1) + begin + if (x1 > power) + begin + prod = prod * rootof2(i); + x1 = x1 - power; + end + power = power / 2.0; + end + if (x < 0) + exp = 1.0/prod; + else + exp = prod; + end + end +endfunction // fabs + +// The function prints an error message if the argument is too large +// (greater than about 180). All error messages in this package are +// followed by $stop to allow the designer to use the debugging +// features of Verilog to determine the cause of the error, and +// possibly to resume the simulation. An argument of less than +// about –180 simply returns zero with no error. The main loop +// assumes a positive argument. A negative argument is computed as 1/e-x. +// The logarithm function prints an error message for arguments less +// than or equal to zero because the real-valued logarithm is not +// defined for such arguments. The loop here requires an argument +// greater than or equal to one. For arguments between zero and one, +// this code uses the identity ln(1/x) = -ln(x). + +function real log; + input x; + real x; + real re,log2; + integer i; + begin + if (x <= 0.0) + begin + $display("log illegal argument:",x); + $stop; + log = 0; + end + else + begin + if (x<1.0) + re = 1.0/x; + else + re = x; + log2 = 0.0; + for (i=7; i>=-23; i=i-1) + begin + if (re > rootof2(i)) + begin + re = re/rootof2(i); + log2 = 2.0*log2 + 1.0; + end + else + log2 = log2*2; + end + if (x < 1.0) + log = -log2/12102203.16; + else + log = log2/12102203.16; + end + end +endfunction + +// The code only divides re by rootof2(i) when the re is larger +// (so that the quotient will be greater than 1.0). Each time +// such a division occurs, a bit that is 1 is recorded in the +// whole number result (multiply by 2 and add 1). Otherwise, +// a zero is recorded (multiply by 2). At the end of the loop, +// log2 will contain 223 log2|x|. We divide by 223 and use the +// identity ln(x) = log2(x)/log2(e). The constant 12102203.16 is 223 log2(e). +// The log(x) and exp(x)functions are used to implement the pow(x,y) and sqrt(x) functions: + +function real pow; + input x,y; + real x,y; + begin + if (x<0.0) + begin + $display("pow illegal argument:",x); + $stop; + end + pow = exp(y*log(x)); + end +endfunction + +function real sqrt; + input x; + real x; + begin + if (x<0.0) + begin + $display("sqrt illegal argument:",x); + $stop; + end + sqrt = exp(0.5*log(x)); + end +endfunction + +// The arctangent [3,7] is computed as a continued fraction, +// using the identities tan-1(x) = -tan-1(-x) and tan-1(x) = π/2 - tan-1(1/x) +// to reduce the range to 0 < x < 1: + +function real atan; + input x; + real x; + real x1,x2,sign,bias; + real d3,s3; + begin + sign = 1.0; + bias = 0.0; + x1 = x; + if (x1 < 0.0) + begin + x1 = -x1; + sign = -1.0; + end + if (x1 > 1.0) + begin + x1 = 1.0/x1; + bias = sign*3.14159265/2.0; + sign = -1.0*sign; + end + x2 = x1*x1; + d3 = x2 + 1.44863154; + d3 = 0.26476862 / d3; + s3 = x2 + 3.3163354; + d3 = s3 - d3; + d3 = 7.10676 / d3; + s3 = 6.762139 + x2; + d3 = s3 - d3; + d3 = 3.7092563 / d3; + d3 = d3 + 0.17465544; + atan = sign*x1*d3+bias; + end +endfunction + +// The other functions (asin(x) and acos(x)) are computed from the arctangent. diff --git a/fpga/usrp3/sim/serial_to_settings/serial_settings_tasks.v b/fpga/usrp3/sim/serial_to_settings/serial_settings_tasks.v new file mode 100644 index 000000000..a9e2c0344 --- /dev/null +++ b/fpga/usrp3/sim/serial_to_settings/serial_settings_tasks.v @@ -0,0 +1,59 @@ + + task serial_settings_transaction; + input [7:0] address; + input [31:0] data; + + integer x; + + begin + scl_r <= 1'b1; + sda_r <= 1'b1; + @(negedge clk); + @(negedge clk); + // Drive SDA low whilst SCL high to signal START + sda_r <= 1'b0; + @(negedge clk); + @(negedge clk); + // Send 8 Address bits MSB first on falling edge of SCL clocks + for (x = 7; x >= 0; x = x - 1) + serial_settings_bit(address[x]); + // Send 32 Data bits MSB first on falling edge of SCL clocks + for (x = 31; x >= 0; x = x - 1) + serial_settings_bit(data[x]); + // Send STOP. + scl_r <= 1'b0; + sda_r <= 1'b0; + @(negedge clk); + @(negedge clk); + @(negedge clk); + @(negedge clk); + scl_r <= 1'b1; + @(negedge clk); + @(negedge clk); + @(negedge clk); + @(negedge clk); + sda_r <= 1'b1; + @(negedge clk); + @(negedge clk); + @(negedge clk); + @(negedge clk); + end + endtask // serial_settings_transaction + + task serial_settings_bit; + input one_bit; + + begin + scl_r <= 1'b0; + sda_r <= one_bit; + @(negedge clk); + @(negedge clk); + @(negedge clk); + @(negedge clk); + scl_r <= 1'b1; + @(negedge clk); + @(negedge clk); + @(negedge clk); + @(negedge clk); + end + endtask // send_settings_bit diff --git a/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/default.wcfg b/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/default.wcfg new file mode 100644 index 000000000..877ce2f20 --- /dev/null +++ b/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/default.wcfg @@ -0,0 +1,86 @@ + + + + + + + + + + + + + + + clk + clk + + + reset + reset + + + scl_r + scl_r + + + sda_r + sda_r + + + scl + scl + + + sda + sda + + + set_stb + set_stb + + + set_addr[7:0] + set_addr[7:0] + HEXRADIX + + + set_data[31:0] + set_data[31:0] + HEXRADIX + + + state[2:0] + state[2:0] + HEXRADIX + + + scl_pre_reg + scl_pre_reg + + + scl_reg + scl_reg + + + scl_reg2 + scl_reg2 + + + sda_pre_reg + sda_pre_reg + + + sda_reg + sda_reg + + + sda_reg2 + sda_reg2 + + + counter[4:0] + counter[4:0] + HEXRADIX + + diff --git a/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/run_isim b/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/run_isim new file mode 100755 index 000000000..e4730676b --- /dev/null +++ b/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/run_isim @@ -0,0 +1,24 @@ +vlogcomp -work work ${XILINX}/verilog/src/glbl.v + +vlogcomp -work work --sourcelibext .v \ + --sourcelibdir ../../../lib/axi \ + --sourcelibdir ../../../lib/fifo \ + --sourcelibdir ../../../lib/control \ + --sourcelibdir ../../../top/b200/coregen \ + --sourcelibdir ../../../top/b200 \ + --sourcelibdir ../../../lib/timing \ + --sourcelibdir ../../../lib/vita \ + --sourcelibdir ../../../lib/packet_proc \ + --sourcelibdir ../../../lib/dsp \ + --sourcelibdir ../../../lib/wishbone \ + --sourcelibdir ../../../lib/gpif2 \ + ../../../lib/control/serial_to_settings_tb.v + + + +fuse work.serial_to_settings_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o serial_to_settings_tb.exe + +# run the simulation scrip +./serial_to_settings_tb.exe -gui #-tclbatch simcmds.tcl + + diff --git a/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/simulation_script.v b/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/simulation_script.v new file mode 100644 index 000000000..d3b669594 --- /dev/null +++ b/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/simulation_script.v @@ -0,0 +1,43 @@ + +`include "../serial_settings_tasks.v" + + initial + begin + clk <= 1'b0; + reset <= 1'b0; + scl_r <= 1'b1; + sda_r <= 1'b1; + end + + always + #5 clk <= ~clk; + + initial + begin + + + @(negedge clk); + reset <= 1'b1; + repeat(10) @(negedge clk); + reset <= 1'b0; + repeat(10) @(negedge clk); + + serial_settings_transaction(8'h0,32'h01b2); + + serial_settings_transaction(8'h3, 32'h5); + + serial_settings_transaction(8'h3,32'hA); + + serial_settings_transaction(8'h3,32'hF); + + + repeat(10000) @(negedge clk); + @(negedge clk); + @(negedge clk); + @(negedge clk); + + $finish; + + end // initial begin + + \ No newline at end of file diff --git a/fpga/usrp3/sim/task_library.v b/fpga/usrp3/sim/task_library.v new file mode 100644 index 000000000..7e878ec1a --- /dev/null +++ b/fpga/usrp3/sim/task_library.v @@ -0,0 +1,297 @@ +/////////////////////////////////////////////////////////////////// +// +// USRP3 Task Libaray +// +/////////////////////////////////////////////////////////////////// + +`define SID(a,b,c,d) ((a & 'hff) << 24) | ((b & 'hff) << 16)| ((c & 'hff) << 8) | (d & 'hff) + +`ifndef TB_FILE_IN_NUMBER + `define TB_FILE_IN_NUMBER 0 +`endif +`ifndef TB_FILE_OUT_NUMBER + `define TB_FILE_OUT_NUMBER 0 +`endif +`ifndef TB_FILE_GOLDEN_NUMBER + `define TB_FILE_GOLDEN_NUMBER 0 +`endif +`ifndef TB_FILE_IN_NAME + `define TB_FILE_IN_NAME "tb_file_in" +`endif +`ifndef TB_FILE_OUT_NAME + `define TB_FILE_OUT_NAME "tb_file_out" +`endif +`ifndef TB_FILE_GOLDEN_NAME + `define TB_FILE_GOLDEN_NAME "tb_file_golden" +`endif + +integer tb_file_in_desc[`TB_FILE_IN_NUMBER-1:0]; + +/* -----\/----- EXCLUDED -----\/----- +reg clk; +reg reset; +reg clear; + -----/\----- EXCLUDED -----/\----- */ + + +/* -----\/----- EXCLUDED -----\/----- +reg set_stb; +reg [7:0] set_addr; +reg [31:0] set_data; + -----/\----- EXCLUDED -----/\----- */ +/* -----\/----- EXCLUDED -----\/----- + +`ifndef CHDR_IN_NUMBER + `define CHDR_IN_NUMBER 1 +`endif + + +reg [63:0] data_in[`CHDR_IN_NUMBER-1:0]; +reg last_in[`CHDR_IN_NUMBER-1:0]; +reg valid_in[`CHDR_IN_NUMBER-1:0]; +wire ready_in[`CHDR_IN_NUMBER-1:0]; + -----/\----- EXCLUDED -----/\----- */ + + +/////////////////////////////////////////////////////////////////// +// +// open_files +// +// The "open_files" task opens all standard stimulus, response, and +// golden response files to drive other tasks in the library. +// Both the numbers of files and there names can be altered by pre-defining +// the TB_FILE* pre-processor definitions. All files are assumed to be +// readmemh style format and will use a ".hex" file extension. +// +/////////////////////////////////////////////////////////////////// +task open_files; + reg [7:0] x; + reg [7:0] y; + reg [8*32:0] filename; + + begin + x = 0; + // Caveman verilog string handling to dynamicly form file name + while (x != `TB_FILE_IN_NUMBER) begin + y = x; + filename = {`TB_FILE_IN_NAME,("0" + (y % 10))}; + while (y/10 >0) begin + filename = {(filename << 8),("0" + (y % 10))}; + y = y/10; + end + // Always use .hex as file extention for readmemh style data + filename = {filename,".hex"}; + tb_file_in_desc[x] = $fopen(filename); + x = x + 1; + end + end +endtask + +/////////////////////////////////////////////////////////////////// +// +// close_files +// +// The "close_files" task closes all files opened by a previous +// call to "open_files". +// +/////////////////////////////////////////////////////////////////// +task close_files; + reg [7:0] x; + + begin + x = 0; + while (x != `TB_FILE_IN_NUMBER) begin + $fclose(tb_file_in_desc[x]); + x = x + 1; + end + end +endtask // close_files + +/////////////////////////////////////////////////////////////////// +// +// write_settings_bus +// +// The "write settings_bus" task performs a single settings bus +// transaction in 3 clock cycles, the first and 3rd cycles being +// idle cycles. "write_settings_bus" is not re-entrant and should +// only be used sequentially in a single test bench thread. +// +/////////////////////////////////////////////////////////////////// + task write_setting_bus; + input [15:0] address; + input [31:0] data; + + begin + + @(posedge clk); + set_stb <= 1'b0; + set_addr <= 16'h0; + set_data <= 32'h0; + @(posedge clk); + set_stb <= 1'b1; + set_addr <= address; + set_data <= data; + @(posedge clk); + set_stb <= 1'b0; + set_addr <= 16'h0; + set_data <= 32'h0; + + end + endtask // write_setting_bus + +/////////////////////////////////////////////////////////////////// +// +// Place 64bits of data on CHDR databus, set last if indicated. +// Wait unitl ready asserted before returning with valid de-assrted. +// +/////////////////////////////////////////////////////////////////// + + task automatic enqueue_line; + input [7:0] input_port; + input last; + input [63:0] data; + begin + data_in[input_port] <= data; + last_in[input_port] <= last; + valid_in[input_port] <= 1; + @(posedge clk); + while (~ready_in[input_port]) begin + @(posedge clk); + end + data_in[input_port] <= 0; + last_in[input_port] <= 0; + valid_in[input_port] <= 0; + end + endtask // enqueue_line + +/////////////////////////////////////////////////////////////////// +// +// Place 64bits of data on CHDR databus, set last if indicated. +// Wait unitl ready asserted before returning with valid de-assrted. +// +/////////////////////////////////////////////////////////////////// + + task automatic dequeue_line; + input [7:0] output_port; + output last; + output [63:0] data; + begin + while (~valid_out[output_port]) begin + ready_out[output_port] <= 1; + @(posedge clk); + end + + // NOTE: A subtle constraint of Verilog is that non-blocking assignments can not be used + // to an automatically allocated variable. Fall back to blocking assignent + data = data_out[output_port]; + last = last_out[output_port]; + ready_out[output_port] <= 1; + @(posedge clk); + ready_out[output_port] <= 0; + + end + endtask // enqueue_line + + +/////////////////////////////////////////////////////////////////// +// +// CHDR Header format: +// Word1: FLAGS [63:60], SEQ_ID [59:48], SIZE [47:32], SID [31:0] +// [63]ExtensionContext, [62]HasTrailer, [61]HasTime, [60]EOB +// Word2: Time [63:0] (Optional, see header bit [61]) +// Word3+: Payload +// +/////////////////////////////////////////////////////////////////// + task automatic enqueue_chdr_pkt_count; + input [7:0] input_port; // Which test bench CHDR ingress port + input [11:0] seq_id; // CHDR sequence ID. + input [15:0] chdr_size; // Total CHDR packet size in bytes. + input has_time; // This CHDR packet has 64bit time field. + input [63:0] chdr_time; // 64bit CHDR time value + input is_extension; // This packet is flaged extension context + input is_eob; // This packet is the end of a CHDR burst. + input [31:0] chdr_sid; // CHDR SID address pair. + + integer i; + reg [15:0] j; + + begin + @(posedge clk); + enqueue_line(input_port, 0, {is_extension,1'b0,has_time,is_eob,seq_id,chdr_size,chdr_sid}); + if (has_time) // If time flag set add 64bit time as second word. + enqueue_line(input_port, 0, chdr_time); + j = 0; + + for (i = (has_time ? 24 : 16); i < chdr_size; i = i + 8) begin + enqueue_line(input_port, 0 , {j,j+16'h1,j+16'h2,j+16'h3}); + j = j + 4; + end + // Populate last line with data even if sizes shows it's not used. + enqueue_line(input_port, 1, {j,j+16'h1,j+16'h2,j+16'h3}); + + end + endtask // automatic + + +task automatic dequeue_chdr_pkt_count; + input [7:0] output_port; // Which test bench CHDR ingress port + input [11:0] seq_id; // CHDR sequence ID. + input [15:0] chdr_size; // Total CHDR packet size in bytes. + input has_time; // This CHDR packet has 64bit time field. + input [63:0] chdr_time; // 64bit CHDR time value + input is_extension; // This packet is flaged extension context + input is_eob; // This packet is the end of a CHDR burst. + input [31:0] chdr_sid; // CHDR SID address pair. + + integer i; + reg [15:0] j; + + reg last; + reg [63:0] data; + + begin + @(posedge clk); + dequeue_line(output_port, last, data); + if ({is_extension,1'b0,has_time,is_eob,seq_id,chdr_size,chdr_sid} !== data) + $display("FAILED: Output port: %3d Bad CHDR Header. Got %8x, expected %8x @ time: %d ", + output_port, data, {is_extension,1'b0,has_time,is_eob,seq_id,chdr_size,chdr_sid},$time); +// else +// $display("PASSED: Output port: %3d Bad CHDR Header. Got %8x, expected %8x @ time: %d ", +// output_port, data, {is_extension,1'b0,has_time,is_eob,seq_id,chdr_size,chdr_sid},$time); + if (has_time) // If time flag set add 64bit time as second word. + begin + dequeue_line(output_port, last, data); + if (data !== chdr_time) + $display("FAILED: Output port: %3d Bad CHDR Time. Got %8x, expected %8x @ time: %d ", + output_port, data, chdr_time, $time); +// else +// $display("PASSED: Output port: %3d Bad CHDR Time. Got %8x, expected %8x @ time: %d ", +// output_port, data, chdr_time, $time); + end + j = 0; + + for (i = (has_time ? 24 : 16); i < chdr_size; i = i + 8) begin + dequeue_line(output_port, last , data); + if ({j,j+16'h1,j+16'h2,j+16'h3} !== data) + $display("FAILED: Output port: %3d Bad CHDR Payload. Got %8x, expected %8x @ time: %d ", + output_port, data,{j,j+16'h1,j+16'h2,j+16'h3} ,$time); +// else +// $display("PASSED: Output port: %3d Bad CHDR Payload. Got %8x, expected %8x @ time: %d ", +// output_port, data, {is_extension,1'b0,has_time,is_eob,seq_id,chdr_size,chdr_sid},$time); + j = j + 4; + end + // Check only bytes included in packet + dequeue_line(output_port, last, data); + if (({j,j+16'h1,j+16'h2,j+16'h3} >> (8-j)) !== ( data>> (8-j))) + $display("FAILED: Output port: %3d Bad CHDR Payload. Got %8x, expected %8x @ time: %d ", + output_port, data >> (8-j), + {j,j+16'h1,j+16'h2,j+16'h3} >> (8-j),$time); +// else +// $display("PASSED: Output port: %3d Bad CHDR Payload. Got %8x, expected %8x @ time: %d ", +// output_port, data >> (8-j), +// {is_extension,1'b0,has_time,is_eob,seq_id,chdr_size,chdr_sid} >> (8-j),$time); + + end + +endtask // dequeue_packet + -- cgit v1.2.3