From ff1546f8137f7f92bb250f685561b0c34cc0e053 Mon Sep 17 00:00:00 2001 From: Ben Hilburn Date: Fri, 14 Feb 2014 12:05:07 -0800 Subject: Pushing the bulk of UHD-3.7.0 code. --- .../sim/serial_to_settings/serial_settings_tasks.v | 59 +++++++++++++++ .../sim_serial_to_settings_1/default.wcfg | 86 ++++++++++++++++++++++ .../sim_serial_to_settings_1/run_isim | 24 ++++++ .../sim_serial_to_settings_1/simulation_script.v | 43 +++++++++++ 4 files changed, 212 insertions(+) create mode 100644 fpga/usrp3/sim/serial_to_settings/serial_settings_tasks.v create mode 100644 fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/default.wcfg create mode 100755 fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/run_isim create mode 100644 fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/simulation_script.v (limited to 'fpga/usrp3/sim/serial_to_settings') diff --git a/fpga/usrp3/sim/serial_to_settings/serial_settings_tasks.v b/fpga/usrp3/sim/serial_to_settings/serial_settings_tasks.v new file mode 100644 index 000000000..a9e2c0344 --- /dev/null +++ b/fpga/usrp3/sim/serial_to_settings/serial_settings_tasks.v @@ -0,0 +1,59 @@ + + task serial_settings_transaction; + input [7:0] address; + input [31:0] data; + + integer x; + + begin + scl_r <= 1'b1; + sda_r <= 1'b1; + @(negedge clk); + @(negedge clk); + // Drive SDA low whilst SCL high to signal START + sda_r <= 1'b0; + @(negedge clk); + @(negedge clk); + // Send 8 Address bits MSB first on falling edge of SCL clocks + for (x = 7; x >= 0; x = x - 1) + serial_settings_bit(address[x]); + // Send 32 Data bits MSB first on falling edge of SCL clocks + for (x = 31; x >= 0; x = x - 1) + serial_settings_bit(data[x]); + // Send STOP. + scl_r <= 1'b0; + sda_r <= 1'b0; + @(negedge clk); + @(negedge clk); + @(negedge clk); + @(negedge clk); + scl_r <= 1'b1; + @(negedge clk); + @(negedge clk); + @(negedge clk); + @(negedge clk); + sda_r <= 1'b1; + @(negedge clk); + @(negedge clk); + @(negedge clk); + @(negedge clk); + end + endtask // serial_settings_transaction + + task serial_settings_bit; + input one_bit; + + begin + scl_r <= 1'b0; + sda_r <= one_bit; + @(negedge clk); + @(negedge clk); + @(negedge clk); + @(negedge clk); + scl_r <= 1'b1; + @(negedge clk); + @(negedge clk); + @(negedge clk); + @(negedge clk); + end + endtask // send_settings_bit diff --git a/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/default.wcfg b/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/default.wcfg new file mode 100644 index 000000000..877ce2f20 --- /dev/null +++ b/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/default.wcfg @@ -0,0 +1,86 @@ + + + + + + + + + + + + + + + clk + clk + + + reset + reset + + + scl_r + scl_r + + + sda_r + sda_r + + + scl + scl + + + sda + sda + + + set_stb + set_stb + + + set_addr[7:0] + set_addr[7:0] + HEXRADIX + + + set_data[31:0] + set_data[31:0] + HEXRADIX + + + state[2:0] + state[2:0] + HEXRADIX + + + scl_pre_reg + scl_pre_reg + + + scl_reg + scl_reg + + + scl_reg2 + scl_reg2 + + + sda_pre_reg + sda_pre_reg + + + sda_reg + sda_reg + + + sda_reg2 + sda_reg2 + + + counter[4:0] + counter[4:0] + HEXRADIX + + diff --git a/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/run_isim b/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/run_isim new file mode 100755 index 000000000..e4730676b --- /dev/null +++ b/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/run_isim @@ -0,0 +1,24 @@ +vlogcomp -work work ${XILINX}/verilog/src/glbl.v + +vlogcomp -work work --sourcelibext .v \ + --sourcelibdir ../../../lib/axi \ + --sourcelibdir ../../../lib/fifo \ + --sourcelibdir ../../../lib/control \ + --sourcelibdir ../../../top/b200/coregen \ + --sourcelibdir ../../../top/b200 \ + --sourcelibdir ../../../lib/timing \ + --sourcelibdir ../../../lib/vita \ + --sourcelibdir ../../../lib/packet_proc \ + --sourcelibdir ../../../lib/dsp \ + --sourcelibdir ../../../lib/wishbone \ + --sourcelibdir ../../../lib/gpif2 \ + ../../../lib/control/serial_to_settings_tb.v + + + +fuse work.serial_to_settings_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o serial_to_settings_tb.exe + +# run the simulation scrip +./serial_to_settings_tb.exe -gui #-tclbatch simcmds.tcl + + diff --git a/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/simulation_script.v b/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/simulation_script.v new file mode 100644 index 000000000..d3b669594 --- /dev/null +++ b/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/simulation_script.v @@ -0,0 +1,43 @@ + +`include "../serial_settings_tasks.v" + + initial + begin + clk <= 1'b0; + reset <= 1'b0; + scl_r <= 1'b1; + sda_r <= 1'b1; + end + + always + #5 clk <= ~clk; + + initial + begin + + + @(negedge clk); + reset <= 1'b1; + repeat(10) @(negedge clk); + reset <= 1'b0; + repeat(10) @(negedge clk); + + serial_settings_transaction(8'h0,32'h01b2); + + serial_settings_transaction(8'h3, 32'h5); + + serial_settings_transaction(8'h3,32'hA); + + serial_settings_transaction(8'h3,32'hF); + + + repeat(10000) @(negedge clk); + @(negedge clk); + @(negedge clk); + @(negedge clk); + + $finish; + + end // initial begin + + \ No newline at end of file -- cgit v1.2.3