From ff1546f8137f7f92bb250f685561b0c34cc0e053 Mon Sep 17 00:00:00 2001
From: Ben Hilburn <ben.hilburn@ettus.com>
Date: Fri, 14 Feb 2014 12:05:07 -0800
Subject: Pushing the bulk of UHD-3.7.0 code.

---
 fpga/usrp3/sim/b2x0/sim_b2x0_1/run_isim | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100755 fpga/usrp3/sim/b2x0/sim_b2x0_1/run_isim

(limited to 'fpga/usrp3/sim/b2x0')

diff --git a/fpga/usrp3/sim/b2x0/sim_b2x0_1/run_isim b/fpga/usrp3/sim/b2x0/sim_b2x0_1/run_isim
new file mode 100755
index 000000000..dd9215934
--- /dev/null
+++ b/fpga/usrp3/sim/b2x0/sim_b2x0_1/run_isim
@@ -0,0 +1,22 @@
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+
+vlogcomp -work work --sourcelibext .v \
+        --sourcelibdir ../../../lib/axi \
+        --sourcelibdir ../../../lib/fifo \
+        --sourcelibdir ../../../lib/control \
+        --sourcelibdir ../../../top/b200/coregen \
+        --sourcelibdir ../../../top/b200 \
+        --sourcelibdir ../../../lib/timing \
+        --sourcelibdir ../../../lib/vita \
+        --sourcelibdir ../../../lib/packet_proc \
+        --sourcelibdir ../../../lib/dsp \
+        --sourcelibdir ../../../lib/wishbone \
+        --sourcelibdir ../../../lib/gpif2 \
+        ../../../top/b200/b200_tb.v
+
+
+
+fuse work.b200_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o b200_tb.exe
+
+# run the simulation scrip
+./b200_tb.exe  # -gui #-tclbatch simcmds.tcl
-- 
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