From fd3e84941de463fa1a7ebab0a69515b4bf2614cd Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Tue, 7 Oct 2014 11:25:20 +0200 Subject: Removed copy of FPGA source files. --- .../sim/axi_dram_fifo/sim_sram_2/Default.wcfg | 388 --------------------- fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/run_isim | 19 - .../axi_dram_fifo/sim_sram_2/simulation_script.v | 91 ----- 3 files changed, 498 deletions(-) delete mode 100644 fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/Default.wcfg delete mode 100755 fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/run_isim delete mode 100644 fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/simulation_script.v (limited to 'fpga/usrp3/sim/axi_dram_fifo/sim_sram_2') diff --git a/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/Default.wcfg b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/Default.wcfg deleted file mode 100644 index 3e6d96fb4..000000000 --- a/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/Default.wcfg +++ /dev/null @@ -1,388 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - clk - clk - - - reset - reset - - - chdr_test_pattern - label - HEXRADIX - - start - start - - - i_tdata[63:0] - i_tdata[63:0] - HEXRADIX - - - i_tlast - i_tlast - - - i_tvalid - i_tvalid - - - i_tready - i_tready - - - o_tdata[63:0] - o_tdata[63:0] - HEXRADIX - - - o_tlast - o_tlast - - - o_tready - o_tready - - - o_tvalid - o_tvalid - - - - embed_tlast - label - HEXRADIX - - i_tdata[63:0] - i_tdata[63:0] - HEXRADIX - - - i_tlast - i_tlast - - - i_tvalid - i_tvalid - - - i_tready - i_tready - - - o_tdata[63:0] - o_tdata[63:0] - HEXRADIX - - - o_tvalid - o_tvalid - - - o_tready - o_tready - - - state[1:0] - state[1:0] - HEXRADIX - - - - fast_fifo_i0 - label - HEXRADIX - - state[1:0] - state[1:0] - HEXRADIX - - - i_tdata[63:0] - i_tdata[63:0] - HEXRADIX - - - FullPathName - i_tvalid - i_tvalid - - - i_tready - i_tready - - - o_tdata[63:0] - o_tdata[63:0] - HEXRADIX - - - o_tvalid - o_tvalid - - - label - o_tready - o_tready - o_tready - - - - fifo_i1 - label - HEXRADIX - - i_tdata[63:0] - i_tdata[63:0] - HEXRADIX - - - i_tvalid - i_tvalid - - - i_tready - i_tready - - - o_tdata[63:0] - o_tdata[63:0] - HEXRADIX - - - o_tvalid - o_tvalid - - - o_tready - o_tready - - - - AXI write bus - label - - axi_awaddr[31:0] - axi_awaddr[31:0] - HEXRADIX - - - axi_awlen[7:0] - axi_awlen[7:0] - HEXRADIX - - - axi_awvalid - axi_awvalid - - - axi_awready - axi_awready - - - axi_wdata[63:0] - axi_wdata[63:0] - HEXRADIX - - - axi_wvalid - axi_wvalid - - - axi_wready - axi_wready - - - axi_bvalid - axi_bvalid - - - axi_bready - axi_bready - - - - space[10:0] - space[10:0] - HEXRADIX - - - occupied[10:0] - occupied[10:0] - HEXRADIX - - - AXI read bus - label - HEXRADIX - - m_axi_araddr[31:0] - m_axi_araddr[31:0] - HEXRADIX - - - m_axi_arlen[7:0] - m_axi_arlen[7:0] - HEXRADIX - - - m_axi_arvalid - m_axi_arvalid - - - m_axi_arready - m_axi_arready - - - m_axi_rdata[63:0] - m_axi_rdata[63:0] - HEXRADIX - - - m_axi_rvalid - m_axi_rvalid - - - m_axi_rready - m_axi_rready - - - - fifo_i2 - label - - i_tdata[63:0] - i_tdata[63:0] - HEXRADIX - - - i_tvalid - i_tvalid - - - i_tready - i_tready - - - o_tdata[63:0] - o_tdata[63:0] - HEXRADIX - - - o_tvalid - o_tvalid - - - o_tready - o_tready - - - - fast_fifo_i1 - label - HEXRADIX - - i_tdata[63:0] - i_tdata[63:0] - HEXRADIX - - - i_tvalid - i_tvalid - - - i_tready - i_tready - - - o_tdata[63:0] - o_tdata[63:0] - HEXRADIX - - - o_tready - o_tready - - - o_tvalid - o_tvalid - - - - axi_fast_extract - label - HEXRADIX - - i_tdata[63:0] - i_tdata[63:0] - HEXRADIX - - - i_tvalid - i_tvalid - - - i_tready - i_tready - - - o_tdata[63:0] - o_tdata[63:0] - HEXRADIX - - - o_tlast - o_tlast - - - o_tready - o_tready - - - o_tvalid - o_tvalid - - - - dram_fifo_output - label - HEXRADIX - - o_tdata[63:0] - o_tdata[63:0] - HEXRADIX - - - o_tlast - o_tlast - - - o_tvalid - o_tvalid - - - o_tready - o_tready - - - diff --git a/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/run_isim b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/run_isim deleted file mode 100755 index 46141fcae..000000000 --- a/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/run_isim +++ /dev/null @@ -1,19 +0,0 @@ -/bin/rm -r isim - -vlogcomp -work work ${XILINX}/verilog/src/glbl.v - -vlogcomp -work work --sourcelibext .v \ - --sourcelibdir ../../../lib/axi \ - --sourcelibdir ../../../lib/fifo \ - --sourcelibdir ../../../lib/control \ - --sourcelibdir ../../../top/x300/coregen \ - ../../../lib/axi/axi_dram_fifo_tb.v - - - -fuse work.axi_dram_fifo_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_dram_fifo_tb.exe - -# run the simulation scrip -./axi_dram_fifo_tb.exe -gui #-tclbatch simcmds.tcl - - diff --git a/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/simulation_script.v b/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/simulation_script.v deleted file mode 100644 index 4a94820b7..000000000 --- a/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/simulation_script.v +++ /dev/null @@ -1,91 +0,0 @@ -wire fail; -wire done; -reg start; -reg [15:0] control; - - - -axi_chdr_test_pattern axi_chdr_test_pattern_i - ( - .clk(clk), - .reset(reset), - - // - // CHDR friendly AXI stream input - // - .i_tdata(i_tdata), - .i_tlast(i_tlast), - .i_tvalid(i_tvalid), - .i_tready(i_tready), - // - // CHDR friendly AXI Stream output - // - .o_tdata(o_tdata), - .o_tlast(o_tlast), - .o_tvalid(o_tvalid), - .o_tready(o_tready), - // - // Test flags - // - .start(start), - .fail(fail), - .done(done), - .control(control) - ); - - - always - #5 clk <= ~clk; - - initial - begin - clk <= 1'b0; - reset <= 1'b0; - clear <= 1'b0; - start <= 1'b0; - control <= 16'h0101; - - - @(negedge clk); - reset <= 1'b1; - repeat(10) @(negedge clk); - reset <= 1'b0; - repeat(10) @(negedge clk); - // Now activate BIST - start <= 1'b1; - - // Wait until simulation is done. - while(!done) - @(negedge clk); - - $display; - - if (fail) - $display("FAILED."); - else - $display("Done 1st pass."); - - @(posedge clk); - start <= 1'b0; - repeat(10) @(negedge clk); - // Now activate BIST - start <= 1'b1; - - // Wait until simulation is done. - while(!done) - @(negedge clk); - - $display; - - if (fail) - $display("FAILED."); - else - $display("PASSED."); - - $finish; - - end - - //initial - // o_tready = 1; - -- cgit v1.2.3